Digital modular control of high frequency DC–DC converters

Abílio Parreira a, Floriberto Lima b, Marcelino Santos a,b,n

a IST, INESC-ID, Rua Alves Redol, 9, 1000-029 Lisbon, Portugalb SILICONGATE LDA, Porto, Portugal

a r t i c l e i n f o

Article history:Received 15 February 2013Received in revised form8 September 2013Accepted 16 December 2013

Keywords:DC–DC converterDigital controlAnalog and mixed signal designPVT tolerant designLow power design

a b s t r a c t

This paper presents a solution for controlling integrated DC–DC converters with high switchingfrequency (420 MHz). The increase of the switching frequency is a trend biased by output filter volumerestrictions and integration demand. The control of DC–DC converters operating at high frequencypresents an opportunity to speed up the converter response time but also a challenge specially for thecontrol solution, quiescent current and to limit the sensitivity to process and operating conditions for themixed signal circuits involved. The solution presented in this work relies on separating the duty-cycleinto three parts: a load-free value that depends only on the input and output voltages, a transient fastcorrection contribution, and an accurate compensation for the IR drop that depends on the load current.The load-free portion of the duty-cycle has a compensation of PVT variations and the fast transient partof the duty-cycle uses a non-linear sliding mode control solution. All the analog blocks required for theimplementation of the proposed solution are detailed.

& 2014 Elsevier Ltd. All rights reserved.

1. Introduction

Integrated DC–DC converters are now present in almost allconsumer electronics due to the need of high efficiency in powersupplies. On portable equipment, where the presence of DC–DCconverters is stronger due to their efficiency impact on the auton-omy, miniaturization is an important figure of merit, contributing tosolutions where DC–DC converters are integrated in Systems-on-Chip (SoC) and the volume of the output filter is progressively beingreduced. In recent years, with the growing presence of portablesystems, DC–DCs have been pushed to increasing switchingfrequencies in order to allow the desired output filter volumereduction. Currently a typical SoC includes DC–DC converterssupplied by lithium batteries and switching below 5 MHz. Theseconverters are required to deliver 100 mA to 3 A @o1.2 V, depend-ing on the application. But there is also a trend to place DC–DCconverters on SoC solutions where previously only linear regulatorswere used like smart cards and security chips. In this cases the fullDC–DC including the output filter needs to be integrated into theSoC and the power requirements for the cryptography machines,flash and communication controllers is 20 mA to 150 mA @o1.2 V.For these cases a much higher switching frequency is required andone of the main challenges is the control implementation.

Analog control solutions that limit the duty-cycle based on realtime decision of comparators are not suitable since the compara-tors response time is longer than the period of switching for highfrequency DC–DCs. Faster comparators could be designed but itwould impact severely the efficiency due to their higher currentconsumption.

A very limited number of proposals for high frequency DC–DCdesign can be found in the literature. Purely analog solutions usingvoltage to delay conversion can be found in [1,2]. However, [1]focuses only the efficiency and does not evaluate the controlsolution used. In [2] a DC–DC converter was designed and operatesat 120 MHz with peak efficiency of 87% at 500 mA using a 36 nHinductor and a 4.7 μF capacitor in the output filter. However, theimpact of process, voltage and temperature (PVT) variations in theanalog voltage to pulse converter and stability are not analyzed andthe slow control speed results into a large output capacitor neededto accommodate the load transients. The major limitation of thesolutions proposed in [1,2] is the fact that the duty-cycle consists ina unique delay controlled by a current, i. The delay depends on 1/iand, therefore, the transient response is strongly dependent on theoperating point dictated by the bias operating point. More recentresearch works on high frequency DCDC converters focused mainlythe integration of the inductor using the packaging parasitics [3,4]and magnetic-on-silicon [5] or present control solutions based onnon CMOS technology [6]. This work proposes to add this DOP witha digitally controlled number of additional delays for transientresponse optimization.

Many digital control solutions have been proposed for thecontrol of DC–DCs. The Proximate Time-Optimal Digital Control

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n Corresponding author at: INESC-ID, Rua Alves Redol, 9, 1000-029 Lisbon,Portugal. Tel.: þ351 213 100 288.

E-mail address: marcelino.santos@silicongate.com (M. Santos).

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(PTODC) [7] combines a linear controller and a non-linear con-troller. Han Wei and Meng Tong Tan [8] use V2 with reduction ofsteady-state oscillations. [9] presents a Hybrid Digital Pulse WidthModulator (DPWM) with a frequency domain ADC. [10] proposesa Dual-Band Switching Digital Controller. An Autotuning DigitallyControlled Buck converter [11] based on relay feedback usesiterative procedures to obtain the PID parameters. A model-freecontrol with “intelligent” PI controllers is proposed in [12]. The“Digital Load Current Feed-Forward Control” [13] uses PID con-troller and feed-forward duty-cycle from the capacitor charge,calculated from the inductor current. The “Fully-Digital HystereticVoltage Mode Control” based on Asynchronous Sampling [14] usesthe output voltage and the control state to estimate the inductorcurrent. A PWM PID digital control is proposed in [15]. A simplenon-linear gain scheduling [16] method in Digital PWM Converteruses the last three samples of the output voltage, and the last dutycycle value, to control the buck converter. A previous descriptionof digital sliding mode control (SMC) for a DC–DC can be foundin [17]. It uses voltage to frequency converter to convert the outputvoltage into a variable frequency square wave. The steady state isachieved by doing the difference, in the frequency domain, betweenthe signal generated by the reference voltage and the convertedoutput voltage. In steady state, a delay line and a counter are used togenerate the DC–DC control signal. The work presents an originaldigital implementation of the SMC with a self-adaptive ADC. Theproposed control presents stable frequency of operation and veryhigh performance for line and load transients for 600 kHz switchingfrequency.

The use of the sliding mode control to control DC–DC conver-sion has the advantage of being a robust control approach. Mostimplementations of the sliding mode control of DC–DCs are analogimplementations. Several authors implemented the sliding modecontrol directly [18–20], while others used the equivalent controllaw obtained from the sliding mode control [21,22]. The majordrawback of analog implementations of the sliding mode controlfor integrated DC–DCs, operating in the few Mega Hertz range, isthe bandwidth required for the amplifier that implements therequired control law. The implementation of suitable bandwidthamplifiers is not feasible for high frequency DC–DCs.

Digital control solutions frequently require frequencies ofoperation higher than the switching frequency in order to com-pute the duty-cycle value in real time. However, for high switchingfrequency, the power consumption of digital control, that requireseven higher control frequency, severely impacts the DC–DCefficiency specially when operating at light loads. Moreover, thepower required for the digital control operation must be added tothe power required for the analog to digital conversion of theoutput voltage. Therefore, non-linear analog-to-digital conversionwith a very limited number of quantization ranges is fundamentalin order to allow fast feedback with limited power being wasted in

this quantification. Recently, the authors of this work presenteda digital control solution for high frequency DC–DC converters thatimplements a non-linear sliding mode control only requiring thequantification of the output voltage in three ranges (two compara-tors) and knowing the output voltage derivative (by comparing twoconsecutive samples) [23]. This work presents the implementationof the proposed high frequency DC–DC control solution, detailingthe required high frequency comparators for the output quantizationand derivative analysis.

The rest of the paper is organized as follows: Section 2 presentsthe proposed control methodology; the implementation is detailedin Section 3, Section 4 presents the high frequency comparators

Fig. 1. DC–DC buck converter.

Fig. 2. DLL for the generation of ictr¼ iref and T�Dideal.

Fig. 3. DLL for the generation of T� (Didealþd).

Fig. 4. Duty-cycle obtained with PVT variation in AMS 0.35 μm with the topologyof Fig. 2.

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details; Section 5 presents simulation results and the conclusions ofthis work are summarized in Section 6.

2. Modular control architecture

Fig. 1 presents the block diagram of a DC–DC buck converter,detailing the transistors that implement the power switches andthe output filter.

When using constant frequency of operation (most of the timesin order to limit the noise spectrum), the purpose of the controlleris to define the duty-cycle of the PWM signal and therefore, theenergy transferred to the output filter. This duty-cycle has threedistinct contributions:

– Dideal—corresponds to the ideal duty-cycle of a converter with-out resistive losses and working in steady state.

– DIRlosses—represents the increment in the duty-cycle required inorder to compensate de resistive losses.

– d—is a temporary addition or subtraction to the duty-cycle thatenables the dynamic correction of the output voltage duringline or load transients.

The sum of the first two contributions is defined as theoperating point duty-cycle (DOP¼DidealþDIRlosses) and correspondsto the steady state duty-cycle for specific values of vout, vBAT and iL.

The variation limits and the dynamics required for each contribu-tion to the duty-cycle is distinct and the ability to optimize themindividually is a major advantage of this modular control approach.Dideal and d usually require a large range of variation while DIRlosses

consists in very limited adjustments to the duty-cycle. The variablesthat dynamically can be used to optimize each contribution aredifferent: Dideal depends only on the input and target output voltages.As defined in (1).

Dideal ¼ vref =vBAT ð1Þ

In order to evaluate which variables are relevant for theoptimization of DIRlosses it is required to analyze the requiredchange in the duty-cycle, ΔDIRlosses, that can compensate anincrease of load current from iL¼ I to iL¼ IþΔi. Considering thatiL flows through R, that represents all the resistive losses, it can beeasily obtained that:

ΔDIRlosses ¼Δi� R=vBAT ð2Þ

Eqs. (1) and (2) allow the conclusion that an increase in theinput voltage causes the obvious reduction of the Dideal, but, in thepresence of a load change, DIRlosses is optimally adapted if it alsovaries proportionally to 1/vBAT. If a mechanism is implemented toadjust Dideal, the required similar dependence of DIRlosses on thesupply voltage can be implemented in the control by making thedigitally controlled increments in DIRlosses proportional to Dideal.

The d contribution for the duty cycle, being the correction factorfor transient variations of the output voltage, can be adjusted takinginto account the output voltage value and its derivative using slidingmode control.

Using a digital modular control it is possible to optimize thedynamics of each contribution.

Fig. 5. Delay line for generation of T� (DidealþdþDIRlosses).

Fig. 6. Derivative sensing of the output voltage.

Fig. 7. Switch comparator suitable for high frequency operation.

Fig. 8. Switch comparator with two outputs with different offsets.

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3. Modular digital control implementation

When designing a control for high frequency of operation oneof the major challenges is dealing with the parametric variationsdue to PVT. In fact, since the delays to control are much shorter,these variations produce much more significant relative impact.Therefore, it is mandatory to use solutions that compensate PVTand are able to produce the expected delays for the control.

The solution used in this work to obtain Dideal is presented inFig. 2 and consists in a delay locked loop working at a fixedfrequency, f¼1/T, controlled in current, and forced to produce anoutput voltage identical to the reference:

vref ¼Dideal � vBAT ð3ÞThis DLL implements two tasks:

– Forces a current controlled delay line to present a delay thatcorresponds to the ideal duty-cycle, T�Dideal. It depends onlyon vBAT and vref.

– Generates a current, ictr, that when used in cells similar to theones used in the delay line, produces a delay proportional to1/vBAT and automatically corrects PVT variations.

The RC filter in Vlx0 and the integrator time constant define theline transient response of the control since, when the supplyvoltage (vBAT) changes, a new Dideal is obtained in this circuit withthe new duty cycle that maintains vout0¼vref. This contribution tothe duty cycle is obtained as the delay from the clock signal to thereset of the latch of Fig. 2. This contribution to the duty cycle istherefore continuous.

Fig. 3 shows how the duty-cycle contribution for the requiredaction during transients, d, is obtained: using a multiplexer, digitallycontrolled that adds or removes delays from the delay line ofthe DLL. The decision is taken based on the information of threecomparators (detailed in the next section):

– One comparator compares the sampled output voltage with thevalue of the previous clock cycle—provides the derivative of theoutput voltage.

– Two comparators, with 5 mV offset and opposite signs, create ahysteresis window of 10 mV centered in vref.

The d contribution to the duty cycle is discrete: the controlalgorithm adjusts the number of inverters included in the delay path.

Fig. 4 shows the Delay Locked Loop (DLL) generating a constantduty-cycle for different PVT parameter values in an AMS 0.35 μmimplementation. Each graph of Fig. 4 represents the evolution ofthe duty-cycle value of node Vlx0 of Fig. 2 (Dideal) for the simulatedPVT condition during the circuit startup. Fig. 4 shows that in half amicrosecond the value of Dideal is obtained.

Based on the information of these comparators, a non linearsliding mode control is implemented as described next: When theoutput voltage is above vref more than 5 mV and the derivative ispositive, d is reduced 1 step in the first occurrence and 3n�1 stepsin the following occurrence n. The d contribution to the duty cycleis reset to the original position at the exact cycle when thederivative changes sign.

Fig. 5 shows how the generation of DIRlosses is obtained. Since, inthis contribution for the duty-cycle, the delays required for aneffective control with the required accuracy need to be very small,a solution was used that consists of using PMOS transistors ascapacitances that are digitally turned on or turned off. The gates ofall transistors are connected to the capacitance node of the delayelement. When the digital control wants to connect the correspond-ing capacitance forces the supply voltage in the drain and source.The delay generator is controlled by two signals, one analogical(a current that depends on the supply voltage) and one digital (thatsets the number of capacitors). Since the current that limits each

Table 1Size of transistors of the two comparators with offset.

W [mm] Fingers L [mm]

Differential pairM0, M1 60 20 0.5

Differential pair switchesM4 0.4 1 0.35M2, M3 5.0 5 0.35

Latch switchesM18, M24 2 2 0.35

Latch resetM19–M22 0.4 1 0.35

Latch pre chargeM5. M14 1.2 1 0.35M6. M11 1.5 1 0.35

Back to back invM6, M7, M12, M13 0.4 1 0.35M9, M10, M15, M16 1.2 1 0.35

Clock bufferingpMOS 1.6 2 0.35nMOS 0.4 1 0.35

Output latchpMOS 1 1 0.35nMOS 0.4 1 0.35

Fig. 9. Monte Carlo simulation of the comparators with offset.

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delay stage is ictr, controlled by the DLL, this delay is proportional to1/vBAT which is the appropriate dependence as shown in Section 2.

The control of this contribution to the duty-cycle is madesynchronized with the correction required for transients (d). Foreach clock cycle that the control of d is acting in the DLL delay line,it also acts adding or removing capacitance to control the DIRlosses.However, when the control of d does a reset due to a derivativeinversion, the value accumulated in DIRlosses remains as is.

Summarizing: the two control variables, d and DIRlosses arecontrolled based on the error sign and the derivative. Each clockcycle with positive derivative and positive error d is exponentiallyincreased and in DIRlosses is incremented. When the derivative signchanges, d is reset but DIRlosses is kept.

The implementation of the digital controller follows the fash-ion, compute – decide – apply. Computation is performed ahead tocommit all the possibilities. Based on the present status, a decision

is made to choose which result is taken into account. After theselected result is applied, the first phase starts at turn off moment,the second phase at the sense moment, and the third previous tothe turn on moment.

4. High frequency comparators

The solution used to implement the derivative sensing of theoutput voltage is presented in Fig. 6. With both switches closed,the capacitor is charged with a voltage that corresponds to thedifference between the input voltage for this sample and thethreshold of the inverter. This sampling is performed only duringthe required time to charge the capacitor and then the switchesare turned off to preserve the capacitor voltage. After one period,only SW1 is closed and the capacitor voltage is the same as in the

Fig. 11. Line transient.

Fig. 10. Layout of the two comparators with offset.

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previous sample. Therefore, the output of the inverter reveals ifthis sample has a lower or higher voltage than the previous one.After sampling the output of the inverter S2 is closed again inorder to sample the input voltage for this new period.

Two comparators that create the required hysteresis windoware implemented based on the switched comparator proposed in[24] and presented in Fig. 7. This comparator was chosen given theacceptable power consumption while presenting high frequencycapability.

The switched comparator of Fig. 7 was analyzed searchingthe best way to implement offsets, since two comparator outputsare required with different offset values. The solution presented inFig. 8 proved to be the more robust after Monte Carlo analysis ofdifferent alternatives to implement the desired offset. The requiredoutput latches are omitted in Fig. 8.

With the dimensions presented in Table 1, implemented in UMC130 nm, the two comparators present a typical current consumptionof 20 μA when clocked at 20 MHz. Fig. 9 presents the Monte Carlo

Fig. 13. Load transient detail.

Fig. 12. Load transient.

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analysis. This analysis shows that the difference between the offsetvoltage of the two comparators presents a minimum value of 5 mVand a maximum value of 15 mV, which are acceptable values for thecontrol of the DC–DC.

Fig. 10 shows the layout of the two comparators with differentoffsets designed together. The latches were designed in the top, thedifferential pair in the middle and the clock buffers on the bottom ofthe cell. The total area is 0.0018 mm2. After the extraction of thelayout, Monte Carlo simulation showed an increase in the maximumoffset voltage of each comparator of 2 mV and an increase in thecurrent consumption from 26 μA to 41 μA for the worst corner.

5. Simulation results

The proposed control method was simulated using a model of aDC–DC converter with frequency of operation 20 MHz, an inductorof 80 nH with an ESR of 5.4 mΩ. The output capacitor has 10 μF anESR of 20 mΩ and an ESL of 0.22 nH.

Fig. 11 presents a line transient when the input voltage changesfrom 3 V to 4.2 V. In this line transient a significant change in theduty-cycle is noticed but the output voltage changes less than 20 mV.

Figs. 12 and 13 present a load transient when the outputcurrent changes from 100 mA to 1.1 A. Once again, very significantchange in the duty-cycle, in this case only during the transient, butwith limited impact on the output voltage. The load transient isvery fast: approximately half a microsecond.

Fig. 13 shows clearly the action of the proposed modular controlapproach: when the load transient occurs, the duty-cycle is increasedwith growing steps until the output voltage derivative changes and,when it does, the d contribution is removed but the increase inDIRlosses made during the transient remains and the figure shows thatthe estimated value for this contribution is correct since the duty-cycle achieves its final steady state value for this load.

6. Conclusions

The present work shows the advantages of splitting the duty-cyclecomponents of a DC–DC converter and of digitally controlling thedelays responsible for each part, with the appropriate accuracy andweight. This modular solution is tolerant to PVT variations and issuitable for the control of high frequency DC–DC converters. A DLL,with forced frequency and forced feedback voltage, generates a currentthat controls all the delays that contribute to the duty-cycle. With thisapproach the desired unitary delay proportionality to 1/vBAT isobtained. Different delay elements are used for the different contribu-tions for the duty-cycle. The transient compensation and the idealduty-cycle (Didealþd) are obtained with current starving invertersacting as delay cells. The higher resolution in the delay required by theDIrlosses is obtained by digitally adding or removing capacitors imple-mented by MOS transistors.

An optimized low power implementation of the high frequencyderivative signal detector is presented and the layout of thecomparators with offset is detailed and validated.

The proposed control method that splits the duty-cycle in threedifferent components was successfully used to obtain very fast lineand load transients.

Acknowledgment

The authors acknowledge the contribution of FCT—Fundação paraa Ciência e a Tecnologia, by supporting this work with a Fellowship

(Ref: SFRH/BD/62497/2009). This work was also partially funded byFCT through the project PTDC/EEA-ELC/113902/2009 and through theINESC-ID multiannual funding (PEst-OE/EEI/LA0021/2011).

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