High Performance Digital Fractional-N Frequency Synthesizers

IEEE Distinguished LectureSSCS, Dallas Chapter

Michael H. PerrottApril 2013

Copyright © 2013 by Michael H. PerrottAll rights reserved.

Why Are Digital Phase-Locked Loops Interesting?

PLLs are needed for a wide range of applications- Communication systems, digital processors, …

Performance is important- Phase noise/jitter is often a limiting factor

Standard analog PLL implementations present issues- Analog blocks pose design and verification challenges- The cost of implementation is becoming too high …

Can digital phase-locked loops offer excellent performance with a lower

cost of implementation?2

Just Enough PLL Background …

4

What is a Phase-Locked Loop (PLL)?

e(t) v(t) out(t)ref(t) Analog

Loop FilterPhase

Detect

VCO

ref(t)

out(t)

e(t) v(t)

ref(t)

out(t)

e(t) v(t)

de BellescizeOnde Electr, 1932

Voltage Controlled Oscillator (VCO) efficiently provides oscillating waveform with variable frequency

PLL synchronizes VCO frequency to input reference frequency through feedback- Key block is phase detector

Realized as digital gates that create pulsed signals

5

Integer-N Frequency Synthesizers

Use digital counter structure to divide VCO frequency- Constraint: must divide by integer values

Use PLL to synchronize reference and divider output

e(t) v(t) out(t)ref(t) Analog

Loop FilterPhase

Detect

VCO

ref(t)

div(t)

e(t) v(t)

Divider

N

Fout = N Fref

div(t) Sepe and JohnstonUS Patent (1968)

Output frequency is digitally controlled

6

e(t) v(t) out(t)ref(t) Analog

Loop FilterPhase

Detect

VCO

Divider

N[k]

Fout = M.F Fref

div(t)

Nsd[k] Σ−Δ

ModulatorM.F

ref(t)

div(t)

e(t) v(t)

Fractional-N Frequency Synthesizers

Dither divide value to achieve fractional divide values- PLL loop filter smooths the resulting variations

Very high frequency resolution is achieved

WellsUS Patent (1984)

RileyUS Patent (1989)

JSSC ‘93

Kingsford-SmithUS Patent (1974)

7

e(t) v(t) out(t)ref(t) Analog

Loop FilterPhase

Detect

VCO

Divider

N[k]

Fout = M.F Fref

div(t)

Nsd[k] Σ−Δ

ModulatorM.F

ref(t)

div(t)

e(t) v(t)

f

Σ−Δ Quantization Noise

The Issue of Quantization Noise

Limits PLL bandwidth Increases linearity requirements of

phase detector

Striving for a Better PLL Implementation

Analog Phase Detection

Pulse width is formed according to phase difference between two signals

Average of pulsed waveform is applied to VCO input

out(t)ref(t) Analog

Loop FilterPhase

Detect

VCO

Reg

D Q

ref(t)

div(t)

phase errorD Q

reset

1

1

ref(t)

error(t)

div(t)

error(t)

Dividerdiv(t)

9

Tradeoffs of Analog Approach

Benefit: average of pulsed output is a continuous, linear function of phase error

Issue: analog loop filter implementation is undesirable

ref(t)

div(t)

error(t)

Phase Detector

Characteristic

Phase Detector Signals

out(t)Analog

Loop FilterPhase

Detect

VCO

phase error

Av

era

ge

of

err

or(

t)

Divider

ref(t)

div(t)

10

Issues with Analog Loop Filter

Charge pump: output resistance, mismatch Filter caps: leakage current, large area

out(t)ref(t) Analog

Loop FilterPhase

Detect

VCO

error(t)Icp

VoutCharge

Pump

Cint

Divider

11

Going Digital …

Digital loop filter: compact area, insensitive to leakage Challenges:

- Time-to-Digital Converter (TDC)- Digitally-Controlled Oscillator (DCO)

Staszewski et. al.,TCAS II, Nov 2003

out(t)ref(t) Analog

Loop FilterPhase

Detect

VCO

Time

-to-

Digital

out(t)ref(t) Digital

Loop Filter

DCO

Divider

Divider

12

Basics- Time-to-Digital Converters (TDCs)- Digitally-Controlled Oscillators (DCOs)

Modeling- Transfer function modeling- Noise analysis

Improving the TDC- Background- Gated-Ring Oscillator (GRO) structure

A high performance digital PLL example- GRO TDC for low noise- Quantization noise cancellation- Low jitter divider design

Outline of Talk

13

Time

-to-

Digital

out(t)ref(t) Digital

Loop Filter

DCO

div(t)

Reg

D Q

Delay

Reg

D Q

Reg

D Q

Delay Delay

ref(t)

e[k]

Dividerdiv(t)

ref(t)

div(t)

e[k]

1

1

1

0

0

Delay

Classical Time-to-Digital Converter

Resolution set by a “Single Delay Chain” structure- Phase error is measured with delays and registers

Corresponds to a flash architecture 14

15

Modeling of TDC

Phase error converted to time error by scale factor: T/2 TDC introduces quantization error: tq[k] TDC gain set by average delay per step: tdel

Time

-to-

Digital

out(t)ref(t) Digital

Loop Filter

DCO

quantizationerror

phaseerror[k]

e[k]

Phase DetectorCharacteristic

time error

de

tec

tor

ou

tpu

t

T

2π

tq[k]

Dividerdiv(t)reference

period

T

TDCGain

1

Δtdel

Δtdel

1

Time

-to-

Digital

out(t)ref(t) Digital

Loop Filter

DCODividerdiv(t)

ref(t)

div(t)

e[k]

1

1

1

0

0

Phase Detector

Characteristic

phase error

de

tec

tor

ou

tpu

t

Delay varies due to mismatch

Impact of Limited Resolution and Delay Mismatch

Integer-N PLL- Limit cycles due to limited resolution (unless high ref noise)

Fractional-N PLL- Fractional spurs due to non-linearity from delay mismatch 16

17

Time

-to-

Digital

out(t)ref(t) Digital

Loop Filter

DCODividerdiv(t)

Va

rac

tor

Va

rac

tor

Analog

Control

DAC

A Straightforward Approach for Achieving a DCO

Use a DAC to control a conventional LC oscillator- Allows the use of an existing VCO within a digital PLL- Can be applied across a broad range of IC processes

Ferriss ISSCC 2007Hsu ISSCC 2008

18

A Much More Digital Implementation

Adjust frequency in an LC oscillator by switching in a variable number of small capacitors- Most effective for CMOS processes of 0.13u and below

Staszewski et. al.,TCAS II, Nov 2003

Time

-to-

Digital

out(t)ref(t) Digital

Loop Filter

DCODividerdiv(t)

Va

rac

tor

Va

rac

tor

Digital

Control

19

Leveraging Segmentation in Switched Capacitor DCO

Similar tradeoffs as segmented capacitor DAC structures- Binary array: efficient control, but may lack monotonicity- Unit element array: monotonic, but complex control

Coarse and fine control segmentation of DCO- Coarse control: active only during initial frequency tuning

Binary array provides efficient control implementation- Fine control: controlled by PLL feedback

Unit element array minimizes dynamic charge transfer

Vara

cto

r

Vara

cto

r

1x 2x 4x 2nx

1x 1x 1x 1x

Binary Array

Unit Element Array

CoarseControl

FineControl

20

Leveraging Dithering for Fine Control of DCO

Increase resolution by dithering of fine cap array Reduce noise from dithering by

- Using small unit caps in the fine cap array- Increasing the dithering frequency (defined as 1/Tc)

Assume 1/Tc = M/T (i.e. M times reference frequency)

Va

rac

tor

Va

rac

tor

CoarseControl

FineControl

InitialFrequency

Tuning

T

Divide-by-K

Tc=T/M

Digital Σ−Δ

Modulator

in[k] DigitalLoopFilter

ref(t)

out(t)

TDC outDCO

21

Hntf(z)z=ej2πfTc

TcM2πKv

s

s=j2πf

in[k]

qraw[k]

Φout(t)

q[k]

PhaseNoise

ff

QuantizationNoise

Noise Spectrum of a Switched Cap DCO

Phase noise- Same as for

conventional VCO (tank Q, etc.)

Quantization noise from dithering- Designed to be

lower than phase noise

Va

rac

tor

Va

rac

tor

Digital

Control

Modeling

23

f

Stq(ej2πfT)

TDC-referredNoise

e[k]T

2π

tq[k] TDCGain

1

Δtdel

Φref[k]

H(z)

LoopFilter

2πKv

s

Φn(t)

1

T

T

1

N

DT-CT

CT-DT

Φdiv[k]

Φout(t)

TDC DCO

Divider

SΦn(f)

-20 dB/dec

f

DCO-referredNoise

z=ej2πfT s=j2πf

Overall Digital PLL Model

TDC and DCO-referred noise influence overall phase noise according to associated transfer functions to output

Calculations involve both discrete and continuous time

24

Key Transfer Functions

TDC-referred noise

DCO-referred noise

e[k]T

2π

tq[k] TDCGain

1

Δtdel

Φref[k]

H(z)

LoopFilter

2πKv

s

Φn(t)

1

T

T

1

N

DT-CT

CT-DT

Φdiv[k]

Φout(t)

z=ej2πfT s=j2πf

25

Define open loop transfer function A(f) as:

Define closed loop parameterizing function G(f) as:

- Note: G(f) is a lowpass filter with DC gain = 1

Utilize G(f) as a Parameterizing Function

e[k]T

2π

tq[k] TDCGain

1

Δtdel

Φref[k]

H(z)

LoopFilter

2πKv

s

Φn(t)

1

T

T

1

N

DT-CT

CT-DT

Φdiv[k]

Φout(t)

z=ej2πfT s=j2πf

26

Transfer Function Parameterization Calculations

TDC-referred noise

DCO-referred noise

27

e[k]T

2π

tq[k] TDCGain

1

Δtdel

Φref[k]

H(z)

LoopFilter

2πKv

s

Φn(t)

1

T

T

1

N

DT-CT

CT-DT

Φdiv[k]

Φout(t)

z=ej2πfT s=j2πf

Key Observations

TDC-referred noiseLowpass with a DC

gain of 2N

Highpass with a highfrequency gain of 1

DCO-referred noise

How do we calculate the output phase noise?

28

fofo2πN G(f) 1-G(f)

SΦn(f)

-20 dB/dec

f

DCO-referredNoise

f

TDC-referredNoise

tq[k] Φn(t)

Φout(t)

Stq(ej2πfT)

f

dBc/Hz

fo

G(f)2πNT1 2

Stq(ej2πfT)

SΦn(f)G(f)1-

2

Phase Noise Calculation

TDC noise- Dominates PLL phase

noise at low frequency offsets

DCO noise- Dominates PLL phase

noise at high frequency offsets

29

fofo2πN G(f) 1-G(f)

SΦn(f)

-20 dB/dec

f

DCO-referredNoise

f

TDC-referredNoise

tq[k] Φn(t)

Φout(t)

f

dBc/Hz

Stq(ej2πfT)

f

dBc/Hz

fofo

Low PLL Bandwidth High PLL Bandwidth

DCONoise

TDCNoise

TDCNoise DCO

Noise

A Closer Look at the Influence of TDC Noise

PLL bandwidth dramatically influences relative impact of TDC and VCO noise

Want high PLL bandwidth?

Need lowTDC Noise

How Do We Improve TDC Performance?

Two Key Issues:• TDC resolution• Mismatch

31

div(t)

Reg

D Q

Delay

Reg

D Q

Reg

D Q

Delay Delay

ref(t)

e[k]

ref(t)

div(t)

e[k]

1

1

1

0

0

Delay

div(t)

Reg

D Q

Delay

Reg

D Q

Reg

D Q

Delay Delay

ref(t)e[k]

Delay2 Delay2 Delay2

div(t)

Delay

ref(t)

Delay2

e[k]

1

1

1

0

0

Vernier

Improve Resolution with Vernier Delay Technique

Effective resolution:

Delay-Delay2

32

div(t)

Reg

D Q

Delay

Reg

D Q

Reg

D Q

Delay Delay

ref(t)e[k]

Delay2 Delay2 Delay2

div(t)

Delay

ref(t)

Delay2

e[k]

1

1

1

0

0

Vernier

Issues with Vernier Approach

Mismatch issues are more severe than the single delay chain TDC- Reduced delay is formed as difference of two delays

Large measurement range requires large area- Initial PLL frequency acquisition may require a large range

Effective resolution:

Delay-Delay2

33

Vernier

div(t)

ref(t)

Coarsee[k]

Delay Delay Delay

Delay2 Delay2 Delay2

Delay Delay Delay

Reg

D Q

Reg

D Q

Reg

D Q

Reg

D Q

Reg

D Q

Reg

D Q

Logic

Mux

Finee[k]

Single Delay Chain

Delay

Delay - Delay2

Two-Step TDC Architecture Allows Area Reduction

Single delay chain provides coarse resolution

(Folded) Vernier provides fine resolution

Ramakrishnan, BalsaraVLSID ‘06

34

Single Delay Chain

div(t)

ref(t)

Coarsee[k]

Delay Delay DelayDelay Delay Delay

Reg

D Q

Reg

D Q

Reg

D Q

Reg

D Q

Reg

D Q

Reg

D Q

Logic

Mux

Finee[k]

Single Delay Chain

Delay

Delay

Time

Amplifier

Amplificationof Time

Two-Step TDC Using Time Amplification

Single delay chain provides coarse and fine resolution

Time amplification is used to improve resolution

Simplified view of: Lee, AbidiVLSI 2007

35

Leveraging Metastability to Create a Time Amplifier

Metastability leads to progressively slower output transitions as setup time on latch is encroached upon- Time difference at input is amplified at output

Simplified view of: Abas, et al., Electronic Letters, Nov 2002(note that actual implementation uses SR latch)

Time

AmplifierLatch

D Qin(t)

ref(t)

out(t)

ref(t)

in(t)

out(t)

ref(t)

in(t)

out(t)

ref(t)

Δtin Δtin

Δtout Δtout

in(t)out(t)

36

Interpolating time-to-digital converter

Interpolate between edges to achieve fine resolution Cyclic approach can also be used for large range

Start

Stop

Tq

Tin

11111

OutStop(t)

Start(t)DelayDelayDelay

Registers

Out

10

Henzler et al., ISSCC 2008

37

Ring OscillatorVdd

Counter

Register

Reset

Count[k]

e[k]

Osc(t)

e[k]

ref(t)

div(t)

Phase Error[1] Phase Error[2]

Logic

div(t)

ref(t)

Count[k]

3 3

An Oscillator-Based TDC

Output e[k] corresponds to the number of oscillator edges that occur during the measurement time window

Advantages- Extremely large range can be achieved with compact area- Quantization noise is scrambled across measurements

38

Ring OscillatorVdd

Counter

Register

Reset

Count[k]

e[k]

Osc(t)

e[k]

ref(t)

div(t)

Phase Error[1] Phase Error[2]

Logic

div(t)

ref(t)

Count[k]

3 3

Quant.Error[k]

q[1] q[3]

-q[0] -q[2]

A Closer Look at Quantization Noise Scrambling

Quantization error occurs at beginning and end of each measurement interval

As a rough approximation, assume error is uncorrelated between measurements- Averaging of measurements improves effective resolution

39

Deterministic quantizer error vs. scrambled error

Deterministic TDC do not provide inherent scrambling For oversampling benefit, TDC error must be scrambled! Some systems provide input scrambling ( fractional-N PLL),

while some others do not (integer-N PLL)

Proposed GRO TDC Structure

41

Ring Oscillator

Counter

Register

Reset

Count[k]

e[k]

Osc(t)

e[k]

ref(t)

div(t)

Phase Error[1] Phase Error[2]

Logic

div(t)

ref(t)

Count[k]

3 4

Quant.Error[k]

q[1] q[2]

-q[0] -q[1]

Enable

A Gated Ring Oscillator (GRO) TDC

Enable ring oscillator only during measurement intervals- Hold the state of the oscillator between measurements

Quantization error becomes first order noise shaped!- e[k] = Phase Error[k] + q[k] – q[k-1]- Averaging dramatically improves resolution!

42

Ring Oscillator

Register

Reset

Count[k]

e[k]

ref(t)

div(t)

Logic

Enable

Osc.Phases(t)

Count[k]

e[k] 11 10

Quant.Error[k]

q[1] q[2]

-q[1]

Phase Error[1] Phase Error[2]

div(t)

ref(t)

-q[0]

Counters

Improve Resolution By Using All Oscillator Phases

Raw resolution is set by inverter delay Effective resolution is dramatically improved by averaging

Helal, Straayer, Wei, Perrott VLSI 2007

43

GRO TDC Also Shapes Delay Mismatch

Barrel shifting occurs through delay elements across different measurements- Mismatch between delay elements is first order shaped!

Enable

Enable

Enable

Enable

Measurement 1

Measurement 2

Measurement 3

Measurement 4

44

Simple gated ring oscillator inverter-based core

Enabled Ring Oscillator Disabled Ring Oscillator

(a) (b)

Gate the oscillator by switchingthe inverter cores to the

power supply

Enable

Enable

Enable

VoiVoi-1

Delay Element

Vo4Vo1

Von

Vo2Vo3

Vo5

M4

M3

M2

M1

Von-1

45

GRO Prototype

GRO implemented as a custom 0.13 m CMOS IC

Straayer,Perrott

15 Stage Gated Ring Oscillator

enable(t)EnDis

Logic error[k]

enable

enable

S QR

46

enable

enable

15 Stage Gated Ring Oscillator

enable(t)

Logic

S QR

error[k]

VariableDelay

Measured GRO Results Confirm Noise Shaping

0.01 0.1 1 10 100-30

-20

-10

0

10

20

30

40

Frequency (MHz)

Am

plit

ude (

dB

)

Noise shapedquant. noise

Harmonics dueto nonlinearity of

variable delay

Input variabledelay signal

47

Measured deadzone behavior of inverter-based GRO

Deadzones were caused by errors in gating the oscillator GRO “injection locked” to an integer ratio of FS

Behavior occurred for almost all integer boundaries, and some fractional values as well

Noise shaping benefit was limited by this gating error

48

Next Generation GRO: Multi-path oscillator concept

Use multiple inputs for each delay element instead of one Allow each stage to optimally begin its transition based on

information from the entire GRO phase state Key design issue is to ensure primary mode of oscillation

Single InputSingle Output

Multiple InputsSingle Output

49

Multi-path inverter core

Lee, Kim, LeeJSSC 1997

Mohan, et. al., CICC 2005

50

Proposed multi-path gated ring oscillator

Oscillation frequency near 2GHz with 47 stages… Reduces effective delay per stage by a factor of 5-6! Represents a factor of 2-3 improvement compared to previous

multi-path oscillators

Hsu, Straayer, Perrott ISSCC 2008

51

A simple measurement approach…

2 counters per stage * 47 stages = 94 counters each at 2GHz Power consumption for these counters is unreasonable

Need a more efficient way to measure the multi-path GRO

N-Stage Gated Ring Oscillator

ResetStart

Stop

Logic

Register

Count[k]

e[k]

Counters

Enable

Helal, Straayer, Perrott VLSI 2007

52

Count Edges by Sampling Phase

Calculate phase from:- A single counter for coarse phase information (keeps track of

phase wrapping)- GRO phase state for fine count information

1 counter and N registers much more efficient

53

Proposed Multi-Path Measurement Structure

Multi-path structure leads to ambiguity in edge position Partition into 7 cells to avoid such ambiguity Requires 7 counters rather than 1, but power still OK

54

Prototype 0.13m CMOS multi-path GRO-TDC

Timing Generation

Out

Enable 47-stageGated Ring Oscillator

StateRegister

Start

Stop

Adder

Z1-47

MeasurementCells

Start

Stop

Enable

CLK

CLK

1 72 3 4 5 6

Two implemented versions:- 8-bit, 500Msps- 11-bit, 100Msps version

2-21mW power consumption depending on input duty cycle

Straayer et al., VLSI 2008

55

Measured noise-shaping of multi-path GRO

Data collected at 50Msps More than 20dB of noise-shaping benefit 80fsrms integrated error from 2kHz-1MHz Floor primarily limited by 1/f noise (up to 0.5-1MHz)

104 105 106 107

Frequency (Hz)

-100

-90

-80

-70

-60

-50

-40

Po

wer

Sp

ectr

al D

en

sit

y

(dB

ps

2/H

z)

65,536 pt. FFT(Hanning window + 20x averaging)

278.6

278.8

279.0

279.2TDC Output after 1MHz LPF

Filte

red

TD

C O

utp

ut

Time (µµs)

0 40 80 120 160 200

Noise of 80fsrms in 1MHz BW

Input of

1.2pspp

Ideal variance of

50-Msps quantizer

with 1ps steps

1.2ps

(a)(a) (b)

56

Measured deadzone behavior for multi-path GRO

Only deadzones for outputs that are multiples of 2N- 94, 188, 282, etc.- No deadzones for other even or odd integers, fractional output

Size of deadzone is reduced by 10x

The Issue of Quantization Noise Due to Divider Dithering

58

The Nature of the Quantization Noise Problem

PFD LoopFilter

N/N+1

Ref Out

M-bit 1-bit

Div

ΔΣ

Modulator

Fout

Noise

FrequencySelection

FrequencySelection

OutputSpectrum

QuantizationNoise Spectrum

PLL dynamicsΔΣ

Increasing PLL bandwidth increases impact of fractional-N noise- Cancellation offers a way out!

59

Previous Analog Quantization Noise Cancellation

Phase error due to ∆Σ is predicted by accumulating ∆Σ quantization error

Gain matching between PFD and D/A must be precise

Matching in analog domain limits performance

60

Proposed All-digital Quantization Noise Cancellation

Scale factor determined by simple digital correlation Analog non-idealities such as DC offset are completely

eliminated

Hsu, Straayer, PerrottISSCC 2008

61

Details of Proposed Quantization Noise Cancellation

Correlator out is accumulated and filtered to achieve scale factor- Settling time chosen to be around

10 us See analog version of this

technique in Swaminathan et.al., ISSCC 2007

62

Proposed Digital Wide BW Synthesizer

Gated-ring-oscillator (GRO) TDC achieves low in-band noise

All-digital quantization noise cancellation achieves low out-of-band noise

Design goals: - 3.6-GHz carrier, 500-kHz bandwidth- <-100dBc/Hz in-band, <-150 dBc/Hz at 20 MHz offset

63

Overall Synthesizer Architecture

Note: Detailed behavioral simulation model available at http://www.cppsim.com

64

Dual-Port LC VCO

Frequency tuning:- Use a small 1X varactor to minimize noise sensitivity- Use another 16X varactor to provide moderate range- Use a four-bit capacitor array to achieve 3.3-4.1 GHz range

65

Digitally-Controlled Oscillator with Passive DAC

Goals of 10-bit DAC- Monotonic- Minimal active circuitry and no transistor bias currents- Full-supply output range

1X varactor minimizes noise sensitivity

16X varactor provides moderate range

A four-bit capacitor array covers 3.3-4.1GHz

66

Operation of 10-bit Passive DAC (Step 1)

5-bit resistor ladder; 5-bit switch-capacitor array Step 1: Capacitors Charged

- Resistor ladder forms VL = M/32•VDD and VH = (M+1)/32•VDD, where M ranges from 0 to 31

- N unit capacitors charged to VH, and (32-N) unit capacitors charged to VL

67

Operation of 10-bit Passive DAC (Step 2)

Step 2: Disconnect Capacitors from Resistors, Then Connect Together- Achieves DAC output with first-order filtering- Bandwidth = 32• Cu/(2•Cload)•50MHz

Determined by capacitor ratio Easily changed by using different Cload

68

Dual-Path Loop Filter

Step 1: reset Step 2: frequency acquisition

- Vc(t) varies- Vf(t) is held at midpoint

Step 3: steady-state lock conditions- Vc(t) is frozen to take quantization noise away- ∆Σ quantization noise cancellation is enabled

69

Fine-Path Loop Filter

Equivalent to an analog lead-lag filter- Set zero (62.5kHz) and first pole (1.1MHz) digitally- Set second pole (3.1MHz) by capacitor ratio

First-order ∆Σ reduces in-band quantization noise

Delta-Sigma modulator dithers the divider value- Divider must support a range of divide values- Want to maintain low jitter as divide value changes

A Closer Look at the Frequency Divider

70

out(t)ref(t) DigitalLoop Filter

DCODivider

N[k]

div(t)

Nsd[k] Δ−ΣModulator

TDC

Divider input to output delay is a function of divide value- Adds significant jitter for dynamic divide value variation

The Issue of Divide Value Delay Variation

71

in(t)

div(t)

N[k]

Tdelay[k]

Tdelay

NTdelay[k-1]

ref(t) DigitalLoop Filter

DCODivider

N[k]

div(t)

Nsd[k] Δ−ΣModulator

TDC

We can realize a given divide value as the sum of lower divide values- Only pass select edges from higher frequency divider

Key Observation

72

in(t)

div(t)

Tdelay[k]Tdelay[k-1]

N1[k] N2[k]

N[k] = N1[k] + N2[k]

div_x2(t)

73

Application of Divider Concept to Digital PLL

Example: desired frequency division range is 64 to 127 Dithered by a third order Delta-Sigma modulator

74

Proposed Divider Structure

Increase division frequency by a factor of 4- Only pass one of four divider edges to GRO TDC

Divide value =N0+N1+N2+N3

75

Removal of Divide Value Delay Variation

Place ∆Σ dithered edge (N2) on edge not passed to GRO- Divide value (N3) is constant for edge that passes to GRO

76

Die Photo of Prototype

0.13-μm CMOS Active area: 0.95 mm2

Chip area: 1.96 mm2

VDD: 1.5V Current:

- 26mA (Core)- 7mA (VCO output

buffer at 1.1V)

GRO-TDC:- 2.3mA- 157X252 um2

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Power Distribution of Prototype IC

Notice GRO and digital quantization noise cancellation have only minor impact on power (and area)

21.0mW (46%)

7.7mW (17%)

Digital

GRO-TDC

Ref. Buffer

DACDivider

VCO Pad Buffer

VCO 6.8mW (15%)

3.4mW (7%)

3.0mW

2.8mW

(7%)

(6%)

1.4mW (3%)

Total Power: 46.1mW

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Measured Phase Noise at 3.67GHz

Suppresses quantization noise by more than 15 dB

Achieves 204 fs (0.27 degree) integrated noise (jitter)

Reference spur: -65dBc

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103

104

105

106

107

−180

−160

−140

−120

−100

−80

−60

−40dB

c/H

z

foffset

VCO NoiseFinepath ΣΔ Quantization NoiseFine−tune DAC ThermalCoarse−tune DAC ThermalDivider Noise (1% left)GRO NoiseRef NoiseClose−loop Noise

Calculation of Phase Noise Components

See wideband digital synthesizer tutorial available at http://www.cppsim.com

Conclusions

Digital Phase-Locked Loops look extremely promising for future applications- Very amenable to future CMOS processes- Excellent performance can be achieved

A low-noise, wide-bandwidth digital ∆Σ fractional-N frequency synthesizer is achieved with- High performance noise-shaping GRO TDC- Quantization noise cancellation in digital domain

Key result: < 250 fs integrated noise with 500 kHz bandwidth

Innovation of future digital PLLs will involve joint circuit/algorithm development

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