Introduction to programmable devices

History of programmable logic devices

Complex Programmable Logic Devices(CPLDs)

Design can run upto 200MHz

Xilinx devices

Spartan-3E Family overview

Spartan 6 family

Spartan 3e

I/O block

I/O capabilities

I/O capabilities

Input delay functions

I/O block

I/O block

Output DDR

Input DDR

BLOCKRAM

One block equals 18Kbits Supports dual port structure Four data paths

Port aspect ratios

BLOCKRAM Symbol

Modes of operation

Write first

Read first

No change

Introduction to programmable devicesHistory of programmable logic devicesSlide Number 3Complex Programmable Logic Devices (CPLDs)Slide Number 5Slide Number 6Xilinx devicesSpartan-3E Family overviewSpartan 6 familySlide Number 10Slide Number 11Slide Number 12Slide Number 13Slide Number 14Spartan 3e I/O blockI/O capabilitiesI/O capabilitiesInput delay functionsI/O blockI/O blockSlide Number 21Output DDRInput DDRBLOCKRAMPort aspect ratiosBLOCKRAM SymbolModes of operationWrite firstRead firstNo change