Digital System Design

Course Introduction

Maziar Goudarzi

Course Outline

• Course contents– Verilog HDL®– Design Methodology– Programmable Logic Devices

• Course timing– Will be put on the Courseware page

• Teaching Assistants– As announced

• Exercise classes– Sunday or Tuesday 12-13, Place: TBA

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Textbook and References

• Textbook– Samir Palnitkar, Verilog® HDL: A Guide to Digital Design and Synthesis,

Second Edition, Prentice Hall PTR, 2003.– Zoran Salcic, Asim Smailagic, Digital System Design and Prototyping Using

Field Programmable Logic and Hardware Description Languages, Kluwer Academic Publishers, 2002.

• Other references– Pong P. Chu, FPGA Prototyping by Verilog Examples, Wiley, 2008.– J. Bhaskar, Verilog HDL Synthesis: A Practical Primer, Star Galaxy Publishing,

1998.– Chan, Mourad, Digital Design Using Field Programmable Gate Arrays, Prentice

Hall PTR, 1994.– Verilog HDL, IEEE 1364-2005 Standard, IEEE Computer Society, Design

Automation Standards Committee, 2006.

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Evaluation

• 50% or more Assignments and Course Project

• 25% Midterm exam• 25% Final exam

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Digital System Design

Introduction to Hardware Description Languages

Digital System

• System• Digital vs. Analog

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Why HDL? Evolution of Logic Design

• Early days– 10s of logic gates

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Evolution of Logic Design (cont’d)

A decade later100s of logic gatesSchematic design

Another decade later1000s of logic gatesStructural Hardware Description Languages (HDL)

State of the art10,000s-1000,000s-10,000,000s logic gatesBehavioral and Register Transfer Level HDL

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Evolution of Logic Design (cont’d)HDL-based Design

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Why HDLs?

• SSI (Small Scale Integration)• MSI (Medium Scale Integration)• LSI (Large Scale Integration)• VLSI (Very Large Scale Integration)

• Important concepts– Simulation = check if design works fine– Synthesis = implement the design on real hardware

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HDL Requirements

• Concurrency• Timing and Delay• Event-driven• Design Hierarchy• Implementation independence• Readability (Documentation)

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Popular Levels of Abstraction

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Behavioral

Data flow

Structural

Switch

problem

Popular Levels of Abstraction (cont’d)

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Behavioral

Data flow

Structural

Switch

problem

Popular Levels of Abstraction (cont’d)

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Behavioral

Data flow

Structural

Switch

problem

Popular Levels of Abstraction (cont’d)

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Behavioral

Data flow

Structural

Switch

problem

HDL Examples

AHDLAltera HDL

CDL: Computer Description Language1965

ISPS: Instruction Set Processor Specification AHPL: A Hardware Programming Language Abel

Small designs such as state machines

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Verilog HDL Verifying Logic Phil Moorby from Gateway Design Automation in 1984 to

1987 (absorbed by Cadence) Verilog-XL Simulator from GDA in 1986 Synopsys synthesis tool in 1988 In 1990 became open language, OVI (Open Verilog

International) IEEE standard 1995 Similar to C Fairly efficient and easy to write

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VHDL VHSIC HDL: Very High Speed Integrated Circuit Hardware Description

Language DARPA workshop on VHSIC in 1981 DARPA released requirement in 1983 A language for hardware documentation VHDL 7.2 in 1985 IEEE standard in 1987 ANSI standard in 1988 For RTL design VITAL added,

VITAL(VHDL Initiative Towards ASIC Library) IEEE revised VHDL & VITAL in 1993 Final review of standard in 2001 Similar to Ada (emphasis on re-use and maintainability) Very general, but verbose

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Hello World! VHDL vs. Verilog

VHDL-------------------------------------------- Design Name : hello_world-----------------------------------------

entity hello_world isend; architecture hello_world of hello_world isbegin stimulus : process begin assert false report "Hello World By Deepak“ severity note; wait; end process stimulus;end hello_world;

Verilog//-----------------------------------------------------// This is my first Verilog Program// Design Name : hello_world// File Name : hello_world.v// Function : This program will print 'hello world‘// Coder : Deepak//-----------------------------------------------------

module hello_world ; initial begin $display ("Hello World by Deepak"); #10 $finish; end endmodule // End of Module hello_world

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VHDL vs. Verilog

• All abstraction levels• Designed for

documentation• Ada based constructs• High level & system

descriptor• No PLI

• All abstraction levels• Designed for hardware

design• C and Ada constructs• Gate & structural descriptor• Very powerful PLI

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VHDL vs. Verilog

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Behavioral

Dataflow

Structural& Gate

Switch

VHDLVerilog

VHDL vs. Verilog

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VHDL, More popular in Europe Verilog, In USA, Japan

Announcement

1. اولین دوره کشوری مسابقه طراحی سیستمهای دیجیتال– مسابقه دو به دو بین طرحهای سخت افزاری– مسابقه طراحی شتاب دهنده برای یک الگوریتم رمزگذاریhttp://fpgasoc.ir

2. FPT’2013 Design Contest– Design hardware for a Game– Designs compete against one another in a live contesthttp://lut.eee.u-ryukyu.ac.jp/dc13/

3. ModelSim Getting Started class– Next Sunday (time and place to be announced)– Software link will be provided– Bring your laptop if any

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