Chapter 9

Multibit Latches, Registers,Counters, and Memory

ECOM 4311Digital System Design using VHDL

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MULTIBIT LATCHES AND REGI STERS

• Two or more D latches with their clock inputs connected together form a multibit D latch or latch array.

• Two or more D flip-flops with their clock inputs connected together form a multibit register (or simply a register).

• The number of memory elements, or bits, in a multibit latch or register determines its width.

• 4, 8, 16, 32, and 64 bit widths are common in computing systems.

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A multibit D latch

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A multibit D latch

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A multibit D latch (continue…)

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An octal register

An octal register functionally

equivalent to a 74HC574

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An octal register (continue…)

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Shift Registers• Bits stored in a simple shift register are

shifted one bit position (right or left) at each triggering clock edge.

• The primary uses for shift registers are: o serial-to-parallel conversion, o parallel-to-serial conversion,o and synchronous delay.

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Shift Registers

• Each flip-flop in a shift register (and any logic associated with the flip-flop) is referred to as a stage.

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A 4-bit right shift register with synchronous clear using a buffer mode port

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Note: the order in which the flip-flop outputs are read and their values assigned does not matter.

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Shift Registers Using Variables• Another technique to allow reading the value

assigned to a port of mode out is to use a variable, rather than a signal. If a variable is used, the order of assignment to elements of the variable vector is critical, because each assignment takes effect immediately.

• Assignments for a right shift must first assign variable q(1) to q(0), then q(2) to

• q(1), q(3) to q(2), and finally si to q(3), as shown in Listing 9.2.3.

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Shift Registers Using Variables

entity shiftreg_rv isport (si, clr_bar, clk : in std_logic;qout : out std_logic_vector(3 downto 0));end shiftreg_rv;

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A 4-bit right shift register using a signal to “read” a mode out port

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Use of the Concatenation Operator to Shift

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SHIFT REGISTER COUNTERS• Using feedback, a shift register can be

configured to produce a characteristic sequence of states.

• Such a shift register functions like a counter with a characteristic count sequence and is often called a shift register counter.

• Two examples of shift register counters implemented by connecting their serial outputs back to their serial inputs:o Johnson countero ring counter

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Johnson Counter

The number of unique states a counter has is its modulus. The count (or state sequence) for a Johnson counter is 2 × n counts long (modulus 2 × n), where n is the number of stages in the shift register.

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a 4-bit Johnson counter

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Ring Counter

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4-bit Ring Counter

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COUNTERS• Counters are simple examples of finite state machines (FSMs).• The simplest counter has no inputs other than a clock and a

reset. The counter’s outputs are taken directly from its flip-flops. After reset, the counter changes state at each triggering clock edge.

• A 3-bit binary counter has a modulus of 8, or is, equivalently, a modulo-8 counter.

With n flip-flops we can create a counter with a modulus of up to 2n

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Synchronous Counters

• A synchronous counter is one in which all the flip-flops are clocked simultaneously by a common clock signal.

• Synchronous designs are easier to verify than asynchronous designs, particularly with respect to timing.

• In addition, most PLD architectures are not well suited to implementing asynchronous sequential systems.

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A 4-bit binary up counter using an integer signal.

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A 4-bit binary up counter using an integer signal. (continue…)

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A 4-bit binary counter using an unsigned signal.

Package NUMERIC_STD overloads the + operator so that it can be used to add an unsigned type to a natural type.

count_us <= count_us + "0001";

we do not have to check whether the count is at its maximum value to force it to 0 on the next count. An unsigned vector naturally rolls over to 0 on the next count after it has reached all 1s

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Counter Using a Variable

• Instead of using a signal to hold the count, we can use a variable.

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Down Counters

• Any of the previous binary counters can be changed to a down counter by replacing the + operator with the – operator.

• If the counter uses an integer to hold the count, then a check must be made to determine if the present count is 0. If so, then the next count must be equal to 2n – 1 (all 1s in binary).

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Up/Down Counters• A control input can be added to make an

up/down counter, which can count in either• direction.• For example, an up input could be added. When

a triggering clock edge is detected, the inner if would determine if up = '1'. If so, the counter is incremented. If not, the counter is decremented.

• Of course, we can easily create counters that count by values other than 1. Also, the amount an up/down counter increments can be different from the amount it decrements.

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Up/Down Counter with an Enable Input

• A count enable input can also be added to a counter, so the counter only counts at a triggering clock edge when it is enabled.

• If the counter is not enabled, its count remains the same at the triggering clock edge

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A 12-bit binary counter with count enable and synchronous reset

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A 12-bit binary counter with count enable and synchronous reset (cont….)

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Loading an Initial Value• Sometimes the initial state of a counter

needs to be a value other than 0. Another approach to providing an initial state, one that solves this problem, is to provide a load input.

• If such an input is synchronous, then, when it is asserted and a triggering clock edge occurs, instead of incrementing (or decrementing), a predefined value is loaded into the counter.

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Truncated Sequence Counters• A truncated sequence counter counts through

a sequence that is not a power of 2. • If at a triggering clock edge the present count

is the last count desired in the sequence, the counter is loaded with the starting (initial) count value, instead of being incremented to the next binary count.

• A truncated sequence down counter is often used as a programmable frequency divider

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Modulo m counter used for frequency division

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Modulo m counter used for frequency division

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BCD Counters• A two-digit (two-decade) BCD counter counts in

decimal, a two-digit BCD counter counts from 00 decimal to 99 decimal. On the next count, it rolls over to 00 decimal.

• The least significant four bits of the counter represent the least significant decimal digit (0 to 9) encoded in BCD.

• The most significant four bits represent the most significant decimal digit, encoded in BCD.

• Since a BCD digit ranges from 0000 to 1001 in binary, when the counter’s value is 00001001 (09 decimal), its value on the next count must change to 00010000 (10 decimal).

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Two-digit BCD counter.

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Two-digit BCD counter.

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Modulo-32 BCD Counter

• This two-digit BCD counter counts from 00 to 31 and then rolls over to 00. The count direction can be up or down.

• The counter has two count enable inputs; both must be asserted for the counter to count.

• Integer variables are used to store the count.

• The counter description is given in Listing 9.4.7. (next slide)

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Modulo-32 two-digit BCD counter.

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Finally….

Any Questions