Digital Systems II: IntroBeginnings

J. Schmalzel

R. Polikar

Digital Foundations

The basic model of a computer system:

CPU MEM

I/O

Central Processing Unit (CPU)

ControlsExecutesComputes (Fixed- and/or Floating-

Point)

Memory

Program storeData storageHigh-speedLow-speedVolatile, Non-volatile

RAM, ROM, FLASH (EEPROM)

FastSlow

Input/Output (I/O)

Communication between CPU and outside world

FastSlowStandardized (e.g., IEEE 802.11b)Parallel (IEEE 1184)Serial (USB

2.0)

Hierarchical View of EP and Digital Systems

CPU MEM

I/O

GatesBoolean Algebra

Design Techniques

MSI Functions

State Machines

Interface Method

Computer Architecture

Operating System

HLLs

Sequential Circuits Include feedback Presence of a clock Behavior is no longer simply a function of

the inputs--must be evaluated synchronously with clock

Flip-flops D-type J-K type etc.

CK

QD

D-F/F

Excitation Function: Dn = Qn+1

Q*

P

C

P C Dn Qn+1

1

0 1 X

1 1 1

1 0 X

1 1 0

0 0 X

1

0

Illegal0

Xilinx F/F’s

FDC: D-F/F w/ asynchronous clear

FDS: D-F/F w/ synchronous set

The FDS will not set upon activation of the set input without also activating clock

State Machines

Mealy: Outputs depend on states and on inputs.

Moore: Outputs depend only on states. One-Hot: A type of Moore machine in

which there is one F/F per state.

State Machine Models

(& One-Hot)

Inputs

State Memory

Combinatorial Network

Clk

Moore Outputs

Mealy Outputs

Sequential Circuit Design

Problem statement State diagram Transition table Simplified excitation functions Implementation Verification

Example

Design a sequence detector that will identify 1011.

SM1011 Z

State Diagram

Input

Input

Input/Output

Input/Output

Name

OutputName

Moore Mealy

One-Hot SMs

Moore machines are glitchless since outputs change only synchronously with clock.

For relatively small numbers of states, techniques of F/F minimization are largely counterproductive with available “sea-of-gates” FPGA. A 12-state SM: Don’t bother to reduce/encode. A 16-bit counter: Definitely encode states.

SM for 1011 Sequence DetectorReset

Found1

Found2

Found3

Found4

Z

Found

None

1

0

0

11

1

0

0

0

1

Note: Dashed lines show non-resetting algorithm.

Transition TableOutput Present State Input Next State

Z F0 F1 F2 F3 F4 X F0’ F1’ F2’ F3’ F4’ 0 1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0

Excitation FunctionsThe Transition Table could be large: 26 = 64, but since this is a One-Hot SM, there can be only one state active at a time. When writing the BA for each excitation function, listing the complemented states is redundant.

For example: DF0 = F0•X* + F2•X*, instead of

DF0 = F0•F1*•F2*•F3*•F4*•X* + F0*•F1*•F2•F3*•F4*• X*

Similarly,

DF1 = F0•X + F1•X + F4•X

DF2 = F1•X* + F3•X* + F4•X*

DF3 = F2•X

DF4 = F3•X

Simplification

If there are any redundant terms, can simplify; however, for One-Hot approach, there are no simplifications possible since must account for every separate state path.

ImplementationAssign one D-F/F per state and complete the combinatorial network required for each input. Implementation of F0 is shown:

Clk

&

&+ D Q F0

F0

F2

X*

X*

The final network output, Z = F4. For reset, use asynchronous F/F inputs: Preset F0 and clear F1-F4.

P

Verification

Check that the SM performs as required.

More complex input vectors are required since the internal state memory expands total possible states.

Use simulation tools.

The Power of One-Hot Design

Can skip transition table--“read” the implementation directly off the state diagram:

Found11

1

Found

None

Clk

&

&+ D Q F1

F0

F1

X

X C

Sequential Circuit Functions

Counters Binary, BCD Ripple, Synchronous

Registers and Latches PIPO, PISO, SIPO, SISO

In-Class Lab

Refer to EP Schematic 090-0016 What is the function of U5? Explain how it operates--what is the address

of LED3? How does it drive the LEDs? What currents are supplied (in or out) by

the 74HC259 to light up the LEDs?

In-Class Lab What is the function of U5? Addressable latch to control

annunciators.

Explain how it operates--what is the address of LED3? An I/O write to address (CS1+2) enables the D-F/F, Q2.

How does it drive the LEDs? A logic 1 output forward-biases the LEDs, turning them on. The current-limiting resistors prevent excessive forward current. Assuming Vf of the LED is approx. 1.7 V, the current through the diode would be about (4.3-1.7)V/470 = 5.5 mA (which is nearly one of the specified load currents!). When an output is a logic 0, the associated LED is zero biased, which won’t turn it on.

What currents are supplied (in or out) by the 74HC259 to light up the LEDs?

Digital v. Analog Electronics

Digital: Concerned with (usually) only two logic levels. Uses saturating logic circuits. For example, “1” = 5.0, “0” = 0.0

Analog: Concerned with potentially infinite number of values between two extremes. For example, 0.0 < V < 5.0.

In-Class Lab

ESD Principles Brief tour of Z-World Core Module Assembly notes Software notes Demo

ESD Principles

Minimize electrostatic charge generationNeutralize chargesDrain off chargesMinimize electrostatic fields and discharge effectsProtect ESD-sensitive devices during handling and

transport

Treat every device as if it were ESD sensitive!

Electrical Model of ESD Field Equipment

Probe

Snap (Wrist) Snap (Mat)1 M 1 M

Assembly Notes

Objective is to add headers and other components to add test points and features.

Good construction practices.Good soldering practices.

Introduction to Embedded Processors

Into the model of an embedded computer system:

CPU MEM

I/O

Introduction to Embedded Processors: User v. Developer User

Transparent product/performance Low-cost Excellent interaction design

Developer Meet schedule and budget (Reuse earlier S/W and

H/W--finish project w/o forgoing sleep) Meet marketing’s specifications Do it better than the last time

Digital Foundations: The Architecture of an EP

The basic model of a computer system:

CPU MEM

I/O

The Bus-Oriented EP

CPU MEMI/O

Add

Data

Con

Bus BasicsNeed to provide a shared medium that prevents contention. Use of these methods provides a way to provide bidirectional signal paths. Of course, does require arbitration.

Tri-State: “1” “0” and “High-Z”

Open-Collector (Drain): Passively pulled high (“1”) or actively pulled low (“0”)

A Y

E A E Y0 1 01 1 1X 0 Z

Example EP Feature List

Small footprint 25.8 MHz CPU 40 CMOS-compatible

parallel I/O lines Four CMOS-compatible

serial ports; max async rate of 806 kbps, max sync rate of 6.45 Mbps

8-bit data bus 13 address lines

Control signals (I/O read, write)

Master/slave config Reset input, output 5, 8-bit and 2, 10-bit

timers 256K flash EPROM,

512KB SRAM RTC Status, WDT outputs

Questions, Comments, Discussion