Digital-to-Analog and Analog-to-Digital Conversion
with Metal Oxide Memristors for Ultra-Low Power
Computing
Ligang Gao, Farnood Merrikh-Bayat, Fabien Alibart, Xinjie Guo, Brian D. Hoskins,
Kwang-Ting Cheng, and Dmitri B. Strukov
Department of Electrical and Computer Engineering
University of California Santa Barbara
Santa Barbara, CA 93106, USA
Abstract— The paper presents experimental demonstration of
6-bit digital-to-analog (DAC) and 4-bit analog-to-digital
conversion (ADC) operations implemented with a hybrid circuit
consisting of Pt/TiO2-x/Pt resistive switching devices (also known
as ReRAMs or memristors) and a Si operational amplifier (op-
amp). In particular, a binary-weighted implementation is
demonstrated for DAC, while ADC is implemented with a
Hopfield neural network circuit.
Keywords— ReRAM; memristor; Digital-to-analog conversion;
Analog-to-digital conversion; Hopfield neural network; hybrid
circuits
I. INTRODUCTION
Analog computing presents an attractive alternative for
data processing that demands extraordinary energy efficiency.
However, as pure analog circuits cannot address the noise
accumulation problem, a practical solution would require
inclusion of analog-to-digital and digital-to-analog stages for
signal restoration [1]. Highly energy-efficient data converters
are therefore expected to play an important role in future
computing platforms and thus new ways of implementing
compact and ultra-low-energy data converters are therefore of
significant relevance.
One promising technology particularly suited for analog
computing is the hybrid circuits which integrate CMOS and
memristor devices [2-5]. Memristors are essentially two-
terminal thin-film devices whose resistances can be tuned in a
nonvolatile and analog way [6-15]. In the context of analog
circuit applications, recent advances in memristive devices
and their integration with CMOS enable efficient
implementations of nanoscale analog-grade resistive elements
which can be fine-tuned after fabrication [16]. In this paper,
we demonstrate binary-weighted DAC and Hopfield-network
ADC circuits which utilize the feature of post-fabrication
resistance tuning for achieving energy-efficient conversion.
II. MEMRISTIVE DEVICES
Fig. 1 shows typical I-V characteristics of TiO2-x
memristive devices, which are obtained by a quasi-DC
-0.5 0.0 0.5 1.0 1.510
-7
10-6
10-5
10-4
10-3
Cu
rren
t (A
)
Voltage (V)
VTiO2
Pt
V
A
Pt
RESETSET
S
(a) (b)
Figure 1. (a) Typical I-V showing analog resistive switching
characteristics of Pt/TiO2-x/Pt memristive device. The inset
shows schematically device structure. (b) Wire-bonded
TiO2-x memristive device in a 40-pin package.
0
20
40
60
80
100
Wo
rkin
g d
evic
es (
%)
no protrusion 35 nm
200 nm
top electrode
bottom electrode
20 nm
50 nm
(a) (b)
Figure 2. (a) TEM images of 50-nm-thick titanium dioxide
devices with e-beam defined protrusion and (b) a yield
comparison between no protrusion and 35nm-long
protrusion devices.
triangular voltage sweep from 0 to 1.5V followed by a quasi-
DC triangular current sweep from 0 to -1mA. The device
structure and fabrication methods are similar to the ones
described in Ref. [16]. Additionally, nanoscale metallic
protrusion has been implemented in each device in order to
localize the switching region (Fig. 2a). This technique, while
not required for truly nanoscale devices, helps improve the
yield (from about 60% for the blanket film devices to 95%+
for devices with protrusion, as shown in Fig. 2b) and
significantly lower the variations in their switching behaviors.
III. BINARY-WEIGHTED DAC
Fig. 3 shows a schematic diagram of a 6-bit DAC
following a binary-weighted style. The circuit consists of 6
memristors and an op-amp with a negative feedback resistor
Rf. For a set of digital input voltages Vi (where i is from 0 to 5)
the analog output voltage Vout can be expressed as -Rf/R×∑i2-
iVi, when the i
th memristor is tuned to a state with a
conductance of 2-i/R. The circuit is implemented with a
discrete integrated circuit (IC) op-amp (ST TL074) and a
packaged memristor chip wired manually on a breadboard.
During the programming stage, memristors are set to the
desired states with high precision (~1% error) with the help of
automated feedback-based algorithm [16] using relatively
large programming voltages |V| > 0.5V whereas input voltage
is always limited to 0.2V during operation which has been
shown to cause negligible drift to the state in the considered
memristors [16]. The experimental results for a 6-bit DAC are
shown in Fig. 4, and its differential nonlinearity (< 0.11 LSB)
and integral nonlinearity (< 0.17 LSB) characteristics are
shown in Figs. 5a and b, respectively. Because of the quasi-
DC testing condition, the main contributing factor to the
nonlinearity is proven to be random telegraph noise [6, 17-20]
in the high resistance states (Fig. 6).
IV. HOPFIELD NETWORK ADC
A 4-bit ADC implemented with a Hopfield neural network is shown schematically in Fig. 7a [21]. It consists of four inverting amplifiers (neurons), each of which is made with
three IC op-amps (Fig. 7b), and a 46 memristor crossbar which defines the connectivity among neurons (and bias). The weights of recurrent part of the network, represented by the conductances of memristors which are listed in Fig. 8, are symmetrical with zero entries in the principal diagonal and Tij=2
(i+j) otherwise, whereas the weights which are serving bias the voltage VR are TjR =2
(2j-1). The analog input VS is supplied
2-1/R
2-2/R
2-3/R
2-4/R
2-5/R
20/R
-
Rf
Op-amp
Vout+
Digital Input
V5
V4
V3
V2
V1
V0
Figure 3. A schematics of 6-bit binary-weighted digital-to-
analog converter implemented with hybrid circuits.
Memristors are programmed to have conductances (at 0.2V)
40µS, 80µS, 160µS, 320µS, 640µS, and 1280µS. The
circuit utilizes op-amp (with the feedback resistor Rf =
3.3k) to form the weighted sum of all input pulses applied
to memristors.
0 10 20 30 40 50 600.0
0.3
0.6
0.9
1.2
1.5
1.8
0 1 2 3 4 5 60.00
0.09
0.18
experimental result
Am
plit
ud
e (
V)
Input code
Am
plit
ud
e (
V)
Input code
Figure 4. Measured transfer characteristics of a 6-bit DAC
as a function of input code. The voltage step (= 26mV) can
be seen clearly in the inset of the figure.
-0.1
0.0
0.1
0 10 20 30 40 50 60
-0.2
-0.1
0.0
0.1
0 10 20 30 40 50 60
DN
L [
LS
B]
INL
[L
SB
]
Input code
(a)
(b)
Figure 5. (a) The differential nonlinearity (DNL) and (b)
integral nonlinearity (INL) measured in least significant bits
(LSB) as a function of input code for a 6-bit DAC.
via fixed IC resistors of weight 2j [21]. In other words, each
neuron gets its input as a weighted sum of three different set of signals: reference bias VR, the analog input voltage VS, and four ADC circuit outputs, i.e. V1 through V4. Fig. 9a shows the measured output voltage for a quasi-DC sweep of input VS from 0 to 3.7V, while Fig. 9b shows the corresponding binary output code. In order to achieve a properly functional circuit, all neurons are reset periodically to ‘zero’, which helps avoid getting stuck in local minima. Additionally, non-ideal behaviors of neurons (most importantly the offset voltage in op-amps) are compensated by fine-tuning bias weights.
V. SUMMARY
We have experimentally demonstrated hybrid circuit implementation of DAC and ADC. The demonstrated work is a proof of concept for using memristors as high-precision weights in conversion circuits. At least for relatively low-precision (< 8 bit) data processing the considered approach could be very compact and energy efficient due to high density of analog weights implemented with memristive devices.
AKCNOWLEDGEMNT
This work is supported by AFOSR under MURI grant
FA9550-12-1-0038 and NSF grant CCF-1028336.
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0 200 400 600 800 1000
-4
-2
0
2
4 8 A @ 0.2V
Vari
atio
n (
%)
Time (s)
0 200 400 600 800 10000.0
0.1
0.2
0.3
0.4
256 A @ 0.2V
Va
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n (
%)
Figure 6. Variations in resistance measurements due to
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(a)
(b)
(c)
V1
V2
V3
VR
(Ref.)VS
(Input)
V4
T21 T31
T32 T42
T13 T23
T24 T34
T41
T12
T14
T43
T1RT1S
T2S
T3R
T4RT4S
T3S
T2R
1
2
3
4
:+
-
+
-
+
-
R1
R1 R2
R3NMOS
Figure 7. (a) Schematics of Hopfield neural network-based
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-0.2
-0.1
0.0
V1
-0.2
-0.1
0.0
V2
-0.2
-0.1
0.0
V3
0.0 0.2 0.4 0.6 0.8 1.0
-0.2
-0.1
0.0
V4
Time (s)
(a)
(b)
0.0 0.2 0.4 0.6 0.8 1.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Dig
ital C
ode
Voltage
(V
)
Time (s)
Digital output
Analog input
Digital output
Analog input
0000000100100011
0111011001010100
1000100110101011
1111111011011100
Figure 9 (a) Measured output voltage of the ADC circuit
and (b) the corresponding digital code as a result of an
application of analog input voltage ramp (shown with red in
panel b) which is varied from 0 to its maximum value. The
outputs of the neurons are periodically reset with a
frequency of 80Hz.
Feed-back
Conductance ([email protected])
Refer-ence
Conductance ([email protected])
T21 2e-5 T1R 4.75e-6
T31 4e-5 T2R 2.19e-5
T41 7.9e-5 T3R 9.33e-5
T12 2e-5 T4R 41.85e-5
T32 7.9e-5 Input Conductance (S)
T42 15e-5 T1S 8.33e-6
T13 4e-5 T2S 1.67e-5
T23 7.9e-5 T3S 3.33e-5
T43 30.9e-5 T4S 6.67e-5
T14 7.9e-5 Neuron Resistance (k)
T24 15e-5 R1 1
T34 30.9e-5 R2 100
R3 2
Figure 8 The conductance values of the memristors used in
the ADC circuit. Resistors R1, R2, and R3 are used in the
neuron circuit to ensure either a 0 or -0.2V output.