16-bit Segmented Type Current Steering DAC for Video Applications
Gaurav Raja† & Basabi Bhaumik‡ Department of Electrical Engineering,
Indian Institute of Technology, Delhi, INDIA.
Abstract In this paper, 16-bit, 50 MHz Current Steering DAC is designed. This DAC is implemented using TSMC 0.35 µm technology. An optimum segmentation is done of 16-bits into binary and thermometric bits. The integral non-linearity (INL) and differential non-linearity (DNL) is less than 0.3 LSB and 0.1 LSB respectively. It occupies only 0.06 mm2 area. The average total power consumption is 165 mW. A novel technique has been applied to reduce the glitch energy. The design is implemented with the matching requirements, required for current sources. Index Terms – Digital-to-Analog Conversion, Segmentation, Matching. 1. Introduction
Wireless and wired line communication systems, such as cellular base stations and cable modems, video signal processing, computer graphics, require high speed and high resolution digital-to-analog converters. Current steering DACs, in which an array of current sources are steered to the output resistive load directly depending on the digital input code, are commonly used for these high speed applications.
Thermometer architectures of current-steering DACs, have guaranteed monotonicity. Also, the matching requirement is significantly less, as 50% matching of the unit current source results in a DNL of under 0.5 LSB. Also, glitches do not contribute to non-linearity in thermometer case because the size of the glitch in thermometer-coded DACs is proportional to the number of switches that switch at a given sample time. But, the major drawback of thermometer architecture is that as the number of bits increases, the area increases significantly. On the other hand, in binary architecture, the output can change by substantially more than 1 LSB, causing a potentially substantial glitch, because during midcode transitions, the MSB source varies in one direction and
†Gaurav Raja is presently working with Intel India Pvt Ltd, Bangalore, India. (Email: [email protected]) ‡Basabi Bhaumik is a professor in Department of Electrical Engg, IIT Delhi, INDIA. (Email: [email protected])
the LSB sources vary in another direction. Also, the severity of the matching problem is determined by the weight of the bit. So, the matching of the MSB current source transistor must be extremely accurate. But, for high bit resolution, binary architecture requires significantly less area than thermometer architecture. So, there are many trade-offs between thermometer and binary architectures.
In this design, an optimum segmentation of bits is done into binary and thermometer type, to have the minimum area requirement, maintaining INL < 1.0 LSB, and DNL < 0.5 LSB. Also, the thermometer bits are split into two groups to reduce area requirement. In this design, the current source dimensions are designed taking all these process mismatches into consideration. Major problem associated with current steering architecture is that if the current required is large, then the dimension of switch, SW1 & SW2 [Fig. (1)] becomes so large, that a glitch of significant height occurs. In this design, a novel technique has been implemented to reduce this glitch height.
Fig. 1 : Current Steering Cell
Section II discusses about the optimum value
of segmentation for a segmented architecture. Section III deals with the current source mismatch variation with respect to yield. Section IV deals with the circuit architecture and obtained results. 2. Optimum Segmented Architecture for
minimum Area
The major issue in current steering segmented architecture is of optimum segmentation. For a given
INL and DNL requirement, Lin and Bult [2] have done the area analysis for 10-bits resolution. In this paper, an analysis for 16-bits resolution is done. This issue is analyzed via a MATLAB simulation. First an analysis is done for only binary coded and only thermometer coded DAC. If same analog area is taken for both the architecture, and if thermometer coded architecture gives DNL of σ, then binary weighted gives 2 N σ, where N is the total number of bits, and σ is standard deviation of current source value. Also, for this same area, both architectures give INL of 0.5* 2 N σ [2]. Since, area α (1/σ2), so a calculation is done for both the architectures, assuming that Aunit is the minimum area required by the thermometer architecture to obtain DNL = 0.5 LSB. The results are summarized in Table 1.
Table 1. Area requirements for specific INL/DNL
Notice that to achieve a given INL the analog area is the same for the two topologies, while to achieve a given DNL specification, the analog area for the binary-weighted device is 216 times as large as the thermometer-coded area. To have the optimized area required for 16-bit segmented DAC, a MATLAB simulation is done. For the thermometer -coded architecture, 2M individual current cells were created, each with one current source, while for the binary-weighted architecture, (16-M) current cells were created. The MSB current cell of binary architecture had 2(16-M) current sources, the next MSB had 2(16-M-1), and so on. The value of M is varied from 0 to 16, i.e. from total binary to total thermometer. Then simulations were run for different values of INL, and for DNL = 0.5 LSB to calculate the analog area required for 16-bit resolution segmented DAC, for every value of M from 0 to 16. A curve for digital area required is also plotted for 0 to 100% segmentation. Note that 0% segmentation corresponds to complete binary and 100% segmentation corresponds to complete thermometer architecture. A plot of “Area” versus “segmentation” for 16-bits resolution is shown in Fig 2. This plot allows us to determine the optimal degree of segmentation. In this plot, normalized term is used to represent Aunit as unity. Straight lines 1, 2, and 3 in the plot represent required area for INL = 0.5, 1.0 and 2.0 LSB, respectively, as
calculated in Table 1. Line 4 shows the required analog area variation for DNL = 0.5 LSB with segmentation. The two extremes of this line are in accordance with the calculated values of area requirement for binary and thermometer coded architecture, as shown in Table 1. Line 5 represents the digital area required. Here it is assumed that digital area required per current cell is approximately 0.35 times of required analog area for that current cell. This assumption is taken in accordance with the available Lin & Bult Plot for 10-bit resolution [2]. The bold curve, (line 6) in the plot represents the total required area variation with segmentation for INL = 1.0 LSB, and DNL = 0.5 LSB.
Fig. 2: Area required versus percentage of
segmentation for 16-bit DAC Any point on the straight portion of the line 6
can be taken for having minimum area required, but the corner point, A of this straight portion gives the maximum portion of thermometer type in the segmented architecture. Thus, optimal degree of segmentation occurs at the rightmost part of the horizontal line (point A) in the plot, which is still a minimum area (limited by INL requirements), meets the DNL specification, and has the smallest Total Harmonic Distortion. From the graph, this optimum value of the segmentation comes out to be 84 %, which in turn gives the optimum value of segmentation as 13-bits of thermometer type and 3-bits of binary type. 3. Current Source Mismatch Variation
with Yield To obtain an accurate estimation of the yield,
the Monte Carlo simulation is done with Matlab. Each
of the current sources is given a random value that has been derived from a gaussian distribution with mean value I and a standard deviation σI. For every digital code the output current of the D/A converter is calculated and compared to the ideal value. If the difference is larger than an LSB, even for only one digital code, the D/A converter is regarded as not functional and is therefore rejected. This procedure is repeated for every σI , for 100 times to obtain reliable results. The yield is given by the ratio of the number of functional D/A converters (INL < 1.0 LSB and DNL < 0.5 LSB) to the total number of try-outs. Fig 3 shows the yield variation with σI for 16-bit segmented resolution for 100 Monte Carlo runs. This curve shows that yield is 97 % for σI / I equal to 0.26 %. This value of σI / I is used in the calculation of W and L of current source transistor (discussed in section IV-B). Using this value of σI / I, INL and DNL plots have been plotted for 16-bit Resolution (13-bits Thermometer coded 3-bits Binary weighted) from 100 Matlab simulations, as shown in Fig 4 (a) and (b). From these curves, the maximum INL and maximum DNL comes out to be 0.8 LSB, and 0.03 LSB respectively, which satisfies the INL & DNL requirement.
Fig 4. (a) INL & (b) DNL Plots for σI / I = 0.26%
Fig 3. Yield variation with σI for 16-bit resolution (for 100 Monte Carlo simulations) 4. Circuit Architecture & Results A. Complete Architecture of 16-bit DAC
The complete circuit with all the blocks is shown in Fig 5. In this architecture, 13-bits of Thermometer coded have been splitted into two groups of 7-bits and 6-bits, to reduce the area. But this introduces a glitch when output jumps from 6-bit block to 7-bit block. Fig 6 shows the circuit of one unit current cell. It consists of an analog part and a digital part. The analog part consists of a differential switch and a cascoded current source. The digital part consists of a decoding logic and a latch. The decoding logic is equivalent to an AND–OR gate function and the latch is essential for timing synchronization, as all the current cells should switch at the same time.
Basic architecture of this Decoding Logic block is shown in Fig. 7(a). With this structure, there occurs one problem. When one column is completely selected, and one more cell is to be added in the output current, then requirement is that the value of all ROW should become ‘0’, and the value of next COL should become ‘1’, and these two actions should occur simultaneously, where ROW & COL are the outputs of row and column decoder. But if there is little bit delay, then a glitch will occur. In the modified structure, some delay is added to ROW and COL input, as compared to COL+1 input (next adjacent COL value). Also, COL is more delayed than ROW. This causes COL +1 to be ‘1’ earlier, which maintain the current status of the total current, and then ROW input goes to ‘0’, so that output
of (ROW ∩ COL) doesn’t give ‘1’, which removes the problem of glitch Fig 7(b). If the switches interrupt the current flow at any time point, then the current source charges the common source point of both the switches towards VDD. And then current source and cascoding transistor may enter into linear region, which may deteriorate the dynamic -performance considerable. Therefore the controlling signals must not cross in the middle of the supply voltage. So, the PMOS transistor size of both inverters (Inv_1 & Inv_3) should be larger than the NMOS transistors to decrease the rise time. Inverters (Inv_5 & Inv_6) are used between digital and analog part to change the analog value of logic ‘0’ at the input of switches, to increase the dynamic range of output voltage.
The critical transistor in the whole analog part is the current source transistor (MC). A little bit change in VT and β can cause a drastic change in the output current. So, VT and β mismatch effects have been taken into the consideration in the W & L calculation of current source (section IV-B). To increase the output impedance of the
current cell, the current source transistor is cascoded by the transistor MCD. B. Mismatch Analysis
As defined by Pelgrom, mismatch “is the process that causes time-independent random variations in the physical quantities of identically designed devices” [1]. Essentially, this means that each current source in the matrix generates a current that varies slightly from the desired current, IREF. Therefore the current sources have to be designed in such a way that random variations do not degrade the performance of the circuit below its desired specifications. Pelgrom’s paper has become the standard for analysis of transistor matching, and thus his formula for the standard deviation of saturation current for two identically sized devices was used for the design. This formula is:
,)()()(4)(
2
2
2
2
2
2
ββσσσ +
−=
ToGS
To
d
d
VVV
II
Fig 5. The complete circuit of 16-bit Current Steering DAC
(a) (b) Fig 8. Glitch problem in 384 µA current cell during transition
where,
WLA
WLAV VTo
To
2
2
222 )( and )( β
ββσσ ==
AVTo and Aβ are the technology dependent parameters. Note that here variation with spacing is neglected. The transistor current in saturation is given by:
2)(***21
TGSOXLSB VVL
WCI −= µ
So, using above mismatch and current equations, calculation for the W and L can be done. The expression derived from these equations can be written as:
)4)(*()(2
*
))(
4)(
()(*
2
222
2
2
4
2
2
2
2
2
T
T
VTGSI
LSB
OX
TGS
V
TGSIOX
LSB
AVVA
II
CL
VVA
VVA
IC
IW
+−=
−+
−=
β
β
σµ
σµ
Since the current of each cell of 7-bit block is of sufficiently high value, which requires a relatively large size of the switch, SW1 & SW2 to pass this large current. But due to overlap capacitance, there occurs a glitch, when any current cell is added. This is shown in Fig 8(a), which represents the output of one current cell, when it changes from off to on state. Fig 8(b) shows the zoomed view of this glitch. To reduce this glitch, a novel approach is used. We call this approach as Finger Approach. In this approach, the large dimension of switch is split into different small switches. The gate inputs of these switches are progressively delayed by an optimum delay (Fig 9). This reduces the height of the glitch, as shown in Fig 10(a), because it splits the big glitch into different small glitches (Fig 10(b)). So, effectively the total height of glitch is reduced. Finger approach definitely reduces the glitch height, but does not completely remove this glitch. So, at the output RC low pass filter is used, to further decrease the height of glitch.
The values of R and C decide the settling time of the output, after filtration. The corresponding output is shown in Fig 11(a), for 50 MHz clock frequency. Its zoomed view is shown in Fig 11(b). INL & DNL comes out to be within 0.3 and 0.1 LSB respectively. The average power dissipation comes out to be 165 mW.
Fig 11.(a) Simulation Result of Current Output (b) zoomed view, of 16-bit Current Steering DAC for decreasing input 5. Conclusion The designed digital-to-analog converter is of 16-bit resolution (13 bits thermometric & 3 bits binary), and is tested using cadence-spectre simulator at 50 MHz clock frequency. The INL & DNL comes out to be 0.3 LSB and 0.1 LSB respectively. The power supply voltage in this design is 3.3 V. This digital-to-analog converter is designed in 0.35 µm TSMC technology. If the 14-bit 20mW DAC in [6] is redesigned for 3.3V supply voltage and 0.35 µm technology and extended to 16bits, it will dissipate (4*(3.3/1.8)2*(0.35/0.18)2*20 mW = 1.02 W, whereas the DAC designed in this paper consumes only 165 mW power. The area involved in this 16-bit DAC is 0.06 mm2, which is very small. The reason behind this small area for 16-bit resolution is because of split of 13 thermometric bits into two groups of 7 bits and 6 bits. A novel approach of Finger concept is used to reduce glitch.
References [1] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G.
Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, pp. 1433–1440, Oct. 1989.
[2] Chi-Hung Lin and Klass Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2”, IEEE J. Solid-State Circuits, vol. 33, pp. 1948-58, Dec. 1998.
[3] Van Den Bosch, M. Steyaert, andW. Sansen, “An accurate statistical yield model for CMOS current-steering D/A converters,” Analog Integrated Circuits Signal Process., vol. 29, pp. 173–180, 2001.
[4] K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, “Characterization and modeling of mismatch in MOS transistors for precision analog design,” IEEE J. Solid-State Circuits, vol. SC-21, pp.1057–1066, June 1986.
[5] Bastos, A. M. Marques, M. S. I. Steyaert. W. Sansen,"A 12-Bit Intrinsic Accuracy High-speed CMOS DAC", IEEE JSSC, Vol. 33, No. 12, pp. 1959-1969, Dec. 1998.
[6] Mika P. Tiilikainen, “A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC”, IEEE JSSC, Vol. 36, No.7, July 2001.
A 1.2-V, 600-MS/s, 2.4-mW DAC for WLAN802.11 and 802.16 Wireless Transmitters
Nicola Ghittoril, Andrea Vignal, Piero Malcovati2 Stefano D'Amico3, Andrea Baschirotto3'Dept. of Electronics, 2Dept. of Electrical Engineering, University of Pavia, Pavia, Italy
3Dept. of Innovation Engineering, University of Lecce, Lecce, ItalyEmail: [nicola.ghittori,andrea.vigna,piero.malcovati] @unipv.it; [stefano.damico,andrea.baschirotto] @unile.it
Abstract- For the present and up-coming WLAN applications(802.11a/g, 802.11n, 802.16), a transmission baseband architec-ture uses a 600-MS/s current-steering DAC with a passive outputload to perform the baseband signal processing, avoiding the useof any active reconstruction filter. In a 0.13-tm CMOS technologythe DAC consumes 2.4 mW from a single 1.2-V supply voltage.The DAC exhibits a full-scale SFDR of 68 dB for an inputsignal frequency of 12 MHz and a full-scale dynamic range of9.7 bits between 0 and 10 MHz. These data correspond to thebest reported Figure of Merit, if compared with state-of-the-artdigital-to-analog converters.
I. INTRODUCTIONPresent baseband sections for telecom standards transmitters
consist of the cascade of a digital-to-analog converter (DAC)receiving the digital signal processor (DSP) bit-stream andan analog reconstruction (or smoothing) filter, which has tosuppress the DAC spectral images. A digital interpolator filteris required between the DSP (which typically operates atNyquist frequency) and the DAC to enhance the data-rate tothe desired value. This architecture is shown in Fig. 1. Thedesign of this baseband section has to optimize the trade-offbetween two possible approaches:
. a low DAC conversion frequency, which implies alow-power interpolator filter between the DSP and theDAC, but requires also a high-order, power-hungry analogreconstruction filter;
* a high DAC conversion frequency, which implies a digitalfilter with a high interpolation factor, but relaxes therequired performance of the analog smoothing filter.
This trade-off is presently optimized with a DAC data-rateabout 8-to-10 times the signal bandwidth and a 4th-to-6thorder analog reconstruction filter. For instance, in the caseof the WLAN standard (whose signal bandwidth is equal to10 MHz), the DAC data-rate is around one hundred MHz [1,2].Looking at future implementations, the above structure
will have to face several critical points due to the CMOStechnology scaling and to the improved standards under def-inition (802.16 and 802.11n, for instance). The technology
~~U : 9 ffi _ <t_ @, ~~~~sectionDSP N DAC 100 MHz Active 4th6th secio8-10bit filter orde
digital section baseband analog section
Fig. 1. Traditional baseband analog section for wireless transmitters
scaling will allow the use of higher-speed and lower-power(proportional to FSCV2D) digital part. On the other hand thesame trend implies analog sections with poorer performance,due to the limited linearity achievable with the available supplyvoltage (which can be 1.2 V or lower).As the new standards will present a larger signal bandwidth
(14 MHz for the upcoming WLAN 802.16 for instance), theuse of traditional TX baseband architectures will result ina more and more critical design of the analog filters, sincetheir cut-off frequency has to be increased (with an increasingsensitivity to the lower CMOS gain and to the non-dominantpoles). Moreover they have to guarantee the required dynamicrange and linearity at the lower supply voltage imposed bythe scaled technologies. These points would determine anincreasing power consumption of the analog filtering blocks.
Thus, maintaining the ratio between the conversion fre-quency and the signal bandwidth equal to about 10 wouldresult in a digital part underperforming its effective possibility,without exploiting the benefits of the reduced supply voltage,and in a power-consuming analog part introducing distortionand noise. As a consequence, the scheme of Fig. 1 will bevery disadvantageous if implemented with future technologiesand/or if used for future communication standards.
II. PROPOSED TRANSMITTER ANALOG BASEBAND CHANNEL
The considerations given in the previous section lead toa novel TX baseband channel design approach. The solutionproposed in this paper is shown in Fig. 2. In this case theinput bit-stream at Fc is interpolated to a kFc rate, with kequal to 30. This operation will require lower and lower powerconsumption in scaled technologies, and the circuit portabilitywill be immediate, due to its digital nature. On the other hand,this increase of the data-rate/signal-bandwidth ratio wouldrequire a lower smoothing filter order. In this way the systemis becoming more digital, as the general SoC trend is, sincethe analog filter simplification is exchanged with a digital partcomplication.The baseband section architecture of Fig. 2 consists of a
digital interpolator filter from 100 MHz to 600 MHz andan 8-bit DAC operating at 600 MHz. In this way the useof an analog active reconstruction filter is avoided, result-ing in a significant power consumption reduction. A singlepole filtering (provided by the DAC passive load), combinedwith the "sinc" attenuation inherently provided by the DAC,
1-4244-0303-4/06/$20.00 C2006 IEEE. 404
DSP *N -M * DAC 600 MHz _ 1 storderN 8 passive f lterdigta section baseband analog section
To RFIsection
Fig. 2. Proposed high-frequency baseband analog section for wirelesstransmitters
suitably suppresses the images around the multiples of aconversion frequency as high as 600 MHz. Considering forexample the signal bandwidth of 10 MHz and 14 MHz forWLAN 802.1 la/g and 802.16 respectively, a DAC output polefrequency set to 40 MHz gives a total attenuation of the firstsignal replica greater than 55 dB. This ensures that all the DACimages lie under the emission mask. Moreover the resultinglarge oversampling ratio determines an improvement in thelinearity performance due to the reduced amplitude of thetransitions between successive codes.The main drawback of this architecture may be the dis-
tributed noise due to the high operating frequency. Howeverthis is mitigated by three considerations: the low number ofoutput bits determines a very small interpolator section, thelarge OSR reduces the number of cells effectively switchingat 600 MHz, and the technology shielding reduces crosstalk.Moreover, differently than in the receiver, in the transmitter asignificant signal level is present, reducing the dynamic rangerequirements. The experimental results demonstrate that thisdistributed noise is not critical.
III. DAC ARCHITECTURE
Fig. 3 shows the architecture of the proposed DAC system,operating from the challenging 1.2 V supply voltage. A fullythermometric differential current-steering structure guaranteeshigh static and dynamic linearity performance. The low reso-lution implies a negligible area of the binary-to-thermometricdecoder. The unit cell, with a current of 5 [tA, is sized toreduce the effect of random mismatch. A relative standarddeviation in the current value equal to 0.7% ensures an INLyield of 99% with a 0.5LSB limit. The overall dimensions ofthe current sources matrix (0.05 mm2) are such that systematicerrors due to process variations do not affect the devicelinearity. The switches, which deviate the unit current towardsthe positive or negative output, are driven with low-swingsignals (from 300 mV to 800 mV) to limit the energy ofglitches. Their sizes are kept to minimum values to reducethe charge injection effects during the switching phase. Twodrivers, placed after the synchronization latches, are used togenerate the desired voltage levels. Each driver is biased witha current of 100 [A.The passive load converts the output currents into a voltage
signal and filters the signal replicas. In Fig. 3, a resistance Requal to 220 Q in parallel with a capacitance C of 17.5 pFimplements the required 40-MHz single pole transfer function.A common-mode feedback circuit, which acts on the two fixedPMOS current sources, adjusts the voltage of the commonnode A of the two impedances to 600 mV. The single-ended
DAC Output StageVDD
GND
ToRF1.section
Unit cell
Fig. 3. Architecture of the implemented DAC
voltage swing of 260 mVpp on each output node does not affectthe linearity of the DAC thanks to the high output impedanceof the current cells. This is achieved by the cascoding actionof the switches in the on state.
IV. EXPERIMENTAL RESULTS
The DAC system is realized in a standard 0.13-[tm CMOStechnology. The chip microphotograph is shown in Fig. 4. TheDAC consumes 2.4 mW from a single 1.2-V supply voltageand occupies 0.27 mm2. The 100-MHz to 600-MHz interpo-lator filter has been designed and it can be implemented bymeans of a 2-kgate block with two 10-stages FIR digital filtersto suppress the baseband images under the emission mask. Theinterpolator filter area is evaluated in about 0.2 mm2, whilethe estimated power consumption is 2.3 mW. The proposedsolution achieves an improvement of more than 50% in powerconsumption with respect to the typical solutions [3].
In the chip of Fig. 4 a dedicated digital part used forhigh-frequency testing has been included in the device, and itoccupies the largest amount of area (24 kgate). The crosstalkbetween the digital and the analog part is kept as low aspossible using a shielding triple well, separated power suppliesand multiple bonding wires to reduce parasitic inductances.The achieved performance immunity to the crosstalk demon-strates the robustness of the proposed structure with respect to
Fig. 4. Chip microphotograph
405
70-
68 -
66 -
64 -
62 -
> 60 -
m 58 -
D 56 -
54 -
52 -
50 -
48-0 5 10 15
Input signal frequency (MHz)20
Fig. 5. Measured HD3 vs input signal frequency, measured IMD3 vs centerfrequency of the two input tones
coupling disturbs.The proposed DAC operates with a conversion frequency of
600 MHz. For a full-scale (FS) single tone with a frequencyFin up to 20 MHz (which accounts also for the WLAN802.11n standard under development) Fig. 5 shows that thethird harmonic distortion (HD3) is higher than 59 dB over thewhole input frequency range. In the same Fig. 5, the measuredIMD3 performance, for two -6-dBFS input tones with AFequal to 1MHz and center frequency up to 20 MHz, is given.The integrated power spectral density (evaluated with a
static code at the DAC input) results in -57 dBm. Conse-quently, the FS dynamic range (DR) of the system, obtainedadding the contribution of the 8-bit quantization noise filteredby the DAC single pole, is equal to about 52.9 dB (8.5 bits).
Fig. 6 shows the output spectrum of a 9-MHz FS tone. Themeasured attenuation deriving from the DAC "sinc" filteringand the single pole filtering at the frequency of the first replicacorresponds to the one expected from design. Fig. 7 shows theoutput spectrum for an intermodulation test with the two tonescenter frequency set to 14.5 MHz. Fig. 8 shows the outputspectrum when one component of a WLAN 802.1 la signalis applied at the DAC input. As expected, the first replica ofthe signal around the conversion frequency remains under thelevel indicated by the standard emission mask.The performance summary is reported in Table I. A com-
parison with other recent published DACs can be made usingthe Figure of Merit reported in [4]:
VswingFOM = .Fin 10SFDR/20 (1)
where Vswing is the output differential peak-to-peak swingexpressed in V, P is the power consumption expressed in mW,Fin is the frequency in kHz at which the SFDR (expressed indB) is measured. Fig. 9 shows that, for signal frequenciesof 10 MHz and 14 MHz, which account for the WLAN802.1 la/g and 802.16 targets respectively, the proposed block
Inpu ton
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Fig. 7. Spectrum of two -6-dB FS tones at 13.6 MHz and 15.4 MHz
performs the baseband digital-to-analog processing with thehighest efficiency. Moreover it is the one operating with asupply voltage as low as 1.2 V, while guaranteeing the standardrequirements.
V. CONCLUSION
A DAC system to be embedded in WLAN 802.11 and802.16 transmitters is presented. The circuit exploits the over-sampling ratio to avoid the use of the analog reconstructionfilter following the DAC. The DAC is fabricated in a standard0.13-[tm CMOS technology and operates with a conversionfrequency of 600 MHz, consuming 2.4 mW from a 1.2 Vpower supply. The measured SFDR is greater than 59 dB foran input frequency up to 20 MHz, which accounts also fornext generation wireless protocols, as WLAN 802.11n and802.16. The IMD3 is higher than 50 dB in the same frequencyrange. The dynamic range in a band of 10-MHz is 60.6 dB,corresponding to an effective resolution of 9.7 bits. These datacorrespond to the highest efficiency baseband digital-to-analogconversion if compared with state-of-the-art DACs.
406
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=., | WLAN baseband signal
10 --- - --- --1 '- -- ------ -- --- -- --
20
30-- -:- :--:- :-:: :-: :- -WN---m-i-m-a
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5 *-this work
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15 18 5.5
knalog supply voltage [V]33
Fig. 8. Spectrum of a component of a WLAN 802.1la signal
This research has been partially supported by the ItalianNational Program FIRB, Contract n° RBNEOlF582.
REFERENCES
[1] S. Mehta et al., "An 802.11g WLAN SoC," ISSCC Dig. of Tech. Papers,pp. 94-95, February 2005.
[2] H. Darabi et al., "A Fully Integrated Soc for 802.1 lb in 0.18 rm CMOS,"ISSCC Dig. of Tech. Papers, pp. 96-97, February 2005.
[3] N. Ghittori et al., "A Low-Power, Low-Voltage (1lmW/8.4mW, 1.2V)DAC+Filter for Multistandard (WLAN/UMTS) Transmitters," VLSI Dig.of Tech. Papers, pp. 334-337, June 2005.
[4] D. Giotta et al., "Low-Power, 14-bit Current Steering DAC, forADSL2+/CO Applications in 0.13 Ftm CMOS," Proc. of ESSCIRC, pp.
163-166, September 2004.[5] Y Cong and R. L. Geiger, "A 1.5V 14b IOOMS/s Self-Calibrated DAC,"
ISSCC Dig. of Tech. Papers, pp. 128-129, February 2003.[6] M. Clara et al., "A 350MHz low-OSR AY Current-Steering DAC with
Active Termination in 0.13 Ftm CMOS," ISSCC Dig. of Tech. Papers, pp.
118-119, February 2005.
Fig. 9. Figure of Merit vs analog supply voltage for recently published DACs
TABLE II
PARAMETERS USED FOR THE EVALUATION OF FOM FOR RECENTLY PUBLISHED
DACS AND FOR THE IMPLEMENTED ONE.
P Vswing SFDR [dB] SFDR [dB][mW] I[V] @14MHz @10MHz
[7] K. O'Sullivan et al., "A 12b 32OMsample/s Current Steering CMOS D/AConverter in 0.44 mm2," IEEE Journal of Solid-State Circuits, pp. 1064-10722, July 2004.
[8] K. Doris et al., "A 12b 500MS/s DAC with >70dB SFDR up to 120MHzin 0.18 Ftm CMOS," ISSCC Dig. of Tech. Papers, pp. 116-117, February2005.
[9] W. Schofield et al., "A 16b 400MS/s DAC with <-8OdBc IMD to 300MHzand <-l6OdBm/Hz Noise Power Spectral Density," ISSCC Dig. of Tech.Papers, pp. 126-127, February 2003.
[10] J. Deveugele and M. Steyaert, "A 10b 250MS/s Binary-WeightedCurrent-Steering DAC," ISSCC Dig. of Tech. Papers, pp. 362-363, Febru-ary 2004.
[11] J. Hyde et al., "A 300-MS/s 14-bit Digital-to-Analog Converter in LogicCMOS," IEEE Journal of Solid-State Circuits, pp. 734-740, vol. 38, no.
5, May 2003.[12] Q. Huang et al., "A 200MS/s 14b 97mW DAC in 0.18km CMOS,"
ISSCC Dig. of Tech. Papers, pp. 364-365, February 2004.[13] T. Chen et al., "A 14-Bit 130-MHz CMOS Current-Steering DAC with
Adjustable INL," Proc. of ESSCIRC, pp. 167-170, September 2004.
407
-;
Go
-50
-60
-70
-80 L II
-1
4u [
A 1.8V 20mW 1mm² 14b 100MSample/s CMOS DAC
Mika TiilikainenNokia Mobile Phones, Helsinki, Finland
A binary weighted current steering DAC is a power-efficient architecture, because almost all the currenttaken from the supply is used for the output signal.Typically, the architecture suffers from poor linearitycharacteristics, but the problem can be prevented with anew calibration method, where the currents generatedfor the most-significant bits are fine-tuned. As a result, avery compact and low-power solution can beimplemented by using a low-voltage digital technology.
1. Introduction
The current steering DACs can be implemented byusing binary weighted and/or unweighted currentsources. At the moment, the focus has been on thesegmented structures, where a few least-significant bits(LSBs) have the binary weighting and the rest of the bitsare switched according to the thermometer code [1],[2].The unweighted currents give better linearity, becausethe matching requirement is set between the LSB and theunweighted bits. In other words, if the four LSBs areimplemented with binary weighted current sources, acurrent matching ratio of 1:25 must be guaranteed. For a14-bit binary weighted DAC a matching ratio of 1:214 isrequired. In practice, a ratio of 1:210 is implementablewith careful layout design and a reasonable current cellsize. The nature of the binary weighted DAC doesneither guarantee the monotonicity, as the unweightedstructures do.
Typically, the problems of nonlinearity are solved bytaking care of symptoms, but not of their causes. Forexample the digital input signal is manipulated to obtainthe correct output signal from the DAC. The correctionwords are stored into a memory and they are dynamicallymapped according to the input signal. On the other hand,the currents can be calibrated by adding extra currentsources in parallel with the DAC, but it increases thenumber of glitching elements in the circuit. In [3] atrimmable MOSFET is introduced, but the area of theanalog parts increases significantly, as in the worst casethe LSB-sized transistor has the same gate bias voltageas the MSB transistor. In addition, such biasing is notvery reliable, because in principle it requires a matchingratio of 1:214.
A new solution for the current source calibrationproblem is introduced in [4], where the drain current of aMOSFET can be fine-tuned with a low resolutioncalibration DAC without significantly increasing thecurrent consumption, area or circuit complexity. Themethod is considered more thoroughly in the nextsection.
2. DAC with the calibration
The topology of the DAC is represented in Fig. 1. Thecurrent source matrices are divided into three parts. Fourtrimmable most-significant bits (MSBs) are generated inthe first matrix, five middle bits in the middle matrix, andfive LSBs in the last matrix. Current scalers are neededto bias the matrices, and the main bias current of 256µAis supplied externally. That is a trade-off between a LSBcurrent of 0.5µA and a MSB current of 4096µA. Theoutput currents are driven to external 50Ω loads,resulting in a full-scale output voltage of 0.8Vpp.
A new method to compensate mismatching, interdieand temperature variations is introduced in [4]. The mainidea is that the effective channel width or thetransconductance of a current source transistor can beadjusted by driving a control current ICAL through theresistive element (MR) placed between the diode (MD)and the current source transistor (MN) in a current mirror,as shown in Fig. 2. The control current or the calibrationcurrent through the resistive element gives rise to avoltage difference between the gates. The voltagedifference is superimposed on the bias voltage given bythe diode transistor. An adjustment in the calibrationcurrent ICAL therefore slightly changes the drain currentof the current source transistor. The technique enables anaccurate trimming of the output current with an almostarbitrary precision.
MSBSOURCES
MIDSOURCES
LSBSOURCESSCALER1 SCALER2
SWITCHES SWITCHES SWITCHES
IB=256µA
IOUT-IOUT+
Figure 1. Block diagram of the DAC.
ICAL
ICALMN-1M1
MN
IOUT
VB
IB2IB1
MR
MD
Figure 2. Calibratable current source.
As the calibration is applied on the MSBs of theDAC, where the currents are in the range ofmilliamperes, MN cannot be biased with the same diodeas the other transistors, because the offset currentbetween the calibration current sink and the sourcewould disturb too much the bias condition, andconsequently the output current. The mismatch betweenthe bias currents is not an issue, if there is enough marginin the calibration range to compensate the difference.The channel width of the MN is purposely slightlysmaller than the channel widths of the other current cellsto guarantee that the calibration range covers all thenonidealities. In practise, the calibration is a linearoperation, because the average drain current of thecalibratable transistor is 128µA and the adjustment rangeis only a few microamperes.
3. Calibration procedure
A state machine is implemented to run the calibration.The procedure used here is the same as the bottom-upself-calibration scheme in [3], but the implementation isdifferent. In this case, only the four MSBs are calibratedand no additional reference currents are needed. Thetotal area is also reduced, because the sizes of the MSBtransistors can be smaller, as a matching ratio of 1:214 isnot needed. The use of deep-submicron technology doesnot reduce the area of the analog parts significantly,because the matching requirements do not shrink with thechannel length.
The simplified calibration circuit is presented in Fig.3. In practise, the simple pmos current mirror is a high-swing cascode current mirror. At first, the higher MSBcurrents are turned off, and the lowest trimmable MSBcurrent (MSB1) is compared to the LSB currents (LSB1-LSB10), including also an additional LSB current. Thecurrent steering calibration DAC generates thecalibration current ICAL for the MSB1 current source. Inphase A, the LSBs are mirrored to the currentcomparator and the MSB current sink is shorted to nodeP. The calibration current is swept from the highest valuetowards zero. The sweep is stopped, when thecomparator changes its state and the result is stored intoa register. In phase B, the currents are compared theother way around and the sweep starts from zero. Thechange in the direction of the sweep between the twophases is one way to maintain the symmetry in the
calibration process. The final calibration code is themean value of the two results.
In the next phase, the trimmed MSB1 is switched intothe LSB current set and the comparison with MSB2starts from phase A etc. If there is no mismatch, and 6-bitcalibration DACs are used, 256 clock cycles are neededto run the calibration.
The current comparator with a low input impedance[5] is used. The comparator is very simple and small;however, it sets the limit for the calibration speed.
The impedances of the current sources and thecomparator determine the voltage VP at the node P. Thusthe voltage slightly drifts during the calibration resultingin the Early effect. However, the error caused by theEarly effect is insignificant, as the current sources havehigh output impedances and the current comparator haslow input impedance. The main problem is the mismatchm introduced in the pmos current mirror, which results inan offset error in the current comparison. That can beprevented by running the calibration sweep twice, and bychanging the routing of the LSBs and MSB currents. Inboth phases, the VP is practically the same, whenLSBs=MSB. That also reduces the error caused by theEarly effect.
The previous considerations can be also presentedwith exact formulas. If the mismatch and the Early effectare described by coefficient εp for pmos current source,and the Early effect by εn for nmos current source, thecalibration equations for phases A and B are given by
( )( ) LSBSnBCBMSBpB
LSBSpACAMSBnA
III
III
εεεε
=+
=+ (1)
where ICA and ICB are the respective correction currentsresulted from the comparisons, and they have respectivecalibration codes CA and CB stored into the registers inthe state machine. IMSB represents the MSB current givenby the current source in Fig. 3, when ICAL=0.Respectively, ILSBS represents the LSB currents with theadditional LSB current. As the MN in Fig. 2 is a narrowertransistor than the M1-MN-1, IMSB<ILSBS is valid. In thiscase, the current comparator has no offset, but if therewas any, it could be also handled with the calibration.
LSBs MSB
CALDAC
A ABB
VSS
VDD
6
1:(1+m)
P∆I
CALLOGIC
ICAL
Figure 3. Calibration circuit.
As the calibration sweeps are practically linearoperations, the desired correction current IC is given bythe mean value of ICA and ICB
−
+= MSBLSBS
pB
nB
nA
pAC III 2
2
1
εε
εε
(2)
Because the Early effect can be ignored, εpA≈εpB=εp andεnA≈εnB=εn hold. In addition εn=1, because no mismatchis needed to be modelled for the nmos sources. Asεp=1+m is approximately equal to one, the followingequation holds
MSBLSBSCp
p IIIp
−≈⇒=+→
21
lim1 εε
ε (3)
The operation of the calibration is illustrated in Fig.4, where the mismatch m is a small positive number. Thedark lines describe the actual currents seen by thecomparator. As a result, the mean value of the codes CA
and CB corresponds to the required correction current IC
given by Eq. (3).
mismatch
← sweep A
code
I
CAmean(CA,CB)CB
ILSBS
IMSB
sweep B → mismatch
0
Figure 4. Principle of the two-phase calibration. Thedark lines represent the actual currents seen by the
current comparator.
4. Experimental results
A 14-bit DAC was implemented in a digital CMOSprocess and the full linearity was achieved with thecalibration. The layout of the DAC is presented in Fig. 5.The micrograph of the chip would be useless, becausethe deep-submicron process is equalized by covering thewhole chip with dummy metal plates. The 6-bitcalibration DACs are oversized and could be reducedsignificantly resulting in a smaller die area. As a result,the calibration increases the area of the DACapproximately 50%. It is not significant, because the areaof the DAC itself is relatively small for manyapplications. The floorplan is basically the same as usede.g. in [2], where the latches are isolated from the analogparts.
In this study, the main emphasis was on the staticlinearity problems of a binary weighted DAC. As shownin Fig. 6, the effective number of bits (ENOB) wouldhave been approximately ten without the calibration.After trimming, the nonlinearities were reduced to lessthan half a LSB, as can be seen in Fig. 7. The variations
in the curves show that there is no extra dynamics, as thecalibration is only applied on the four MSBs. Thelinearity curves could be suppressed more by trimmingalso the higher LSBs of the DAC.
The SFDR of 84dB can be achieved with 100kHzinput signal frequency and 100MSample/s update rate, asshown in Fig. 8.
The even-order distortion dominated themeasurements at higher signal frequencies, because itwas not compensated. The second- and third-orderharmonic distortions (HD2 and HD3) are presented inFig. 9. In general, the mismatch in the binary weightedcurrent sources causes only odd-order harmonics. Theeven-order harmonics results from the unbalance in adifferential structure. Therefore, an excellent staticlinearity does not guarantee a good dynamicperformance, which is dependent on glitches and timingerrors. However, by adding e.g. a simple track andattenuate circuit to the output of the DAC as in [1], theproblem of HD2 could be reduced significantly.Simultaneously, also a part of the HD3 should be slightlymore suppressed.
Figure 5. Layout of the DAC.
1 4096 8192 12288 16384
−4
−2
0
2
4
code
INL
[LS
B]
1 4096 8192 12288 16384−6
−4
−2
0
2
code
DN
L [L
SB
]
Figure 6. Static linearity without the calibration.
MSBLSB MID
SCALERS
CALDACS
LOGIC
CALMIRRORSSWITCHES
LATCHES
1 4096 8192 12288 16384−1
−0.5
0
0.5
1
code
INL
[LS
B]
1 4096 8192 12288 16384−1
−0.5
0
0.5
1
code
DN
L [L
SB
]
Figure 7. Static linearity with the calibration.
0.2 0.4 0.6 0.8 1−100
−80
−60
−40
−20
0
frequency [MHz]
ampl
itude
[dB
c]
fs=100MS/sfin=100kHz
SFDR=84dB
Figure 8. Output spectrum for the 100kHz inputsignal with the 100MS/s update rate resulting in
SFDR of 84dB.
0.1 1 10
50
55
60
65
70
75
80
85
90
output signal frequency [MHz]
HD
2, H
D3
[dB
c]
HD2
HD3
fs=100MS/s
Figure 9. SFDR for higher output frequencies isdominated by the HD2 (100MS/s update rate).
5. Conclusion
A 14-bit binary weighted current steering DAC wasimplemented in a digital process without using anyanalog options, and the full linearity was achieved withthe calibration. By using the binary weighted structure,the die area and current consumption can be significantlyreduced, as compared to the published segmented DACs,where unweighted parts require more analog and digitalcomponents. The measured DAC characteristics aresummarized in Table 1.
The use of a deep-submicron technology does notreduce the analog area of the DAC significantly, as thesize of the analog components cannot be shrunkappreciably because of the matching requirements. Thusthe results are valid also for technologies with largerminimum gate lengths.
The DAC has been designed in Nokia ResearchCenter. The author thanks Jari Patana, Tom Ahola andSami Kallioinen for their support during the project.
7. References
[1] A.R. Bugeja, B.-S. Song, "A Self-Trimming 14b100Msample/s CMOS DAC", ISSCC Dig. Tech. Paper,February 2000, pp. 44-45.
[2] J. Vandenbussche, et al., "A 14b 150Msample/s UpdateRate Q² Random Walk CMOS DAC", ISSCC Dig. Tech.Papers, February 1999, pp. 146-145.
[3] A. Tang, C. Toumazou, "Novel Self-Calibrated High-Speed D/A Converter using Trimmable Current Sources",Proceedings of ISCAS, June 1994, vol. 5, pp. 469-472.
[4] M. Tiilikainen, "A Novel High Precision AdjustmentMethod for the Transconductance of a MOSFET", CICC Dig.Tech. Papers, May 1999, pp. 525-528.
[5] H. Träff, "Novel approach to high speed CMOS currentcomparators", Electronics Letters, 1992, vol. 28, no. 3, pp.310-312, January 1992.
8- I
A 1 Ob, 400 MS/s Glitch-Free CMOS D/A Converter K. Khanoyan, F. Behbahani, and A.A.Abidi
Electrical Engineering Department University of California
Los Angeles, CA 90095-1 594
Introduction Recent reports on high-speed CMOS D/A Converters (DACs) demonstrate clock rates and effective bandwidths of the well-known current-steering DAC architecture of loo’s of MHz [l, 21. In this work, new circuit design and layout methods are applied to a glitch-free 10b DAC based on the pipelined charge redistribution architecture [3,4]. Transients in the output current as codes change are called glitches, and because glitch characteristics depend nonlinearly on codes, they result in spurious tones in the output frequency spectrum. In the glitch-free DAC, on the other hand, the analog voltages are sampled and held at each clock cycle. The 0.6-pm CMOS prototype described here clocks at up to 400 MS/s, and delivers a superior spurious-free dynamic range (SFDR) over the Nyquist band compared to other CMOS DACs. This circuit is part of digitally based agile frequency synthesizer for a fast-frequency hopping wireless transmitter, and is intended to drive on-chip capacitor loads.
The core of the DAC successively bisects charge in an array of equal unit capacitors (Figure l(a)) . Switches driven by a three-phase clock force charge to move from the LSB towards the MSB capacitors. Each data bit precharges the corresponding capacitor to one of two reference voltages, and in the next clock cycle the charge is bisected. The charge on the MSB capacitor constitutes the final converted value. An op amp at the end of the capacitor array converts this into a buffered voltage (Figure l (b) ) . Latches with appropriate pipeline delays supply data to the cells.
Design Considerations Overall DAC linearity is limited by mismatch in the unit capacitors, stray capacitance bypassing the series switch between cells, and slew-rate limited response of the op amp buffer [4]. The capacitors are implemented here as poly over gate oxide over n+ diffusion. Published match- ing data shows that the plate area of a 0.5 pF unit capaci- tor is large enough to guarantee 1Ob matching [ 5 ] . Matching of the MSB capacitors is most important. The MSB and MSB-1 capacitors are close together and not expected to suffer gradient-induced mismatch. Accuracy of charge bisection depends only on capacitor matching,
This research was supported by DARPA and an industrial consortium under the State of California MICRO program.
and is not affected by capacitor voltage-coefficient. When the switch connecting adjacent cells is OFF, charge leaks through the inter-wire stray capacitance across the switch. This error charge produces spurious tones in a synthesized sinewave, which get worse as the sinewave frequency rises. To lower this critical capacitance to about 0.2 fF, the switch FET is laid out with interconnect metal at diagonally opposite ends, and a farther separa- tion than normal between the metal contacts to the source and drain (Figure 2).
The RC settling time at each unit capacitor imposes an upper limit to the highest clock rate. The two series switches precharging each unit capacitor in an earlier prototype [3] are replaced here by a single switch con- trolled by an AND gate lying outside the analog signal path (Figure 3). This also eliminates an undesired inter- line capacitance, which injects stray charge into the cell. The settling time constant at each node is now 65 ps, which gives almost 10-12.t settling accuracy.
The DAC reference voltages (Vrefl, Vref2) are supplied off-chip. The O N resistance of the FET switch only lightly damps the resonant circuit comprising wirebond and leadframe inductance and DAC capacitors (Figure 4). The natural frequency is several times the clock fre- quency The resultant ringing in the DAC capacitor voltage produces errors as large as 5 LSBs at the end of precharge phase. After considering various ways to dampen the ringing, the solution adopted was to decouple the reference voltage pads to ground with a 0.5 nF on- chip capacitor. The capacitor occupies otherwise vacant area on the die. It guarantees that the reference voltage settles to an accuracy of better than 1 LSB at the end of the precharge phase. Furthermore, as inaccuracy in precharge of the MSB cells contributes proportionally larger DAC error, the voltage reference pads for the three MSBs are separated from the common reference pad supplying the remaining cells.
Clock skew must be considered when interfacing to the DAC input. The DAC operates on a three-phase clock, and receives inputs from an integrated ROM-based direct digital frequency synthesizer (DDFS) clocked by a single phase. If the pipeline registers use the same clock as the DDFS, a clock skew can result in the incorrect precharge on every 31d DAC cell (Figure 5(a)). Instead, the pipeline registers are clocked by the three phases of the DAC, such that the DDFS output is sampled on $2. Clock phases $1
73 4-93081 3-95-6199 1999 Symposium on VLSl Circuits Digest of Technical Papers
and $3 are assigned to the subsequent register stages in such a way that the precharge of each DAC cell can tolerate clock skews as large as the interval of one clock phase (Figure 5(b)). This scheme uses ten more flip-flops compared to a conventional implementation of the pipeline register [3].
A single cascode op amp with capacitor feedback (Figure 6(a)) acts as a charge-to-voltage buffer a t the output of the quasi-differential DAC. Long-channel PMOS pull-up FETs raise the buffer’s D C gain. This op amp settles faster than a gain-boosted cascode, and in this applica- tion linear, fast settling is paramount. To avoid slew-rate limiting, the input FETs are biased such that the linear range of the differential input, J2(VG,-Vt), encompasses the 0.5V ptp differential full-scale voltage swing at. the last DAC stage. A continuous-time common-mode feedback circuit is used because it settles faster than a SC circuit (Figure 6(b)). The simulated DC gain of the op amp is 50 dB. Voltage coefficient of the feedback capaci- tor, which transforms the final D/A converted charge to voltage, will contribute to the overall DAC INL. The op amp is reset to zero after each amplifying phase, which has important consequences for SFDR flatness versus frequency, as discussed below.
Experimental Results and Discussion The prototype consists of a 10b DAC, integrated with a DDFS and a very linear transconductance buffer to drive off-chip measuring instruments (Figure 7(a)). The DAC, pipeline registers, and multi-phase clock generation circuits together consume 1.2 mmz chip area, and dissi- pate 90 mW from 3.3V when clocked a t 300 MS/s. Of this, the op amp consumes 25 mW, logic circuits the rest. The area and power are comparable to a very compact 10b current-steering DAC [l] . Careful board layout with low inductance grounds was important in obtaining the reported performance (Figure 7(b)).
The DDFS and DAC can be clocked up to 400 MS/s. Sinewaves are synthesized from low frequencies up to Nyquist a t various sample rates, and the resulting worst- case SFDR is plotted versus normalized frequency (Figure 8(a)). At low clock rates with high oversampling, the SFDR is almost 63 dB dominated by the 3rd harmonic. The most likely cause is nonlinearity in the op amp feedback capacitor, which is specified with a voltage coefficient of 0.1 %/I! As the synthesized frequency approaches Nyquist, SFDR falls by only about 3 dB. It is noteworthy that at all sample rates the SFDR declines by only 3 dB over the Nyquist band. The most likely cause of decline in SFDR is the tiny fringing capacitance that remains between adjacent cells in the DAC core. As the op amp is reset to zero after every sample, as long as it settles fully its dynamics are the same whether a sinewave is synthesized at a low frequency o r a t Nyquist. Although the op amp is designed to settle to 77 a t 300 MS/s, the
portion of the settling transient arising from nonlinear transconductance becomes more significant in the waveform of the discrete sinewave (Figure 8(b)). Owing to this effect the SFDR a t all synthesized frequencies drops by about 8 dB when the clock rate is raised from 50 to 300 MS/s. Representative spectra show that only two spurious tones are important (Figure 9).
As DAC performance benefits directly from technology scaling, this circuit can only be fairly compared with others fabricated in a comparable CMOS technology The comparison circuits are a O.5pm CMOS version of a 10b current-steering DAC [ l ] (detailed SFDR data in [6]), and a 12b current-steering DAC also in O.5pm CMOS [2]. In both cases (Figure 10) this DAC outperforms the compari- son circuits a t high sinewave frequencies, significantly in the case of [2]. The SFDR of current-steered DACs falls steeply with synthesized frequency due to the increasing significance of code-dependent glitches, whereas in this glitch-free DAC the SFDR remains relatively flat. Both comparison current steered DACs are highly segmented, which accounts for the larger SFDR a t low frequencies compared to this non-segmented DAC. However, this feature is of little value in a wideband frequency synthe- sizer, where constant SFDR is desirable. This DAC overtakes the best comparison current-steered DAC in worst-case SFDR across the Nyquist band a t clock rates above 100 MS/s (Figure 11).
The current-steered DAC has been used for many years in high-speed applications. This work shows that the glitch- free CMOS DAC is superior in such uses as digitally synthesized sinewave generators, which have only recently become interesting as integrated components of wireless transceivers.
111 C.-H. Lin and K. Bult, “A lob, 250 MS/s CMOS DAC in lmm’,” in Int’l Solid-state Circuits Conf., San Francisco,
[2] A. Marques, J. Bastos, A. Van den Bosch, J. Vandenbussche, CA, pp. 214-215, 1998.
M. Steyaert, and W. Sansen, “A 12 b Accuracy 300 Msample/s Update Rate CMOS DAC,” in Int’l Solid-state Circuits Conf., San Francisco, CA, pp. 216-217, 1998.
[3] G. Chang, A. Rofougaran, M. K. Ku, A. A. Abidi, and H. Samueli, “A Low-Power CMOS Digitally Synthesized 0-13 MHz Agile Sinewave Generator,” in Int’l Solid State Circuits Conf., San Francisco, pp. 32-33, 1994.
[4] A. Rofougaran, G. Chang, J. J. Rael, J. Y.-C. Chang, M. Rofougaran, I? J. Chang, M. Djafari, M. K. Ku, E. Roth, A. A. Abidi, and H. Samueli, “A Single-Chip 900 MHz Spread- Spectrum Wireless Transceiver in 1-pm CMOS (Part I: Architecture and Transmitter Design),” IEEE J. of Solid- State Circuits, vol. 33, no. 4, pp. 515-534, 1998.
[5] M. J. McNutt, S. LeMarquis, and J. L. Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE I. of Solid-state Circuits, vol. 29, no. 5,
[6] C.-H. Lin, A 10b 500MSamples/s CMOS DAC in 0.6mm2, pp. 611-616, 1994.
PhD Thesis in Electrical Engineering. University of Califor- nia, Los Angeles: 1998.
1999 Symposium on VLSl Circuits Digest of Technical Papers 74
LSB Initializing Capacitor (a)
* * - MSB
(b) Figure 1. (a) Three adjacent unit cells at the LSB end of the DAC. (b) MSB end of the DAC, showing charge-to- voltage buffer.
Figure 2. Layout of switch FET to lower the stray capacitance across the OFF switch.
Previous design Faster design
vref'p i?
Figure 3. Improved switch and logic which lowers node capacitance, and removes a path of stray charge injection.
Vref
p,. D'Acap T"
I Off Chip On Chip
U 01 'I
Other half of differential circult
Figure 4. Ringing during precharge of DAC capacitors causes error. Large on-chip decoupling capacitor damps ringing.
Correct sampling Effect of skew
(a) mz I I I I T-' DAC cell precharges la unknown voltage Pipeline Register with
single-phase clack
I
DDFS Output Word
' \ \ l l I I I - f + + + '\\ I!, \ (1 $2
'\\ l
$1
Figure 5. (a) Illustrating the problem caused by clock skew when DAC samples DDFS output. (b) Skew tolerant clock scheme in pipeline register.
T Vcmfb
* CMFB
Figure 6. (a) Cascode op amp. (b) Common-mode feed- back circuit.
75 4-93081 3-95-6199 1999 Symposium on VLSl Circuits Digest of Technical Papers
Figure 7 . DAC layout and close up of test board. -110
70
60 m 2 e m
50
40 0.0 0.1 0.2 0.3 0.4 0.5
fsidfclk
(4
(b) Figure 8. (a) Measured SFDR vs. Normalized synthesized sinewave frequency (fsin) at various sample rates (fclk). (b) Non-exponential settling transient arising from nonlinear I-V characteristic of OTA.
70
65
m 60
* 55
50
45
40
a
0 25 50 75 100 125 Synthesized Freq, MHz
70
65
60
=- 55 2
50
45
40
m -U
cn
0 30 60 90 120 150 Synthesized Freq, MHz
Figure 10. Comparison of SFDR vs. synthesized sinewave frequency
Clock Rate, MS/s
Figure 11. Comparison of SFDR (worst-case over Nyquist band) versus sample rate.
76 1999 Symposium on VLSl Circuits Digest of Technical Papers
The presented 10-bit binary weighted current-steering DAC hasover 60dB SFDR at 250MS/s for signals from dc to Nyquist. Thechip draws 4mW from a dual 1.5/1.8V supply plus load currents.The active area is less than 0.35mm2 in a standard 1P-5M 0.18µm1.8V CMOS process. Both INL and DNL are below 0.1 LSB.
The degree of segmentation of a current-steering DAC has amajor influence on both the structure of the converter and on itsperformance. Segmented rather then binary weighted architec-tures are often used for improved DNL, glitch, and SFDR per-formance [1]. This however comes at a price. An increase in thenumber of unary decoded bits has an exponential influence onthe area and increases the complexity of the decoder. Thisincreases the power consumption and the required design time.The additional benefit of decoding one extra unary bit gets smallif the number of decoded bits is high. Even worse, as the digitalnoise increases and time skews get bigger in large decoders, thedynamic performance may drop. It is clear that a good segmen-tation choice is important. Yet this choice is often based on expe-rience rather than on founded decisions. We have carefully stud-ied this trade-off and pushed our design to a binary weightedstructure. The DAC has a highly regular structure, good dynam-ic performance and low power consumption.
In a segmented structure the DNL is often big at the boundariesof the unary and the binary decoded parts. In [2], the linearityproblem is solved by using calibration. It can be solved also if allcurrent sources are composites of the same unit cell. Thisremoves the systematic error typically caused by using differentstructures for the MSB and the LSB parts. Therefore the sourcearray consists of 1023 identical sources plus the current mirrorand dummies. The DNL specifications are met if one designs forthe correct INL yield (99.7% yield for INL < 0.5 LSB) [3]. Themeasured INL and DNL plots can be seen in Fig. 20.2.1.
For good dynamic performance, it is essential to use equal struc-tures whenever possible, and switching must be identical for allbig current sources. The chip presented here uses a pseudo-seg-mented structure with 6 pseudo-unary bits and 4 binary bits.Therefore the structure is identical to that of a 10-bit 6+4 seg-mented DAC. The inputs are, however, not decoded but bufferedlocally. The MSB consists of parallel connected pseudo-unarycells distributed over the switching core.
When it comes to dynamic performance, there are two main dif-ferences between a pseudo-segmented (binary) DAC and a seg-mented converter. The first is the lack of a decoder. Since thebuffering requires little power, less digital noise is injected intothe output. The second difference is that in a binary DAC a lot ofundesirable switching of sources occurs. For example, at majorcode transitions in a 10b DAC y = 0 to 511 extra switches areswitched on, while a similar number of switches are switched off.However, if the sum of the differential output currents IL an IR
remains constant during switching, then this switching is notseen at the output, and the performance of the binary DAC isthen equal to that of the unary DAC. The deviations from theideal must be minimized.
One way to state this problem is to say that the glitch energy hasto be minimized. Then the area of the positive deviations equals
the area of the negative deviations. Reducing the glitch energy tozero does not eliminate all spurious responses in the Nyquistband, but pushes most of the energy out of the band. Fast tran-sitions push the spurious outputs to even higher frequencies,further reducing the impact in the Nyquist band. In addition,fast switching can decrease the transition energy. The chargeinjected by the capacitive coupling of the digital signals to theoutput is independent of the switching speed, but the time ofunbalanced switching is reduced. Therefore we designed thisDAC for minimal glitch energy and as fast as possible switching.
The latch composed of transistors M1-M6 and inverters I1-I2 canbe seen in Fig. 20.2.2. Transistors M2-M5 and inverters I1-I2form a David-Goliath latch. It is fast and gives good control overthe glitch energy in all process corners. The latch has one pitfall.During switching, nodes 1 and 2 are shorted, as are nodes 3 and4. A large glitch occurs at these nodes if the logic values differedbefore switching. A buffer designed to drive the capacitances onnodes 2 and 3 has too small a capacitance, and extra capacitanceis added at nodes 1 and 4. This increases the power consumptiona little, but significantly improves the SFDR. It is essential thatall buffers are scaled identically. This ensures that the glitch atnodes 2 and 3 is signal independent. This is also important forsegmented structures in which each decoder stage has a differ-ent structure and capacitance, leading to code dependency.Adding a deglitch stage can have the same effect, but at an extracost, and the ratio of the capacitances must still be optimizedtheretoo. Note that many other latches have comparable criticalnodes.
Transistors M7-M8 set the voltages on nodes 5 and 6. The nodeabove the on switch is set by bias voltage Bias3 and the current.The influence of the output voltage is reduced by the gain of thecascode device. The node above the off switch is charged expo-nentially until the transistor on top of the switch enters sub-threshold. This charging is complete at the end of one clock peri-od at 250MS/s. The cascode thus shields the switches from theoutput voltage variation, and simplifies the design of the driver-switch-latch combination for low glitch energy.
All measurements are done at 250MS/s with 10mA load currentunless explicitly stated. Figure 20.2.3 shows the spectrum for a122.5MHz signal for which the SFDR is 62.3dB. Figure 20.2.4summarizes the spectral performance. The SFDR is over 60dBfor all measured frequencies. The DAC was also characterizedwith a load current of 5mA. For this condition, the SFDRdropped by less than 3dB over the Nyquist band. Figure 20.2.5shows a two tone test with sine waves at 100 and 102.5MHz. TheSFDR in a 17.5MHz wide band is 67.8dB. Figure 20.2.6 summa-rizes the specifications. Of the power, 2mW out of 4mW is usedby the clock buffering and buffering at the bondpaths. Figure20.2.7 shows a die photograph. The chip is bondpath limited, andthe active area is less than 0.35mm2. Due to the highly regularbinary structure, the drivers, switches and latches consume verylittle area.
Acknowledgments:We thank Robert Taft and Chris Menkus from National Semiconductor.This work has been sponsored and manufactured by NationalSemiconductor.
References:[1] C. H. Lin and K. Bult, “A 10-b, 500-MSamples/s CMOS DAC in0.6mm2,” IEEE J. Solid-State Circuits, vol. SC-33, no. 12, pp. 1948-1958,Dec 1998.[2] M. P. Tiilikainen, “A 14-bit 1.8-V 20 mW 1- mm2 CMOS DAC,” IEEE J.Solid-State Circuits, vol. SC-36, no. 7, pp. 1144-1148, Jul 2001.[3] M. Borremans, A. V. D. Bosch, M. Steyaert, and W. Sansen, “A LowPower 10-bit CMOS D/A Converter for High Speed Applications,” IEEECICC Digest, pp. 265-268, May 2000.
Figure 20.2.7: Chip photograph. The die is bondpath limited.
320 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006
A 10-bit 250-MS/s Binary-WeightedCurrent-Steering DAC
Jurgen Deveugele, Member, IEEE, and Michiel S. J. Steyaert, Fellow, IEEE
Abstract—This paper studies the impact of segmentation on cur-rent-steering digital-to-analog converters (DACs). Segmentationmay be used to improve the dynamic behavior of the converterbut comes at a cost. A method for reducing the segmentationdegree is given. The presented chip, a 10-bit binary-weightedcurrent-steering DAC, has 60 dB SFDR at 250 MS/s from DCto Nyquist. At 62.5 MHz signal frequency and 250 MS/s, weoperated the device in 9-bit unary, 1-bit binary-weighted mode.The obtained 60 dB SFDR in this measurement demonstratesthat the binary nature of the converter did not limit the SFDR.The chip draws 4 mW from a dual 1.5 V/1.8 V supply plus loadcurrents. The active area is less than 0.35 mm2 in a standard1P-5M 0.18- m 1.8-V CMOS process. Both INL and DNL arebelow 0.1 LSB.
Index Terms—Binary weighted, digital-to-analog converters,low power.
I. INTRODUCTION
CURRENT-STEERING digital-to-analog converters(DACs) are well suited to generate broadband signals for
single-hop transmitters. They are fast and able to offer highspurious-free dynamic range (SFDR) up till high frequencies.This high level of performance can be achieved since nointernal nodes with large capacitances must be charged or dis-charged. It has been shown that segmentation, that is, weightingthe MSB current-sources unary and the LSB current-sourcesbinary, is important for dynamic performance. In [1] and [2],for example, two similar structures are used for the DAC. Themain difference between both is that the converter in [1] uses5-bit unary plus 5-bit binary-weighted segmentation, while [2]uses full binary-weighted decoding. The segmented converterachieves 10-bit dynamic accuracy up to the Nyquist frequencyfor a sample rate of 1 GS/s. The binary-weighted converter,however, achieves 10-bit dynamic accuracy up to the Nyquistfrequency for only a sample rate of 30 MS/s. However, highdegrees of segmentation do come at a price. Segmentation addsto the power consumption, complexity and size of the converter.Too much segmentation can worsen the performance ratherthan improve it; the big dynamic core deteriorates timing andincreases the digital noise. The correct timing of a converterwith a big dynamic core can become challenging as the dis-tances between the various segments is increased and the largeportion of logic adds more load to the clock line. Therefore,making the assumption that increasing segmentation is the best
Manuscript received December 16, 2004; revised August 19, 2005. This workwas supported and manufactured by National Semiconductor.
The authors are with ESAT-MICAS, Katholieke Universiteit Leuven, 3000Leuven, Belgium (e-mail: [email protected]).
Digital Object Identifier 10.1109/JSSC.2005.862342
way to boost dynamic performance [3] may ignore better waysof dealing with dynamic nonlinearities.
Reducing the segmentation degree may thus be advantageousfor the overall performance of the converter. Although somepapers discuss the importance of segmentation [3], it is stillpoorly understood. Rather than assuming that extra segmenta-tion improves the performance, we tried to separate the effectscaused by segmentation from the effects caused by other mech-anisms. Soon we realized that very few mechanisms for gen-erating spurious signals are strongly related to the segmenta-tion. Addressing these mechanisms could thus yield a binary-weighted DAC with high SFDR at high signal and clock fre-quencies. So, we designed a binary-weighted converter ratherthan a segmented one. We see that the binary-weighted con-verter is still less tolerant to poor design than the segmentedone, so we chose, for simplicity, to use generous margins on allparameters.
II. STATIC PERFORMANCE
An -bit binary-weighted converter has only currentsources with sizes ranging from one times the LSB currentto 2 times the LSB current. This can lead to large linearityerrors at the major code transitions. It is important to limit thelinearity errors at these major code transitions, otherwise theycan reduce the obtained SFDR. Therefore, we take a closerlook at this. Our design specifications are as follows:
• INL LSB• DNL LSB.A DNL smaller than 1 LSB ensures that the converter is
monotonic: every increase of the digital input code leads to anincrease of the analog output value. The DNL is always smallerthan 1 LSB if the INL is smaller than 0.5 LSB. An INL smallerthan 0.5 LSB guarantees that the maximum linearity error issmaller than the maximum quantization error. We thus designfor an INL smaller than 0.5 LSB, a common specificationfor DACs. Via Monte Carlo simulations, we obtain the plotof Fig. 1, which shows the yield in function of the standarddeviation for both unary and binary decoding. We aim for ayield, meaning that 99.7% of the converters must have an INLsmaller than 0.5 LSB. For a yield, the required area is com-parable in both cases. Simulations show that the expected DNLis higher for a binary-weighted converter than for a segmentedone. However, our simulations and calculations indicate thatthis does not pose a problem for reaching 10-bit accuracy aslong as we meet the mentioned INL and DNL specifications.
Fig. 1 is only correct if all basic current sources have the samephysical dimensions. In many segmented converters this is not
DEVEUGELE AND STEYAERT: A 10-bit 250-MS/s BINARY-WEIGHTED CURRENT-STEERING DAC 321
Fig. 1. Yield as a function of the standard deviation on the current sourcesfor both unary and binary-weighted converters.
the case. The use of different basic types of current-source tran-sistors, e.g., transistors with widths equal to 1 m and transistorswith widths equal to 16 m, often leads to systematic errors andhence reduces static performance. We will take a look at the dif-ferent options for the current-source array.
A. Unary-Weighted Current Sources
An -bit converter can generate 2 1 different outputcodes. In a pure unary implementation of the current-sourcearray, 2 1 equal current sources are used. Only identicalcurrent sources are used, as one transistor with double thewidth will behave slightly differently than two transistors inparallel. The segmentation level of the current-source arraycan be shielded from the segmentation level of the decoder byputting the correct number of unary-weighted current sourcesin parallel, as is explained below.
B. Split Structures for MSB and LSB Current Sources
The current-source array of a 10-bit converter needs 1023basic current sources in a pure unary implementation. Thisamount of current sources requires more area and interconnectsthan an implementation with fewer individual current sources.Therefore, many designers use two different structures forthe MSB and LSB parts. This adds an additional matchingrequirement between the biasing currents. Also, care must betaken to cancel out the differences in systematic errors betweenthe two structures, to avoid further matching errors.
C. Division of the Current of One MSB Current Source inLSB Currents
In this case, the current-source array consists of MSB unitsonly. The current of one unit is further split into smaller cur-rents. This guarantees that the total current of all LSB sourcesmatches well to the rest of the structure, as in [4]. The transis-tors that split this MSB current have relatively relaxed matchingspecifications. They require extra voltage to maintain adequateheadroom, so this technique is less suited for low-voltage de-sign.
Fig. 2. One quarter of the switching scheme used. Current sources withnumbers 1 to 15 are used for the pseudo-segments. Current sources withnumber 0 are used for the LSB part. The scheme is tolerant to gradient errorsand reduces the impact of the edges of the current-source array.
D. Implementation of the Current-Source Array
We opted for unary-weighted basic current sources. Thesebasic current sources are connected in parallel to weight thembinary. There is no distinction between MSB and LSB basicsources, eliminating this systematic error. The large number ofbasic sources is used to reduce the gradient errors [5]. It is alsoused to reduce the influence of the errors on the current sourcesclose to the edge of the array [6]. Dummies around the current-source array further reduce the linearity degradation caused bythe edges.
One quarter of the switching sequence is shown in Fig. 2. Ourconverter is binary-weighted, but we design it as if it were a 4-bitunary, 6-bit binary segmented converter. Then we replace the4-bit thermometer decoder by a binary-weighted decoder. Wecall this approach “pseudo-segmentation.” The pseudo-segmen-tation is reflected in the switching scheme. The current sourceswith numbers 1 to 15 form the 15 pseudo-unary current sources.The current sources with number 0 are used to form the LSB cur-rent sources. This pseudo-segmentation is mainly used for thedynamic behavior and will be discussed later.
The measurements of our binary-weighted DAC show that thecurrent-source array has good static linearity. We have an INLand DNL both smaller than 0.1 LSB. As we stated in the begin-ning of this section, an INL smaller than 0.5 LSB is sufficientfor the dynamic performance.
III. DYNAMIC PERFORMANCE
In the previous section, we have shown that the static be-havior is not responsible for the low dynamic performance ofmost binary-weighted DACs; the difference in performance be-tween segmented and binary-weighted converters must be foundsomewhere else. We track it by comparing the difference instructure between a unary-weighted and a binary-weighted con-verter.
A. Pseudo-Segmentation
Segmented current-steering DACs perform well at high fre-quencies, but the published binary-weighted converters in theliterature do not. Ideally, the only difference between both struc-tures is located in the digital part: the bits are decoded in another
322 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006
Fig. 3. Scheme for a segmented converter. The converter has a decoding stage,a switching core with the switches, cascodes and latches, and a current-sourcearray.
Fig. 4. The thermometer decoder seen in Fig. 3 is replaced by abinary-weighted one, shown here, in order to obtain a fully binary-weightedconverter.
way. We believe, therefore, that the best way to design a bi-nary-weighted converter is to design a segmented one, replacingthe 4-bit thermometer decoder by a binary-weighted decoder.In this way, we modify the converter just enough to make it bi-nary-weighted. We call this approach “pseudo-segmentation”.It is indeed very tempting to scale some parts of the design ifthey seem to be oversized. This scaling, however, may for ex-ample generate different delays for the different bits. We alsonarrow the design space. Fig. 3 shows the outcome of the firststep, the design of a general segmented converter. Then, we re-place the thermometer decoder by the decoder shown in Fig. 4.The “switching core” holds all the switches, latches, cascodesand cascodes above the switches.
B. Glitch Energy
The glitch energy is the energy difference between the idealtransition and the real transition, as Fig. 5 shows. The majorcode transitions have the biggest glitch energies. Fig. 5 showsthat most of the energy is due to the slower-than-ideal transition.This is not an issue to most designers, as this happens for all tran-sitions and does not affect linearity. Therefore, most glitch mea-surements show the major transi-tion.
However, for time-domain applications such as video DACs,such waveform distortion from transitions is undesired. This
Fig. 5. The glitch energy equals to the energy difference between the idealtransition and the real transition. Most of the energy is due to the slower thanideal transition.
distortion shows up in the video image. For frequency-domainapplications, the effect of transitions on the SFDR and SNDR inthe frequency-band of interest is more important. In this work,we focus on DACs with high SFDR.
C. Glitch Energy and Unary Decoding
In a unary-decoded DAC, exactlyswitches are switched on or off for a code transition from
to . Ignoring the quantization, the codechange is the derivative of the signal to the time.
The signal can be represented by its frequency components.Each frequency component is a sine wave with a certain ampli-tude and phase. The derivative of each sinusoidal component isa sinusoid with the same frequency. If all transitions are equaland proportional to the code change, then the code transitionsgenerate spurs at the signal frequencies themselves, creating nodistortion components [3].
However, the condition that all transitions are equal is oftennot fulfilled; the up-transitions may differ from the down-transi-tions. The transitions are also dependent on the output voltage.Both effects lead to signal dependencies of the glitch andthus cause dynamic nonlinearities even for unary-decodedconverters.
D. Glitch Energy and Binary Decoding
In a binary-decoded DAC, at leastswitches are switched on or off for a code transition from
to . Another switches are switched si-multaneously on and off. During switching we have thus asuperposition of (a) the transient effect of the unary-decodedconverter, and (b) the transient effect of the switches that areswitched simultaneously on and off. Therefore, the dynamicnonlinearities are a superposition of the dynamic nonlinearitiesof a unary-decoded converter and the additional dynamic non-linearities of the binary-decoded converter. This is in line with
DEVEUGELE AND STEYAERT: A 10-bit 250-MS/s BINARY-WEIGHTED CURRENT-STEERING DAC 323
Fig. 6. Basic buffer-latch-switch structure.
the common belief that binary-weighted converters producemore spurs than segmented ones.
Fig. 6 shows the basic buffer-latch-switch structure. If thesum of the currents through the switches M7–M8 remainsconstant at all times, then the additional dynamic nonlinearitiesfrom the binary switching are not seen. For example, in thetransition from code 511 to code 512, there are 511 switchesswitched off and 512 switches switched on. If the sum of thecurrents through the switches M7–M8 remains constant at alltimes, then the 511 currents that are switched off are perfectlycompensated by another 511 currents that are switched on.These 511 simultaneous up and down transitions are then notseen. Only the one additional switch that is switched on is seenat the output. The converter then behaves as a unary-decodedone. Note that this condition requires that all transitions areequal and signal independent. In other words, if we can makea binary-weighted DAC that performs as well as a segmentedconverter, then we can control the additional nonlinearities.This can only be achieved by reducing the signal dependenciesduring switching, making the binary-weighted DAC the idealtest case to verify if the switching is well controlled or not.
IV. MODELING THE BINARY-WEIGHTED CONVERTER
In the previous section, we qualitatively discussed the glitchenergy and its relation to segmentation. Here, we model it toget quantitative results. We only model two effects: the effect ofthe different up and down transitions, and the influence of theoutput voltage on the switching time. In [7], the impact of timeskew and jitter on binary and unary-weighted structures is mod-eled. The models show that the binary-weighted architectureshave slightly smaller SFDR due to timing differences than theunary architectures. We agree with this, but add that the time
Fig. 7. Exponential up and down transitions with different time constants.
differences often are smaller in the binary-weighted convertersas these devices are simpler and smaller structures.
A. Different Up and Down Transitions
We define both transitions to be exponential functions withdifferent time constants. They are plotted in Fig. 7. Exampletime waveforms for a unary and a binary-decoded 16-bit con-verter are shown in Fig. 8. The input code is a step functionwith a step size of 2048 LSB.
Fig. 9 shows the simulated SFDR as a function of the rela-tive frequency for both unary and binary-weighted converters,single-ended. At the in-band distortioncaused by these effects is located at the same frequency as thesignal, explaining the irregularity in the plot. We see that the dif-ferent up and down transitions have more impact at low frequen-cies in the binary-weighted converter. At high frequencies, the
324 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006
Fig. 8. Example waveforms for unary and binary-decoded 16 bit converters.Between times 4000 and 5000, a major glitch is seen in the binary-decodedsignal due to the transition of the MSB.
Fig. 9. Simulation of the SFDR as a function of frequency with different upand down transitions, single-ended. (upper plot) Unary-weighted converter.(lower plot) Binary-weighted converter.
unary-decoded converter is more susceptible to this effect. Theeffect of the different up and down transitions has even-orderdistortions only. Therefore, it is not necessary to simulate thedifferential case.
B. Influence of the Output Voltage on the SFDR
A high output voltage is preferred as it increases the signalpower. The output voltage, however, is likely to influence thetransitions from one code to another. Transistors M7–M10 inFig. 6 are operated in the saturation region. They act as cas-codes between nodes N7, N8, and N9. Due to the finite gain ofthe transistors some part of the output voltage is seen on nodeN5–N6 and N9. This influences the timing of the switching. Inour model, we define the transition waveforms to be exponen-tial functions that have time constants that are dependent on theoutput voltage. If the input code is increasing, then the rise time
Fig. 10. Simulation of the influence of the output voltage on theSFDR, single-ended. (upper plot) Unary-weighted converter. (lower plot)Binary-weighted converter.
Fig. 11. Simulation of the influence of the output voltage on the SFDR,differential-ended. (upper plot) Unary-weighted converter. (lower plot)Binary-weighted converter.
is modeled to be dependent on the mean value of the output be-fore and after switching. We make this assumption because webelieve the rise time is dependent on both the output voltageat the beginning of the transition and on the output voltage atthe end of the transition. If the code is decreasing, we make thefall time dependent on the output voltage of the complementaryoutput in order to keep the fully differential nature of the struc-ture.
Fig. 10 shows the influence of the output voltage on the SFDRfor the single-ended case. The spurious signals caused by theoutput voltage are even and odd order. The results for the dif-ferential case are shown in Fig. 11. Here again, we see that theunary-decoded converter outperforms the binary-decoded at low
DEVEUGELE AND STEYAERT: A 10-bit 250-MS/s BINARY-WEIGHTED CURRENT-STEERING DAC 325
frequencies, but has poorer worst-case performance over the en-tire Nyquist range.
C. Influence of the Transition Time
In the previous subsection, we modeled the transition timeto be dependent on the output voltage. In this subsection, wemake the assumption that slow transitions align with larger timedifferences due to the output voltage. In other words, we assumethat the influence on the transition time is relative to the totaltransition time.
We resimulated the influence of the output voltage with twiceas large time constants and equal relative impact on these timeconstants. On average, the SFDR is over 8 dB worse. It is thusimportant to have transitions that are as fast as possible.
V. IMPLEMENTATION
Our analysis (and the analysis in [7]) both indicate that thereis no clear reason why a unary (or segmented) converter outper-forms a binary-weighted converter by an order of magnitude inpublished designs. We also showed that transition times mustbe as fast as possible. We therefore opt to make a pseudo-seg-mented converter with as fast as possible transition times. Apseudo-segmented converter is identical to a segmented one, ex-cept that the bits at the input of the segments are decoded binaryinstead of unary.
A. Differences Between Segmented and Pseudo-SegmentedStructures
The converter can be split into two parts. The decoder trans-forms the binary input code into a number of bits used by theanalog part. The analog part takes these digital signals as inputsand generates the appropriate output current. The only differ-ence between a segmented and a pseudo-segmented converteris how the digital part decodes the input code. This differencehas been modeled in the previous section and does not seem toreduce the SFDR over the Nyquist range. However, the interfacebetween the digital and the analog structure is often carried outdifferently.
For example, the same driver is used for the MSB as for thesmaller bits. More subtle differences do exist. The digital partof the segmented converter often has a large driving capabilitywhereas the binary-weighted converter often has a minimum-size digital connection to the analog part.
B. Basic Structure
The basic schematic for a pseudo-segment is depicted inFig. 6. The input buffer, latch, the David–Goliath inverters, andparasitic capacitances are depicted in Fig. 12. Note that wetransform the differential schematic from Fig. 6 to an equivalentsingle-ended schematic in Fig. 12. Inverters I1 and I2 are thedifferential David inverters, and transistors M2 to M5 form thedifferential Goliath inverters. Nodes N10 and N11 in Fig. 12match with nodes N1 and N2 for the left side of the differentialstructure seen in Fig. 6, and with nodes N4 and N3 for the rightside of the schematic. Inverter I3 is composed by transistorsM11 and M12 for the left part of the differential circuit and bytransistors M13 and M14 for the right part. Inverter I3 acts as
Fig. 12. Simplified schematics of the basic buffer-latch structure.
Fig. 13. Example simulated waveform when the clock turns high.
an inverting buffer, buffering the digital input. Capacitance C2holds the current state of the segment. Capacitance C1 holds thenext state. The David–Goliath structure is used to regeneratethe node while the clock is low.
If the clock is switched to high, then nodes N10 and N11are shorted. If both states differ, then the two nodes with dif-ferent voltages are shorted. A capacitive division between C1and C2 occurs. This can temporarily flip the digital value storedon node N10. This transition can take a long time dependingon the driving strength of inverter I3, the parallel capacitanceof C1 and C2 and the strength of the David inverter. Examplewaveforms are shown in Fig. 13 when the clock turns high. Notethat this simulation still assumes a reasonably big capacitanceC1 and driving inverter I3. Increasing the driving strength of in-verter I3 and the capacitance on node N10 from minimum sizesto 30 times the minimum size increases the simulated SFDR inSpice by roughly 20 dB. This increase in SFDR is mainly at-tributed to the increased switching speed. To be more precise,we increased the dimension of the nMOS transistor from min-imum size to 30 times the minimum size. We increased the di-mension of the pMOS transistor from 2 times the minimum sizeto 60 times the minimum size. This increases the power con-sumption, but the total power consumption still remains small.The waveforms plotted in Fig. 13 are simulated with an inverterI3 that has four times the minimum dimensions.
C. Power Savings of the Design
It is clear that a binary-weighted converter has a very simpledecoder. This far less complex decoder consumes only a smallamount of power. Furthermore, we have a very regular structure.In the layout, we only use parallel instances of the switching
326 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006
Fig. 14. Unoptimized layout of parallel inverter instances.
Fig. 15. Mirrored layout of parallel inverter instances reduces the area requirements and the parasitic capacitances.
core segments. Fig. 6 shows the schematic of the switching coresegments together with the current source. For the 4 MSB, theblocks are identical, that is, for the MSB 8 of those blocks areplaced in parallel. For the second MSB 4 of those blocks areused in parallel. For the 6 LSB, the switching core segments arealmost identical. They only differ in the sizing of the switches,the cascodes and the cascodes above the switches. As these tran-sistors have smaller sizes, they still fit in the same area as thebasic layout.
The “binary decoder” is just a number of parallel buffers. Wecall these buffers the decoder buffers. These buffers are simpleblocks that fit easily in a very regular layout. Combining theswitching core segments and the decoder buffers we have avery regular basic block and layout instance. We place these in-stances in a mirrored fashion on the layout. We then can sharepower supplies, wells and sources of the transistors connectedto the power supplies. Sharing these layout features reduces thepitch of the instances quite a bit.
An example layout for a simple inverter is given in Fig. 14 be-fore and in Fig. 15 after sharing the layout features. The resultof using very regular, layout-optimized and mirrored basic in-stances is that we have a very regular and compact decoder andswitching core with a high fill factor. We use only very shortconnections between all devices. This results in minimal para-sitic capacitances. Due to these small connections, it is easy tocontrol the delay differences. This reduces the need to oversizethe devices driving these lines. Furthermore, the clock line issmall and has a small load. This decreases the power consump-tion of the clock, maintaining the desired sharp clock edges.
The removal of the thermometer decoder requires precaution.Our simulations showed that two things are critical to makehigh-performance binary-weighted DACs: all segments must beas close to equal as possible, and the switching must be as fastas possible. As explained in Section V-B, the switching speedis strongly increased if we increase the size of the buffer. Wethus traded the accuracy of the latch for speed. Compared tothe latch presented in [1], our latch is simpler, faster, and con-sumes less power. Because we traded accuracy for speed, we donot need any correction on the operating point [8]. We there-fore avoid the associated power consumption. Because we useda good switching sequence for reducing the systematic errors[6], we did not need background calibration [9] or dynamic av-
Fig. 16. Measured INL and DNL.
Fig. 17. Measured spectrum for a 122.5-MHz signal at 250 MS/s.
eraging [10] of the current sources, again reducing power con-sumption. In the entire converter, we do not use power-hungryoperational amplifiers nor gain-boosting [4]. All the simplicityin the design thus allowed us to have low power consumptionwhile the optimization of the latches allowed us to have gooddynamic performance.
DEVEUGELE AND STEYAERT: A 10-bit 250-MS/s BINARY-WEIGHTED CURRENT-STEERING DAC 327
Fig. 18. SFDR plot for measured frequencies. The sample rate is 250 MS/s.
Fig. 19. Two-tone measurement. Tones are at 100 and 102.5 MHz. The SFDRin the shown band is 66.76 dB.
VI. MEASUREMENT RESULTS
All measurements are done at 250 MS/s with 10-mA load cur-rent unless explicitly stated otherwise. Fig. 16 shows the mea-sured INL and DNL, which are both within 0.1 LSB. Fig. 17shows the spectrum for a 122.5-MHz single-tone signal. TheSFDR is 62.3 dB in the Nyquist band. The measurements aredifferential, but still we have large parts of second-order distor-tion in the measurement results. Fig. 18 summarizes the spectralperformance for the full-scale single-tone signals. The SFDR isover 60 dB for all measured frequencies. We also measured theDAC with a load current of 5 mA, because many published re-sults stress that it is important to have a good crossing point[8]. By using only half of the current that the converter is de-signed for, we operate it far from the optimal crossing point.This leads to a less than 3-dB SFDR drop over the Nyquistband. This demonstrates that our buffer-latch combination is in-sensitive to the exact crossing point. We have thus successfullytraded precision for speed in the latch, easing deep-submicronintegration.
Fig. 20. Measured spectrum for a 0.01 full-scale signal around the midcode.
Fig. 21. Measured SFDR for 0.01 full-scale signals+40 dB. The SFDR forfull-scale signals is plotted for comparison.
Two-tone tests and small-signal tests around the middle codeare important for a binary-weighted converter. Fig. 19 showsa two-tone test with sine waves at 100 and 102.5 MHz. TheSFDR in a 17.5-MHz wide band is 67.8 dB. Fig. 20 shows thespectrum for a small signal that has only codes ranging from506 to 517 around the middle code. So, we positioned the signalaround the major transition, theworst possible location. Fig. 21 shows the measured SFDR forthe 0.01 full-scale signals plus 40 dB. The plot shows that thespurious do not get worse for smaller signals. Therefore, thedynamic range is not compromised by the binary structure.
We also measured thesequence.
With this dataset, the converter actually works as if it werea 9-bit unary 1-bit binary segmented converter. This one se-quence allows us to have an idea about the performance thatan equivalent segmented converter would have. The measured
328 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006
TABLE ISPECIFICATIONS
Fig. 22. Chip photograph. The current-source array and the drivers, switches,and latches are indicated. The chip is bond-path limited. Most of the area is filledwith dummies.
SFDR here is also 60 dB, indicating that the binary weighting ofthe converter did not limit the SFDR and that the two modeledeffects in Section IV are not dominant.
Table I summarizes the specifications. The clock buffer andthe buffers that we placed at the bond-paths for regeneratingthe signal strength of the input signals consume 2 mW out of4 mW. Fig. 22 shows a die photograph. The chip area is bond-path limited. The active area is less than 0.35 mm . Due to thehighly regular binary structure, the drivers, switches, and latchesrequire only a minimal amount of area. They are denoted as theswitching core in Fig. 22.
VII. COMPARISON WITH OTHER BINARY-WEIGHTED DACS
In [11], a 14-bit binary-weighted and calibrated DAC is pre-sented. It has 84 dB of SFDR at low signal frequencies but itdrops fast as the signal frequency is increased. The converterin [2] had the highest SFDR at high frequencies for a binary-weighted converter known to the authors. Our converter has60 dB SFDR at 5 times higher sample rate and at 8 times highersignal frequencies. The frequency behavior of each design isshown in Fig. 23 and Table II compares specifications.
Fig. 23. SFDR of published binary-weighted converters.
TABLE IICOMPARISON WITH OTHER BINARY-WEIGHTED DACS
VIII. CONCLUSION
In the presented work we studied the differences betweenunary-weighted and binary-weighted converters. The work pre-sented in [2] and in [7] and our modeling here indicated that ithad to be possible to build binary-weighted DACs with high dy-namic performance. We discovered that the boundary betweenthe decoder and the latch is critical as the signals there are bothanalog and digital. This problem can be alleviated by increasingthe capacitance on this node and by making all buffer-latchstructures identical. Using this approach, we managed to de-sign and measure a 250-MS/s 10-bit binary-weighted current-steering DAC with over 60 dB SFDR over the entire Nyquistbandwidth. Specific codes exist where the spectral behavior isidentical to the one of a highly segmented converter. At thesecodes, the performance did not increase. The binary nature ofthe converter thus did not pose limits to the SFDR. The perfor-mance drop while operating the device far outside the nominaloperating point was limited, showing that the accuracy in thelatch can be traded with speed. These new insights allow for
DEVEUGELE AND STEYAERT: A 10-bit 250-MS/s BINARY-WEIGHTED CURRENT-STEERING DAC 329
fast and compact current-steering converters that scale well indeep-submicron technologies.
ACKNOWLEDGMENT
The authors thank R. Taft and C. Menkus for their support attape-out.
REFERENCES
[1] A. V. den Bosch, M. Borremans, M. Steyaert, and W. Sansen, “A 10-bit1-G sample/s Nyquist current-steering CMOS D/A converter,” IEEE J.Solid-State Circuits, vol. 36, no. 3, pp. 315–324, Mar. 2001.
[2] M. Borremans, A. V. den Bosch, M. Steyaert, and W. Sansen, “A lowpower, 10-bit CMOS D/A converter for high speed applications,” inProc. IEEE Custom Integrated Circuits Conf. (CICC), May 2001, pp.157–160.
[3] C.-H. Lin and K. Bull, “A 10 b, 500 M sample/s CMOS DAC in 0.6mm ,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948–1958, Dec.1998.
[4] A. Bugeja, B. Song, P. Rakers, and S. Gillig, “A 14-b, 100-MS/s CMOSDAC designed for spectral performance,” IEEE J. Solid-State Circuits,vol. 34, no. 12, pp. 1719–1732, Dec. 1999.
[5] G. V. der Plas, J. Vandenbussche, W. Sansen, M. Steyaert, and G. Gielen,“A 14-bit intrinsic accuracy Q random walk CMOS DAC,” IEEE J.Solid-State Circuits, vol. 34, no. 12, pp. 1708–1718, Dec. 1999.
[6] J. Deveugele, G. V. der Plas, M. Steyaert, G. Gielen, and W. Sansen,“A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC,” IEEE Trans. Circuits Syst. I: Fund. Theory Appl., vol.51, no. 1, pp. 191–195, Jan. 2004.
[7] K. Doris, C. Lin, and A. van Roermund, “Synchronization distortion andspatio-temporal switching in current steering D/A converters,” in Proc.IEEE Benelux Workshop on Circuits, Systems and Signal Processing(ProRISC), The Netherlands, Nov. 2000, pp. 259–266.
[8] B. Schafferer and R. Adams, “A 3 V CMOS 400 mW 14 b 1.4 GS/sDAC for multi-carrier applications,” in IEEE Int. Solid-State CircuitsConf. (ISSCC) Dig. Tech. Papers, vol. 47, Feb. 2004, pp. 360–361.
[9] Q. Huang, P. A. Francese, C. Martelli, and J. Nielsen, “A 200 Ms/s 14b 97 mW DAC in 0.18 m CMOS,” in IEEE Int. Solid-State CircuitsConf. (ISSCC) Dig. Tech. Papers, Feb. 2004, pp. 364–365.
[10] K. O’Sullivan, C. Gorman, M. Hennessy, and V. Callaghan, “A 12-bit320-M sample/s current-steering CMOS D/A converter in 0.44 mm ,”IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1064–1072, Jul. 2004.
[11] M. P. Tiilikainen, “A 14-bit 1.8-V 20-mW 1-mm CMOS DAC,” IEEEJ. Solid-State Circuits, vol. 36, no. 7, pp. 1144–1147, Jul. 2001.
Jurgen Deveugele (S’01–M’05) received theMaster’s degree in electronic engineering and thePh.D. degree in electronics from the Katholieke Uni-versiteit Leuven (K.U.Leuven), Heverlee, Belgium,in 1999 and 2005, respectively.
His main research interests are in low-powerand high-speed current-steering digital-to-analogconverters.
Michiel S. J. Steyaert (S’85–A’89–SM’92–F’04)received the Master’s degree in electrical-mechanicalengineering and the Ph.D. degree in electronics fromthe Katholieke Universiteit Leuven (K.U.Leuven),Heverlee, Belgium, in 1983 and 1987, respectively.
From 1983 to 1986, he obtained an IWNOL fel-lowship (Belgian National Fundation for IndustrialResearch) which allowed him to work as a ResearchAssistant at the Laboratory ESAT at K.U.Leuven.In 1987, he was responsible for several industrialprojects in the field of analog micropower circuits
at the Laboratory ESAT as an IWONL Project Researcher. In 1988, he was aVisiting Assistant Professor at the University of California, Los Angeles. In1989, he was appointed by the National Fund of Scientific Research (Belgium)as a Research Associate, in 1992, as a Senior Research Associate, and in 1996,as a Research Director at the Laboratory ESAT, K.U.Leuven. Between 1989 and1996, he was also a part-time Associate Professor. He is now a Full Professorat the K.U.Leuven. His current research interests are in high-performance andhigh-frequency analog integrated circuits for telecommunication systems andanalog signal processing.
Prof. Steyaert received the 1990 and 2001 European Solid-State Circuits Con-ference Best Paper Award. He received the 1991 and the 2000 NFWO Alcatel-Bell-Telephone award for innovative work in integrated circuits for telecommu-nications. He received the 1995 and 1997 IEEE ISSCC Evening Session Awardand the 1999 IEEE Circuit and Systems Society Guillemin–Cauer Award.
A 1-V 2.5-mW Transient-Improved Current-Steering DACusing Charge-Removal-Replacement Technique
Ka-Hou Ao leong, Seng-Pan U 1 and R.P. Martins 2Analog and Mixed-Signal VLSI Laboratory, FST, University of Macau, Macao, China
1-Also with Chipidea Microelectronics (Macao) Ltd., 2-On leave from Instituto Superior Tecnico (IST)/UTL, Lisbon, Portugal
Abstract - A charge-removal-replacement (CRR) technique isproposed to realize a low-voltage low-power current-steeringdigital-to-analog converter (DAC) for minimizing transition timein current switching. Implemented in a 0.18-pm CMOS process,the 10-bit 120-MS/s DAC focused on WLAN applicationsconsumes only 2.5 mW from a single 1-V supply. The simulatedmonotonic performances achieve a mean value of IINLI < 0.14LSB and IDNLI < 0.18 LSB, respectively. The averaged SFDRobtains 67.23/62.45 dB with/without the CRR technique.
I. INTRODUCTIONThe demand for high performance digital-to-analog converters
(DACs) has obviously increased for the fast development ofadvanced telecommunication systems, e.g., wireless local areanetworks (WLANs). In view of that, most of data converters aredesired to be fully integrated into a CMOS System-On-a-Chip(SoC) wireless transceiver with including RF transceiver, digitalphysical layer (PHY), corresponding media access controller(MAC) and all other analog baseband building blocks [1]. Toavoid any supply-voltage constraints for the technology scaling,low-voltage building blocks with low-power consumption ishighly required.
In practice, current-steering DAC is preferred for wirelesscommunications due to its high sample rate, capability of drivingresistive loads and relatively low-power consumptions. Thecurrent cells with cascoded topologies as shown in Fig. 1 aresatisfactory for static and dynamic output-impedance requirements[2]-[3]. Alternatively, the cascoded-switch topology [4] presents asadditional digital signal feedthrough isolation and output influencereduction through the insertion of two cascoded transistors (M,a,+and M, -). However, asymmetry in rising-falling transitions andlong settling time will degrade the dynamic performance directly,especially applied in high speed and high resolution DAC whichunit current is small. This paper proposes a charge-removal-replacement (CRR) technique that fixed those transient problems.For demonstrated purposes, a 1-V 10-bit 120-MS/s DAC with lessthan 1.3-jtA unit current was designed and simulated, the currentswitching transient is highly reduced and the dynamicperformances of the DAC are dramatically enhanced.
After this introduction, the proposed CRR technique will bepresented in section II. In section III, it will be applied to a low-voltage current-steering DAC with a detailed description of eachbuilding block. In section IV, simulation results will be presented.Finally, the conclusions will be summarized in section V.
II. CHARGE-REMOVAL-REPLACEMENT TECHNIQUEThe main disadvantages of the conventional cascoded-switch
current source (CSCS) topology are the long settling time andasymmetry settling time (falling settling time is slower than that inrising), which distorting output current of the DAC. The tarryfalling settling time is caused by the node voltage, which belowthe off switch (MA,,1M,), is discharged exponentially until the
(a) (b)Fig. 1 (a) Cascoded-current-source and (b) cascoded-switch topology.
Vm+rnt CRR , OFF
Ml' - ONH
vssvss ~~~~~~~~~~~~Time
nVwell nAwell A VSSTime
(a) (b)Fig. 2 (a) Operational principles of CRR technique and (b) the
corresponding control signals.
cascoded switch (Me.,lVLa) enters in the subthreshold region. Asa result, an amount of current leaks into the path even if thecorresponding switch is in the off stage. Such current is given bythe subthreshold expression of the drain current (ID),
ID =IoexpV><(1)where ;>I is a nonideality factor and VT=- kT q. Moreover, withparasitic capacitance present in the source terminal of cascoded-transistor Mc,. Mc,. , the transition will be further extended.
Operational Principles The CRR technique is depicted inFig. 2(a), where a capacitor (CcR) driven by an inverter is insertedbetween the gate and drain terminals of the switched transistor.When the desired switch is turning off, the inverter generates aninverted control signal to draw out the positive charge((IqD) fromthe inversion layer and the ubiquitous parasitic capacitance at nodeXb such that any lengthy discharge procedure can be eliminated.
To avoid current sources from being turned off simultaneously,digital control signals with lower crossing point apply to the switch
current and (c) node voltage vx of unit current cell.
inputs [Fig. 2(b)]. If the switching control signals directly cross-couple to the capacitor CCRR, the charge Aq+ will drawcontinuously when the path is turned off Thus, the inverter isnecessary required to generate a delayed control signal to balancethe falling and rising transitions.
Timing Benefits - Two advantageous features are summarizedbelow:(a) Balanced Speed and Advanced Transition: The CRRtechnique improves the rising transition by replacing some positivecharge, given that the node voltage vx is faster settling to itssteady-state value while the current path is turning on. On the otherhand, when the current path is desirable turned off, the CRRtechnique removes the residual charge and prompts the nodevoltage vx to steady state (i.e., vx is leaded to reduce). Therefore,the cascoded switches no longer suffers from the criticalexponential discharge problem, establishing balanced falling andrising speeds. As illustrated in Fig. 3(a), the falling transition of asingle-ended output current is enhanced in terms of speed toachieve more balanced rising-falling characteristic. Even though adifferential-ended output signal [Fig. 3(b)] can suppress even-harmonic distortion in the conventional CSCS structures, thetransient nonlinear problem still exists, which can be solved by theCRR technique presented.(b) Recovered Synchronization for Each Current Source: In thecurrent-steering DAC, the digital control input signals switch thecorrespondent current paths on/off Delay differences amongactive current paths create an input-data-dependent nonlinearityand increase the susceptibility to asynchronous glitches. Theconventional CSCS endures input-data-dependent delay even theclock nets are perfectly synchronized. The reason is the nodevoltage vx requires a long settling time, even though the outputcurrent has already settled [Fig. 3(b) and (c)]. The node voltage vx,
0 20M 40M 60M 80M 1OOM 120M
Input Code Rate of Unit Current Cell (Hz)
Fig. 4 Input code rate vs. instantaneous node voltage vx settling level, andrising/falling delay of differential output current.
................. RR
................. ...|0 fl j=j ~~~~~~~~~~.
o 45.99%[1 .~I d_
......... C8V rio tion
tt...... .......
_ ..
.. C ........ ........... .............................................................~~ ........... ....
Fig. 5 Rising/Falling delay with capacitor variation
(t: Calculated by [different] I[average] in the range of input code rate.)
thus, requires different charging time in every clock cycle,
resulting in a non-constant rising delay for switching on the current
path. As shown in Fig. 4, the CRR technique reduces the variation
of vx from the steady-state voltage for different switching rates,
and it also leads the rising/falling delays of the differential output
currents to be more independent of the input code rate. In fact, the
difference between rising/falling delays is dependent on the
capacitance of CCRR. With capacitor variation, the performance is
slightly degraded as shown mn Fig. 5. However, the tmprovement is
still significant when comparing with the performance of
conventional structures. Furthermore, pushing the cascoded
switches to the deep subthreshold region can eliminate the induced
current, such that the accuracy of the D/A conversion will not be
degraded.
Output-Impedance Influence -The output impedance of the
current source affects both the static and dynamic linearity of the
DAC. The output resistance ofCSCS is given by [3],
Rout = maGstoatstc (2)
and the output impedance (Z0ut) has two poles and two zeros as:
Pi P2 = mc=as (3)
2Zcr0csCo 2ZcrosC1 hcC0 2zcC1
APCCAS 2006
< settle ,,wl CRRCRR
\ ,~~~~~~~~,settle
- 5 10 15 20 25 30 35 40 45 50Time (ns)
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0.4-not settle |_
0.3 settle
0.2._
..R
I
5n
(L0)
184
0.1k 10k IM 1O0MFrequency (Hz)
Fig. 6 Output impedance with and without CRR.
where gm, and ro are the transconductance and output resistance ofthe corresponding transistors, respectively, as noted in Fig. 6.
The CRR technique inserts an additional capacitor CCRR intothe current cell, which is equivalent to an increase of thecapacitance C1 and a frequency shifting of the pole P2 to a lowervalue. As illustrated in Fig. 6, this effect can be neglected (i.e.,only 1-kHz difference) because the add-on capacitor CC istypically small in size.
III. DESIGN EXAMPLEA 1-V 10-bit 120-MS/s fully binary-weighted current- steering
DAC with the CRR technique was designed for WLANapplications. The floor plan is shown in Fig. 7, where the circuitconsists of a set of digital input buffer, a clock driver, a biasingcircuit, a switch & latch array (SWATCH), and a current-sourcearray (CSA). Utilizing a transimpedance output stage [5], whichhas a lower input impedance node, improves static and dynamiclinearity concurrently. However, this current-to-voltage buffer isnormally required to drive a smaller feedback resistor, imposinglarge power dissipation. For power saving, instead of using thetransimpedance output buffer, the designed DAC drives a resistiveload (RL) directly [6].
Current Source Array (CSA) - In the conventional current-steering DAC, the segmented architecture improves the DNL andglitch performance by using more unary decodes. However,increasing the use of unary decoding occupies large chip area,increases power, digital noise, time skews and design complexity.In the design of a 10-bit DAC with an equal structure and a fullybinary decode [7] is more attractive to achieve low power, highaccuracy, linearity and speed, as well as size compaction.
The matching is critically determined by the area of the unitcurrent source. In the behavioral-level simulation, a maximumrelative standard deviation (alIl) of a unit-current source is 0.2%for correct INL and DNL yields (99.7% yield for INLI and IDNLI<0.5 LSB). In fact, aqJ, of a binary-weighed DAC is normallydetermined from the DNL yield. The minimum area (WL)m,n of theunit current source is estimated by [8],
(W L)min )2 L D
where AA and AvTare the matching parameters, and (VGS-VT) is theoverdrive voltage of the current source transistor.
clk BO B9
Fig. 7 Floor plan of the designed fully binary-weighted DAC.
Switch + Latch (SWATCH) - The switch array of the DACis constructed by cascoded switches to enhance the outputimpedance of the current sources. In practice, the length of theinput (L,) and cascoded (Lca,) switches is chosen at minimumlength to further reduce the digital feedthrough. Beside the effectof finite output impedance, the dynamic performance of a current-steering DAC is mainly limited by the imperfect synchronizationof the control signals and the drain-voltage variation of the currentsource. For lowering the glitch errors as the current is switched tothe desired output, it is essential that the driving signals exhibit alower crossing point. The rise/fall-time-based latch [9] has beenexploited for its high-speed capability [Fig. 7], and NMOS positivefeedback loop exhibits a faster fall than rise time of the latch.Moreover, an additional feedback using small inverters (IH and I2)reduces the clock-feedthrough (CFT).
The CRR technique is embedded into the swatch array, and thePMOS capacitor (Mc) is utilized instead of capacitor CCRR for area
saving. In this way, not only the charge injection is reduced(similar to a dummy switch), but also removed/replaced thepositive charge while improving the transient characteristic anddynamic performances.
In the designed DAC, the full-scale current is 1.25 mA and theresistive load RL is 200 Q. The resulted differential peak-to-peakoutput voltage is 0.5 V.
IV. SIMULATION RESULTSA 1-V 10-bit DAC simulated using 0.18-ptm CMOS
technology was designed to demonstrate the above technique. Toevaluate the static linearity performance of the DAC, 300-timeINL and DNL Monte-Carlo simulations are illustrated in Fig. 8(a)and (b), respectively. The statistical histograms show that the JINLIand IDNLI exhibit a [mean, standard deviation] of [0.134, 0.049]and [0.178, 0.081] LSB, respectively. The scatter plot obtainedfrom the same Monte-Carlo simulations [Fig. 8(c)] clearly showsthat the required specifications are met with the appropriate margin.As mentioned, the CRR technique can improve the switchingbehavior of the current cells. In order to compare the dynamicperformance between the conventional and the proposed technique,
(a) (b) (c)Fig. 8 Histogram of (a) INL, (b) DNL and (c) scatter plot of INL vs. DNL from a 300-time Monte-Carlo simulation.
0 1OM 20M 30M 40M 50MFrequency (Hz)
60M 0 1OM 20M 30M 40MFrequency (Hz)
50M 60M'
Desired Signal Band
\.
Conventional
avg SFDR 6245dB
:::M 1M
Output..Signa Fre. ....
(a) (b) (c)Fig. 9 Simulated output spectrum at 5 MIHIz, 120 MS/s (a) without and (b) with CRR technique. (c) SFDR vs. output signal frequency.
the output spectrums are presented in Fig. 9 (a) and (b),respectively. With the new technique, the averaged SFDR isimproved by 4.78 dB within the Nyquist band [Fig. 9(c)]. Asummary ofthe simulation performances is listed in Table 1.
V. CONCLUSIONThis paper presented a charge-removal-replacement (CRR)
technique for improving the transient performances of current-steering DACs. Adopted in a 1-V 10-bit 120-MS/s fully binary-weighted current-steering DAC, the technique removes (replaces)the node charge when the desired current path is turned off (on).The discharging (charging) time is reduced leading to a higherspeed in D/A conversion. Compared with the conventionalcascoded-switch current source (CSCS) topology, the switchingtransition, asymmetry rising-falling settling and synchronizationproblems are minimized with negligible power (< 0.15 mW) and
Table 1 Summary of the DAC performance.Specification Unit Value
Technology 0.1 8-,tm CMOSNumber ofbits 10Sample rate MS/s 120Supply voltage (Analog & Digital) V 1Differential output signal V 0.5Load (RL) Q 200JINLI [Mean, Sta Div] LSB [0.134, 0.049]IDNLI [Mean, StaDiv] T LSB [0.178,0.081]SFDR @ Desired signal band j dB > 63Glitch energy pV-s 0.4Power consumption mW l_ 2.51 l
t: Power Breakdown: 1.3 mW (Analog), 1.2 mW (Digital).
chip area overheads. In average, 4.78-dB improvement in SFDR isachieved within the Nyquist band.
ACKNOWLEDGMENT
This work was financially supported by the University ofMacau under the research grant with Ref No RG069/02-03S/MR/FST.
REFERENCES[1] S. Mehta, et al., "An 802.11g WLAN SoC," in IEEE ISSCC, Digest of
Technuical Papers, pp. 94-96, Feb. 2005.[2] B. Razavi, Principles of Data Conversion System Design. IEEE Press,
1995.[3] A. V. D. Bosch, et al., "SFDR-Bandwidth Limitations for High Speed
High Resolution Current Steering CMOS D/A Converters," in Proc. ofICECS, VOL. 3, pp. 1193-1196, Sept. 1999.
[4] H. Takakura, et al., "A 10 bit 80MHz Glitchless CMOS D/A Converter,"in Proc. ofCICC, pp. 26.5.1-26.5.4, May 1991.
[5] K. -H. Ao leong, et al., "A Frequency Up-Conversion and Two-StepChannel Selection Embedded CMOS D/A Interface," in Proc. ofISCAS,pp. 392-395, May 2005.
[6] N. Ghittori, et al., "A Low-Power, Low-Voltage (1 1mW/8.4mW, 1.2V)DAC+Filter for Multistandard (WLAN/UMTS) Transmitters," in Proc.of VLSI Circuits, pp. 334-337, Jun. 2005.
[7] J. Deveugele, et al., "A 10b 250MS/s Binary-Weighted Current-SteeringDAC," in IEEE ISSCC, Digest of Technical Papers, pp. 362-532, Feb.2004.
[8] M. J. M. Pelgrom, et al., "Matching properties of MOS transistor", IEEEJSSC, VOL. 24, NO. 5, pp. 1433-1439, Oct. 1989.
[9] A. V. D. Bosch, et al., "A 10-bit 1-GSample/s Nyquist Current-SteeringCMOS D/A Converter," IEEE JSSC, VOL. 36, NO.3, pp. 315-324, Mar.2001.
APCCAS 2006
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40
50
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186
A DIGITAL CALIBRATION FOR A 16-BIT, 400-MHZ CURRENT-STEERING DAC
Jussi Pirkkalaniemi, Marko Kosunen, Mikko Waltari1, Kari Halonen
Helsinki University of Technology, Electronic Circuit Design LaboratoryP.O. Box 3000, FIN-02015
A digital calibration for current-steering D/A converters ispresented. The calibration corrects errors originating frommismatched thermometer decodedMSB current sources. Thecalibration principle is to measure the mismatches and skipover transfer function discontinuations. Four redundantMSBsources compensate for reduced input range caused by theskipping action. The mismatches are measured by using asimple comparator. Manners for extending the calibrationrange, thus enhancing linearity, are straightforward. Simu-lations show that the errors caused by the MSB sources arecancelled resulting in clear improvement in static linearity.
1. INTRODUCTION
Development of wired and wireless telecommunications sys-tems has created a need for high-speed, high-resolutionDACs. Used in typical applications, such as digital-IF radiotransmitters, a DAC has to provide large dynamic range toa low impedance load, the most important performance cri-terion being spectral purity. Because of these demands thecurrent-steering architecture is often considered the mostsuitable structure.
Even though spectral purity is the key performance para-meter, the static linearity must be taken into account as wellsince it contributes to dynamic performance. The most im-portant static linearity errors (INL, DNL) in current-steeringDACs exist due to mismatched current sources. Mismatchesoriginate basically from process and temperature variationson the silicon die. Current source mismatch can be com-pensated to some extent by means of special layout tech-niques [1], but over 12-bit intrinsic static linearity is elusivewithout considerable silicon area cost. Thus some calibra-tion or trimming is obligatory if the resolution is very high.
Traditionally current sources are calibrated either by laser-trimming [2] or adjusting bias voltages of individual tran-sistors [3]. However, the feasibility of these methods is lim-
This work was supported by the Finnish National Technology Agency(TEKES) and Nokia Networks.
1Currently with Conexant Systems Inc., San Diego, CA, USA.
ited because laser trimming requires special process tech-niques and cause harmful thermomechanical stress. Ana-log biasing schemes becomes impractical as supply voltagesscale down and they may suffer from long term stabilityproblems without regular recalibration.
Another way of performing calibration is to measurecurrent source mismatches and store them digitally into mem-ory registers. After calibration period one or several calibra-tion DACs can be used for mismatch correction [4, 5]. Stor-ing mismatch information digitally is advantageous sincerecalibration is needed relatively seldom. However, addi-tional calibration DACs must match with the main DAC.
The digital calibration presented here take advantage ofdigital mismatch information storage. The method does notrequire usage of additional calibration DAC or accurate A/Dconverter since mismatch is measured with a simple com-parator. Calibration is also suitable for high clock rates andlow supply voltages.
2. DAC ARCHITECTURE
The architecture of the core DAC is shown in Fig. 1. Cur-rent sources are constructed of unit current sources, whichare separated into two arrays. In the MSB array there are 67equal current sources, which are switched by 7 thermometerdecoded MSBs. Four additional MSB sources provide re-dundancy exploited by the calibration. 10 LSB currentsources are binary weighted. Additionally there are threecalibration sources providing currents corresponding to 1/2LSB, 1/4 LSB and 1/8 LSB that are placed into the LSBarray.
The current-source arrays need different bias currents,which are generated in the current scaler. For testing pur-poses the bias current ratio can be adjusted by 11 externalcontrol bits, which is used for controlling the systematicmismatch between the current source arrays. Output cur-rents drive external 50-Ω load resistors directly.
Clock signals are created in the clock generator, whichbasically consists of a clock buffer and an adder type clockdivider. Differential external clock signal is converted tosingle ended in the clock buffer. The divider is needed be-
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" !
Fig. 1. DAC block diagram.
cause calibration unit clock frequency must be lower thanthe 400-MHz full speed clock. 12-bit clock control enablestrimming of the division ratio.
3. CALIBRATION
Usually the worst static linearity errors in current-steeringDACs originate from mismatched current source arrays. Thebias current ratio adjustment can remove any systematic mis-match, but it is ineffective against random DNL errors. Theobjective of the calibration is to correct the residual randommismatch caused by the MSB array.
3.1. Calibration method
The output current of each 67 MSB sources are trimmedwith the bias current adjustment to be systematically lessthan the maximum output current of the LSB array. It isnecessary for the calibration algorithm to work correctly.The resulting output transfer function has negative steps atevery point a new MSB current source is connected to theoutput. This is illustrated in Fig. 2, which contain part ofuncalibrated and calibrated DAC transfer function.
The concept of the calibration has similarities with themethod published in [4]. The fundamental difference inthis approach is that the discontinuations are skipped overinstead of using a calibration DAC. Skipping is analogousto consider the mismatch related pieces of the uncalibratedtransfer function as forbidden and disuse them. The draw-back is reduced full input range, which should be extendedaccordingly. The four additional MSB sources are used forthat purpose. Full 16-bit input range is achieved if the sumof all the mismatches is less than the redundancy which
Fig. 2. Calibration principle.
means that the more accurate the MSB array is, the lessredundancy is required. Contrary to the MSB array, cur-rent sources in the LSB array must achieve adequate match-ing intrinsically. However, even highly linear LSB array issmall comparing to the MSB array.
Calibration is carried out by measuring mismatch off-sets depicted in Fig. 2. Once an offset is calculated it issummed with the preceding offsets giving a cumulative off-set. Cumulative offsets are stored into memory registers. Innormal operation there are four possible cumulative offsetvalues for an input code, since the cumulative offset can beas large as 4 times the MSB code value (210). If the in-put code gives a location in a forbidden section, the corres-ponding cumulative offset is added to the code performingskipping over discontinuation.
3.2. Calibration process
At start-up situation the calibration unit in Fig. 1 is givencontrol over DAC current switches via input control. Thecore of the calibration unit is a state machine, which ex-ecutes consecutive calibration steps. Comparator, describedlater on, is controlled by the calibration unit also. It is cap-able of sampling and thus able to compare two differentDAC output voltages. By using three calibration sourcesthe offsets can be measured with accuracy of 1/8 LSB.
The procedure for measuring the offsets is depicted inFig. 3. CAL-value refers to the output current of a MSBsource, which is under calibration. The CAL-value is com-pared to a REF-value (reference), which is swept down infour LSBs steps as shown by arrows in Fig. 3. Down-sweepcontinues until the comparator toggles. Then sweep direc-tion is changed and the step size is reduced to 1/8 LSB.The offset is calculated at the point the comparator togglesagain. The calibration proceeds with the rest of the MSBsources until all the 67 offsets are measured.
By using a sampling comparator the offsets can be foundwithout a high-resolution A/D converter that are slow ingeneral. However, for mitigating the effect of noise an av-
Fig. 3. Offset measurement procedure.
erage over sufficient number of comparisons must be takenat each REF-value resulting in increased calibration time.For experimental reasons the number of comparisons canbe chosen arbitrarily between one and two million.
3.3. Accuracy considerations
The LSB array dominates the post-calibration non-linearity.Hence, special attention must be paid to dimensioning ofthe LSB current sources. Sufficient intrinsic linearity isachieved by distributing all of the unit current sources in acommon-centroid layout. The matching of the LSB sourcescan be further improved by following methods.
The transistor area of the LSB sources can be increasedbecause the overall silicon area is relatively small, as a resultof reduced area consumption of the MSB sources. That isdue to the fact that poorer matching, thanks to the proposedcalibration, can be allowed for the MSB current sources.
The matching accuracy of the LSB current sources canalso be enhanced by extending the same calibration methodfor few largest LSB currents. However, the LSB sources tobe calibrated are required to have also the systematic offsetfor ensuring the functionality of the calibration algorithm.In addition, the required amount of memory is doubled pereach bit added to the calibration range.
The memory requirement can be alleviated by measur-ing the offsets of the LSB sources at one code value only.That results in accumulation of the quantization error of
In+
In-
Res1
Res1
Res2
Res2
Res3
Res3
Sample
Sample
Comp
CompVref
Res4
Res4
Out-
Out+
Res1
Res2
Res3
Sample
Res4
Comp
CAL-valueat input
REF-valueat input
Fig. 4. Comparator structure.
the measurement to the cumulative offsets. However, thatshould be tolerable if only a few largest LSB current sourcesare to be calibrated.
3.4. Comparator
The comparator and its control waveforms are sketched inFig. 4. The structure is an offset insensitive switched-capacitorcircuit consisting of several operational amplifiers, switchesand capacitors. High resolution is achieved by cascadingfour amplifiers.
Comparison begins in reset mode. CAL-value is sampledby opening the reset switches of the first three stages. Oncethe CAL-value is sampled, the DAC is switched to a REF-value and a differential voltage is stored by opening samplingswitches. Then the fourth reset switches are opened. Com-parison is accomplished by connecting the last coupling ca-pacitors to a reference voltage Vref. The Vref voltage levelis half of the supply voltage.
The comparator is fully insensitive to the amplifier off-set but some error originate from switch charge injections.Most of the charge injections are canceled as they are storedwith the amplifier offsets to the capacitors of the next stages.However, some residual error is caused by mismatched chargeinjections of the fourth stage reset switches. The final erroris the error voltage at the input of the fourth amplifier di-vided by the gains of the three preceding stages [6].
If the fourth stage charge injections are mismatched, thecomparator still have some offset due to finite gains of thefirst three stages. This limits the accuracy since it accumu-lates with every cumulative offset thus giving rise to non-linearity.
Because of the possibility of charge injection mismatchdespite of careful layout design, the calibration period startswith a measurement of the comparator offset. The man-ner of the measurement is shown in Fig. 5. First a con-stant reference point on the DAC transfer function is chosen.The corresponding output value, added with 1/8 LSB, issampled to the comparator. After that the DAC is switchedto the first comparison point, which must be larger than
Fig. 5. Comparator offset calibration.
the reference point. Both the reference point and the firstcomparison point are selected externally via a control vec-tor. The comparison result should indicate that the refer-ence point is lower so the procedure continues by sweepingthe comparison point down in 1/4 LSB steps until the com-parator toggles. The comparator offset is calculated at thistoggle point. Correct toggle point is guaranteed because the1/8 LSB calibration source is connected with the referencevalue only. The measured comparator offset is subtractedfrom each cumulative offset resulting in adequate cancella-tion.
4. SIMULATIONS
The effect of the calibration on static linearity was simulatedwith MATLAB. 1000 DACs were generated with two dif-ferent LSB array matching profiles. Matching of the MSBcurrent sources corresponded to the requirements of a 12-bitDAC.
If the matching of the LSB current sources correspondedto the linearity requirements of a 13-bit DAC, the calibrationimproved the DNL yield from 0% to 99.7% and the INLyield from 0% to 89.2%. If 14-bit matching was definedfor the LSB sources, the improvement of the DNL and INLyields were from 0% to 100% and from 0% to 97.8%, re-spectively.
Envelope curves for the minimum and maximum DNLand INL values of the 13-bit LSB matching are presented inFig. 6. Worst case DNL is calibrated from 1.5 LSB down to0.7 LSB. INL is improved from 5.5 LSB to 0.75 LSB.
5. CONCLUSIONS
A digital start-up calibration for current-steering DACs hasbeen proposed. The calibration method does not requireadditional calibration DAC or A/D converter, but uses asimple comparator for mismatch measurement. The ideaof skipping over transfer function discontinuations and theuse of four redundant MSB sources to achieve full 16-bitinput range has been demonstrated. The simulations show
clear improvement in static linearity and that the residualnon-linearity originates from the LSB array. The possibilit-ies of linearizing the LSB array by extending the calibrationrange are discussed. By using the presented calibration, aDAC with 12-bit intrinsic static linearity, can be improvedso that 16-bit linearity is achieved.
6. REFERENCES
[1] G. A. M. Van der Plas, et al., “A 14-bit Intrinsic Accur-acy Q2 Random Walk CMOS DAC”, IEEE Journal ofSolid-State Circuits, pp. 1708-1718, Dec. 1999.
[2] D. Mercer, “A 16-b D/A Converter with IncreasedSpurious Free Dynamic Range”, IEEE Journal of Solid-State Circuits, pp. 1180-1185, Oct. 1994.
[3] D. W. Groeneveld, H. J. Schouwenaars, H. A. H. Ter-meer, and C. A. A. Bastiaansen, “A Self-CalibrationTechnique for Monolithic High-Resolution D/A Con-verters”, IEEE Journal of Solid-State Circuits, pp.1517-1522, Dec. 1989.
[4] Y. Manoli, “A Self-Calibration Method for Fast High-Resolution A/D and D/A Converters”, IEEE Journal ofSolid-State Circuits, pp. 603-608, Jun. 1989.
[5] Y. Cong, R. L. Geiger, “A 1.5V 14b 100MS/s Self-Calibrated DAC”, Solid-State Circuits Conference, Di-gest of Technical Papers, pp. 128-129, Feb. 2003.
[6] E. A. Vittoz, “ The Design of High-Performance Ana-log Circuits on Digital CMOS Chips”, IEEE Journal ofSolid-State Circuits, pp. 657-665, Jun. 1985.
A STATISTICAL METHODOLOGY FOR THE DESIGN OF HIGH-PERFORMANCE CURRENT STEERING DAC’S
Paolo Crippa, Massimo Coizti, Claudio Turclaetti
Dipartimento di Elettronica e Automatica, University of Ancona Via Brecce Bianche, 60131 Ancona, ITALY
Random device variations are a key factor limiting the perfor- mances of high-resolution CMOS current steering D/A convert- ers. In this paper a novel design methodology based on statistical modeling of MOS drain current has been developed. This tech- nique requires firstly an estimation of mean value and autocorre- lation function of a single stochastic process, which all the pro- cessldevice variations are lumped in. Then a behavioral model of D/A converters has been developed. Finally the statistical simu- lation of static performances (DNL and INL) has been carried out for different DAC architectures.
1. INTRODUCTION
Designing high-performance DAC’s requires a deep understanding of the relationship between performance and source of technolog- ical errors, especially for high-resolution DAC’s to reach a higher effective number of bits. Earlier works have presented several ap- proaches facing this problem [l, 21.
Recently new architectures using segmentation have been sug- gested which benefits the advantages of both the binary- and the thermometer-coded architecture [3]. However one of the main lacks in designing high-performance DAC’s is the statistical mod- eling of the error sources, which results not adequate to predict statistical effects on performance. In particular assuming uncor- related error sources, as done in previous works, not only gives unreliable results but also results scarcely useful in reduction mis- match effect through a suitable layout design. Instead a reduction of performance sensitivity to mismatch error can be obtained by exploiting the statistical behavior of error sources and in particular their dependence on position in the die, so as to choose a suitable layout minimizing the mismatch effect.
2. MISMATCH MODELING
We assume that mismatch effect could be modeled as an error source 17 coupled in parallel with the nominal current I D . as shown in Fig. I , so that the total drain current io is given by
io = I D + 71. ( 1 )
The non-random term I D represents the usual dc drain current, while the term 71 gives raise to some random fluctuations (around I D ) depending on the device position in the wafer, the region of operation of the device and its dimensions T I ‘ and L.
On the basis of such considerations the following simple model of the random term will be assumed
11 = I& (IT., L ) y (x, y) (1)
where the term I: accounts for the device operating region (being /3 a fitting parameter), g (111 L ) takes into account the dependence on dimensions and y(z: y ) summarizes all the sources of error de- pending on the device position in the die. Therefore y(z, y) can be considered as a spatial stocliastic process. while 11 is a stochastic process, assumed to be with zero mean, not only dependent on the coordinates (2; y) but also on bias and device sizes.
Referring to a circuit with N devices placed at different posi- tions in the die, Ai sources of error act in the circuit. The statistical properties of such a system can be summarized by means of the autocorrelation function R,,,, resulting in
R,,, ( . % . I . ? / r , ~ j , ~ j ) = E ( 7 1 ( r ( . Y! 171 (r.1 i Y I ) = ~ ( , ~ ~ ( ~ : ‘ , ~ ~ ) - I r ~ ) ( ? ~ ~ ( . ~ . , ~ ? / , ~ ) - ~ r ~ ) ( 3 ) = c,,,, ( : l : , , ? / > ; : r , , . y j ) .
Eq. (3) means that the covariance function C,,, ,” of i n is the same as the autocorrelation function of ’1. As the non-random temis can be taken out from the expected value we have
C,,,, = A . R?; . A = C , , , , (4)
where C , ’, is the covariance matrix of drain currents whose generic i,j-element is
and
This work was pnrtially supported by CNR - Prog. Final. MADESS I1 Eq. (4) is of central importance since it relates the covariance of
V-311 0-7803-6685-9/01/$10.000200l IEEE
Shared Gate 6 2
Figure 2: Schematic and layout of transistors' array with selection circuitry.
the current to the covariance of the error source, making possible to derive a model for C,,,, once a mathematical model for R,, has been assumed. An usual choice for R?-, is the Gaussian function, namely for a stationary process
where ( I , , IC.,.. and IC,, are fitting parameters and T , ~ = :r, - x;,,, T,, = U, - I,, are distances between a pair of devices along :r:- and y-axis respectively. As a consequence C,,, , predicts a dependence on ( . I . : y) . other thin on voltages and dimensions.
3. MODEL ESTIMATION FROM EXPERIMENTAL DATA
To estimate C,,, , a test pattern with different sized transistors ar- ranged in A..I mays with A', rows and N, columns of identical transistors has been designed. By assuming io (3:: g). or that is the same ? ( x . y). is a wide-sense stationary process, thus the mean value of the drain current w , ~ , (n:,;y) = I D = c o r i ~ t . can be esti- mated from measurements through the following relationship
where ~ is the drain current of the device placed at //-position of t -th 'array. Additionally. from measurement we can estimate the covariance matrix of drain currents whose generic /j-th element is given by:
In order to have a suitable amount of data for estimation, nine as- pect ratios have been chosen for both PMOS and NMOS transis- tors: II-/L = 2/10. 5/1.4. 2/1, l / O . i ' , 0.i/O.5, 0.5/0.35. 1/1. O . T / l . 0.3/1 / / i i i /p~ii . Thus 18 arrays (one for each geometry) of 8 x 8 cascode transistor pairs have been designed in a single die. Finally 39 replicas of the die have been implemented on an 8-inches wafer manufactured with 0.35 pm CMOS technology.
Figure 2. shows the schematic of a single m a y with row and column decoders added for selecting one transistor at a time. Fig- ure 3 shows the covariance matrix C , , , , obtained by applying
Figure 3: Covariance matrix C , , , , obtained from a set of arrays build with devices having an aspect ratio of II-/L = 2/10 ,um/pm and biased with 12;s 1 = 0.6 1 ~ and 1 b s = 3.0 1 -.
Figure 4: The autocorrelation function R,, obtained by fitting measured data reported in Fig. 3.
the above methodology to a set of device arrays with aspect ra- tio of 11-/L = 2/10 pi i /pin and biased with 1 ;;SI = 0.6 1 and ID.? = 3.0 I - . The current variance cr;D corresponding to C ' l D ; D ( O . 0) is also reported in Fig. 3. A Gaussian function as in (7) has been assumed for R,, where cy1, IC.r, and Ayl/ are esti- mated from measurements. The procedure for fitting the autocor- relation function model to measured data has been implemented in MATLAB by exploiting algorithms based on least square min- imization of errors. For data reported in Fig. 3 the following pa- rameter values have been obtained: 0-, = 1.2 ' 10-". K,z = 0.0187 p - ' and K!, = 0.1689 pn - ' while the resulting auto- correlation function R,, ( T , ~ ~ T ~ ) is reported in Fig. 4.
4. STATISTICAL SIMULATION OF DAC'S PERFORMANCES
Statistical simulation at system level is essential as a first stage in statistical design of high-performance DAC's in order to com- pare different architectures. It requires, as schematically shown in Fig. 5. the following steps:
i ) Establish the vector of performances c p , that is the perfor-.
V-3 12
l o OUT DAC - ARCHITECTURE - Figure 5: Simulation at system level.
I .vdd
B PERFORMANCE +
U
0 8 -
0 6 .
0 3
02.
Figure 7: Normalized covariance matrix C, , of error sources.
It can be shown that DNL and INL are related to the vector 77 through the following matrix equations
mances which characterize the behavior of the system, i.e. Differ- ential Non-Linearity (DNL), Integral Non-Linearity (INL), ...
ii) Define for a given architecture a relationship relating the DAC output OUT to the vector of all current sources io and a mathematical model relating the performances cp to the output.
At the end of this process, assuming a linear relationship be- tween L+Y and io (achieved through linearization in case of non- linearity), it is straightforward to derive the covariance of the per- formances as a function of the covariance of the currents, resulting in
(10) where S is a matrix depending on the DAC architecture.
c;, = s ' c,,,, ' sT
4.1. Non-dynamical performances
To derive an input-output relationship relating DAC output to the vector error sources q, we define OUT as the vector whose com- ponents are the 2" output levels and which will be assumed as the output of the DAC. Referring to the architecture shown in Fig. 6(a) for a binary weighted DAC, that in Fig. 6(b) for a thermometer coded DAC and to a mixed mode DAC which uses both the ar- chitectures, a relationship relating the output OUT to the current vector i~ can be derived. Since all the architectures considered are linear networks, the dependence of output on source currents will be linear as well. Therefore, it results
OUT = T iD (11)
being T a matrix dependent on the specific architecture whose ex- plicit relationships have been derived for the three architectures mentioned before.
In order to obtain non-dynamical performances DNL and INL, it is useful to derive the vector _10[TT whose components are the random variables associated with the ideal output levels. By combining eqs. ( 1 ) and ( 1 1 ) i t results
1 0 1 'T = T ' q (12)
being Dnl and In1 matrices independent of the architecture. Eqs. (13) and (14) establish a linear dependence between the
performances DNL, INL and the random sources 77. Thus it is straightforward to derive the covariance matrices of DNL and INL
C D V L D N L = J D N L . C,,, . J T n n r ~ , (17)
C I . ~ L I h ' L = Jlh L . c,,, . J T A ~ L . (18)
These equations, whose form is the same as eq. ( IO) , are the re- quired relationships for statistical simulation of DAC architectures.
5. APPLICATION EXAMPLES
On the basis of the behavioral DAC models previously derived the statistical simulation of the performance can be carried out.
Before proceeding with such a task it is worth to note that in general every current source ZD in a DAC is implemented with a set of sub-sources I'D (of LSB value or less) whose total current ex- actly fits the 7,9 value. In such a way the large number of freedom degrees can be used to reduce statistical technological variations. Thus as the covariance matrix C,,,, refers to the errors q of the cur- rents in , a new matrix C , , J , ~ , taking into account the errors q' of sub-currents 2;) has to be defined. Because every current ZD is a sum of one or more &,, the vector q is achieved from q' through a linear transformation L, that is
q = L 77' (19)
so that it results G1', = L ' C,f,,f ' LT
In the simulation examples we assume all the error sources y are correlated with the autocorrelation function given by eq. (7). The random samples have been generated by a suitable software pro- gram according to the distribution chosen. The covariance matrix behavior derived in such way for a weal; correlation between error sources is reported in Fig. 7.
V-3 13
To describe the current sources arrangement we use a matrix notation in which the term Bx (Tx) represents a sub-source related to the x-th binary (thermometric) source. With such a notation, re- femng to a 6-bit purely binary DAC, the current sources arrange- ment shown in the box of Fig. 8 has been chosen. In this case the results achieved are not satisfactory as clearly appears from Figs. &(a) and 8(b) reporting the diagonal terms of the covariance matrices C D N L D , V L and CI,VL I ,WL respectively (normalized to the variance of LSB), that is the variance of the performances as function of the input code. As you can see both DNL and INL have a maximum variance corresponding to the half-code transition.
Better results have been obtained with a layout solution sug- gested in [I], which takes into consideration mismatch effect. The arrangement chosen shown in the box of Fig. 9 is such that all the six binary sources have been split into arrays of not contigu- ous unitary sources. As you can see in Fig. 9(a) the maximum in the variance at half-code disappears, as well as the values of the variance at the other transitions decrease. Moreover the maximum values result even less than the ones in the case of uncorrelated er- ror sources, meaning that correlation between random sources can be suitably exploited. Also INL improves with such a layout as it clearly appears from Fig. 9(b).
Let us now consider a thermometer DAC. In this case the vari- ance of DNL ( ~ 6 . ~ ~ is simply o iSB for every transition. With re- gard to INL it is worth noting that in order to reduce its variance a suitable sequence of current source selection, named “hierarchical symmetrical switching” [ 2 ] , has been adopted. The thermometer current sources have been arranged as shown in the box of Fig. 10 making possible to obtain the results shown in Fig. IO.
6. CONCLUSIONS
A statistical method to design high-performance CMOS current- steering DAC’s has been presented. The methodology allows the designers to explore DAC architectures and study the technology- dependent effects of circuit layout on the system performances without using CPU-time expensive Monte Carlo simulations. This technique takes into account the mismatches of current sources de- vices by using a simple statistical MOS model based on stochas- tic processes theory. For the model characterization a test pat- tern with different sized arrays of identical transistors has been designed. Behavior level DAC model for two main static perfor- mances, namely DNL and INL, has been derived and used in the simulation tool. As application examples, simulations of three dif- ferent DAC topologies have been performed.
7. REFERENCES
[ I ] C. A. A. Bastiaansen, D. W. J. Groeneveld, H. J. Schouwe- naars, and H. A. H. Termer, “A IO-b 40 MHz 0.8-pm CMOS current-output DIA converter.” IEEE J. Solid-Stare Circuits, vol. 26, n. 7, pp. 917-921, July 1991.
[ 2 ] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazava, “A IO-b 70-MSIs CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 26, n. 4, pp. 637-642, April 1991.
[3] G. A. M. Van der Plas, J. Vandenbussche. W. Sansen, M. S. J . Steyaert, and G. G. E. Gielen “ A 14-bit intrinsic accuracy Q’ random walk CMOS DAC,” IEEE J. Solid-State Circuits, vol. 34.11. 12, pp. 1708-1718, Dec. 1999.
35
30
25 0,
20
15
10
5
0 (b)
10 20 30 40 50 60 Input Code
Figure 8: Diagonal terms of the covariance matrices (a) CO \ L D \ L and (b) C , \ L 1 L for a 6-bit DAC (current sources are ‘arranged as shown in the box).
_ _ _ . _ ~
B 1 8 6 85 86 8 3 86 B5 86
86 8 3 86 05 86 04 86 85
85 86 81 86 B5 86 82 86 16
I BS 65 BS 81 86 85 BS 81
81 86 85 86 84 86 85 W
2 10 86 64 86 B5 86 8 3 86 85
BS 65 BS 81 86 85 BS 81
81 86 85 86 84 86 85 W
Input Code
Figure 9: Diagonal terms of the covariance matrices (a) CO \ L D \ L and (b) C , \ L \ L for a 6-bit DAC (current sources are arranged as shown in the box).
TSP T3T T61 Tn T25 T51 T41 TYI
T I0 T U 759 T27 l31 163 TIP Tu)
20 30 40 50 h u t Code
Figure 10: Diagonal terms of the covariance matrix C I \ L I \- L for a 6-bit DAC (current sources are arranged as shown in the box).
V-3 14
IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE
A Study Of Error Sources In Current Steering Digital-to-Analog Converters
This paper will discuss a number of error sources which potentially limit the distortion and S N R performance of modem current steering Digital-to-Analog Converter designs. Static matching errors as well as timing and non-linear output impedance errors will be presented along with possible design solutions.
Introduction Fine line CMOS technologies have become the process of choice for high sample rate switched current digital to analog converter design [ 1 - 41. Switching speeds of sub-micron gate length MOS transistors has allowed sample rates of many hundreds of MHz. Unlike switched capacitor circuits used in many ADCs which require so called mixed-signal process variants with high quality poly-poly or metal-metal capacitors, switched current DACs can make use of the standard CMOS processes. The designs have marched down the process generations from 0 . 8 ~ to 0 . 1 8 ~ and beyond. There are certain common features of these designs which have become givens.
Universally, DACs with resolutions from 8 bits to 16 bits are split into two or more segments. The most significant bit (MSB) segment is always made from unit weighted elements and is thermometer coded. The number of bits in the MSB segment can vary from as few as four to as many as 7 bits, with 5 and 6 being the slightly more common choice. The rest of the bits may be binary coded but are often further segmented into a thermometer coded intermediate significant bit (ISB) section and a least significant (LSB) binary coded section. A notable exception to the use of thermometer coding is proposed by Deveugele in [ 181. Here competitive performance is achieved using unit elements but combined and switched in binary fashion.
It also seems that PMOS currents and switches are used more often then NMOS currents. Using PMOS devices on a standard twin well process on P-type wafers provides the opportunity to isolate the back gates of the devices and bias them at some potential other than a power supply or ground. With PMOS there is the convenience of having the output load referenced to ground as well. Newer triple well processes have become available in deep sub-micron which provide the ability to isolate the NMOS devices but poorer l/f noise performance has limited the appeal of going with NMOS currents.
Power or supply current in a CMOS switch current DAC can be divided into three categories. The first comes from the digital logic and clock section and often directly scales with the sample frequency and the data pattern. CMOS has the advantage that the design will benefit from advances in process and supply voltage scaling. The second and third supply current categories are analog in nature. The full scale output current can be a big part of the current in the analog supply and can range from as little as 1 mA or less and up 20 mA. The rest of the analog supply current is overhead and comes from the reference and bias circuits for cascodes and output switches. Sometimes this overhead current can be made to at least partially scale with the full scale output. Sometimes
I - ,
designs make use of mixed voltage process options to allow the analog sections to be powered from higher supply voltages and provide larger voltage swings on the output.
Static Errors and Calibration Device matching in CMOS processes has been studied and is well documented starting with the often cited work by Pelgrom [SI. By taking advantage of statistical averaging, layout techniques and random switching order, accuracy of up to 14 bits has been reported by Vandenbussche [6] . To achieve even higher accuracy or to increase yields with less layout area trimming or calibration techniques are often used as in Schofield [4] and Groeneveld [7], There are two basic approaches to implementing self-calibration, foreground and background. A converter which is foreground calibrated must be taken off line and not used while being calibrated because as each current source is measured it is removed from the output. In background calibration an additional current source is used to replace each current source as it is calibrated. This allows the DAC to be in use while being continuously calibrated. However, the operation of removing and replacing current sources from the output could cause extra disturbances.
There are also two basic approaches to storing the correction factors for the individual current sources. One technique as proposed in [7], is shown in figure 1. Here a correction voltage is stored on the gate capacitance of a MOS transistor M1. A dynamic technique such as this needs to be constantly refreshed and lends itself to background calibration. There is also a minimum clock rate reauirement and the calibration will be lost if the clock is turned o k during power saving modes.
CW Figure 1 Calibration (a) Normal Operation (b)
There are certain systematic sources of error in this technique. The operating conditions of trim device M1 and the devices in the main current source Im vary between the calibration and operation modes. The Vds of the devices is set equal to the Vgs of M1 while in calibration. However, while in normal operation, the Vds is set by whatever circuitry is connected to the terminal OUT. This could be a cascode device or the output switches of the DAC. Because of the finite output impedance of these devices the current that results in the operating mode will be different than that which flowed in the calibration configuration. Each cell is slightly different and the amount of adjustment needed, i.e. the gate voltage of M1, will be different. The change in current between calibration and
0-7803-8495-4/04/$20.00 02004 IEEE. 9-5-1 185
operation modes will depend on the level of the adjustment. This will limit the accuracy of the calibrated result. In order to maximize the headroom in designing current sources the devices are often biased such that the vds is marginally larger than vdsat of the device. In this configuration the Vds of M1 and Im must be equal to the Vgs of M1 when in calibration.
Static storage of a digital correction value as used in [4] does not need to be refreshed and would lend itself to foreground calibration. In this approach, shown in figure 2, the current to be calibrated is measured against a master reference current and the difference adjusted as close to zero as possible through the successive approximation register (SAR) logic and a CAL DAC which injects a small correction current in parallel with the main current source. .......................
a a a a a td *
IL
Figure 2 Static digital storage correction. The switches which redirect the current either to the output node or the calibration hardware act as the cascode devices and thus fix the drain voltage of the main current source device to be the same, within the matching of the Vgs of the two cascode switches, in both cases. This can result in a much more accurate calibration. The additional circuitry used for the calibration is not clocked during normal operation and does not use power or inject noise into the main signal path.
Figure 3(a) Code dependent output impedance
Finite Output Impedance An INL. mechanism that results from the use of a thermometer coded architectures is code dependent output impedance, figure 3(a). As the number of unit elements is switched to the output, the resistance RSW of that element's current source appears in parallel with the load resistor RI.. As the number of elements turned on increases the effective output impedance of the DAC in total decreases. The varying impedance in parallel with the load resistor results in a non-linear output voltage across the load. This gain compression effect in each output is
ploted in fig. 3(b) for a 7-bit segment case. The magnitude of the resulting INL curve, fig. 3(c), is a function of the number
Figure 3 (b)Output ( 4 JNL When the single-ended harmonic distortion analysis done by Van den Bosch in [8] is extended for differential third order distortion, a single cascode causes the output impedance to limit third order intermodulation distortion at low a frequency as seen for the lower curve in figure 4. This limit can be increased with a second cascode as in seen in the upper curve.
I ...........
1#
eo 60
4cI
20
Figure 4 Single vs double cascode While it is true that output impedance requirements are greatly reduced for fully differential output configurations, as pointed out by Luschas in [9], it is important to design the output switches and their gate voltages so as to keep the output switches in saturation. This maximizes the attenuation of the output swing 'seen at the common source nodes of the differential switches. The small signal attenuation of the switches is given by the ratio of the device gp to gds. Typical values of this ratio are in the range of 20.
T mJ Vbias *e I lmsb
v cs 2,- cs cs
... Figure 5 Differential current switch
186 9-5-2
Early work in BiCMOS by Mercer in [16] pointed out that high-speed operation requires a small and linear source node capacitance for the switches.. A switch unit element will see an attenuated output signal on the switch common source node, and any non-linear back gate capacitance, depicted as C1 in figure 5 , on this node will produce distortion. Tying the switch and cascode transistors’ back gates to the supply reduces non- linear capacitances, but for a large array, the total non-linear capacitance can be significant. The input of a unity-gain level- shifting amplifier can be connected to the switch common source node and used to drive the back gate of the switches and cascode [4]. The non-linear back gate capacitances now see the signal on both plates, thereby bootstrapping the well capacitances and leaving small linear parasitic capacitances. The amplifier’s dc level shift should set high to minimize the switch’s non-linear capacitance.
Switch Gate Drive It is very necessary to optimize the waveform, i.e. the crossing point of the gate drive signals of the current source switch pair as shown in figure 5 . The circuit that drives the differential switches Ml,M2 needs to ensure that the current is always flowing at a constant value. If the voltage at node Cs is allowed to move then some of the current will flow in the parasitic capacitance, C 1, shown in the figure. The best way to insure that the current flow is constant is to have the gate signals cross at a point below the nominal DC voltage of the common node Cs equal to the Vgs of one of the switch devices ( M1,M2 ) when 1/2 of the current is flowing through the switch. This minimizes the excursion of the voltage at Cs during a transition and hopefully the disturbance is symmetric around the nominal DC value as indicated by the center waveforms in the figure. An important point is that it is not necessary to bring the gates of the switch devices any higher than the voltage on the Cs node when turning off the device (Vgs = 0). This reduces any feed through of the gate drive signals to the outputs or the common source node Cs.
.
(c) Figure 6 Common Source Waveforms
Another source of dynamic error relates back to the fact that a small attenuated amount of the output signal leaks through the gds of the differential switch onto node Cs. The amplitude of the signal seen at node Cs is typically about 1/20 that seen at outputs IA and IB or 50 mV for a 1V swing at the output. Each
switch element turns on at a different point in the transfer function and as a result will have a different wave shape on node Cs. In figure 6(a) the complementary outputs IA and IB are shown. Referring to figure 5 , node Cs will have the attenuated version of IA when M1 is on and the attenuated version of IB when MI is off ( M 2 on ). In figure 6@) we see what the signal on Cs will look like when a switch element is near the lower end of the transfer function. Similarly, for figure 6(c) we see the signal on Cs when a switch element is near the top of the transfer function.
In figure 5 , note that the point at which M1 and M2 switch is determined by the crossing point of gate drive signals G1, G2 with respect to the value of node Cs. If the relative value of Cs is modulated by the output swing and where in the transfer function the switch element is, the actual time point when the switches change will also be a function of the output swing and their position in the transfer function. This will result in a signal dependent jitter seen in the output. As indicated in figure 6@) M1 switches from on to off when Cs is at its low point and M1 switches from off to on when Cs is near the high point. For the case shown in figure 6(c) just the opposite happens. The amount of jitter depends on the magnitude of the signal on Cs and the rise/fall time of the gate drive signals.
time, nSeconds Figure 7 Switching delay vs output swing
An example case is shown in figure 7, where the normalized zero crossing point of the differential output voltage at IA,IB is shown for three cases. The horizontal axis is 5 pSec per division and the vertical axis spans about 1 mV. The three curves are for cases where the difference between IA and IB when the switch flips is -333 mV, 0 V and +333 mV. For these three cases the node Cs has shifted its nominal value by a total of 32 mV or approximately 1/20 of the output. We see a shift in time of 4 pSec, which results fiom a differential slew rate on the gate drive signals Gl,G2 of 125 pSecN. This could be a significant source of error when generating high frequency outputs.
Similarities between DAC and Flash ADC The thermometer coded segments of a switched current DAC are very much analogous to the full parallel flash ADC. The complexity and hardware of both doubles for each bit of resolution. In the ADC, the distribution of the analog input signal to the comparators with matched delays is much the
9-5-3 187
same as the collection and combining of the individual unit current outputs of the DAC. Also, as in the Flash ADC where the delays in the clock distribution to the individual comparators must be tightly matched, the clock distribution network driving the final stage of re-timing latches in the DAC is equally important.
Delay = A jClOCk Input
Figure 8 Distribution by Propagation Matching One possible approach to this is propagation delay matching [4] illustrated in figure 8. Here if we assume that each cell has the same delay A and the delay along the clock distribution line from cell 1 to cell n is 61 and the delay along the output line is 62 then the sample timing is preserved if61 = S2.
Clock Input -
$1 DAC Output -
- Delay A
Figure 9 Distribution by Constant Wavefront Matching Binary tree distribution structures are often used to match these delays as well as done by Schafferer in [15]. This results in a constant wavefront as illustrated in figure 9. The clock distribution tree is arranged to have equal lengths ffom the driver to each cell. Likewise the output collection tree is arranged with equal length ffom each cell to the output pad(s). The clock tree delay does not need to match the output tree delay.
The physical placement of the unit cells in the layout is an important consideration and geometric shuffling of the placement is often used to breakup any linear gradients in the cell delay A ( figure 8,9 ) that might be present.
Digital data pattern dependent noise Gonzales in [lo] observed that noise generated by the data passing through the digital logic portions, specifically the thermometer decode section, of a DAC can cause spurious tones and distortion in the analog output. Gong [ 1 11 teaches us that it is possible to concentrate this noise at the clock frequency Fs or Fs/2. This is accomplished by including a shadow or mirror data path with a one to one correspondence to the main data path. This shadow data path is driven by a data pattern is such a way that for each node in the main data path that does not change value at a give clock transition the corresponding node in the shadow path does. Likewise, when a node in the main path does change the corresponding shadow node does not change. This makes the sum total of all nodes changing at each clock transition constant and independent of the data pattern.
An example of this technique in an over-sampled switched current audio DAC is proposed by Rueger in [17]. In this design a dummy data shift register creates constant local digital edge activity on the supply, ground and substrate. NMOS switch devices, driven by full rail swings, are used to switch the cascoded PMOS current sources. The use of the dummy data to drive dummy switch devices balances the switching activity injected into the output stage thus minimizing the demodulation of out-of-band noise into the base band.
A similar notion referred to as modified mismatch shaping (MMS) is proposed by Shui in [12]. The idea is to set the number of elements or cells switching per clock period to a constant. This tums the errors caused by non-ideal element dynamics into a dc offset and energy at Fsl2. Shui assumed an oversampling converter, where the maximum output bandwidth is reduced. The choice of what fraction of the total number elements to set the constant to is problematic and the optimum is a function of the nature of the signals being converted, however. In any case, the constant can never be set to more than 1/2 the number of elements. This limits either the maximum amplitude or the maximum output frequency to only 1/2 of what it would have been otherwise. Therefore, we conclude that, for a Nyquist rate converter, to make use of this constant element switching concept we would need twice as many elements.
Data Dependent clock loading A rather important special case of data pattern dependent timing error comes from the varying load seen by the final clock driver which drives the last re-timing latch of the DAC. The basic issue is that all latches to some extent present a load to the circuit, which drives the clock input, that depends on whether the content ( state ) of the latch is changing or not. Given the finite strength of the driving circuit, the rise time of the clock waveform will be a function of the number of the multiplicity of latches connected to this common clock driver which are changing their state at a given time. This results in a shift in time of the output samples which is a function of the rate of change on the waveform and thus gives rise to odd order distortions mainly third order.
An example of this effect is shown in figure 10. The time when the rising edge of the clock signal crosses mid supply (1.25 V) is plotted for the case of a single latch when the input data is not changing and when the input data is changing. This simulation shows a 2 pSec difference. This effect is magnified when a large number of latches are driven by the same
188 9-5-4
common clock driver and is proportional to the number of latches which change their state. In the case of thermometer coded data the number of data bits changing is proportional to the rate of change of the output waveform.
1.8 I I I I I I I
I I I I I I I -20 -15 -10 -5 0 5 10 15 20
time, pSeconcla Figure 10 Data dependent clock delay
We can get a workable solution by taking the shadow or mirror data paths concept of [ l l ] and combining it with what we concluded from [ 121 and realize that by doubling the number of latches by simply adding the second as a mirror path for each original latch and driving the mirror latch in such a way as to cause it to change state only when the main data latch does not. One way this mirror data can be generated is shown in figure 11. By combining the main data signal with a clock signal at Fs/2, or 1/2 the main clock rate, with an exclusive OR gate the mirror data signal is created such that it changes only when the main data does not. By doubling the number of latches we have doubled the load on the clock driver but it is now independent of the incoming data pattern.
I
DATA , LFp
Fclock 4 Figure 11 Data pattern independent clock loading
Return-to-Zero Switching Another way to re-time the data samples at the output of the DAC is to use a return-to-zero output stage as proposed by Bugeja in [13]. In this case a set of additional switches have been added in the output path between the current switches and the external output load as shown in figure 12, for one of the
"\ %:k Driver
differential outputs. Switch M1 is switched off for 1/2 of the clock period while the DAC current switches (IDAC) change and then back on after the currents have settled. Resistor R1 provides a load while M 1 is off. As well, there is switch M2 to short the output to ground, through resistor R2, when the other switch is off thus the return-to-zero operation. This effectively reduces the timing skew between the various DAC switches. There is however a loss of 1/2 of the signal amplitude, 6&, due to the return-to-zero output.
Figure 12 Return to Zero Concept, output waveform Return to zero switching can reduce the distortion from digital data noise induced timing errors, but for very high sample rates if the output does not completely settle in each half of the cycle then the history effect or inter-symbol interference is not eliminated and can result in signal dependent distortions. It is important to note that this scheme is not totally free of signal dependent timing errors. The turn on and turn off points for M1 and M2 will depend on the signal levels seen at the node OUT. It is difficult to tell if the reported SFDR results for this method are really any better than those reported in [4] because both seem to be limited to about -75 dBc for output fkquencies above 25 MHz, which seems the measurement limit of most spectrum analyzers
Quad Switching I Constant Data Activity Dynamic element matching or distortion spreading techniques are popular methods of improving spurious free dynamic range by smearing the distortion into a noise like component in the output of the DAC. Random spreading produces a more white noise like result. Other approaches can shape the noise characteristic to place it out of the band of interest, if there is some amount of oversampling in the system. While DEM will increase the amount of data activity it is not constant for each clock cycle. When constant switching techniques are used the distortion or noise is concentrated as a tone at the sampling frequency.
Ordinary differential current switching results in some data- dependent distortions arising from the jump or glitch on the common source node of the switch pair. This ordinary switch does not toggle every clock transition, and as a result the switching event is dependent on the data pattern, introducing distortion in the band of interest. Another approach to the data pattern dependent dynamic errors pointed out in [ 121, is a quad differential current switch proposed by Park in [14] for an oversampling DAC and again by Schafferer in [15] for a multi- bit Nyquist DAC.
189
By using four switches instead of the normal two, we are in effect interleaving two return to zero switches. The configuration of the quad switch is shown in figure 13. There are four switch devices M1, M2, M3 and M 4 which share a single common source connection Cs. The unit element current Im is supplied to node Cs as in the ordinary differential switch. Only one of the four switches is on at any given time as indicated by the switching waveforms of figure 14.
,I lmsb
Figure 13 Quad Switch
G J I U
G2
. . G3 u
t L I
G4 I \ I I U
IA ‘“B Figure 14 Quad Switch Waveforms
The gate of each switching transistor is driven by a signal shown in Fig. 14, three of the four gates will be high and one low for a given clock cycle. Each clock cycle the gate that is low will transition high and another gate will transition low. At the bottom of the figure the outputs IA and IB indicate where the current Imsb is being directed. The output at IA and IB is logically the same as with ordinary differential switching. There will be switching glitches as indicated even if the current does not change outputs. Switching in this manner eliminates the nonlinearity due to uneven pulse duration, as in RZ switching, because every pulse has the same width. There are at least two and only two signal transitions, one rising and one falling, per clock transition. Switching noise is now moved to the sample clock frequency by the constant toggling of both sides of the switch. It also important to note that the disturbance seen on the common source node Cs is constant and independent of the input data pattern.
Quad switching like this incorporates some of the good points of both RZ switching and ordinary differential switching, is suitable for high sample rates, and reduces transition- dependent noise. A drawback of quad switching is an increase in complexity, four gate signals need to be generated and the increased dynamic power consumption due to the fact that one pair of the four switches each cycle.
Conclusions Seven major contributors to errors and distortion in modem switched current Digital-to-Analog converters have been discussed. Static device matching can be addressed either though statistical averaging or calibration. One or more cascodes can be included, along with insuring that the output switches remain in saturation, to reduce the effect of output impedance variation. The importance of gate drive signals was explored. Much like the flash ADC, clock distribution is a key factor. Digital data pattern generated noise needs to be addressed and the effect on clock jitter can be a major source of distortion. Return-to-zero switching can be employed to re- time the output sampling time. The use of a quad switch and constant data activity switching techniques can shift spurious outputs to the sampling frequency.
References [l] Mercer D., Singer L.; “12-b 125 MSPS CMOS D/A Designed For Spectral
Performance”; ISLPED 1996 Digest of Technical Papers, Pages 243-246 [2] Lin C-H., Bult K.; “A lob 250MSample/s CMOS DAC in I d ”;
ISSCC 1998 Digest of Technical Papers, Pages 214-215 [3] Tesch B., Pratt P. Bacrania K, Sanchez M.; “A 14-b, 125 MSPS Digital to
Analog Converter and Bandgap Voltage Reference in 0.5um CMOS”; ISCAS 1999 Digest of Technical Papers, pages 11452-455
[4] Schofield, W., Mercer, D., St Onge, L.; “A 16b 400MS/s DAC with < -8OdBc IMD to 300MHz and < -160dBm/Hz noise power specaal density”; ISSCC Digest of Technical Papers , 9 Feb. 2003 Pages:126-127
[SI Pelgrom, M.J.M.; D u i i i j e r , A.C.J.; Welbers, A.P.G.; ”Matching properties of MOS transistors” IEEE JSSC .Volume: 24 , Issue: 5 , Oct. 1989 Pages1433 - 143
[6] Vandenbussche, J. et al.”A 14 b 150 Msample/s update rate 42 random walk CMOS DAC”, ISSCC 1999 Digest of Technical Papers, 15-17 Feb. 1999 Page(s): 146-14
[8] A.Van den Bosch, et al., “SFDR Bandwidth Limitations for High Speed High Resolution Current Steering CMOS D/A Converters,” Proc. ICECS,
[9] Luscbas S., Lee H.-S.; “Output impedance requirements for DACs” Proceedings of the 2003 ISCAS, Volume: 1 ,25-28 May 2003 Pages:I-861 - 1-864 vol. 1
[IO] Gonzalez, J. L.; Alarcon, E,; “Clock-jitter Induced Distortion In High Speed CMOS Switched-current Segmented Digital-to-analog Converters” ISCAS 2001 Digest of Technical papers, May 2001, Pages 1-512-515
[l I] %g; ” Digital signal processor with reduced pattern dependent noise’’, United States Patent no. 5,719,572 issued 17 Feb. 1999
[12] Shui T., Schreier, R., Hudson, F.; “Mismatch shaping for a current-mode multibit delta-sigma DAC” Solid-state Circuits, IEEE Journal of ,Volume: 34, Issue: 3 ,March 1999 Pages:331 - 33
[I41 Park, S.; Kim, G.; Park, S.C.; Kim, W.; “A digital-to-analog converter based on differential-quad switching” Solid-state Circuits, IEEE Journal of , Volume: 3 7 , Issue: 10 , Oct. 2002 Pages:1335 - 1338
Chapter 1: Introduction ...................................................................................................11.1 Description of IDDQ ......................................................................31.2 Reliabili ty Benefits Derived from IDDQ........................................51.3 Literature Review.........................................................................51.4 Chapter Organization...................................................................9
Chapter 2: The Digital-to-Analog Converter (DAC) Design .........................................102.1 Performance Specifications of Digital-to-Analog Converter ......122.2 Digital-to-Analog Converter Architectures.................................192.3 Digital-to-Analog Converter Operation.......................................24
2.3.1 Capacitor Array Design.......................................272.3.2 Operational Ampli fier Design .............................302.3.3 A Two Stage CMOS Opamp Topology...............332.3.4 Current Mirrors....................................................332.3.5 Active Resistor.....................................................372.3.6 Unity Follower.....................................................452.3.7 Sample-and-hold circuit.......................................472.3.8 The Transmission Gate Switch............................502.3.9 The Storage Capacitor .........................................51
Chapter 3: Built -in Current Sensor Design .....................................................................613.1 Current Testing in CMOS Integrated Circuits Using BICS.........613.2 IDDQ Hardware..............................................................................62
3.3.1 Open Faults.........................................................673.3.2 Bridging Faults....................................................703.3.3 Gate-Oxide Short Defects...................................73
3.4 Definition and Description of IDDQ of a Faulty Circuit ................73 3.4.1 Description of IDDQ of a Faulty Inverter ............753.5 Design Considerations of BICS...................................................77
3.5.1 Previously Proposed Schemes...........................773.5.2 The Design of the BICS.....................................78
3.6 The Implementation of BICS.......................................................80
iv
3.6.1 BICS in Normal Mode......................................803.6.2 BICS in Test Mode...........................................823.6.3 Detailed Analysis of BICS ...............................83
3.7 Layout, Simulation and Timing Diagrams for BICS...................843.7.1 Current Mirror Circuit.......................................843.7.2 Current Differential Ampli fier..........................843.7.3 BICS..................................................................87
3.8 Fault Detection, Simulation and Testing .....................................873.8.1 Fault-Injection Transistor...................................89
Chapter 4: Theoretical and Experimental Results ...........................................................974.1 Simulation Results.......................................................................97
Chapter 5: Conclusion and Scope of Future Work .........................................................121
Appendix A: SPICE LEVEL 3 MOS Model Parameters for Standard n-well CMOS Technology ........................................................................127
Appendix B: Chip Testabili ty ..........................................................................................129
2.9b Equivalent circuit with MSB =1, and all other bits set to zero............................23
2.10 Schematic block diagram of a 10-bit charge scaling DAC..................................25
2.11 Integrated Capacitance network, multiplexer switches and ampli fier part of the circuit of Fig. 2.10.....................................................................................26
2.12 Layout of a unit capacitance made of poly1 and poly2 used in the design .........28
2.13 Layout of the capacitor array using unit capacitor configuration........................29
2.14 Layout showing the use of dummy capacitors to match the capacitors present at the corner of the capacitor array..........................................................31
2.15 Block diagram for an integrated opamp...............................................................32
2.16 A CMOS operational ampli fier............................................................................34
2.17 PMOS current mirror design................................................................................36
2.18 NMOS current mirror design...............................................................................36
vii
2.19 Layout of an operational ampli fier design of Fig. 2.16.......................................40
2.20 Post-layout transfer characteristics of the circuit of Fig. 2.16.............................41
2.21 Input and Output response of the ampli fier circuit of Fig. 2.16..........................42
2.22a Frequency response characteristics of the circuit of Fig. 2.16.............................43
2.22b Phase response characteristic of the circuit of Fig. 2.16......................................44
2.23 The non-inverting OPAMP configuration...........................................................46
2.24 The CMOS operational ampli fier as a unity gain ampli fier (follower) ...............48
2.25 Schematic diagram of a sample-and-hold ampli fier ............................................49
2.26 Sample and Hold CMOS circuit ..........................................................................54
2.27 Layout of a CMOS sample-and-hold circuit (S/H) circuit...................................55
2.30 Sample and hold response of circuit of Fig. 2.26 obtained from postlayout SPICE simulations....................................................................................58
2.31 Layout of a 10-bit charge-scaling DAC...............................................................59
2.32 DAC output response for all (0000000000 – 1111111111) combinations of the input digital word.......................................................................................60
3.1 Faulty (IDEF) and fault-free (IREF) IDDQ current ....................................................63
3.2a Off-chip IDDQ current measurement using an automatic test equipment..............65
3.2b Off -chip IDDQ current measurement .....................................................................65
3.3 Block diagram of IDDQ testing..............................................................................68
3.4 Open circuit defect ...............................................................................................69
3.5 Drain-source and inner-gate bridging faults in an inverter chain ........................71
3.7a Gate-oxide-short (GOS) in a MOSFET ...............................................................74
3.7b Equivalent circuit model. RS is the effective resistance of the short. B models the rectifying behavior of new current path introduced by the defect .................74
3.8 Bridging fault causing IDDQRB drop and a path to the ground.............................76
3.9 CMOS built -in current sensor circuit...................................................................79
3.10 Built -in current sensor with CUT ........................................................................81
3.11 n-MOS current mirror circuit ...............................................................................85
3.12 Schematic of a current differential ampli fier .......................................................86
3.13 Layout of a built -in current sensor circuit............................................................88
3.15 Layout of a 10-bit DAC with BICS showing the defects induced in the CUT using fault-injection transistors..............................................................92
3.16 CMOS operational ampli fier circuit with defect 1 introduced using a FIT..........93
3.17 CMOS unity gain buffer circuit for S/H with defect 2 introduced using a FIT....94
3.18 CMOS MUX circuit with defect 3 introduced using a FIT ..................................95
3.19 CMOS MUX circuit with defect 4 introduced using a FIT ..................................96
4.1 CMOS chip layout of a 10-bit charge scaling DAC with four fault injection transistors distributed across the chip............................................98
4.2 MOS chip layout of a 10-bit charge scaling DAC including BICS within apadframe of 2.25mm × 2.25mm size....................................................................99
4.3 Microchip photograph of 10-bit charge scaling DAC and BICS for
4.4 Simulated and measured characteristics of a 10-bit charge scaling DAC...........102
4.5 Measured DNL characteristics of a 10-bit charge scaling DAC...........................103
4.6 Measured INL characteristics of a 10-bit Charge Scaling DAC...........................104
ix
4.7 Voltage gain response of op-amp with fault introduced.......................................105
4.8 Transfer function of op-amp with fault (VE1) induced..........................................106
4.9 Gain versus frequency response of the CMOS opamp circuit with fault introduced.....................................................................................................107
4.10 Simulated output response of the multiplexer circuit of Fig 3.18 without defect........................................................................................................108
4.11 Simulated output response of the multiplexer circuit of Fig. 3.18 with fault activated................................................................................................109
4.12 Simulated BICS output of the circuit of Fig 3.16 when Error-signal-1 for defect-1 is activated.........................................................................................110
4.13 Simulated BICS output of the circuit of Fig 3.17 when Error-signal-2
for defect-2 is activated ........................................................................................112
4.14 Simulated BICS output of the circuit of Fig. 3.18 when Error-signal-3
for defect-3 is activated.........................................................................................113
4.15 Simulated BICS output of the circuit of Fig.3.19 when Error-signal-4
for defect-4 is activated.........................................................................................114
4.16 CMOS circuit diagram of 10-bit charge scaling DAC with four fault injection transistors distributed across different parts of the circuit .............115
4.17 Simulated BICS output with defects induced using fault injection transistors.....116
4.18 HP 1660CS logic analyzer test results on a fabricated CMOS 10-bit charge scaling DAC showing the performance of BICS in normal and test modes.........118
5.1 Block diagram of a sigma-delta ADC...................................................................122
B.1 Pin configuration of 10-bit DAC with BICS.........................................................134
B.2 Microchip photograph of 10-bit charge scaling DAC and BICS
for IDDQ testing .....................................................................................................135
x
Abstract
This work presents an effective built -in current sensor (BICS), which has a very
small impact on the performance of the circuit under test (CUT). The proposed BICS
works in two-modes the normal mode and the test mode. In the normal mode the BICS is
isolated from the CUT due to which there is no performance degradation of the CUT. In
the testing mode, our BICS detects the abnormal current caused by permanent
manufacturing defects. Further more our BICS can also distinguish the type of defect
induced (Gate-source short, source-drain short and drain-gate short). Our BICS requires
neither an external voltage source nor current source. Hence the BICS requires less area
and is more efficient than the conventional current sensors. The circuit under test is a 10-
bit digital to analog converter using charge-scaling architecture.
1
Chapter 1
Introduction
Conventional logic testing applied in digital circuits can detect faults, which can
cause logic errors [1]. It, however, cannot detect several physical defects such as the gate-
oxide shorts, floating gates and the bridging faults. These physical defects do not cause
any logical error at the time of testing but can manifest into a fault at an early stage of the
circuit li fe. Thus, circuits should also be tested for physical defects apart from logic
errors. Though methods exist for testing digital circuits but testing of analog circuits is
still a problem. Mixed signal circuits are even more diff icult to test. A general and
eff icient solution for testing mixed-signal integrated circuits is still not available.
Functional test approach applied to test the functionali ty of analog and mixed-
signal integrated circuits is based on empirical development of a test set [2, 3]. This
approach needs a reasonably large number of sample circuits for collecting the test data.
The approach also does not have any inherent test metric to measure the achievement of a
test goal. Design for testabili ty (DFT) is another widely used method [4]. Oscill ation test
strategy is based on the DFT technique [4, 5], which gives good fault coverage and does
not require any test vectors. In this method, the complex analog circuit is partitioned into
functional building blocks such as an ampli fier, comparator, Schmitt trigger, filter,
voltage reference, oscill ator, phase-lock loop (PLL), etc., or a combination of these
blocks. During the test mode, each building block is converted into a circuit that
oscill ates. The oscill ation frequency, fOSC of each building block can be expressed as a
function of its components or performances. The oscill ation test method allows removing
the analog test vector generator and output evaluators, and consequently reduces the test
2
complexity, area overhead, and test cost. However, the method suffers from performance
degradation in complex integrated circuits since it is not usually possible to divide the
circuit into the fundamental blocks. Built i n self-test (BIST) method is based on
measuring the output data and calculating the performance of the system using an on-chip
circuitry [6,7]. This method reduces testing complexity of mixed-signal integrated
circuits by incorporating all or some of the testing circuitry on the sili con. An important
component of a mixed-signal BIST is a precision analog signal generator required for on-
chip stimulation. While the area overhead is kept to a minimum, these generators should
be capable of synthesizing high-precision single-and multitone signals with controllable
frequency and amplitude. This method also suffers from performance degradation and
does not cover physical defects.
The steady state or quiescent current (IDDQ) testing of CMOS integrated circuits is
known to be very eff icient for improving test quali ty [8, 9]. The test methodology based
on the observation of the quiescent current on power supply lines allows a good coverage
of physical defects such as gate-oxide shorts, floating gates and bridging faults. These
defects are neither well modeled by the classical fault models, nor detectable by
conventional logic tests. In addition, IDDQ testing can be used as a reliabili ty predictor due
to its abili ty to detect defects that do not yet involve faulty circuit behavior, but could be
transformed into functional failures at an early stage of circuit li fe. Thus, IDDQ testing
became a powerful complement to the conventional logic testing. In analog circuits, the
quiescent current, termed as IPS may be in the order of µA’s or mA’s [10]. Under the
fault conditions, the normal values of IPS may be increased, decreased or generally
3
distorted. Thus, fault detection can be accomplished by monitoring the IPS current
fluctuations using a current sensing circuit.
In this thesis, a simple built -in current sensor (BICS) is presented, which provides
a digital output for supply current monitoring and testing in mixed-signal circuits. The
proposed BICS is based on current differential ampli fier architecture providing a digital
output proportional to the IDDQ (IPS) current of the circuit under test. BICS is inserted in
series with the power supply or the ground of the CUT to detect abnormal IDDQ current in
the integrated circuit [5] as shown in Fig. 1. The new BICS requires less area and has less
performance degradation than reported earlier [11-18]. Furthermore, BICS requires
neither an external voltage reference nor a current reference since the reference is
generated on chip. It only requires two extra control pins, which control the mode of
operation of the BICS and one output pin. The proposed BICS has been designed to test a
Figure 2.30: Sample-and-hold response of the circuit of Fig. 2.26 obtained from post-layout SPICE simulations. Note. Input signal peak-to-peak voltage is 4V.
59
Multiplexer
TG - Switch
Capacitor - ArrayOp-amp
Unity gain buffer
Storage capacitor (CH)
Figure 2.31: Layout of a 10-bit charge-scaling DAC.
60
0
0.5
1
1.5
2
0 1000 2000 3000 4000 5000 6000
Time(us)
(a)
DAC output characteristics
0
0.5
1
1.5
2
2.5
0 256 512 768 1024
Digital Input Code
Ana
log
Out
put V
olta
ge
(b)
Figure.2.32 DAC output response for all (0000000000 – 1111111111) combinations of the input digital word.
61
Chapter 3
Built-in Current Sensor Design
This chapter focuses on IDDQ testing using built-in current sensors (BICS), the
design and implementation of the BICS in a 10-bit charge scaling DAC, the fault
simulation and detection methodology. It also discusses previously proposed schemes for
IDDQ testing and the important physical faults commonly seen in the design of integrated
circuits. Simulations and design considerations for the BICS are also discussed.
3.1 Current Testing in CMOS Integrated Circuits Using BICS
IDDQ testing of CMOS ICs is shown very efficient for improving test quality. The test
methodology based on the observation of quiescent current on power supply lines allows
a good coverage of physical defects such as gate oxide shorts, floating gates and bridging
faults, which are not very well modeled by the classic fault models, or undetectable by
conventional logic tests [1]. In addition, IDDQ testing can be used as a reliability predictor
due to its ability to detect defects that do not yet involve faulty circuit behavior, but could
be transformed into functional failures at an early stage of circuit life. Due to obvious
quality and reliability improvements, this approach became powerful complement to the
conventional logic testing. Quiescent current monitoring is considered as an interesting
and efficient technique for mixed-signal testing, where fault detection of analog parts
requires the precise measure of the IDDQ. In analog circuits, the quiescent current, termed
as IPS, may in the order of µAs or even mAs. Under fault conditions, the normal values of
IPS may be increased or decreased or generally distorted. Thus, fault detection can be
accomplished by monitoring the IPS current fluctuations. Figure 3.1 shows the fault free
IDDQ current in the quiescent state, which is about 1mA and shooting to 3mA when fault
62
is injected in the CUT [19]. Elevated IDDQ does not necessarily result in nonfunctional
behavior. However, data are available confirming that IDDQ failures will result in
reliability problems [33]. Considerable impact can be made towards achieving higher
quality by incorporating IDDQ testing along with conventional logic testing.
Built-in current sensors (BICS) have speed and resolution enhancements over
off-chip current sensors, mainly because the large transient currents in the output drivers
are by-passed and less parasitic are encountered. On chip current testing is both time-
efficient and sensitive. Moreover, on-chip current tests can also be used as an on-line
testing tool, and is important when components are to be used in high reliability systems.
For high speed and high sensitivity, unaffected by large pad currents, a fast built-in
current testing circuit is desired [34]. In the present work, a simple design of a built-in
current sensor is presented to detect bridging faults in a 10-bit charge scaling DAC. A
novel method has been introduced for the fault injection to simulate physical defects
present in a chip.
3.2 IDDQ Hardware
IDDQ measurements require analog circuitry that can ideally measure current
below 1 µA in the range 10 KHz- 33 MHz [35]. Different methodologies exist for IDDQ
testing. IDDQ testing can be classified in two groups, 1) external IDDQ testing and 2)
internal IDDQ testing. External IDDQ testing monitors power supply current through the
power pins of the integrated circuit package while internal IDDQ testing monitors power
supply current built-in current sensors [36].
63
+ 2.5v
-2.5vVERROR - SIGNAL
IREF
1mA
10US 20US 30US 40US 50US 60US 70US 80US
1mA
Time
3mA
IDDQ
IDEF
Figure 3.1: Faulty (IDEF) and fault-free (IREF) IDDQ current. Note: IREF is same as IDDQ. IDEF is the current in presence of faults. VERROR is the signal output.
64
3.2.1 External IDDQ Testing
The simplest form of hardware for testing is the automatic testing equipment
(ATE) precision measurement unit. It can be connected to the CUT’s power pin and used
to measure IDDQ. This strategy is acceptable if the number of measurements is less than
20; otherwise test time becomes expensive [1]. Figure 3.2 shows off-chip instrumentation
schematic. Figure 3.2 (a) illustrates an approach for an off-chip IDDQ instrumentation
[33]. The tester is connected in series with the VDD line of the CUT. CDD is the total
capacitance at the VDD node and includes that due to the IC itself and any capacitance
added by the tester and instrumentation circuit. The tester measures dVo/dt during the
quiescent time and can estimate IDDQ if CDD is known using [1].
IDDQ = CDD dVO/dt (3.1)
Figure 3.2 (b) shows another schematic for off-chip IDDQ current measurement [35]. An
off-chip sensor monitoring the power supply current is a simple implementation of IDDQ
testing and widely used in production testing. The transistor Q1 is ON only during
transient when the CUT is drawing large currents. To filter the high impedance noise at
high frequencies, a small capacitor C1 in the range of 2-2.5nF is added in between the
sense circuit and the CUT [37]. Once transients are settled, the Q1 is OFF and capacitor
C1 supplies the static current to the CUT. IDDQ is measured by the voltage drop across the
transistor Q1.
Off-chip current measurement technique has the ability to detect vast majority of
manufacturing defects, including those that are not detected by the traditional stuck-at
fault testing [34]. However, off-chip measurement techniques have speed and sensitivity
65
VDD IDD
TESTER
CDD
1pF
V0
CUT
.
Figure 3.2 (a): Off-chip IDDQ current measurement using an automatic test equipment.
CUT To powersupply
Tosample &hold
C1C1
Q1
Sense Circuit
n-MOS
Figure 3.2(b): Off-chip IDDQ current measurement.
66
limitations [38]. Low-current resolution is critical in detecting defects such as floating
gates, which do not cause large abnormal currents. Off-chip measurements may not
detect this small current due to its sensitivity limitations. Several other factors can
degrade off-chip IDDQ instrumentation. 1) All testers have current probes, which offer
significant capacitive loading at the power supply, causing a large voltage drop across it,
and lack in DC accuracy [1,20]. 2) The test board exists in a noisy electrical environment
and long leads are used and electromagnetic fields are high [35]. Current measurement is
slow and susceptible to static noise in the power supply bus. Considerable noise is
therefore introduced into the measurement. 3) Above all, the major portion of the IDDQ
current in CMOS VLSI chips is generated at the output pad circuits, and abnormal IDDQ
current is overshadowed by the output currents [36]. Owing to these limitations with off-
chip current measurements, the built-in current sensor is a preferred approach in many
applications. It can be integrated in to the CMOS design to test for physical faults in the
circuit.
3.2.2 Internal IDDQ Testing
The effectiveness of IDDQ testing can be enhanced if built-in current sensors are
applied on chip to monitor defect –related abnormal currents in the power supply buses
[34]. This testing technique applies on-chip current sensors that detect abnormal power
bus currents and overcomes the limitations of the off-chip IDDQ current measurements.
Essentially, this technique adds a BIC sensor in series with VDD or GND lines of the
circuit under test. A series of input stimuli is applied to the device under test while
monitoring the current of the power supply (VDD) or ground (GND) terminals in the
quiescent state conditions after the inputs have changed and prior to the next input change
67
[35]. Figure 3.3 shows the block diagram of the IDDQ testing with BICS. The many
advantages of BICS over the off-chip current testing or the ATE, include: reduction of
test equipment cost, increase of testing rate, improvement of the detectability and high
current sensing resolution [38].
Typically, sub-threshold current in the transistors, which are ‘off’ in a CMOS
static circuit should be negligibly small. However, in some cases, due to charge presence
in a gate oxide or latch-up, the sub-threshold current may be large enough to become an
essential component of IDDQ . The BICS can be designed to detect this current also.
3.3 Physical Faults in CMOS Integrated Circuits
In CMOS technology, the most commonly observed physical failures are bridges,
opens, stuck-at-faults and gate oxide shorts (GOS). These defects create indeterminate
logic levels at the defect site [1]. Very large-scale integrated circuits processing defects
cause shorts or break in one or more of the different conductive levels of the device [36].
We briefly discuss these physical defects that cause an increase in the quiescent current.
3.3.1 Open Faults
Figure 3.4 shows a 2-input NAND open circuit defect. Logic gate inputs that are
unconnected or floating inputs are usually in high impedance or floating node-state and
cause elevated IDDQ [34]. In Fig. 3.4, node VN is in the floating node-state. For an open
defect, a floating gate may assume a voltage because of parasitic capacitances and cause
the transistor to be partially conducting [37]. Hence, a single floating gate may not cause
a logical malfunction. It may cause only additional circuit delay and abnormal bus current
[34]. In Fig. 3.4, when the node voltage (VN), reaches a steady state value, then the output
voltage correspondingly exhibits a logically stuck behavior and this output value can be
68
PMOSBLOCK
NMOSBLOCK
BICS
INPUTS
OUTPUT
PASS/FAIL
CUT
Figure 3.3: Block diagram of IDDQ testing.
69
VDD
Q1 Q2
Q3
Q4
VA
VN
V0
Figure 3.4: Open circuit defect.
70
weak or strong logic voltage. Open faults, however, may cause only a small rise in IDDQ
current, which the off-chip current sensor may not detect because of its low-resolution
[1]. It can be detected using BIC sensors. An open source or open drain terminal in a
transistor may also cause additional power-bus current for certain input states. In this
scope of work, we deal with bridging faults.
3.3.2 Bridging Faults
The short circuit faults in very large-scale integrated circuits are popularly termed
as bridging faults. When IDDQ measurements are used, a bridge is detected if the two nets,
which compromise it, have opposite logic values in the fault-free circuit [37] and are
connected by a bridge due to the introduction of the fault in the circuit. Bridging faults
can appear either at the logical output of a gate or at the transistor nodes internal to a
gate. Inter-gate bridges between the outputs of independent logic gates can also occur.
Bridging fault could be between the following nodes 1) drain and source, 2) drain and
gate, 3) source and gate, and 4) bulk and gate. Examples of bridging fault are shown in
Figs. 3.5 and 3.6, respectively. Figure 3.5 shows example of possible drain to source
bridging faults in an inverter chain in the form of low resistance bridges (R1, R2 and R4).
Resistance bridge, R3 is an example of inter-gate bridge. Figure 3.6 shows examples of
gate to source and gate to drain bridges in an NAND gate circuit.
Bridging faults can be modeled between adjacent metal lines in a 10-bit
charge scaling DAC at different conducting levels. We have introduced faults in the 10-
bit charge scaling DAC by using “fault-injection transistors” instead of hard metal shorts
invented in our group [19]. The introduction of a fault via the “fault-injection”
71
VDD
VSSPath from VDD to ground
V1 Vo
R2
R1
R3 R4
Figure 3.5: Drain-source and inner-gate bridging faults in an inverter chain.
72
VDD
VA
VB
V0
Bridge 1: Drain-gate
Bridge 2 : Gate-source
Figure 3.6: Bridging defect.
73
transistor enables the 10-bit DAC to function fault-free under the normal conditions. The
faults considered include source-drain bridge, drain-gate bridge and source-gate bridge.
Bridging defect cannot be modeled by the stuck-at model approach, since a bridge often
does not behave as a permanent stuck node to a logic value [37]. IDDQ testing using BICS
is an effective method of detecting bridging shorts.
3.3.3 Gate-Oxide Short Defects
Gate-oxide short (GOS) defects occur frequently in CMOS technology. The
principle physical reasons for GOS are the breakdown of the gate oxide and the
manufacturing spot defects in lithography and processes on the active area and
polysilicon masks [38]. Figure 3.7 illustrates the circuit level gate oxide short defect
model [37]. These defects can be seen as short-circuits between the gate electrode and the
conducting channel of the device through SiO2 . GOS short causes an undesirable current
injection in to the channel [36, 38]. This current injection forces a substantial increase in
the quiescent current. The diode-resistor combination could be used to model the
rectifying behavior of the new current path introduced by the defect [38].
These defects are unlikely to produce logical errors, but cause important deviation
of parametric specification especially important in low power equipment [39].
3.4 Definition and Description of IDDQ of a Faulty Circuit
IDDQ’s definition is the level of power supply current in a CMOS circuit when all
the nodes are in a quiescent state. Static CMOS circuits use very little power and at stand-
by or quiescent state, it draws practically negligible leakage current [35]. In steady state,
there should not be a current path between VDD and GND path. Ideally, in a static CMOS
circuit, quiescent current should be zero except for associated p-n junction leakage
74
SourceGate
Drain
n+ n+
p - Si
(a)
S D
G
B
Rs
(b)
Figure 3.7(a): Gate-oxide-short (GOS) in a MOSFET. Figure 3.7(b). Equivalent circuit model. RS is the effective resistance of the short. B models the rectifying behavior of new current path introduced by the defect.
75
currents. Any abnormal elevation of current should indicate presence of defects. To
assure low stand-by power consumption, many CMOS integrated circuit manufacturers
include IDDQ testing with other traditional DC parametric tests [36].
3.4.1 Description of IDDQ of a Faulty Inverter
Figure 3.8 shows how an IDDQ test can identify defects. The current in static
CMOS is not constant during transient [40]. When an output transition occurs, a peak of
IDDQ current is observed. This peak is due to charging and discharging of the load
capacitance at the output circuit and corresponds to the short circuit. When the transition
is completed, the circuit is in the quiescent state. IDDQ is very sensitive to physical faults
in the circuit. In mixed-signal CMOS circuits such as data converters. IDDQ is around
1mA, which increases in presence of defects.
Let us evaluate current testing in CMOS circuits in the presence of bridging
faults. Two nodes connected by a bridge must be driven to opposite logic levels under
fault-free conditions for bridging fault to occur. In Fig.3.8, a typical bridge is one
between the node VO and VDD. To detect this defect, input pattern must drive the node
VO1 to the logic low value (‘0’), as this node is assumed to be bridged with the power rail.
Thus, a path from power to ground appears allowing the existence of an abnormal high
IDDQ current. IDDQ value is directly dependent on the resistance offered by the conducting
path and hence on the size of the transistors in the conducting path. The presence of the
physical fault causing the high abnormal current can be effectively detected by IDDQ
testing using BICS. A set of realistic bridges have been modeled between adjacent
metal lines in a 10-bit charge scaling DAC at three different (conducting levels), to
76
VDD
VSSPath from VDD to ground
V1
(IDDQ RB), V
V01 V02
RB
Figure 3.8: Bridging fault causing IDDQRB drop and a path to the ground.
77
examine the effect on the value of IDDQ and detect the presence of the fault using the
BICS.
3.5 The Design Considerations of BICS
A simple design of a BIC sensor built into the 10-bit charge scaling DAC is
presented using the current mode design. It determines whether the circuit quiescent
current is below or above a threshold level. Previously proposed schemes and the
characteristics required for a good BICS are discussed briefly in this section.
3.5.1 Previously Proposed Schemes
Different BICS schemes have been proposed for detection of the abnormal IDDQ
current and the physical faults commonly observed. While most BICS designs
concentrate on mere detection of the fault, some can detect the location of the fault as
well [41]. The entire design is divided into n sub blocks (SB) where n equals the number
of outputs. The divided SB’s are checked individually through their corresponding output
and a faulty area is easily detected by observing the outputs. The performance impact of a
BICS on a circuit under test (CUT) is the key issue to be considered when designing
BICS. Insertion of the BIC sensor between CUT and GND involves series voltages, and
these voltages could degrade the performance of the CUT [40,11]. A large number of
earlier BICS are based on voltage amplifiers such as differential amplifiers or sense
amplifiers. The stability of the BICS is limited in this case since the quiescent point (Q-
point) of an amplifier may not be stable and can vary with the change of dc supply
voltage, VDD. The detection time and hardware overhead is increased due to the extra
hardware required to stabilize the Q-point.
78
To overcome problems of slow detecting time, resolution, instability of the BICS
and large impact on the CUT performance, the current-mode circuit design approach has
been adopted using a single power supply. In this work, simple design of a BICS
employing current mirrors and current differential amplifier has been proposed. It has
minimum area over head in the chip and no impact on over all performance.
Characteristics required for a good BIC sensor are [39]:
1. Detection of abnormal static and dynamic characteristics of the CUT.
2. Minimal disturbance of the static and dynamic characteristics of the CUT.
3. The design should be simple and compact to minimize the additional area
necessary to build it.
4. The IDDQ test should have good resolution and speed.
3.5.2 The Design of the BICS
Figure 3.9 shows the CMOS circuit diagram of the built-in current sensor. It
consists of a current differential amplifier (M2, M3), two current mirror pairs (M1, M2 and
M3, M4) and an inverter. The n-MOS current mirror (M1, M2) is used to mirror the current
from the constant current source which is used as the reference current IREF for the BICS.
The current mirror (M3, M4) is used to mirror the difference current (IDEF-IREF) to the
current inverter, which acts as a current comparator. The differential pair (M2, M3)
calculates the difference current between the reference current IREF and the defective
current IDEF from the CUT. The W/L size of the n-MOS current mirrors (M1, M2) is set to
27/1.6 and (M3, M4) is set to 72/1.6. Therefore ID3 = IDEF-IREF. The constant reference
current is set to approximately the same value as the quiescent state current when the
79
CUT
VENABLE
IREF EXTIDEF
IDEF - IREF OUTPUT
M0 M1M2 M3 M4
M5
M6
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
27/1.627/1.6
60/1.6
150/1.6
25/1.6
72/1.6 72/1.6
18/1.6
6/1.6
IREF( PASS/ FAIL )
Figure 3.9: CMOS built-in current sensor circuit.
80
CUT is fault free. In the present design, the reference current, IREF is set to 1mA. The
output inverter buffer has an aspect ratio ((W/L)P / (W/L)N) of 6/1 to counter capacitive
parasitics at the output node and detect the presence of the physical fault through the
PASS/FAIL flag at the output.
The proposed scheme operates in two modes: the normal mode and the test mode.
The mode of operation is controlled by ‘VENABLE’ signal applied to the gate of transistor
M0. The W/L size of the M0 is 60/1.6. This enables the 10-bit charge scaling DAC, which
is the CUT to operate as fault-free in the normal mode of operation. Further explanation
on the design is provided in section 3.6.
3.6 The Implementation of BICS
Figure 3.10 explains the basic structure of the BIC sensor connected between
CUT and GND in IDDQ testing. The BICS is inserted in series with GND or VSS line of
the circuit under test. The proposed BICS works in two modes: the normal mode and the
test mode. The mode of operation is decided by the VENABLE signal. In the normal mode
(VENABLE = ‘1’), the BICS is isolated from the CUT. In the test mode (VENABLE = ‘0’), the
quiescent current from the CUT is diverted in to the BICS and compared with reference
current to detect the presence of the fault.
3.6.1 BICS in Normal Mode
During the normal operation, the signal ‘VENABLE’ is at logic ‘1’ and all the IDD
current flows to ground through M0 (control transistor). When switching occurs, M0 is
turned on. Therefore, the n-MOS current mirrors have no effect on dynamic current. It
follows that the BICS’s output is not affected by the dynamic current. Thus, in the normal
mode, the BICS is totally isolated from the 10-bit DAC (CUT). Since in normal mode the
81
VIN
CUT
Output
VDD
PMOSBLOCK
NMOSBLOCK
VENABLE
IREF EXTIDEF
IDEF - IREF
OUTPUT
M0 M1M2 M3 M4
M5
M6
60/1.6
18/1.6
6/1.6
27/1.6
27/1.672/1.6
72/1.6
150/25
VDD
VDD
VSS
VSS
VSS
IREFPASS/FAIL
Figure.3.10: CMOS built-in current sensor with CUT.
82
current coming from the CUT is same as the reference current the difference current IDEF
– IREF becomes negligible and the output of the BICS is at logic ‘0’. In the normal mode,
it cannot detect the presence of any physical fault in the CUT.
Since the BICS is inserted in series with GND line of the CUT, it causes a voltage
drop and large capacitance between the CUT and the substrate. These effects cause
performance degradation and ground level shift. To reduce these extra undesirable
effects, an extra pin EXT is added to the proposed BICS. Pin EXT is connected to the
drain of transistor M0. In the test mode, it is left floating. In the normal mode, EXT gets
connected to logic ‘0’. In the normal mode, since the EXT pin is grounded by passing the
BICS, the disturbance of the ground level shift during normal operation of the circuit
never happens. Therefore, there is no impact on the performance of the DAC, while the
BICS is in normal mode.
3.6.2 BICS in Test Mode
During the test mode, the ‘VENABLE’ signal is at logic ‘0’. The IDDQ current from
the CUT is diverted by the BICS and the n-MOS current mirror pair replicates the
reference current to the current differential amplifier which assigned a value nearly same
as the fault-free current. This mirrored reference current is compared with defective
current IDEF current coming from the CUT. The output of the current comparator, which
is in the form of PASS/FAIL, will detect the presence of the fault.
The difference current is converted to a voltage by mirroring it and getting the
drop of VDS across the transistor M4. In the test mode, the difference current is large
which turns-ON M4 heavily and forces its output node pulled-down to logic ‘0’ and is
detected as PASS/FAIL output ‘1’, indicating presence of defects in CUT. In the testing
83
mode, EXT pin is floating. The ‘VENABLE’ signal is connected to GND and M0 is off. The
timing diagram and detailed analysis of BICS are explained in the following sections.
3.6.3 Detailed Analysis of the BICS
The current differential amplifier and the current mirror are most important parts
of the proposed BICS. Performance of the current mirror greatly affects the BICS’s
ability to detect abnormal current due to physical defects. The current mirror has a
property that, in a constant current stage, the reference current in one branch of the circuit
is mirrored in the other branch [22]. The current differential amplifier on the other hand
receives reference current IREF one input, and the defective current IDEF from CUT as the
other input. The differential amplifier calculates the difference between the two currents.
The other n-MOS current mirror mirrors the difference current calculated by the current
differential amplifier to the inverter (M4, M6) which acts as comparator (Fig.3.10). The
output of the current comparator is used as the PASS/FAIL flag. If the IDDQ is greater
than the reference current, we presume there are defects within the functional circuit. If
the IDEF is less than the IREF, we assume that the functional circuit is free from physical
defects that induce abnormal IDDQ current. Functionally, in inverter, ID = IREF – IDEF . If
IDEF > IREF, then the PASS/FAIL output shows a logic ‘1’. Conversely if IDEF < IREF, a
logic ‘0’ will appear at the PASS/FAIL output. Input impedance of the inverter is very
large [23]. Because of the high input impedance of the current comparator and the
utilization of the current mirror along with current differential amplifier, even a very
small difference between IDEF and IREF can be distinguished. That means the BICS can
achieve a high resolution. Several SPICE simulations were performed to determine the
functionality and performance of the BICS design.
84
3.7 Layout, Simulation and Timing Diagrams for BICS
3.7.1 Current Mirror Circuit
The simplest form of constant current source consists of current mirrors
constructed by passing a reference current through a diode-connected (gate tied to drain)
transistor as shown in Fig. 3.11. The voltage developed across the diode-connected
transistor provides the constant current output. The current ratio IOUT / IREF is determined
by the aspect ratio of the transistors in the current mirror circuit design. Both n-MOS
transistors have the same W/L ratio of 27/1.6. The output current of the current mirror
circuit mirrors the input current to it. Therefore,
IOUT / IREF = 1 (22)
In our design,
IOUT = IREF =1mA.
3.7.2 Current Differential Amplifier
The current differential amplifier used in our design is the most important part of
the BICS. The current differential amplifier calculates the difference between the
reference current IREF and defective current IDEF. Figure 3.12 shows the circuit diagram of
differential amplifier. The currents IREF (i1) and IDEF (i2) are the input currents of the
amplifier. The difference current (IDEF – IREF or i2 – i1) is calculated and mirrored to
output of the current differential amplifier. The BICS design comprises of two n-MOS.
current mirrors and a current differential amplifier. One n-MOS current mirror provides
the reference current as one input to the differential amplifier and the other input current
comes from the CUT. The other n-MOS current mirror replicates the difference current to
85
M1 M2
IREF
IOUT
Figure 3.11: n-MOS current mirror circuit.
86
M1 M2 M3M4
VDD
VSS
i1i2
i2 - i1 i2 - i1
27/1.627/1.6
72/1.6
72/1.6
i1i2 - i1
Figure 3.12: Schematic of a current differential amplifier.
87
the output inverter which acts as a current comparator. The proper design of the current
mirrors is most crucial for working of the BICS. The input impedance of the current
differential amplifier is simply the small-signal resistance of a diode connected
MOSFET, and is given by
Rin = 1/ gm. (23)
The current differential amplifier finds applications in both low-power and high-speed
circuit design.
3.7.3 BICS
Figure 3.9 shows the circuit diagram of the BICS. It comprises of two current
differential amplifiers and a current comparator. It operates in two modes: 1) normal
mode and 2) test mode. The test signal is applied to an n-MOS transistor, M0 (W/L =
60/1.6), which decides the mode of operation. When the test signal is ‘0’, the BICS is in
the test mode. When the test signal is at logic ‘1’, the BICS is isolated from the CUT and
its output is at logic ‘0’. The output inverter buffer has an aspect ratio ((W/L)P/(W/L)N) of
6/1. Figure 3.13 shows the layout of the BICS of the circuit shown in the Fig. 3.9.
3.8 Fault Detection, Simulation and Testing
The primary reason for a fault is a defect in the integrated circuit. A manufacturing defect
causes unacceptable discrepancy between its expected performance at circuit design and
actual IC performance after physical realization [34]. A defect may be any spot of
missing or extra material that may occur in any integrated circuit layer.
Two nodes are connected if there is at least one path of conducting transistors
88
Figure 3.13: Layout of a built-in current sensor circuit.
IREF IDEF
VENABLE
EXT
BICS O/P
VSS
VDD
89
between them. If the two nodes are at opposite potentials under fault-free conditions, a
conducting path between them will increase the IDDQ current due to fault in the circuit.
After transient switching, each node in a digital circuit is one of the following four states
1. VDD state: This state occurs when the node is connected to VDD.
2. GND state: This state occurs when the node is connected to GND.
3. Z state: The high-impedance state occurs when the node is neither VDD nor GND
connected.
4. X state: This state occurs when the node is both VDD-connected and GND-connected
[34].
The ‘X’ state should never occur in fault-free CMOS integrated circuits. Many
defects cause an X state to occur in CMOS integrated circuits. Thus, we can view testing
as a way to detect the X state, which causes detectable abnormal steady state current.
Bridging faults have been induced in the DAC at various conducting levels using a fault-
injection transistor (FIT), discussed further ahead, which cause abnormal elevation of the
steady state current.
3.8.1 Fault-Injection Transistor
In this work, four bridging faults have been placed in the 10-bit DAC design using fault-
injection n-MOS transistors. Activating the fault-injection transistor activates the fault.
The use of a fault-injection transistor for the fault simulation prevents permanent damage
to the 10-bit DAC by introduction of a physical metal short. This enables the operation of
the DAC without any performance degradation in the normal mode. Figure 3.14 (a)
shows the fault-injection transistor. To create an internal bridging fault, the fault-injection
transistor is connected to opposite potentials. When the gate of fault-injection transistor
90
ME) is connected to VDD, a low resistance path is created between its drain and source
nodes and a path from VDD to GND is formed. In the Fig. 3.14(b), an internal bridging
fault is created in the CMOS inverter between the drain and source nodes using the fault-
injection transistor. Logic ‘0’ is applied at the input of the inverter. Therefore, the output
of the inverter is at logic ‘1’ or VDD. When the logic ‘1’ is applied to the gate (VE) of the
n-MOS fault-injection transistor (ME), it turns on. This causes a low resistance path
between the output of the inverter and the VSS. This gives rise to an excessive IDDQ
current as a path from VDD to GND is created, which can be detected by the BICS.
Figure 3.15 shows the layout of a 10-bit charge scaling DAC with BICS. The area
of the DAC alone is 692 × 502 µm2. The entire area of the CUT along with BICS is 692 ×
516 µm2. Therefore the BICS occupies only 242 × 40 µm2 of the entire chip area. Four
defects have been introduced using fault-injection transistors. The n-MOS fault-injection
transistor (ME) is designed for W/L equal to 4.5/1.6. The fault-injection transistors are
activated externally using ERROR signals VE1, VE2, VE3 and VE4, respectively. Error
signal VE1 is applied to the gate of the fault-injection transistor in defect 1, which forms a
short between the source and drain in the operational amplifier circuit shown in Fig. 3.16.
Error signal VE2 is applied to the gate of the fault-injection transistor in defect 2, which
forms a short between the drain and gate in the unity gain buffer circuit shown in Fig.
3.17 for S/H. Error signal VE3 is applied to the gate of the fault-injection transistor in
defect 3, which forms a short between the gate and the source in the multiplexer circuit
shown in Fig. 3.18. Error signal VE4 is applied to the gate of the fault-injection transistor
in defect 4, which forms a short between the gate and the substrate in the multiplexer
Figure 4.15: Simulated BICS output of the circuit of Fig.3.19 when Error-signal-4 for defect-4 is activated.
115
-
+
CC2C4C8C16C32C64C128C256C512C
CAPACITOR ARRAY ARCHITECTURE OPAMP
A = 1-
+
CH
Sample and Hold Input
+
-
Vo
TG SWITCHUNITY-GAIN
BUFFERSTO RAGE
CAPACITO R
CIRCUITRY TO GENERATE DIGITAL INPUT WO RD
VREF
Control Signal
Output of Multiplexer
VDD
VSS
CC =30FFVout
+ Vin
- Vin
M9 M3 M4
M5
M6
M7M8
M1 M2
W/L=45/3
W/L=45/3W/L=45/3
W/L=90/3
W/L=90/3W/L=90/3
W/L=90/3 W/L=90/3
W/L=9.6/3
Fault-Injection Transistor (S-D)
VE
W/L=4.5/1.6
VDD
VSS
CC =30FFVout
+ Vin
- Vin
M9 M3 M4
M5
M6
M7M8
M1 M2
W/L=45/3
W/L=45/3W/L=45/3
W/L=90/3
W/L=90/3W/L=90/3
W/L=90/3 W/L=90/3
W/L=9.6/3
Fault-Injection Transistor (G-D)
W/L=4.5/1.6
VE
VREF
Control Signal
Output of Multiplexer
Fault Injection Transistor ( G-S)
VE
VREF
Control Signal
Output of Multiplexer
Fault Injection Transistor ( Sub-S)
VE
W/L=4.5/1.6
Figure 4.16: CMOS circuit diagram of 10-bit charge scaling DAC with four fault injection transistors distributed across different parts of the circuit.
Figure 4.17: Simulated BICS output with defects induced using fault injection transistors.
117
BICS when four FIT’s are activated. In Fig. 4.17, when the VENABLE is ‘high’ the BICS is
disabled and when it is low the BICS is enabled. When the BICS is enabled and if there is
any Error-Signal going ‘high’ the BICS detects the fault. Table-1 shows the faulty IDDQ
values obtained for the different kinds of faults are injected in the chip. Figure 4.18
shows the wave forms obtained form the logic Analyzer. The error signal is kept ‘high’
and the BICS is tested for its operation in the normal mode and test mode. When the
VENABLE is ‘low’, the BICS is in the test mode and if the error signal is ‘high’,
PASS/FAIL gives logic ‘1’ and thus, it detects the fault induced. When the VENABLE is
‘low’, the BICS is in the normal mode, PASS/FAIL gives logic ‘0’ thus, no fault is
detected.
Table 4.1 summarizes calculated (simulated) and measured IDDQ values
corresponding to four different faults distributed across the chip. The reference current, is
IREF is 1mA. Table 4.1 shows that in the presence of faults IDDQ reaches to 3mA. The
calculated and measured IDDQ values are in close agreement. Table 4.2 summarizes a
comparative study of design of previously reported BICS with the present BICS design.
Our BICS design uses only seven transistors and an inverter buffer. The BICS requires
neither an external voltage source nor a current source. Further more, the BICS does not
require clocks.
118
Figure 4.18: HP 1660CS logic analyzer test results on a fabricated CMOS 10-bit charge scaling DAC showing the performance of BICS in normal and test modes.
119
Table 4.1 Theoretical and measured IDDQ for different fault types
Note: The reference current, IREF =1mA
Defect Faulty IDDQ (Sim) mA
Faulty IDDQ (Meas) mA
Source-Drain short 3.00 mA 2.8 mA Gate-Drain short 2.8 mA 2.7 mA Gate-Source short 2.7 mA 2.6 mA Gate-oxide short 2.5 mA 2.2 mA
120
Table 4.2: Comparison of built-in-current sensors
# Device Clock Signal Mode Select Control Pin
Output Pin
Maly’s Design[13]
TR: 10 Inv: 2
Nand: 1
Single Clock Y 5 1
Miura’s Design[15]
TR: 16 R: 1 C: 1
Not Used Not Reported
3 1
Shen’ Design[16]
TR: 13 Diode: 1
Two Phase Clock
N 3 2
Tang’s Design[38]
TR: 24 R: 1
Single Clock N 3 1
Favalli’s Design[14]
TR: 2*gates+1
Not Used Y 1 1
Nigh’s Design[17]
TR: 13 Inv: 1
Two Phase Clock
Y 3 1
Proposed Design
TR: 7 Inv: 1
Not Used Y 2 1
Note: Mode Select: Normal Mode / Test Mode, Control Pins: VENABLE and EXT.
121
Chapter 5
Conclusion and Scope of Future Work
A 10-bit DAC using charge-scaling architecture is designed in standard 1.5 µm n-
well CMOS technology. The DAC is tested with all 1024 digital input word
combinations. The unit step is about 1.9mV. DAC operates with ±2.5V supply voltages.
The reference voltage used is 2V for a ‘HIGH’ and ground (0V) for a ‘LOW’. The 10-bit
DAC is used as a circuit under test (CUT). The CUT is tested with a novel built -in
current sensor (BICS), which has a very negligible impact on the performance of the
circuit under test.
The present BICS works in two-modes: normal mode and the test mode. In the
normal mode, BICS is isolated from the CUT due to which there is no performance
degradation of the circuit under test. In the testing mode, BICS detects the abnormal
current caused by permanent manufacturing defects. The BICS requires neither an
external voltage source nor a current source. The present BICS is designed with only
seven transistors and an inverter buffer. The present BICS design which is based on
current comparison, combined with the novel fault-injection technique, can be used for
IDDQ testing of other type of data converters of the type shown in Fig. 5.1 and is
suggested for future work. The built -in current sensor of the present work requires less
area and is more eff icient than the conventional current sensors. It is shown that with the
use of a novel fault injection technique, combined with a built -in current sensor design,
has significantly improved the testing of mixed signal integrated circuits
122
First O rder M o dulatorA nalog Input
O versampling C lock
D ecimator
1-B it D igital O utput
8-B itD igital O utput
(a)
1-B it D igital O utputIntegrator 1-B it A DC
1-B it D A C
A nalog Input
(b)
Figure 5.1: Block diagram of a sigma-delta ADC
123
Bibliography
[1] R. Rajsuman, Iddq Testing for CMOS VLSI, Artech House, 1995.
[2] C.Y. Chao, H. J. Lin and L. Milor, “Optimal testing of VLSI analog circuits,” IEEE. Tran. on Computer-Aided Design of Integrated Circuits and Systems, vol.16, Jan. 1997. pp. 58-77.
[3] C.Y. Pan and K.T. Cheng, “Pseudorandom testing for mixed-signal circuits,”
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol 16, Oct.1997. pp. 1173-1185.
[4] K. Arabi and B. Kaminska, “Design for testability of embedded integrated
operational amplifiers,” IEEE J. Solid-State Circuits, vol. 33, April.1998. pp. 573-581.
[5] K. Arabi and B. Kaminska, “Testing analog and mixed-signal integrated
circuits using oscillation-test method,” IEEE. Trans. on Computer-Aided Design of Integrated Circuits and Systems, July 1997, pp. 745-753.
[6] B. Dufort and G. W Roberts, “On-chip analog signal generation for mixed-
signal built in self-test,” IEEE J. Solid-State Circuits, vol. 34, March 1999. pp. 318-330.
[7] K. Arabi, B. Kaminska and J. Rzeszut, “A new built-in-self-test approach for
digital-to-analog and analog-to-digital converters,” Proc. 12th Int. Conf. on Computer-Aided-Design, Nov. 1994. pp. 491-494.
[8] B.D. Brown. R.D. McLeod, “Built-in current mode circuits for Iddq
monitoring,” Proc. 1993 IEEE Custom Integrated Circuit Conference, 1993, pp. 30.6.1-4.
[9] C.W. Hsue and C. J. Lin, “Built-in current sensor for Iddq test in CMOS,”
Proc. Int. Test Conf., 1993, pp. 635-641. [10] S. Siskos, Th. Laopoulos, A. A. Hatzopoulos and M. Bafleur, “A current
conveyor based BIC sensor for current monitoring in mixed-signal circuits,” Proc. ICECS, 1996, pp. 1210-1212.
[11] J.B. Kim, S. J. Hong, and J. Kim, “Design of built-in current sensor for IDDQ
testing,” IEEE J. Solid-State Circuits, vol. 33, Aug. 1998, pp. 1266-1272.
[12] T.Y. Chang, C. C. Wang, and J. B. Hsu, “Two schemes for detecting CMOS analog faults,” IEEE J. Solid-State Circuits, vol. 27, Feb. 1992. pp. 229-233.
124
[13] W. Maly and M. Patyra, “Built-in current testing,” IEEE J. Solid-State Circuits, vol. 27, May. 1992, pp. 425-428.
[14] M. Favalli, P. Olivo, M. Damiani, and B. Ricco, “Novel design for testability
schemes for CMOS IC’s,” IEEE J. Solid-State Circuits, vol. 25, Oct. 1990, pp. 1239-1246.
[15] Y. Miura and K. Kinoshita, “Circuit design for built-in current testing,” Proc.
Int. Test. Conf., Nov. 1992, pp. 873-881. [16] T.L. Shen, J. C. Daly, and J. C. Lo, “A 2-ns detecting time, 2-µm CMOS
built-in current sensing circuit,” IEEE J. Solid-State Circuits, vol. 28, Jan. 1993. pp. 72-77.
[17] P. Nigh and W. Maly, “A self-testing ALU using built-in current sensing,”
Proc. 1989 IEEE Custom Integrated Circuit Conference, 1989, pp. 22.1.1-22.1.4.
[18] W. Maly and P. Nigh, “Built-in current testing-feasibility study,” in Proc. Int.
Conf. Computer. –Aided Design, Nov.1988, pp. 340-343. [19] A. Srivastava and S. Aluri, “A Novel Approach to IDDQ testing of mixed-
signal integrated circuits,” Proc. of 45th IEEE Int. Midwest Symposium on Circuits and Systems, 2002, pp. II 270-273.
[20] S.D. McEuen “IDDQ benefits”, Proc. of 1991 IEEE VLSI Test Symposium,
paper 14.1, 1991, pp. 285-290. [21] J. Argüelles, M. Martínez and S. Bracho, “Dynamic IDD test circuit for
mixed signal ICs,” Electronic Letters, vol. 30, no. 6, 17th March 1994, pp. 485-486.
[22] K. Arabi and B. Kaminska, “Design and realization of an accurate built-in
current sensor for on-line power dissipation measurement and IDDQ testing,” Proceedings International Test Conference, 1997, pp. 578-586.
[23] Y. Maidon, Y. Deval, P. Fouillat, J. Tomas, J. P. Dom; “On-chip IDDX
Sensor”, Proc. of. IEEE IDDQ Workshop, 1996, pp. 64-67. [24] J. Segura, I.D. Paul, M. Roca, E. Isern, C.J. Hawkins, “Experimental analysis
of transient current testing based on charge observation,” Electronics Letters, vol. 35, no. 6, 18th March 1999, pp. 441-447.
[25] I. Pecuh. M. Margala and V. Stopjakova, “1.5 Volts Iddq/Iddt current
monitor,” Proc. of the 1999 IEEE Canadian Conference on Electrical and Computer Engineering, May 9-12, 1999, pp. 472-476.
125
[26] V. Stopjaková, H. Manhaeve and M. Sidiropulos, “On-chip transient current monitor for testing of low-voltage CMOS IC,” Proc. Design, Automation and Test conference and exhibition in Europe, March 1999, pp. 538-542.
Simulation, IEEE Press 1998. [28] R.L. Geiger, P.E. Allen, N.R. Strader VLSI Design Techniques for Analog and
Digital Circuits, McGraw-Hill, 1990. [29] P.E. Allen and D.R Holberg, CMOS Analog Circuit Design, Second Edition,
Oxford University Press, 2002. [30] R.T. Howe and C.G. Sodini Microelectronics: A Integrated Approach,
Prentice Hall, NJ, 1997. [31] Y. Tsividis, Mixed Analog-Digital VLSI Devices and Technology, McGraw-
Hill, 1996. [32] J.P. UYEMURA, Fundamentals of MOS Digital Integrated Circuits, Addison-
Wesley, 1988. [33] J.M. Soden, C.F. Hawkins, R.K. Gulati and W. Mao “IDDQ testing: a review,”
Journal of Electronic Testing: Theory And Applications, vol.3, 1992, pp. 291-303.
[34] P. Nigh, W. Maly, “Test generation for current testing,” IEEE Design and
Test of Computers, Feb. 1990, pp. 26-38. [35] S.D McEuen, “Reliability benefits of IDDQ,” J. of Electronic Testing: Theory
and Application, Vol.3, 1992, pp-904-910. [36] A. Rubio, J. Figueras and J. Segura, “Quiescent current sensor circuits in
digital VLSI CMOS testing,” Electronics Letters, vol. 26, No.15, 19th July 1990, pp. 1204-1205.
[37] J.A. Segura, V.H. Champac, R.R. Montanes, J. Figueras and J.A. Rubio,
“Quiescent current analysis and experimentation of defective CMOS circuits,” J. of Electronic Testing: Theory and Applications, Vol.3, 1992, pp. 337-346.
[38] K.J. Lee and J.J. Tang, “A built-in current sensor based on current-mode
design,” IEEE Transactions on Circuits and Systems-II Analog and Digital Signal Processing, Vol. 45, No. 1, Jan.1998, pp. 133-137.
[39] J. Rius and J. Figueras, “Proportional BIC sensor for current testing,” J.
Electronic Testing: Theory and Applications, Vol.3, 1992, pp. 387-396.
126
[40] T.L. Shen, J. C. Daly, and J. C. Lo, “On Chip current sensing circuit for CMOS VLSI,” Proc. IEEE VLSI Test Symposium, paper 16.2, 1992, pp. 309-314.
[41] C. Hwang, M. Ismail, J.E. DeGroat, “On chip IDDQ testability schemes for
detecting multiple faults in CMOS IC’s,” IEEE J. of Solid State Circuits, vol. 31, No.5, May 1996, pp. 732-739.
[42] www.mosis.edu.
127
Appendix A
SPICE LEVEL 3 MOS MODEL Parameters for standard n-well CMOS Technology [42]
ABSTRACT To obtain a high resolution CMOS current-steering digital- to-analog converter, the matching behavior of the current source transistors is one of the key issues in the design. At this moment, these matching properties are taken into account by the use of time consuming and CPU intensive Monte Carlo simulations. In this paper a formula is derived that allows to accurately describe the impact of the mismatch on the INL (integral non-linearity) yield of current-steering D/A converters without any loss of design time.
1. INTRODUCTION
The evolution in the field of wireless communications and the mixed signal area pushes the designer to put an increasing amount of effort in the integration of digital and analog systems on one chip. Consequently, the interface between these systems is becoming one of the most challenging blocks to design in the telecommunication devices of today. The demand for high performance digital-to-analog converters - with applications in the area of e.g. video, HDTV and GSM - has strongly increased.
Nowadays CMOS current-steering D/A converters are frequently used for such applications since these circuits can be implemented using a small silicon area (in comparison with resistor ladder based implementations) and can be easily integrated in fully digital CMOS technologies implying a considerable cost reduction. However, a current-steering D/A converter falls into the category of circuits which are made using a large number of identical building blocks (current sources) and therefore its most important specifications are dependent on the matching behavior of these blocks. It is important to be able to determine the number of functional current-steering D/A converters as a function of the matching properties of the current sources.
In section 2, the yield estimations found in open literature are evaluated and their pro’s and contra’s are discussed. In the following section a new yield model will be presented that in a minimum of time gives the wanted result. Finally a conclusion will be formulated in section 4.
2. INL-YIELD ESTIMATION IN LITERATURE
2.1 Introduction
Due to the mismatch of the current source transistors, the INL (integral non-linearity) specification of different D/A converters made in the same process technology will vary randomly. It is therefore important to be able to predict this specification within certain boundaries. For this purpose, the concept of the D/A converter’s INL-yield has been introduced. This yield figure is defined as the percentage of functional D/A converters with an INL specification smaller than half an LSB (least significant bit).
In this section analytical expressions for the D/A converter’s INL-yield found in open literature will be discussed and evaluated. All of the models including the new one start from the assumption that the unit current source errors have a gaussian nature.
2.2 Lakshimikumar approach
A first suggestion to analytically determine the yield of a D/A converter as a function of the matching parameters of the current source transistors has been made in [ 11 :
-1 Q i INL - yield = n erf (-)
i=2 Jz
Qi
N = the number of bits, z i = the mean normalized output at code i
00 = unit current relative standard deviation
However, this formula is based on the assumption that there exists no correlation between the outputs of the current-steering D/A converter. The INL-yield can then be obtained by multiplying the probabilities that each output has an error smaller than half an LSB (eq.1). To demonstrate that this assumption is not correct the following example is given. The outputs corresponding
-
I
0-7803-5482-6/99/$10.00 02000 IEEE
IV- 105
with the digital input word 01100 and 01101 are strongly correlated since they are both implemented using the same current sources. The formula given in eq.1 gives us a rather pessimistic view on the INL-yield (fig.1) leading to an oversizing of the current source transistors [2] (eq.2) and hence of the total chip area.
In [3] an adjustment of the formula in eq.1 has been presented. Here the MSB (most significant bit) transition is viewed as the most critical one since in a binary implementation this transition has the largest probability of generating an output error. Furthermore, the D/A converter's outputs before and after the MSB transition are not correlated and the yield can then be described as :
2" -I
ZNL-yield = erf (a) i=2"-'-1 Jz
(3) Qi
N = the number of bits, zi = the mean normalized output at code i
I
-
= unit current relative standard deviation
However, the yield estimation given in eq.3 is too optimistic (fig.1) since the influence of only two outputs is taken into account while the errors generated by the other outputs are being ignored.
Comparing the two approaches one can conclude the following : designing a chip using eq.1 can lead to a large but nearly fault-free D/A converter while eq.3 gives you a compact but low yield circuit. The correct yield estimation is situated somewhere in between these two results.
2.3 Monte Carlo approach
To obtain an accurate estimation of the INLj ie ld , the Monte Carlo simulation [4,5] has been up till now considered to be the only good altemative. The following procedure can be used. Each of the (2N-1) current sources has a random value that has been derived from a gaussian distribution with mean value and a standard deviation o(1). For every digital code the output current of the D/A converter is calculated and compared to the ideal value. If the difference is larger than half an LSB - even for only one digital code - the D/A converter is regarded as not functional and is therefore rejected. For every o(1) this procedure is repeated a Iarge number of times (> 100) to obtain reliable results. The INL-yield is then given by the ratio of the number of functional D/A
converters (INL<1/2 LSB) to the total number of try-outs. In this way the relation between the unit current standard deviation and the INL-yield is determined (fig.1). However, to obtain the results depicted in fig.1 a large amount of CPU time is necessary. Running a Monte Carlo simulation for a high resolution D/A converter takes several hours and that is a major drawback for this approach.
Fig. 1 : Monte Carlo simulations(0)of the INL-yield compared to the results of the formulas in eq.l(+) and eq.3(.) for a 10 bit DIA converter
3. NEW INL-YIELD FORMULA
3.1 Introduction
In this section, a formula will be presented that describes the INL-yield of the D/A converter as accurately as the Monte Carlo simulations but without any loss of design time. The idea will be elaborated for an arbitrary number of bits N. For the simplicity of notation the following symbols are defined :
Definition 1 : X(j) is the sum of j non correlated unity
Definition 2 : Yfj) is the difference between Xu) and the
Every current source has a normal distribution with a mean value I,,, and a standard deviation o(1). This implies that both Xu) and Yu) also have a normal distribution with the following properties (eq.4) :
current sources
sum of the ideal current sources
3.2 Theory The exact possibility that an INL error will occur is based on the fact that each current source can generate an error and hence is given by the following sum of probabilities (eq.5) :
IV- 106
P(INL-error) =
P((Y (1)l Z 0.5 & IY (2)( < 0.5 & ... & Y ( 2 N 1) < 0.5) + P(IY(2)I 2 0.5 & ... & Y ( 2 N -1) < 0.5) + ... + ( 5 )
I - I I I
P ( k ( 2 N -l)l> 0.5)
However, this equation is not transparent and therefore not suitable for practical use.
The basic idea behind the new theory is based on the assumption that if at any point IY(i)l reaches half an LSB, there exists a 50% chance that the error increases and 50% chance that it decreases again since a normal distribution with mean value zero is used. Extending this line of thought one can say that if an INL error occurs - when passing through all the possible codes generated by the 2N-1 digital input words - there is a 50% chance that this error still exists for the fictive code 2N ((Y(2N)J > 0.5).
Fig.2 : the shaded area determines the probability P(Y(2N)) < 112 LSB
This idea can be expressed as :
P ( 3 j E [1..(2N - 111 : IY ( j ) l> 0.5) P ( Y ( 2 ) > O S ) = (6) I N I 2
At this point the INL-yield of the D/A converter can be integrated in the calculation since there exists an obvious relation between the yield and the possibility of an INL error to occur :
INL-yield = 1 - P ( 3 j ~ [1..(2N - l ) ] : ~ Y ( j ) ~ > O S ) (7)
Combining eq.6 and eq.7 :
1 - INL - yield 2
From eq.8 the possibility that no INL error occurs at code 2N can be easily derived and equals :
INL- yield 2 (9)
Since Y(2N) has a normal distribution with a standard
deviation P o ( I ) (eq.4), the relation existing between the IN-yield of the current-steering D/A converter and the matching properties of the current source transistors
can be deduced from eq.9. At this point, the INL yield is no longer described as a sum of probabilities (eq.5) but as the possibility that a sample from a normal distribution is smaller than half an LSB. This requirement can be written as :
-1 I ZLSB -Co (10) INL - yield
2 = 0.5 +
with P ( Y ( ~ ~ ) ) the probability density function (fig.2).
Eq.10 directly gives the following result :
C *B ( Y ( 2 N ))I -LSB
with:
1 2
) C = inv -norm(-,,,)(0.5 + INL - yield
2
1 INL- yield 4
C = inv -norm(-,,,)(0.75 +
Eq.11 can be rewritten as a relationship between the unit current relative standard deviation and the INL-yield of the D/A converter (incorporated in coefficient C) :
Fig.3 shows the Im-yield of the D/A converter in function of the coefficient C.
In fig.4 the INL-yield of a 10 bit D/A converter calculated using the new formula (eq.12) and simulated using the Monte Carlo approach are depicted. From this figure it can be concluded that the formula is in good agreement with the Monte Carlo simulations. To gain more insight in eq.12, the unit current standard deviaticn is plotted in logarithmic scale versus the
IV-107
100
Fig.4 : Comparison between the Monte Carlo simulations (*) and the formula (line) for a I O bit D/A converter
resolution of the D/A converter (fig.5). As can be seen from fig.5 these are straight lines since
Furthermore, one can easily conclude from this figure that for the design of a high accuracy current-steering CMOS D/A converter the matching parameters play a significant role. A small deviation of the required sigma(I)/I can lead to a severe yield degradation.
0 1
0.01
0.001 I------ _ _ _ _ _ _ _ -
4 I 6 8 10 12 14
number of bits
Fig.5 : The unit current relative standard deviation in function of the resolution of the D/A converter for a 30 yield of 99.7% (+), a yield of 50% ( 0 ) and of 10% (m)
The time to create a figure like fig.5 using Monte Carlo simulations in MATLAB is given in table 1. In this table the results for the INL-yield from 100% to 10% for a current-steering D/A converter with different resolutions can be found. For all the simulations twenty values for the relative unit current standard deviation were taken. This can be understood as follows. In a first coarse approximation a simulation using 10 values for sigma(I)/I - that span a wide range- is run. From the obtained result the interval for the sigma(I)/I that obtain a high INL-yield can be specified. In this interval another 10 points are
simulated. In almost all cases this procedure gives accurate results.
Constructing fig.5 using the new formula takes only a few minutes. The time to write the short program For MATLAB is so to speak the most time consuming. It is also worth noting that the time necessary to calculate .the yield is independent of the resolution of the D/A converter while the time consumption of the Monte Carlo simulations “explodes” with an increasing D/A converte:r’s accuracy.
14 bit
Table1 : comparison between the time consumption of the Monte Carlo simulations and the new formula
4. CONCLUSION
Since high resolution current-steering D/A converters are strongly dependent on the matching characteristics of the technology in which they are processed, it is important to know the number of functional chips in a set of fabricated devices. It is proven in this paper that time consuming Monte Carlo simulations are no longer necessary to obtain results for the Im-yield with a good accuracy. A new formula has been presented that directly gives you the INI-yield of a current-steering D/A converter in function of the transistor mismatch parameters of the current sources without any loss of design time.
5. REFERENCES [ I ] K. Lakshimikumar and al., “Characterization and Modeling
of Mismatch in MOS Transistors for Precision Analog Design”, IEEE Journal of Solid State Circuits, v01.21, Dec
[2] M. Pelgrom, A. Duinmaijer and A. Welbers, “Matching Properties of MOS Transistors”, IEEE Journal of Solid State Circuits, vol. SC-24, Oct. 1989, pp. 1433-1439
[3] K. Lakshimikumar and al., “Reply to ‘A Comment on : Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design”, IEEE Journtzl of Solid State Circuits, vo1.23, Feb. 1988, pp. 296
[4] C. Conroy, W. Lane and M. Moran, “A Commenf. on ‘Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design,’” IEEE Journd of Solid State Circuits, ~01.23, Feb. 1988, pp. 294-296
[5] J. Bastos and al., ‘‘ A 12 bit Intrinsic Accuracy High Speed CMOS DAC,” IEEE Journal of Solid Slate Circuits, vo1.33, No.12, Dec. 1998, pp. 1959-1969
1986, pp. 1057-1066
IV-108
Characterization of a CMOS Current-Steering DAC using State-Space Models
K. Ola Andersson and J. Jacob Wikner Dept. of E.E., Linkoping University
SE-581 83 Linkoping, Sweden
MERC, Ericsson Microelectronics AB Box 1885, SE-581 17 Linkoping, Sweden
Abstract - Performance limitations on current-steering dig- ital-to-analog converters (DACs) are due to 6nite output impedances, nonideal switches, parasitic capacitances, match- ing, etc. In this work we present a dynamic state-space model of a 14-bit current-steering DAC which includes dynamic non- idealities. Simulation results are presented and compared to measurement results. The model can be used for fast perform- ance estimation of DIA converters.
I. INTRODUCTION
For high speed and high resolution communication appli- cations the current-steering digital-to-analog converter PAC) is suitable [ 11. In this work we focus on the dynamic properties of the current-steering converter. With increasing signal frequency, dynamic errors, e.g., nonlinear settling errors and glitches, tend to determine the performance of the DAC. We need good behavioral-level models of the dynamic properties in order to understand the DAC design criteria.
In Sec. I1 we introduce the different nonideal components used in a current-steering DAC. These components are put together to a circuit level model of the whole DAC, as pre- sented in Sec. 111.
In Sec. IV we present a mathematical analysis of the cir- cuit-level model. The differential equations of the system are given on a state-space form, yielding short simulation times. The model helps us understand what can be done to minimize the influence of dynamic errors. The model is Spice-like, but used in Matlab it has an improved modularity and flexibility.
In Sec. V we discuss the application of the model on a 14-bit current-steering DAC. Single-tone and multi-tone properties are discussed.
n. NONIDEAL CURRENT-STEERING DAC CIRCUIT ELEMENTS
In this work we focus on the influence of unwanted resis- tive and capacitive parts (parasitics). The parasitics in the current sources have one of the most crucial impacts on per- formance. Matching is not considered but can easily be introduced in simulations of the model presented by simply changing the numerical values of currents and parasitics.
A. The Current Source
The ideal current source (Fig. l(a)) should have an infi- nite output impedance. A cascoded PMOS implementation of a current source is shown in Fig. l@). The cascode tran-
source transistor -Id cascade transistor
t lout @)
Fig. 1. (a) Ideal, (b) PMOS, and (c) simplified model of MOS current source.
sistor increases the output impedance [2], but still the source will have a finite output impedance (Fig. l(c)). The output impedance contains a capacitive part [ 11, which will degrade the performance at higher signal frequencies.
B. Theswitch
Using differential signal paths is an effective way of rejecting noise and distortion, e.g., substrate noise or chan- nel charge injection, if the two paths are symmetrically designed [2]. Therefore, differential current switches are commonly used and they are implemented with two or more MOS transistors in parallel (Fig. 2(a)). In this work the switch is represented by the MOS switch-on resistance(Fig. 2@)). There also exist parasitic capacitances in the switch, but these are lumped into the parasitics of the current source and output wire.
C. The Output Wire
The output wires of the DAC should have zero imped- ance to reduce the voltage drops. In reality, the wires contain resistive as well as capacitive and inductive parts. For high accuracy, a transmission line model or an RC-ladder should be used for the wire [3]. However, we want to achieve short simulation times, i.e., a small number of circuit nodes. Therefore, we trade accuracy for a lower complexity model. As a simple approximation, we use a resistor and capacitor in parallel, i.e., a simple RC-ladder, as shown in Fig. 3. The impedance includes the internal wire impedance as well as the off-chip load.
III. CIRCUIT-LEVEL MODELING
In this section we briefly present the ideal current-steer- ing DAC, followed by a presentation of the nonideal DAC constructed with the components described in Sec. 11.
668 h c . 43rd IEEE mdwest Symp. on Clrcuits and System, Lanslng MI, Aug 8-11,2000 0-7803-6475-9/00/$10.~~~~ 2oM)
Fig. 2. (a) Ideal and (b) nonideal differential switch.
Fig. 3. Model of the output wire.
A. The Ideal Current-Steering DAC
An ideal differential current-steering DAC is shown in Fig. 4(a) where all current sources have infinite output impedance. The switch and wire impedances are zero and the load imped- ance is purely resistive.
B. The Nonideal Current-Steering DAC
The ideal components are substituted with the nonideal components presented in Sec. II forming the circuit of Fig. 4@). This is the architecture we examine in our work.
Iv. STATE-SPACE MODEL OF ONE CHANNEL
To illustrate the model we formulate the differential equa- tions describing one of the DAC outputs. We look at the tran- sient behavior between two consecutive switching instants. The switching instants occur at multiples of T s and for sim- plicity we start at t = 0 .
Assume that we during a certain period have K current sources connected to the output as illustrated in Fig. 5 , i.e., the current sources I . where j = 1, . . ., K . The following equa- tions hold for this system
I
Combining the equations yields
We want to write the equations on vector form and we introduce the voltage vector, V , defined as
h h .......... ._......__ 4L %@
+ Fig. 4. The (a) ideal and (b) nonideal current-steering DAC.
T '('1 = [vl(t) *.. v K ( f ) v,(f)l
We form the state vector X
X ( t ) = V(t) - V ( 0 ) (4)
where V ( 0 ) is the initial value of V just before the switching occurs. We rewrite the equations and get
V(t) = X(t) = A . X( t ) + B . u(t) (5)
where the elements of the (K + 1) x (K + 1) matrix A tare
aj, = -(&.+;)$, for j = I, ..., K J
- 1 for j = 1, ..., K a . j , K + 1 - - Rs, jcj
- 1 for j = 1, ..., K a K + 1, i - R ~ , j c and
a . . = 0 for all other i, j 1, J
and the vector B is given by
669
I . . . . . . . +....... I
R lo@
- Fig. 5. One output channel during a switching period.
B = A . V ( O - ) + [ y c , ... I K / c K d T (7)
The input signal, u(t) , is a unit step. Since the final values of the nodal voltages, V i ( T ) , will become initial values in the next switching period, all those are needed as output signals from the state-space system. We also need the output voltage, VJ?) , and it is convenient to define the output, Y , as
Y(t) = V(t) = X(t) + v(o-) . u(t) (8) Equation (5) together with (8) is a standard state-space formu- lation of the differential equations describing the system [4]. At a first stage, the issue for the simulator is to determine the output values at multiples of T.
v. SIMULATION RFSJLTS
The results from Sec. IV enables us to do simulations in a numerical computation environment, e.g., Matlab, which has been chosen for this work. The advantages of using mathe- matical over circuit-level simulators are for example the sim- plicity of creating different input signals to the system and the powerful signal processing tools.
Quantitative values on parasitics and other nonidealities have been estimated through layout extractions and process parameters of a 0 . 3 5 ~ CMOS process. The values have been used to simulate the behavior of a 14-bit current-steering DAC. In Table I we show the circuit values used in the simula- tions. Simulations are compared to measurements of a 14-bit converter with approximately the same properties as given in Table I.
A. Simulated Signal Spectra
We have carried out single-tone simulations of the 14-bit DAC at different frequencies. In Fig. 6(a) a half-scale single- tone spectrum of the differential output signal is shown, where the sampling frequency is f, = 2 MHz . Fig. 6(b) shows the situation for f = 10 MHz . In both cases the ratio between the signal and sampling frequencies is prime and
In the 2 MHz case we basically find no difference between f signal'f s 1'9
( 4 PSD plot for a single-lone input, fsample = 2 MHz
0 I -20.
E g -40-
e -60- 0 - .g -80- m a-100- a
@) PSD pld for a single-tone input, fsample = 10 MHz
0-
-20
I I
5
0.1 0.2 0.3 0.4 0.5 -8""
Normalized Frequency
Fig. 6. Single-tone spectra for the DAC model using sampling frequencies of (a) 2 MHz and (b) 10 MHz.
TABLE I SMULATION VALUES FOR SOURCES AND PARASIllCS.
Component LSB value MSB value
Source output resistance 150 GQ 18.3 MSZ
Source output capacitance
Source output current 1.22 p A 1 O m A I I
Switch on-resistance I 50051 I 16 51
I Loadcapacitance I 120 pF ~ - -1 I Wire resistance I 100 SL I
the nonideal and an ideal spectrum. No visible spurious tones are appearing, only the quantization noise is present. How- ever, when the frequencies are increased by a factor of 5, we clearly see how the dynamic nonidealities introduce distortion of odd order. In the separate channels there also exist harmon- ics of even order that are cancelled in the shown differential output spectrum. These even order terms become visible in the differential spectrum aswell, if there is a slight mismatch between the two channels, e.g., a difference between the load resistances. In a real implementation we would expect to have spurious tones even at relatively low frequencies, due to cur- rent source mismatch and other nonidealities not included in the modeling.
670
B. Single-Tone Linearity
One important single-tone linearity measure is the spuri- ous-free dynamic range (SFDR), which is defined as the power-ratio between the signal and the largest spurious tone.
In Fig. 7 we show simulated and measured values of SFDR as a function of signal frequency. The sampling frequency is fs = 10 MHz . Simulated and measured results show a close agreement. However, for increased sampling frequencies the model show worse performance than measurements, e.g., at f, = 40MHz the simulated SFDR is approximately 10 dE3 worse than the measured. This implies that a somewhat more complex model is needed to closer resemble reality at high clock frequencies. The rough model of the wire probably accounts for a significant part of the discrepancies between measurements and simulations, and how the wire should be modeled for enough accuracy without to much increase of complexity requires further investigation. The output imped- ances and switch resistances has been modeled as linear com- ponents, although they are nonlinear. This is another source of model errors.
C. Multi-Tone Linearity
In several communication applications a multi-tone input signal is commonly used, e.g., discrete multi-tone (DMT). In these cases, the multi-tone power ratio (MTPR) is an impor- tant linearity measure. The MTPR is determined using M tones with equal amplitudes, a , and equally spaced in the fre- quency domain. One of the tones is left out, and MTPR is defined as the ratio between the power of the used tones, i.e., a 2 / 2 , and the power of the distortion term appearing at the leftout frequency position. This is illustrated in Fig. 8, where M = 33 and a = 2”- ’ / (2M) to avoid signal clipping.
Besides the in-band distortion determining the MTPR, we can also see that the nonlinearities introduce a significant amount of distortion outside of the signal band.
Multi-tone properties are more complex than single-tone properties. MTPR is strongly dependent on the peak-to-aver- age ratio (PAR) of the signal, i.e., a higher PAR yields a lower MTPR [SI. In the simulation presented in Fig. 8 there is a ran- dom phase in each tone for reduced PAR.
75
370 e
E “65-
PSD plc4 for a multi-tone input, fsample = 10 MHz
-
-
- - - - -
SFDR vs Signal Frequency, 10 MHz sampling frequency 80, I
simulated \ ‘,
6o t 55‘ I 1 o5 1 on 10’
Signal Frequency [Hz]
Fig. 7. Simulated and measured SFDR as a function of the signal frequency. The sampling frequency is 10 MHz.
0.1 0.2 0.3 0.4 ( -1 40;
Normalized Frequency
Fig. 8. Multi-tone spectrum for the DAC model using a sampling frequency of 10 MHz.
VI. CONCLUSIONS
5
A simple state-space model of a CMOS current-steering DAC has been presented, and used to characterize the single- tone performance of a 14-bit DAC. Comparisons between measurements and simulations verify the model to relatively high accuracy, and the model explains some important limita- tions on DAC performance. The concept of mismatch can eas- ily be introduced in the model by simply changing the numerical values of currents, impedances etc.
In some applications a higher accuracy behavioral-level model can be desired. This can be done by introducing, e.g., nonlinear parasitics and transmission line model of wires. However, a major advantage of the model is low simulation times with relatively high accuracy. A refinement of the model as discussed above will probably increase simulation times significantly, perhaps to a level where a circuit-level simula- tor, e.g., Spice or Spectre, inight be preferred.
ACKNOWLEDGMENTS
The authors would like to thank MSc. Niklas U. Anders- son, Ericsson Microelectronics, for valuable discussions and all help with DAC measurements.
REFERENCES
M. Gustavsson, J.J. Wikner, and N. Tan, CMOS datu converfers for communications, Kluwer Academic Publishers, Boston, U S A , 2000, ISBN 0-7923-7780-X
D.A.’Johns and K. Martin, Analog integrated circuit design, John Wiley and Sons, New York, U.S.A., 1997, ISBN 0-471-14448-7 Z.F. Jin, J.J. hurin, and Y. Savaria, “A new approach to analyze inter- connect delays in RC wire models,” in Proc. of the 1999 IEEE Int’l Symp. on Circuits and Systems (ISCAS’99), vol. 6, pp. 246-249, Orlando, FL, USA, May 30 - June 2,1999 T. Glad and L. Ljung, Reglerteori - jervuriabla och olinjara metoder, Studentlitteratur, Lund, Sweden, 1997, ISBN 91-44-00472-9 AN971 8, Application Note, Intersil Corporation, April, 1997
67 1
Clock Jitter Compensation for Current Steering DACs
Andreas Wiesbauer, Dietmar Luis Hernandez Daniel GruberStraussnigg, Richard Gaggl,
Martin Clara Universidad Carlos III Telematics / Network EngineeringMadrid, Spain Carinthia Tech Institute, CTI
Infineon Technolgies Austria AG luis.hernandezguc3m.es Klagenfurt, AustriaVillach, Austria daniel.grubergedu.fh-kaernten.ac.at
Abstract-Clock jitter is an important source of error in high- digital means. Simulation results and the simulation setup arespeed current-steering D/A converters. A technique to discussed in section IV, revealing the required hardwarecompensate these errors is introduced. Simulations show a complexity to significantly reduce clock jitter sensitivity forsignificant reduction to clock jitter sensitivity for the example a 30MHz analog bandwidth, 12bit resolution SD DAC. Weof a Sigma Delta DAC with an analog bandwidth (ABW) of 30 consider random timing errors as the dominant timing errorMHz clocked at 360 MHz. throughout this paper, even though the method can handle
nonrandom jitter as well.I. INTRODUCTION -------------------------------------
' ~~DACanalogue signalItis well known, that continuous-time sigma-delta (CT digital analogue signal (+ errorej) corrected)
SD) ADCs suffer from sensitivity to clock timing errors signal DACestimated ~ 'esfimatedcaused dominantly by injection of these errors into the sigma
errorestimated esimaldelta loop via the current steering DAC in the outermost ------------- -es--------- digntal eofeedback branch [1]. A model and an analytical description Clkof the jitter error effect were described in [2]. The jitter esfimatedsensitivity is inherent to any current steering DAC either r---- errorsignalused inside a CT SD ADC or as a stand-alone DAC. i ero
' j i er error.. ... .. ' ~~~~~~~~~~~~measuring 0 estimationTo reduce the clock jitter sensitivity several methods are ci * digital
known in the literature. The highest sensitivity is given if the correctionDAC has a low resolution [1], e.g. single-bit SD DAC. analogue
Jitter error modeling correctionTherefore the sensitivity can be reduced by using multi-bitDACs, at the cost of an increase in circuit complexity.Another way to circumvent the problem is to use switchedcapacitor (SC) DACs instead of current steering DACs.However, SC-DACs don't allow as high update rates or II. JITTER ERROR ESTIMATIONcause higher power drain compared to switched current It was shown in [2] how the error introduced by jitter canDACs. Furthermore, there are pulse-shaping techniquese, a teereoe whc tage to reuc clc jitrsniiiyb be modeled. Based on this model, a jitter-error estimation
reortedzichthcurrent pulse shape [3]. hardware is developed next. For non return to zero codedoptimizing the cuff ent pulse shape [3].*DACs, the discrete time error sequence ej[n] induced by jitterIn this paper we introduce a method which in principle can be described by
allows removing errors caused by clock jitter. A blockdiagram of the configuration is shown in Fig. 1. Essentially,the error caused by the clock jitter is estimated and thereafter ej [n] = (y[n]-y[n -l ]) - ATDACLn (1)subtracted in the analog or digital domain from the erroneous Tsignal. If the estimated jitter error signal matches well withthe generated error signal a perfect compensation is obtained. where y[n] represents the digital signal and ATDAC[n] the
In section lI.thejitter eror estimation is described in time error in each clock-cycle and T the ideal clock period.detail and aosibecicutimla. , Therefore an error-estimation can be performed bydetail and a possible circuit implementation is presented. multiplying the time-error sequence with the first derivative
Section III ws efent ementation of thejt of the digital signal, as depicted in Fig. 3.error compensation where the error subtraction iS done by
A. Clock Jitter Measurement Accuracy requirements for the measurement circuit,In order to get a representation of ATDAC[n] an analog such as gain error, offset error and noise, will be discussed in
circuit has to be developed. The approach suggested in this the simulation section and implementation-cost issues will beartcl*isshwnin Fig. 2. A single-bit current steering DAC summarized in the conclusions. However, both the SC-DACaril is shown............... and I-DAC have a resolution of one bit only and a fixed
(I-DAC) delivers a charge proportional to the clock period toan integrator. At the same time, via a SC DAC, a fixed input set to '1', allowing simple circuit design.amount of charge is subtracted. When properly dimensioned,the charge stored in the integration capacitor is proportional III. JITTERERROR COMPENSATIONto the time error in each clock-cycle. After a full clock cyclethe integrator is read out via an ADC and reset by closing the Fig. 4 shows the block diagram of a typical setup of a SDswitch across the integrating capacitor. For proper timing DAC, consisting of a DAC and a noise-shaper extended withand readout it might be necessary to implement two such the before discussed implementation of the jitter errorcircuits and operate them in ping-pong mode. Because, as compensation method. To allow an efficient DAC design thewill be shown in subsequent sections, the required accuracy well known digital noise-shaper concept [4] is used to reduceof the measurement circuit is small compared to the accuracy the digital wordlength of the noise-shaper input X(z) (m-bit)of the main converter, the area and power overhead incurred to the DAC input Y(z)( n-bit ).by using this compensation method will be very limited.
As indicated before the clock jitter induces a jitter error atthe output of the DAC, which can be compensated by theinjection of an estimated digital jitter error E.(z) in the
SC L DA |feedback loop of the noise-shaper.measured
I bit, input--I . clock jitter digital noise-shaper(analogue)
differentiated It follows from the linear model of a noise-shaper that an
digital digital signal error EJ(z) subtracted from the signal in the feedback loop ofsignal T W the noise-shaper will contribute to the output Y(z) of the
noise-shaper in the form
Y(Z) = X(Z)+ Eq (Z)(1 - R(Z))- Ej (Z)R(Z) ' (2)where R(z) is the transfer function of the loop filter in the
Figure3. Clockjittererrorestimation feedback branch as depicted in Fig. 4 and Eq(z) is thequantization error. If properly dimensioned, (11-R(z)l) << 1
B. Jitter Error Estimation in the band of interest resulting in
Jitter error estimation is based on (1) and requires Y(z) , X(z) - Ej (z) for f < (fample 1(20SR)) (3)multiplying the measured clock time-error with thedifference of two consecutive samples (YSTEP). For single-bit at the output of the noise-shaper. This means that theDACs YSTEP can have only three values (+1,-i,0). Therefore architecture in Fig. 4 provides a signal to the DAC which isthe required hardware is negligible. Multi-bit DACs in predistorted by the estimated jitter error E.(z). In case Ej(z) isgeneral require more hardware for the implementation. equal to the real jitter error at the output of the DAC, theHowever, if the DAC is of oversampling type, YSTEP is most Jitter error is canceled perfectly.often limited to the range [±2,±1,O,-1,-2], again allowing acost efficient implementation of the multiplier.
5376
IV. MODELLINGAND SIMULATION RESULTS Additionally to the measured values the theoretical SNRvalues achievable with the given long-term clock jitter were
The clock jitter sensitivity of a DAC with a noise-shaper calculated using the formula derived in [6]for the wordlength reduction from 12bit to 6bit was Kevaluated. A clock of 360MHz for the DAC and an SNR=-20 logl 2zf ig " I|. (4)oversampling ratio of 6 are assumed (30MHz bandwidth). y2fJThe noise-shaper was designed for a peak Signal-to-NoiseRatio (SNR) of 72dB. 80
Fig. 5 shows the PSD ofthe output signal ofthe modeled I III I I IDAC including the jitter error and compensated with the 70 7QTestimated jitter error. Furthermore the PSD of the modeled H \\clock source, which resembles a typical PLL-type on-chip 60 - .FT - - rT- -1 T1 r TFITr-F \-IrI T T -TI-T -I-
clock synthesizer [5], can be seen on the top right side. -_ - i_ _ _ < L - 1 -_-5040 __ _I_I liii I liii IQI liii I
~~~~~~l II~>II
24011 signa -ocompensat on
',
4theoretical SNRfor givenGl1t 1 1 1 1 1 11
ii1-YF ,1 3 fi lt iM II IIII IIIII I11 I11 I11
'£j -812 -1 -^4410 -9Cit S
~~~~~~~~~~~f1010 0 e1i=0 10l0.X
W | iK i 6 1 M Xi [ " t . | ~~~~~~~~~Figure 6. SNR vs. clock jitter
0 2 4 6 8 10 12 14 16 The second set of simulations includes a more realisticlequency [Hz] X1 measurement of the clock jitter values. These were sampled
and quantized, simulating an analogue-digital conversion ofFigure 5. Spectrum ofFthe signal with jitter error and the jittered clock the clock jitter values.
(upper right corner)
To show the impact on the performance of the proposedw.corrpensation
correction method several simulation scenarios were 70r-7alisi--c- K ----- Vinvestigated. As a size for the jitter intensity the long term me o -co j vals T Srms-jitter (ola) was used. To measure the performance ofqthe 65 simlain a analogue-digital ofproposed jitter error compensation method the SNR vs. clock 60t0- - - -- -- - - -F-Aes.- -- + i \ <K- Kjitter is evaluated. corner)
- 1 4 1-G1 1 1 1 1 1 I
A. Idea/measurement and compensation z 50 - - -I -~-I-~-~~6 --I - A- - - 4 - +A- - --- -
For the first set of simulations ideal measured clock jitter I I 1111 I I II II illl lXlIvalues for each sample instance were assumed. The result of 45-h--I_I- -le 4-these simuationsl aoncompensationFig.o6 40 al wlo co\ l o |tneseslmulatlonscanseseenmrlg.O. 400 clock jittersamplingresolution:2bicjtralgeo. -
.. . . . ,. . , > ||~~~~~~~~~~~clock jitter sampling resolution: 3 bit i i i i iAt low jitter values quantization noise limits the SNR. 35 - - clock jitter sampling resolution: 4 bit 4 L -_ _--With increasing clock jitter, starting at 2ps, the SNR of the-r signal with ideal compensationI I Iuncorrected signal decreases linearly with the logarithm of 10-11 -10the long-term clock jitter. The signal with compensation 10 t[si 10shows much better performance up to high clock jitterintensity. The decrease of the SNR at a long-term clock jitter Figure 7. SNR vs. clock jitter for different ADC resolutionintensity of about l00ps results from limitation of thecompensation values the values in the feedback loop may The modeled jitter error is no longer exact and introducesnot exceed reasonable size. The compensation does no additional quantizationnoiseinthe feedbackloop. Thereforelonger cancel the error fully but does still decrease it. the performance of the compensation deteriorates with
decreasing resolution of the ADC converting the clock jittervalues. Fig. 7 shows the SNR vs. clock jitter for different
5377
ADC resolution. The ADC had full scale at 5 times the compensation. The resolution of the jitter measurement is 8standard deviation of the cycle-cycle clock jitter values bits lower than the converter resolution. Compared to thewhich covers over 99°0 of the possible clock jitter values. main DAC the measurement DACs and integrator noise and
accuracy specifications are relaxed by a factor of 256,C. Influence ofmeasurement errors leading to an almost negligible cost adder.
The final set of simulations was performed to show therobustness of the jitter error compensation against 75 I 7
measurement errors in the clock jitter measuring circuit, 704 - - -I-I-I-I HI -- -HI Imainly gain and offset errors. Both result in lower I 1111111 I I I Iperformance of the compensation method as they degrade 65 - - -i- -- H-- I4 A-I-
the jitter error estimation. I I ii I60 - - - -1- - -1-I 1-1-lX1-4 X -1-I 4-44X41 W----] X.\ . ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~I I I1 1 II I\I I I IIIII\II
1) Gain error I 111 I I I I IEE -1- 1-1-1 -I4 4-I--- --]
As can be seen in Fig. 8, the method is robust towards m ---1-1-5IIiIK- I _gain errors. With a 1dB gain-error, clock jitter sensitivity C II____ __ _Zl I0- - 1 -1114 I II Al--reduction by one order of magnitude is maintained. Gain- I I IIaccuracy of 1dB can be achieved with conventional low cost 45 - --_ - - --___I- --1 - -- -_ 4- -- - -¼_circuitry. signal w/o compensation I I I_
40 4-4 4~~~~~~~~~4 -I_]-G signal with ideal compensation I I I I I I I I
offset error 10% ADCfull scale I I l1 11 11 1Il 35 offset error20% ADCfull scale 1-1-I! L _ t
I l111 1 I l11l l l l l l l l l l l l offset error 50% ADCfullscalefulllscal70 ..= - 3 1 1 -lo 11WWWW
I- I1- I I___ IC -A I I liL 1JA\I-1-0
10 10
65 - - ---T-T---- -0 g _ \_ _T 7 [s]X1111I IN
IIIIIlulL lI Ii I II I x
I I1111111 I ~~~~~~~II I1I1I1I I60 - - - Iit-- --t - 4-11-- --4\_- Figure 9. SNR vs. clock jitter for different offset errors
Em 55 1111 - -t t
rr I I I1I111 V. CONCLUSIONSz 50 - - - -- + 1 1 -+ +Ht It-+ --t11111 I 11
A method for compensating clock jitter errors was45 --I41 I41I14 -4 A45 ---I--I--I-HI-HI-----H--t-H4-4I b
I 4I-M presented. Sensitivity reduction of one order of magnitudesignal w/o compensation I IIIII \ was shown in the example of a 12bit 3OMHz analog
40 - signal with ideal compensation - K 4 4 1 K14 _ _--x- gainerror of 1dB 1 1 bandwith current steering DAC. Application of this method
35 gain error of 2dB - L 4 2 1 Ll l - X allows realizing high resolution data converters without thegain error of 3dB l
III1111 I ~need for clock sources exhibiting high spectral purity.10~1 1o~0
Glt [s] REFERENCES
Figure . SNRvs.cockjttersfodiffrentain[1] Cherry, J.A.; Snelgrove, W.M.; "Continuous-Time Delta-SigmaFigure 8.SNR vs. clock jitter [s] for different gainerrorsModulators for High-Speed A/D Conversion", Kluwer Academic
Publishers, Boston, MA, 19992) Offset error [2] L. Hernandez, A. Wiesbauer, S. Paton, A. Di Giandomenico,An offset error occurs if the jitter measuring circuit adds "Modelling and Optimization of Low Pass Continuous-Time Sigma-
a constant value to the measured clock jitter values. Due to Delta Modulator for Cock Jitter Noise Reduction ," Proceedings ofthe estimation this error reduces the signal amplitude slightly 2004 IEEE ISCAS, May 23 - 26, pp. 1072-1075, May 2004but shows little to no effect on the compensation if it is [3] M. Ortmanns, Y. MAnoli, F. Gerfers, "A Continuous-TIme Sigma-within reasonable bounds. An offset error does only affect Delta Modulator with Reduced Jitter Sensitivity," Proc. of 28ththe performance of the compensation if it leads to saturation ESSCIRC, pp. 287-290, Sept. 2002.of the error estimation circuit but this requires rather big [4] Candy, James; Temes, Gabor: "Oversampling Delta-Sigma DataConverters Theory,Design, and Simulation". New York: IEEEoffset values. The impact of an offset error on the Press,1992.compensation performance can be seen in Fig. 9. With [5] A. Hajimiri and T. H. Lee, "The Desing of Low Noise Oscillators",increasing offset errors the SNR curve drops sharply at lower Norwell, MA: Kluwer, 1999intensity of the clock jitter. [6] N. Da Dalt, M. Harteneck, C. Sandner, and A. Wiesbauer,
,,Numerical modeling of PLL jitter and the impact of its nonwhite3) Noise spectrum on the SNR of sampled signals", in Proc. Southwest Symp.Noise in the jitter measurement circuit will contribute Mixed-Signal Design 2001, Austin, TX
directly to the output signal. According to the simulations insection IV- B, additional noise equivalent to 4bitquantization noise will have little effect on the jitter
5378
CLOCK-JITTER INDUCED DISTORTION IN HIGH SPEED CMOS SWITCHED-CURRENT SEGMENTED DIGITAL-TO-ANALOG CONVERTERS
Jose' Luis Gonzdez and Edtrard Alarcdn
Department of Electronic Engineering, Universitat Politecnica de Catalunya, Gran Capita s/n, Modul C4 Campus Nord UPC, 08034 Barcelona, Spain
The design of high-speed CMOS current-steering (sometimes called switched-current) segmented DAC converters requires an optimal segmentation to balance area and performance requirements. In this paper a new design criteria is introduced based on the effects of the clock-jitter in the DAC spectral performance measured through the SFDR. The study of the clock-jitter produced both by a random process. independent of the input sequence. and by the dUdt noise originated in the binary to thermometer decoder is presented. In this later case the clock-jitter is not independent from the input sequence and is related with the number of input bits assigned to the thermometer code segment. Simulation results providing design guidelines for selecting the proper segmentation are also given.
1. INTRODUCTION
Modern broad-band communication integrated circuits require as a fundamental part of the system high-speed and high-resolution digital to analog converters (DAC) [l]. Wide bit-count DACs working at sampling clock fiequencies in the range of the hundred of MHz will be required. The goal of this work is the evaluation of a 16 bit high- speed current-steering DAC with thermometerhinary code segmentation against clock-jitter produced by random noise and switching noise (dl/dt noise). The DAC performance is analyzed through the spurious-free dynamic range (SFDR) measurement. The output waveform distortion of a DAC comes &om two sources. First. the amplitude of the output current corresponding to a certain input word may be slightly different from the expected value due to the DAC output current sources MOS transistors mismatching [2]. Second. the output samples should be converted at futed times determined by the input clock signal. However, a phase noise superimposed with the clock signal produces slight time displacements in the output samples. If the time displacements vary from sample to sample. the output signal is distorted. The thermometer code segmentation is used to reduce the distortion both due to random mismatching by limiting the size of the largest output current source and by avoiding input-dependent glitch energy [3]. Thermometer code also assures monotonicity. New switching schemes for current-steering segmented DAC to rednce even more the gradient based mismatching induced distortion have been recently reported [4][5][6]. In this paper we will focus on the distortion produced by the clock-jitter. Several authors have used as a criterion to find the optimum DAC segmentation a trade-off between the distortion due to mismatch and the area of the digital binary to thennometer decoder [5]. The originality of this work is the introduction of a third parameter in the optimization loop: the distortion due to the sampling clock-jitter. The clock-jitter can be related with the DAC segmentation because it can be originated by the switching noise generated by the simultaneous switching of many bits at the digital binary to thermometer decoder input. The larger the
thermometer section is the higher the maximum number of simultaneous switching bits would be and hence. a larger clock-jitter should be produced, because the noise induced in the internal power supply lines dynamically affect the delay of the clock driver. In section 2 the relation between the DAC architecture. the switching noise amplitude and the clock-jitter is addressed. Section 3 presents the high-level model of thel6-bit DAC converter and the simulation procedure used for detennining the SFDR. Section 4 shows the SFDR results obtained for different DAC segmentation schemes and various clock-jitter amplitudes. Finally. section 5 summarises the main results of the work.
2. INPUT DEPENDENT CLOCK-JITTER PRODUCED BY DI/DT NOISE
Figwe 1 shows a block diagram of a 16-bit current-steering segmented DAC. The n lowest bits of the input are the binary code segment of the converter and they control directly the switches of the N LSB binary weighted output cnrrent sources. The 171 highest bits are the thennometer code segment. They are decoded to drive the switching of 2"' output current sources. all of them of the same unary weight. The size of the decoder increases exponentially with n7.
w u r data[li 01 clock
1 n ! I
I LhI;;;y I I lp;,;;;;!L, I "::,:::::':r'ig
Fig. 1. Segmented current-steering DAC. 2.1 dUdt noise generated by the decoder. When multiple bits of the thennometer code segment (TCS bits) of the input signal switch simultaneously. the decoder will generate dUdt noise (or switching noise) at the internal power supply nodes. The amount of dI/dt noise roughly depends on the effective power and ground pins package inductance. the on-chip built-in decoupling capacitance and the digital current pulse shape. The later is determined by the logic signal rise times. the saturation current of the gates output transistors and the number of simultaneously switching gates [7]. In this way. there is a relation between the TCS bits simultaneously switching and the amount of switching noise that is generated. The maximum noise will be produced when all the TCS bits make a simultaneous transition. This. a larger 111 (the number of input bits assigned to the TCS) increases the maximiun dUdt noise that is generated by the decoder in the worst case. For the sake of simplicity it will be assiuned in this work that the amplitude of the dUdt noise spike increases linearly with the number of simultaneously changing bits. Tliis is justified by the fact that the circuits with highest fan-out are the inverters that
1-5 12 0-7803-6685-9/01/$10.0002001 JEEE
complement the input bits and distribute them to several decoder gates. For example. in the vicinity of the crossover point of a sinusoidal input, one sample should be 01 11 11 11 11 11 11 11 and the next should be 1000000000000000. If the thermometer code segment has a length in = 8 bits, there will be a total of 8 simultaneous switching large fan-out inverters at the input of the decoder. Meanwhile, at the decoder output only one of the 256 bits will tum on. 2.2 Clock jitter produced by the dUdt noise. The exact time at which the analog output signal switches is fixed by the clock signal edges. The clock driver generates the internal clock signal from an external clock. The digital input codes are supplied to the synchronized with the external clock. The input bits changes generate Wdt noise at the internal power supply nodes, as explained before. That noise is either coupled directly to the clock driver if it shares the same digital power supply or it is coupled through the substrate if it does not. The dVdt and/or substrate noise affects the delay of the output driver. generating clock-jitter [SI. Figure 2 shows the simulated delay change of a clock driver due to Wdt noise generated by the decoder when multiple bits of the input code simultaneously change. The simulation was performed using HSPICE with a 0.5pm technology transistor models [9] and a typical clock driver circuitry. not shown here for confidentiality reasons. The on-chip decoupling capacitance and damping resistance are S pF and 1 R. respectively. and the power supply package pins inductance is varied from 3 nH to 10 nH. The triangular current pulse used to model the decoder activity is 500 ps wide and its amplitude is varied from 5 mA to 100 mA. The input data is changed 3 ns before the clock rising edge. Even if the current pulse due to the input data change is not simultaneous with the external clock edge (as is the case here). the damped oscillation generated by the dUdt noise pulse in the package-chip RLC resonant circuit [lo] affects the internal clock edge delay. Different noise levels from sample to sample produce different delay changes in the clock driver and this is the cause of the internal clock-jitter. This effect is much more pronounced than that due to thermal noise. as shown in [SI. h the following analysis it will be used a linear expression relating the clock-jitter amplitude and the number of input bits simultaneously switching based on the explanations of subsection 2.1 and the results of figure 2. Only the changes in the TCS bits are relevant. In this way. an increase in the size of the thermometer segment I I I will raise the maximum clock-jitter and produce a lower SFDR. as s h o w below.
w
m
Fig. 2. Clock signal delay changes caused by dVdt noise.
3. SIMULATION SET-UP
The model of the 16-bit DAC used for the simulations is based in the work of [l l] . This model is implemented in the SABER simulator [12]. An ideal ADC that samples an analog sinusoidal voltage source generates the digital sample values. This ADC is implemented using a C routine that obtains the samples by applying a successive approximation algorithm to an analog input source (see figwe 3). The ADC block provides the digital input word and the clock signal to the DAC model. mhich performs the digital-to-analog coilversion. This model contains a simple struchral description of the DAC itself
implemented using a binary array of switched current sources. In our analysis all the non-idealities that may be included in the DAC model. such as current source finite output resistance, different switching times. parasitic elements and mismatching. are hmed off. since we are interested only in the clock-jitter effects. In this case the binary output structure can be used for both binary and thermometer segments. The DAC incorporates a first order reconstruction output filter with a cut-off frequency equal to half the sampling frequency. The sampling frequency isfs = 105 MHz (sampling period T, = 9.52 us). The converter is sized to provide a differential output with a 2 V maximum amplitude across a 50 R load resistor. The exact sizes of the perfectly scaled output current sources are not relevant for the results of the analysis because they are considered ideal current sources without mismatching.
Fig. 3. DAC siinulation set-up The clock-jitter is introduced in the ADC block that generates the clock signal for the DAC by adding a variable delay to an external clock signal (see figure 3). This delay can be of two different types. One type causes a random clock-jitter. The other type causes input- dependent clock-jitter and it is calculated from the number of TCS bits changing from sample to sample using the model presented in section 2. The number of TCS bits that change is multiplied by the jitter amplitude. that is a parameter of the simulation. In the case of the random jitter a uniformly distributed random number is generated for every sample and the sample's clock delay is calculated from that number. The amplihlde of the distribution of that random number is also a parameter of the simulation. In order to determine the effects of clock-jitter in the output signal distortion and the relation ~ t h the DAC segmentation struchwe. a set of simulations are performed. The parameters of the simulations are: input frequency v,,). type of clock-jitter (random or input-dependent). number of TCS bits ( n i that ranges form 0 to 16) and clock-jitter amplitude. In the case of the random clock-jitter. the amplitude is defmed as the 50% value of the positive uniform random distribution. In the case of the input-dependent clock-jitter the amplihrde is defmed as the slope of the linear relation between the number of bits changing from sample to sample and the delay added to tlie clock signal (i.e. an amplitude of 0.5 ps/bit will produce a change in the clock signal delay of 2.0 ps if 4 of the 111 input bits of the thermometer segment switch simultaneously). Three different input frequencies are selected (1.08 MHz. 5.13 MHz and 10.9 MHz). Transient simulations are perfoimed containing SO cycles of the input sinusoidal signal. Then the FFT of the analog outpnt signal is obtained taking 131072 samples and usiug a H&g window to obtain the frequency spectnun of the output signals and to measure the SFDR.
4. RESULTS
4.1. Uniformly distributed random clock-jitter: When the clock- jitter comes from a uniform random process (i.e. thermal noise or any other source of switching noise coupled to the clock driver but not correlated with the input code stream) the observable effect in the output s iba l spectnun is an increase in the noise floor. The results are s h o w iu figure 4. where tlie noise floor obtained due to quantization errors is also included as a lower boiiiid.
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An increase of a factor of 10 in the jitter amplitude produces a 20 dB increase in the noise floor. There is also depeudeuce with the input frequencykampling frequency ratio. For lower ratios. the noise floor is lower than for higher ratios.
Uniformely distributed random clock jitter 16 bit DAC
-40 1 (AUsvAtching t f
P 80 I--to.5ps
0 2 4 6 8 10 12
Input frequency (MHz)
!s)
Fig. 4. Effects of random clock-jilter on the DAC perfonuance. Analytically, considering as the ideally sampled sinusoidal signal:
and assuming the random jitter to be described by a Gaussian distribution of N(O.O;,,,~, ) , the non-uniformly sampled jitter-distorted signal with uncertain sampling instants &can be properly modeled -[13][14]- by a uniformly sampled signal with an amplitude error As. though the mean of the slew rate, yielding an approximated noise power given by
S ( l ) = Asirz(2&t) (1)
The previous expression holds provided that the following coudition is fulfilled:
2 T L l ~ j l , , w << 1 (3) Thus. fmally. the noise power due to the DAC jitter corresponds to:
(4) The 20 dB/dec dependence on b0th-L aiid jitter accurately models the shulatiou results. When condition ( 3 ) does uot hold. the jitter- induced equivalent noise tends to saturate as a functiou of6,. as can be seen in figure 4. 4.2. Input code dependent clock-jitter: hi this case. the clock-jitter depends on the number of bits changing iu two consecutive input codes. Only the changes of the TCS bits are accouuted for. The length of the thermometer code segment 111 is varied from 0 to 16 of a total of 16 input bits. The SFDR results are shown in figure 5. The SFDR depends on the segmentatiou until a certain I I I . and then saturates. h the flat part of the curves the behavior of the SFDR is equivalent to the case of random clock-jitter (there is a 20dB reduction of the SFDR for each 10x iucrease iu the jitter amplitude and the same dependence with the input frequeucy/sampling frequency ratio. For 111 small (few TSC bits) the SFDR degrades rapidly with increasing 111.
The saturatiou in the SFDR versus ti? curves can be explained by looking at the samples binary value distribution for sinusoidal signals showi in figure 6. The fi-we shows an histogram of the number of switching bits from cousecutive input codes corresponding to different TCS lengths and for two iuput frequencies. As show in the figure. the average number of bits increases proportioually to the leugth of the thermometer segment up to 111 = 8. For larger segments the ceuter of the distribution does not change appreciably and it is around 6 to 7 simultaneous switching bits for the highest input frequency and around 5 to 6 for the lowest freqneucy. This means that the saturation point (the m value where the corner iu the SFDR ciirves appears) depends on the input frequency.
a U)
70 -
60-
m- 40 10 15 20
#bits in Thermometer code ( m ) tin = 5.13 MHz
’lo 100 -71 Clock-jitter amplitude
P 80
J o I 1 40 10 15 20
#bits in Thermometer code ( m ) fin = 10.9 MHz
110 7
Clock-jitter amplitude
(AUsvAtching b P 80 - 0 . 5 ~ ~
I 0 5 10 15 20
#bits in Thermometer code ( m )
Fig. 5. Effects of input-dependent clock-jitter on the DAC performance.
Iu the followiug. an insight on the saturation on the SFDR versus 111
curves is given. For small 111 values only the most significant bits are respousible of the clock-jitter. These bits change less frequently than the less significant bits. for an ordered sequence. A sinusoidal input produces an ordered sequence slowly changing in the mini” and maximum of the waveform and rapidly changing in the crossover part. As 111 increases the less significant bits are included in the input of the decoder. To assure that the sequence of all the 2N codes for a given number of input bits (N) appear at the input of the DAC it must be verified that in the worst case two samples of the sinus correspond to two consecutive quantization levels. This occurs at the crossover part of the wavefonn where the slope is the highest possible. As just the 111 most significaut bits are connected to the decoder input. there is a limit ratio between the sampling frequency and the input frequency. or equivalently. there is a limit 191 value that verifies that all the possible input codes are used: [$)<- 1
2 ‘’I IT ~I
For higher 111 some iuput codes are randomly skipped from the ordered sequence (if there is no relatiou between the input and the sampling frequency) and the number of TCS bits that change from sample to sample behave as a random process.
1-5 14
with the same effects on DAC performance show previously. There is a linear dependence with jitter amplitude (a 10x factor in jitter amplihide reduces 20dB the SFDR) and with input frequency (approximately 3dB of SFDR are lost for every 2x increase in the input frequency). The results obtained in this work reveal the importance of limiting the clock-jitter in high-speed DACs to values below 0.1% of the sampling period by avoiding large Wdt or substrate noise that causes clock- jitter and distorts the output signal. The influence of ni (the number of thermometer code segment bits) is only important for small segmentation ratios (nr 5 4). For larger segmentation ratios. SFDR shows no dependence on nz. Several techniques can be used to reduce the dvdt or substrate noise. but they are out of the scope of this paper. Interested readers are referred to the bibliography [7]. The dependence with the segmentation ratio that has been found in the case of input-dependent clock-jitter is proposed as an additional design criteria that can be used to find the optimal segmentation for high-speed current-steering DACs. Acknowledgements. Work supported by CICYT Project No. TIC-469. and by Fulbright fellowship FU 1998-0038446010. The authors would like to thank David Anderson and Paul Hu, from Motorola, Phoenix (AZ) and Prof Olgierd A. Palusinski form University of Arizona. Tucson (AZ) for providing the simulation models of the driver and Guido Stehr and Tao Wu for helping with the DAC SABER modeling.
0 2 4 6 8 10 12 14 16 Number of swltching bits inside the thermometer code segment
Fig. 6 Nstograin of the number of swtchmg bits causlng clock-jitter m the l6-blt DAC for two different mput frequencies and for vanous
thennoineter code segnent lengths
5. CONCLUSIONS
hi this paper the effect of clock-jitter in the performance of high- speed segmented cuurent-steering DACs has been show. The clock- jitter affects the performance either by increasing the noise floor and thus reducing the number of significant bits or by reducing the SFDR. When a randoin process independent from the input sequence originates the clock-jitter. the noise floor increases linearly with the jitter amplitude. There is also a dependence with the input frequency: for a fixed sampling frequency. higher input frequencies are more affected by clock jitter than lower frequencies. The clock-jitter is also produced by the switching noise generated in the binary to thermometer decoder. The noise generated by the decoder modifies the delay of the clock driver. The decoder switching uoise depends on the input sequence. This. the dVdt originated clock- jitter depends on the input sequence and on the decoder size. Larger segmentation ratios produce larger switching noise because the decoder comprises more bits. ln this case. dependence between the SFDR and the thermometer segment size has been found. An increase in the thermometer code segment bit count ( i n ) reduces the SFDR up to a certain ni value. For higher in values. SFDR reduction saturates and does not depend on in. Thus the input dependent clock-jitter for large segmentation ratios can be considered as random clock-jitter
REFERENCES
[l] H. Samueli, “Broadband Communications ICs: Enabling high-bandwidth connectivity in the home and office”. in Proc. IEEE 1999 ISSCC, Feb.
[2] Marcel J.M. Pelgrom, Aad C. J. Duinmaijer, and Anton P.G. Welbers, “Matching Properties of MOS Transistors”. IEEE J. Solid-Store Circriifs,
[3] David A. Johns, Ken Martin. Analog Integoied Circriit Design. John Wiley& Sons. Inc. New York, 1997.
141 Geet A. M. Van der Plas, Jan Vandendbussche, Willy Sansen, Michel S. J. Steyaert, and Geroges G.E. Gielen, “A 14-bit Intrinsic Accuracy Q’ Random Walk CMOS DAC, IEEE J. Solid-Side Circtiit.y, Vol. 34, No. 12,Dec. 1999,pp. 1708-1717.
[ 5 ] Chi-Hung Lin and Klaas Bult, “A 10-b, 500-Msaples/s CMOS DAC in 0.6 , IEEE J . Solid-Strite Circiiits, Vol. 33, No. 12, Dec. 1998, pp. 1948-
1958. 161 Yonghua Cong, and Randall L. Geiger, “Switching Sequence
Optimization for Gradient Error Compensation in Thermometer-Decoded DAC Arrays“, IEEE Tr. on Circriits rind .y\srenn-II, Vol. 47. No. 7, July
[7] Xavier Aragones, Jose Luis Gondez. and Antonio Rubio,. Ano!isis ond Soliitions for Siiitching Noise Coripling in Mixed-Signril ICs. Kluwer Academic Publishers. Boston, 1999.
[SI F r d Herzel, and Behzad Razavi, “A Study of Oscillator Jitter Due to Supply and Substrate Noise”, IEEE Tr. on Circriits rind Sistenrs-ll, Vol. 46, No. 1, Jan. 1999, pp. 56-62.
1999, pp. 26-30.
Vol. 24, NO. 5, Oct. 1989, pp. 1433-1440.
“ 2 . .
2000. pp. 585-595.
[9] MOTOROLA 0.5pm proprietaly process. [IOIPatrik Larsson, “Resonance and Damping in CMOS Circuits with On-
Chip Decoupling Capacitance”. IEEE Tr. on Circriits rind Ststenid, Nol. 45, No. 8, Aug. 1998, pp. 849-858.
[11] Guido Stehr. Behcwiorircil Modelling of o High-precision, High-speed Digitcil-to-rincinlog Converter, Master’s Thesis. Universitat Karlsruhe (TH). Germany, 1999.
[12] Sober Sinriilrrror Ver 5.0, Analogy Inc.. Beavrton, OR (USA) [13] Selim Saad Awad, ‘Analysis of Accumulated Timing-Jitter in the Time
Domain’, IEEE Tr. on Instrrinientrition rnid Memrirenrent, Vol. 47, No. 1, Feb. 1998, pp. 69-73.
[14] Ham0 Kobayashi, Masanao Moriniura, Kensuke Kobayashi. and Yoshitaka Onaya, ‘Aperture Jitter Effects in Wideband Sampling Systems’, Proc. of IMTC‘99 Conference, 1999. pp. 880-885
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of-bn
.
Combining DACs for Improved Performance
K. Ola Andersson1,2, Niklas U. Andersson1,2, Mark Vesterbacka1, and J. Jacob Wikner3
1Dept. of E.E., Linköping University, 581 83 Linköping, Sweden, fax +46131392822LiDC, Ericsson Microelectronics AB, Box 1554, 581 15 Linköping, Sweden
SummaryThis work is an overview of recently proposed methodson combining DACs in order to improve performance.Some further development of these techniques are alsopresented. The techniques aim at reducing glitches andsensitivity towards limited output impedance in currentsources.
1. IntroductionToday’s telecommunication applications require high-speed and high-resolution data converters. In, e.g., digitalsubscriber line (DSL) applications the requirements onthe digital-to-analog converter (DAC) is in the order of12-14 bits of resolution and several MHz of signal band-width. These requirements are not always easily fulfilled,and in this work we give an overview of some recentlyproposed techniques utilizing several sub DACs com-bined into one DAC for improved performance.
The current-steering approach (see Fig. 1(a)) is oftenused in high-speed applications, since the architecture en-ables fast operation. The performance is however oftenlimited by linearity problems. Mismatch between thetransistors in the current sources causes errors in the bitweights and limits the static linearity of the DAC. Tosolve this problem calibration or randomization tech-niques, so called dynamic element matching (DEM, seee.g. [1]), are often suggested. In some applications distor-tion is more crucial than the noise, especially in oversam-pled systems where much of the noise typically can befiltered out. DEM techniques utilize redundant codes andrandomization to transform distortion into noise with thebenefit of linearizing the device but introducing moreswitching activity and hence noise. There are schemes tominimize the glitching activity and still maintain a rea-sonable amount of randomization [2, 3]. It is also knownthat the glitching activity is reduced by using specialcodes, such as segmentation of the MSBs or other ar-rangements. In this work we overview different ways tocombine a pair of converters to reduce the glitches to arelatively low (digital) hardware cost. In Sec. 3 we high-light an example where the converters are linearly coded[4] yielding low glitch errors.
For higher signal and updating frequencies dynamic erors tend to be the limiting factor on the linearity. Onsource of dynamic nonlinearity is the nonzero output cpacitance of the current sources, causing signal depeent settling errors, which in turn yields an overanonlinear behavior. This phenomenon was modeled wMatlab in [5]. The equivalent circuit representation othat Matlab model is shown in Fig. 1(b). It includes thoutput capacitance and resistance of the current sourcswitch resistance, wire resistance and capacitance.Sec. 4 we give an example on how to use two sub DACto reduce the distortion due to limited output impedancby introducing redundancy which allows the commonmode signal to be varied.
2. General multi-DAC conceptAssume that we have an -bit DAC consisting of a set
parallel sub DACs, with their outputs summed to produce the total output. The number of weights in the suDACs are chosen so that the overall -bit resolution ca
Figure 1: (a) Ideal and (b) model of current-steeringDAC including parasitic resistances and capacitances
NM
N
I0 Ij IN-1
b0 bj bN-1
RLRL
I-I+A+ A-
(a)
(b)
tedni-
2
le.e
bi-e ofsf],
ei-
-hu-intoy
n-s
ag-r
C
hi-
c-wee
be met. The input to each sub DAC is denoted . Welet the outputs of the sub converters, and , be dif-ferential, where . is the maxi-mum amplitude that can be represented by the given subDAC. The sum of inputs equals the overall input and thesum of the outputs equals the wanted output.
In e.g. [1] investigations are presented on how the influ-ence of analog errors can be spectrally shaped and atten-uated in the signal band. The investigations use theconcept of DAC banks and then digital encoding circuitsto redistribute the signal to the different DACs. As men-tioned, the drawback with these methods is the increasedswitching activity and in e.g. [2] and [3] we find methodsto reduce the glitching and still maintain randomization ata reasonable low hardware cost.
3. Combined DACs with small relativeglitch error and DEM
In this section we present a DAC architecture that can beused to improve the glitch performance of high-speed andhigh resolution D/A converters. The basic architecturewas previously presented in [4]. In this work we alsoshow how a simple form of DEM can be incorporated inthe structure.
3.1 Linear-coded DAC architectureA linear-coded DAC is obtained by weighting the cur-rents in Fig. 1(a) according to ,j = 0, 1,…,n–1 [4]. An interesting property of the linear-coded DACis that the glitch magnitudes are small for transitions in-volving low values, and become increasingly larger fortransitions involving higher values. The distribution ofglitches is rather different from, e.g., a segmented con-verter, which has a constant envelope of glitch magni-tudes for all values. The property of nonuniform glitchdistribution can be utilized to design a DAC with lowglitch magnitudes around the DC level, i.e. a DAC with asmall relative error with respect to glitches. This is ob-tained by connecting two linear-coded DACs in parallelaccording to Fig. 2, where one DAC converts negativevalues, and the other positive values. Note that the 4:1multiplexers are used to illustrate the principle. In an im-plementation they can be simplified to one layer of ANDgates.
To explain the function of the combined DAC architec-ture we set the control inputP(n) to zero. The magnitudeof the input will be linear encoded. If we have a positiveinput, then the sign of the input is used to connect the lin-ear-coded word to DAC 2 via the 4:1 multiplexer. Mean-while, DAC 1 outputs the highest value that can berepresented. Assuming a binary-weighted number repre-sentation, this corresponds to inverting all bits of a zeroas illustrated in Fig. 2. On the other hand, if the input is
negative, the linear-coded word is inverted and connecto DAC 1, i.e. the inversion causes an increase in magtudes to a corresponding decrease in the output. DACoutputs zero.
The control inputP(n) has been designed to change roof DAC 1 and DAC 2 with respect to the sign of the dataHence, a simple form of DEM can be incorporated in thstructure by connecting this input to a pseudo-randomnary sequence (PRBS) generator that alternates the usthe DACs randomly. Note that this improvement requirelittle additional hardware. The overhead is a layer oXOR gates compared with the solution presented in [4plus the PRBS generator.
3.2 SimulationTo characterize the amount of glitching in the DAC wuse a first-order model that considers the glitch magntude G(X(n–1), X(n)) to be proportional to the sum ofweights involved in a transition from valueX(n–1) toX(n). In Fig. 3 the glitch magnitude is plotted for two 14bit DACs, where a conventional segmented DAC witseven thermometer-coded most-significant bits is simlated in (a), and the new DAC-architecture is simulated(b). A ramp with a slope of one has been used as inputboth DACs. If larger transitions are investigated, e.g., bincreasing the slope, the trend is that the glitch error is icreased, but the distribution is similar. The plot indicatethat we can expect about the same worst-case glitch mnitudes for both DACs, but a much improved behavioaround the DC level for the combined linear-coded DAarchitecture.
4. Combined DACs for immunity towardslimited output impedance
In this section we present another redundant DAC arctecture that can be utilized to limit the impact of finiteoutput impedance in the current sources. This architeture was previously presented in [6], together with a feexamples on how utilize the redundancy. In this work walso present a further developed method of utilizing thredundancy.
XmAm
+ Am–
Am– Am
max Am+–= Am
max
I j j 1+( )I 0=
Figure 2: Proposed linear-coded DAC architecturewith small relative glitch error and DEM.
0LinearencoderX(n) |X|
DAC 1 A+
Ij=(j+1)I0 A–
DAC 2 A+
Ij=(j+1)I0 A– I– I+
RL RL
X<00
0
0
0
0
P(n)
0
0
e
-.ntle,e-v-
hto
e
lyie,oide-en-ed
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de
4.1 Architecture overviewThe single-ended output currents for the ideal current-steering DAC in Fig. 1(a) are given by
and , (1)
and the differential output current by
(2)
where is the unit current, is bit of the input code, is the inverse of , and is the weight of bit .
The proposed redundant architecture is shown in Fig. 4,composed of two parallel, nominally identical, current-steering DACs (DAC1 and DAC2). The input signal toDACi is denoted , where
and (3)
. (4)
is a control signal and is the maximum valuof , which occurs when for all . If is binarycoded, then is achieved by inverting all individual bits of , motivating the inverter symbol in Fig. 4The terminals of each DAC is connected to a sileDC voltage . With ideal DACs, the control signa
is added to both output currents (multiplied with thgain of the DACs). For the differential current
, the same operation as is achieved as bfore. This architecture is redundant in that there are seeral ways of representing the differential signal witdifferent common-mode signals, since is addedthe common-mode input signal . Onefactor that limits the possibly useful control signals is thcommon-mode rejection of the following circuitry.
In an implementation, the two DACs have to be mutualwell-matched, preferably manufactured on the same dsharing same master bias, etc. It is also important to avclock skew between the two DACs, and therefore it is dsirable that they share the same clock net. Obvious palties, compared to conventional DACs are increasarea requirements and power consumption
4.2 SimulationsOne choice of discussed in [6] is a random dithesignal with a given amplitude. This choice of yielda form of DEM. Another choice that was mentioned i[6], is to choose as the smallest constant signavoiding overflow of and . In this way the parasitic load at the output nodes is lowered. This approachonly applicable to a limited class of signals, i.e., the onthat do not utilize the possible input range, and need totimate the maximum value of all future samples of the input signal. In this work we modify this approach aninstead choose as the smallest integer fulfilling thboundary conditions
and (5)
(6)
Figure 3: Glitching in 14-bit DACs with (a)conventional 7-bit segmented architecture and (b) theproposed linear-coded architecture.
Boundary condition (5) ensures that overflow is avoided,and is chosen such that the common mode varia-tions can be sufficiently rejected in following circuitry (inthe previous approach, ). The boundary con-ditions should hold for all , so we need to keep track ofa few future samples of , otherwise we risk choosing
too small to fulfil both (5) and (6) for some futuresample. However, since we need to keep track of lesssamples than before, this approach is more suitable for anactual implementation.
In Fig. 5(a) and (b) we show simulated 3-tone PSD plotsfor a single DAC and for the proposed redundant DACwith chosen as above respectively. The simulationmodel is a 14-bit binary weighted version of the one pre-sented in [5] (see Fig. 1(b)), parameter values are givenin Table 1, and . The peak-to-peak value forthis particular input signal is approximately 10600, andthe spectra have been normalized with respect to the peakpower. The largest distortion term is reduced from –72dB to –82 dB.
5. ConclusionsWe have presented ideas on how to combine multipleDACs in order to improve the performance in terms ofglitches and decreased sensitivity towards limited outputimpedance.
References[1] I. Galton, “Spectral shaping of circuit errors in digit-
al-to-analog converters,”IEEE Trans. on Circuitsand Systems II, vol. 44, no. 10, Oct. 1997, pp. 808-17
[2] M. Rudberg, M. Vesterbacka, N. Andersson, andJ.J. Wikner, "Glitch minimization and dynamic ele-ment matching in D/A converters,"IEEE Proc. The7th Int. Conf. on Electronics, Circuits, and Systems,ICECS’00, vol. 2, Beirut, Lebanon, Dec. 17-20,2000, pp. 899-902.
[3] C. Lyden and A. Keady, “Tree structure for mis-match noise-shaping multibit DAC,” IEE ElectronicsLetters, vol. 33, no. 17, Aug 14, 1997, p. 1431-2
[4] M. Vesterbacka, "Linear-coded D/A converters witsmall relative error due to glitches,"Proc. IEEE 2001Midwest Symp. on Circuits and Systems, MWS-CAS’01, vol. 1, Fairborn, Ohio, Aug. 14-17, 2001,pp. 280-3
[5] K.O. Andersson and J.J. Wikner, "Characterizatioof a CMOS current-steering DAC using state-spacmodels,"Proc. IEEE 2000 Midwest Symp. on Cir-cuits and Systems, MWSCAS’00, Lansing, Michigan,USA, Aug. 8-11, 2000
[6] K.O. Andersson, N.U. Andersson, M. Vesterbackand J.J. Wikner, "A differential DAC architecturewith variable common-mode level," accepted tIEEE International Symposium on Circuits and Systems, ISCAS’02, Scottsdale, Arizona, USA, May 26-29, 2002
Parameter Value
Output resistance (unit current source)
Output capacitance (unit current source)
Switch resistance (all switches)
Load and wire resistance
Load capacitance
Table 1: Simulation parameters and their values.
∆rmax
∆rmax 0=n
Xr n( )
r n( )
∆rmax 20=
1 GΩ
5 fF
100 Ω
100 Ω
200 pF
Figure 5: Simulated 3-tone PSD plot for (a) a single(conventional) DAC and (b) the proposed redundantarchitecture.
0 1 2 3 4 5
x 106
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0
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Frequency [Hz]
PS
D [d
B/H
z]
(a)
0 1 2 3 4 5
x 106
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−80
−60
−40
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0
3−tone PSD for redundant architecture
Frequency [Hz]
PS
D [d
B/H
z]
(b)
Current Mode Deglitcher for Current-Steering DACs
Jussi Pirkkalaniemi, Mikko Waltari,Marko Kosunen, Lauri Sumanen,
A current mode track-and-hold circuit designed fordeglitching a 14-bit current steering DAC is presented.The deglitcher is based on a developed highly linear cur-rent memory. The prototype circuit is designed using a0.35-m BiCMOS (SiGe) technology. According to mea-surements, a -66.8-dBc THD is achieved with a 9.1-MHzinput signal and 30-MHz clock frequency. Two-tone testgives intermodulation levels below 68 dBFS at 40-MS/ssampling rate. The power dissipation is 360 mW from a3-V power supply.1
1. Introduction
Traditionally the applications of high-speed DACshave been in video and computer graphics applications,but recently the migration to wideband wired and wire-less telecommunication standards and the evolution of ra-dio transmitter architectures toward the software-definedradio have created a need for high-speed, high-resolutiontelecommunication DACs.
In the past the research and development of DACshave been heavily concentrated on improving the static(DNL, INL) and, to some extent, the time domain specifi-cations (settling time, glitch area), almost totally neglect-ing spectral purity and other frequency domain character-istics that are essential in telecommunication devices.
Practically all high-speed DACs are based on the cur-rent steering architecture, one of the main reasons forthis popularity being its capability of driving resistiveloads without buffering. A 14-bit static linearity hasbeen achieved by using trimming, self-calibration [3],and even intrinsically [1]. A typical problem in theseDACs is the rapid increase in harmonic distortion whenthe signal frequency is increased. This is mainly due tothe glitches occurring at the code changes. The glitchesare results of incoherent timing of the current switches,non-optimal shape of the switch control waveforms, andcoupling of the digital signals to the analog output.
Attempts to reduce glitches include the use of latchesto synchronize the switch controls, circuits to generate
1This work was supported by Nokia Networks and the Finnish Na-tional Technology Agency (TEKES).
Current Switches
Biasing
8 Binary Weighted 2 Binary Weighted
15 Nonweighted
Digital TrimmingCurrent Bias
IB,LSB IB,MSB
IOUT+ IOUT-
IDAC+ IDAC-
4 to 15 encoder
Latches
14
10
1525
ClockBuffer
8 171 1
DAC Clk
DG ClocksClk+
Clk-
MSBLSB
Current SourcesCurrent Sources
+
5
DigitalInput
Current Output
1 : 256
Deglitcher
Figure 1. Block diagram of the DAC.
optimal control waveforms for the switches, and the useof return-to-zero-type output to suppress the output dur-ing the code changes. The return-to-zero technique uti-lized in [2] yields a clear improvement in high-frequencySFDR compared to earlier reported DACs, but still hassome limitations, such as the difficulty of providing largeamplitudes to a low-resistance load, the complicated cir-cuitry needed to handle signal dependent parasitics, andsensitivity to clock jitter, which is not relaxed, unlike inconventional DACs, when signal frequency is decreased.To alleviate the first two of these problems the sameauthors have proposed the track/attenuate technique [3],which is basically a switch put in parallel with the load toshort the output during the DAC switching.
To avoid the jitter problem and signal attenuation it ispossible to use a track-and-hold circuit as a deglitcher;the DAC is cascaded with a T/H circuit which tracks theDAC output when it is in steady state and holds a sampledvoltage during DAC settling. Although the deglitcherdoes a good job of removing code-dependent glitches ittypically cannot achieve as high a speed as a current-steering DAC and, furthermore, the voltage output pro-vided by the T/H needs to be buffered in order to driveresistive loads.
The deglitcher presented here is based on currentmode circuitry. The output is provided in the form of
479
ESSCIRC 2002
a current which eliminates the need for a buffer. A highspeed is achieved by employing parallelism. The circuitdoes not rely on matching, which makes it very robustand eliminates the need for calibration.
2. Architecture
The core DAC, shown in Figure 1, is based on seg-mented architecture. The current sources are dividedinto two unit current source arrays, with 8 LSBs in oneand 6 MSBs in the other. In the LSB array the currentsources are binary-weighted and constructed of parallelunit sources distributed around the matrix to compensatefor linear and center-symmetric process variations. Inthe MSB matrix the two least significant bits are binary-weighted and the remaining four are formed with 15 un-weighted sources constructed of four unit sources laidout in common centroid geometry. To reduce cumula-tive mismatch errors, the consecutive unweighted sourcesare selected in such a manner that if one source is con-structed of transistors on the periphery of the matrix, thenext one will have its transistors closer to the center, andvice versa.
The current bias for the LSB and MSB arrays is gen-erated in a bias array from a single external reference cur-rent. The bias array is a current mirror that generates twocurrents, the LSB bias being 1/64 and the MSB bias 4times the reference. The current ratio can be manuallytrimmed with an external 5-bit control signal.
The current switches are controlled with a 10-bit bi-nary code and a 16-level thermometer code, which aresynchronized with a latch stage before the switches.
The DAC output is connected to the deglitcher, whichrequires a 1.75-V voltage headroom; thus, the DAC hasto fit within 1.25 V when a 3.0-V supply voltage is used.This has an effect on the sizing of the current sources andthe DAC switches; the current sources are biased to a 1.2-V gate-source voltage to minimize the effect of thresholdvoltage variation in the available voltage headroom.
The clock signal is brought into the chip in differen-tial form to improve the noise rejection on the board andpackage level.
3. Deglitcher
The principle of the deglitcher is shown in Figure 2. Itconsists of four single-ended current mode sample-and-hold circuits and four switch pairs that operate in time-interleaved fashion. During one clock cycle the DAC dif-ferential output current is sampled into two current mem-ories and the other two supply to the output the currentwhich has been sampled in the previous clock cycle. Thisway the DAC is never directly connected to the outputand the sampling phase is extended to cover nearly thewhole clock cycle, maximizing the speed.
In the sampling phase the current memory is enclosedin a feedback loop that forces its current to be equal to
memoryCurrent
4
memoryCurrent
DAC
Digital input
DAC clkVc3
Vc1
Vb1 M1
M2
M3
3
CurrentSteering
IDAC+IDAC-
IOUT+
Clk+Clk-
Clk+
I3 I4Clk1 Clk2
Figure 2. The deglitcher.
Clk-Clk+
DAC clkClk1Clk2
I3
I4
Figure 3. Clock signals.
the DAC output current. At the end of the phase the feed-back loop is opened and the current gets sampled in thememory. In the hold phase the current memory acts as acurrent source, whose value is the one stored in the mem-ory. In this phase the circuit is connected to the externalload. Since the current value is set by feedback and keptunchanged when the circuit is connected to the load, noaccurate matching is required between the current mem-ories.
The clock waveforms for the circuit are shown in Fig-ure 3. The DAC is clocked at the full rate, while thedeglitcher uses a set of half-rate clocks. The currentswitches are controlled with the complementary signalsClk+ and Clk-, which have a 50% duty cycle. SignalsClk1 and Clk2 are non-overlapping clocks for the currentmemories. Two currents I3 and I4 are also shown to clar-ify the operation.
A more detailed implementation of the deglitcheris shown in Figure 4. There, the current switches are im-plemented with bipolar transistors and a cascode transis-tor is inserted between the current switch and the circuit
DAC
Digital input
DAC clkVc3
Vc1
Vb1 M1
M2
M3
CurrentSteering
IDAC+IDAC-
IOUT+
Clk+Clk-
Clk+
I3 I4Clk1 Clk2Current
Memory3
CurrentMemory
4
Figure 4. Implementation of the deglitcher.
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output. In addition, a cascode current source is added inparallel with the DAC to bias the current memory. Thebase currents of the switch transistors—as long as thetransistors in the switch pair are matched—are not a prob-lem, since the switches are enclosed in the feedback loopwhen the current is sampled.
3.1. Current Memory
Typically, the current memories are based on a MOStransistor whose gate capacitance is used as an internalstorage element, while the memory input and output areboth the drain current.
As regards high resolution applications, the most se-vere limitation of this circuit is the harmonic distortionoriginating from the sampling switch charge injection.The nonlinear relationship between the gate voltage andthe drain current results in a situation where even a con-stant charge injection produces harmonic distortion in theoutput current. Moreover, the switch operates againstthe gate voltage (VG), which makes the charge injec-tion signal-dependent. Ways of reducing the effect ofthe charge injection range from the use of differential cir-cuitry and dummy switches to the very accurate S2I tech-nique [4].
In this design the approach taken to achieve 14-bitresolution is two-fold. First, the linearity of the currentmemory is maximized to make the circuit less sensitive tothe constant charge injection, and second, the signal de-pendency of the charge injection is significantly reduced.Furthermore, when the current memory is linear, even anerror linearly dependent on the signal can be tolerated,since it only affects the signal amplitude.
The current memory is shown in Figure 5. The gate-source voltage of the sampling switch (MS) is made vir-tually constant by using bootstrapping. Neglecting thebulk effect, this makes the channel charge, as well asthe injection resulting from its release, constant. The ac-tual switch realization is based on the circuit presentedin [5]. Bootstrapping is also a reliable way to increasethe gate voltage above the supply voltage without vio-lating the technology reliability specifications [6]. Themaximum gate overdrive yields a low on-resistance witha small switch transistor, minimizing the nonlinear para-sitic capacitances, which are effectively in parallel withthe memory capacitor.
Besides the channel charge, there is also charge re-distribution in the gate overlap capacitance CGol. Since,when entering the off-phase, the switch gate is pulled toa constant voltage, the resultant signal-dependent errorcharge is CGol VG. When the capacitances are constant(which is mostly true) and the current memory linear theerror results in only a small change in signal amplitude.If necessary, this error could be avoided by switching thegate to a voltage that is the VG properly buffered andlevel-shifted.
The high linearity of the current memory is based onthe fact that the transistor M1 (Figure 5) is biased in the
triode, not the saturation, region. There, the drain currentis given by
ID =CoxW
L
(VGS VT )VDS
V 2
DS
2
: (1)
Now, if the drain-source voltage is kept constant, the cir-cuit is perfectly linear. To make the voltage on the drainas constant as possible M1 is cascoded with the bipolartransistor Q1, which has an inherently large gm, whichis further boosted by using regulation. To achieve a highlinearity it is necessary to bias the transistor M1 deep inthe linear region. The cascode current source, consistingof M2 and M3, is for biasing M1.
The sampling speed of the deglitcher is determinedby the time constants associated with the feedback loop.When the loop is broken at the gate of M1 (leaving thecapacitor C1 on the output side) there is only one highimpedance node (the DAC output), which justifies theuse of the single pole approximation, giving the follow-ing gain-bandwidth product:
GBW =gm1
C1 + CDAC; (2)
where gm1 is the transconductance of M1 and CDAC theDAC output capacitance. Since the transconductance (to-gether with the full-scale output current) determines thevoltage swing on the memory capacitor and the capacitorvalue the sensitivity to charge injection and noise, thereis a tradeoff between speed and accuracy. The samplingswitch on-resistance and the other nodes in the loop pro-duce non-dominant poles that affect the phase margin.
3.2. LimitationsA potential problem in all circuits using time inter-
leaved parallelism is mismatch between the parallel cir-cuits. Such mismatch can produce an offset componentat half the clock frequency and a spectral image of thesignal around it. Similar image can be generated by aclock skew in the half-rate clocks. Therefore any devia-tion in the timing of the current switches should be min-imized. The current memory-based deglitcher, however,does not rely on matching as long as charge injections ofbootstrapped sampling switches and base currents of thecurrent switch pairs match. To reduce the skew error thehalf-rate clocks for the current switch control circuit aregenerated by dividing the full-rate clock with a carefullymatched synchronous divide-by-two circuit constructedwith a fully differential D-flipflop. For prototyping pur-poses a manual rise time control circuit was included inthe signal path for fine-tuning the duty cycle.
4. Experimental Results
The circuit was designed using a 0.35-m BiCMOS(SiGe) technology and the chip (Figure 6) occupies a to-tal 5.7 mm2 of silicon area. The majority of the area isconsumed by the DAC current sources, the deglitcher be-ing only a small block on the lower right corner of the
481
−
+
M1
M2
IMEM
Vref
Fb_in
Clk
n1
MS
C1
A1
biased intriode region
M3
Q1
bootstrappingcircuitry
Figure 5. BiCMOS current memory cell.
Figure 6. A microphotograph of the chip.
chip. Attention was paid to the power distribution issuesand symmetry because any deviation in the ground volt-age level between the deglitcher and its biasing circuitryresults in misbiasing of the deglitcher. A spectrum mea-sured from differential output with a 9.1-MHz input sig-nal and 30-MHz clock frequency is shown in Figure 7.The second harmonic, aliased to 11.8 MHz, lies 66.8 dBbelow the signal level. Mismatch between current mem-ories operating at the opposite clock phases produce a50-dBc offset component at half the clock frequency.Figure 8 shows measured two-tone test with input sig-nals at frequencies 11.5 MHz and 12.5 MHz, clock fre-quency being 40 MHz. Intermodulation products are be-low 68 dBFS. The power consumption, which is domi-nated by the deglitcher, is 350 mW measured from a 3.0-V supply with 40-MHz clock frequency and a 12-MHzinput signal.
5. Conclusions
The idea of using a current mode track-and-hold cir-cuit as a deglitcher after a current-steering DAC hasbeen proposed and demonstrated with a prototype circuit.The time-interleaved deglitcher uses the current copyingprinciple, which minimizes its sensitivity to componentmatching. The current memorys good linearity is basedon a bootstrapped sampling switch and a transconductorconstructed of a triode region MOSFET cascoded with aregulated bipolar transistor. Measurement results showthat good dynamic performance is achieved with high in-put signal frequencies at relatively high sampling rates.The design presented demonstrates that a current modetrack-and-hold circuit, which does not need any output
0 2 4 6 8 10 12 14 16−90
−80
−70
−60
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0
10
fclk
/2
fsig
2fsig
Frequency [MHz]
POWER SPECTRUM @ 30 MS/s
SIG
NA
L P
OW
ER
[dB
c]
Figure 7. Spectrum with a full-scale input signal.
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25−90
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2f1+f
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f2
f2−f
12f
2+f
1
Frequency [MHz]
POWER SPECTRUM @ 40 MS/s
SIG
NA
L P
OW
ER
[dB
FS
]
Figure 8. Two-tone test with -6 dBFS input signals.
buffering, can be used for removing glitches from the out-put of a high-speed current-steering DAC.
[1] G. A. M. Van der Plas, et al., “A 14-bit Intrinsic AccuracyQ2 Random Walk CMOS DAC,” IEEE JSSC, pp. 1708–1718, Dec. 1999.
[2] A. R. Bugeja, B-S. Song, P. L. Rakers, S. F. Gillig, “A14-b, 100-MS/s CMOS DAC Designed for Spectral Perfor-mance,” IEEE JSSC, pp. 1719–1732, Dec. 1999.
[3] A. R. Bugeja, B-S. Song, “A Self-Trimming 14-b 100-MS/sCMOS DAC,” IEEE JSSC, pp. 1841–1852, Dec. 2000.
[4] J. B. Hughes, K. W. Moulding, “S2I: A Switched-CurrentTechnique for High Performance,” IEE Electronics Letters,no. 16, pp. 1400–1401, Aug 1993.
[5] M. Dessouky, A. Kaiser, “Input switch configuration forrail-to-rail operation of switched opamp circuits,” IEEElectronics Letters, no. 1, pp. 8–10, Jan 1999.
[6] A. M. Abo, P. R. Gray, “A 1.5V, 10-bit, 14.3MS/s CMOSPipeline Analog-to-Digital Converter,” IEEE JSSC, pp.599–606, May 1999.
482
DESIGN AND IMPLEMENTATION OF VIDEO DAC IN 0.13pm CMOS TECHNOLOGY
Cristiun Ionuqcu Dun Burdid 'Department of Applied Electronics and Intelligent Systems e-mail address: c ionascuQetc. tuiasi . ro dburdia@etc. tuiasi . ro
2Department of Telecommunications
Faculty of Electronics & Telecommunications "Gh. Asachi" Technical University o f l a s i
ABSTRACT This paper presents the design and implementation of video
digital-to-analog converter (DAC) in CMOS 0.13pm technology on 8 bits resolution, 500 MS/s, with good performances, smaller area low glitch energy, which makes it suitable for RAMDAC (Random Memory Access Digital to Analog Converter) application. The proposed current steering DAC is a fully thermometer architecture which assumes a smaller area for a single DAC unit with a new deglitching circuit architecture added to improve the dynamic performances. In this way the interface between the digital part, which operates at low power supply 1.2V. and the analog part operating at 3.3V supply is made possible.
1. INTRODUCTION
The demand of circuits that operate at higher clock frequencies is continuously increasing. especially in signal proccssing domain. The evolution of DAC's follows the evolution of cmos technology. however the frequency is increased in nano-cmos technologies but there are more severe limitations in performances, depending on the application.
RAMDAC circuit contains triple digital-to-analog converters, according to the three fundamental colors used in color television and three input registers [ 6 ] . This kind of circuits is used to convert the digital signal derived from color palette table (usually a RAM circuit) in analog signal for VGA display. The most important block is the DAC which has to operate at pixel clock frequency with minimum distortions, to provide high current scale and precise voltage full scale level compatible with standards such RS-170, RS-343 [6] and standard load terminations (75 Ohm). Its speed determines the rtsolution level and corresponding refresh rate. Faster RAMDAC speeds. allow more pixels per second to be placed on the screen. This result in two important benefits: higher resolution allows the viewer to see better and a faster refresh rate reduces flicker and eyestrain.
Most of conventional high-speed digital to analog converters employ current steering architectures for their speed and linearity. However, the current steering DAC's show static and dynamic performance limitations due to process variation, current mismatch, and glitch energy.
There are two well-known current steering architectures: binary- weighted and unary decoded. In the first, every input signal drives directly a switch that leads the current source hinary- weighted to the output load. The drawbacks of this architecture
are high glitch energy even with very carefully design of switches and large DNL (differential nonlinearity) error [Z]. The second supposes a conversion of digital inputs into a special code named thermometer, where the number of the outputs is equal to the decimal value of the input signal. The advantages of this structure are good DNL and small dynamic switching errors. The mathematical description of current sources behavior for these two StNCtUreS is:
u(N) = K * L S B ( I ) (Binary-weighted) I
AI) = 0 LSB (2) (Unary current sources) I
In ( I ) and (2) it is assumed a normal distribution for unit current sources with standard deviation O(1)
In this work a good trade-off between performances, resolution and area concepts are described. The proposed circuit is based on the well-known current steering architecture [I]; structured on two matrix current cells with a relatively new deglitching circuit and a modified current cell schematic. The block schematic is presented in figl.
4b DAC LSB CELL i 2 rFp+--+ chlhh
8Digibl Inputs
4b DAC MSB CELL
Fig1 The block schematic ofRAMDAC (a single DAC.unit)
0-7803-7979-9/03/$17.00 02003 IEEE 381
This structure has a great advantage: the smaller area occupied by the circuit as compared to the similar converters with full thermometer decoder architecture. For example, while a 8 bits resolutions requires 256 current cells, in the 'proposed DAC structure only 15+15 current cells are needed, which is obviously a smaller area. The main drawback with this structure is the dificulty to match those two DAC's 4b (MSB cell and LSB cell) that are connected in parallel. Another important drawback is the glitch energy that occurs at code transition 00001111 into 00010000, even with equal delays of entire digital structure. The proposed deglitching circuit with careful design and layout for switches and current cells salves these tu'o drawbacks.
The 'input registers, row decoder, column decoder and the selection circuit were designed using low voltage transistors, 1.2V normal models. The thermometer decoder, practically, is made,of row. column decoders and the matrix switching decoder (selection circuit). Unlike [I] , more buffers should he added in row and column decoder to equalize time delays between MSB and LSB matrix and inherently delays between gates for these decoders. Achieving equal delays is very important in all the digital parts but especially in selection circuit [I] . Anyway in layout this task is a more dimcult one, but the deglitching circuit proposed will increase the dynamic performances (section 2).
2. DEGLITCHING CIRCUIT The schematic of this circuit is shown in fig2. A RAMDAC
circuit requires the load termination 75 ohm, as generally all video circuits, because of impedance matching with coaxial cable used in video-frequency. It could he also possible to add a special output buffer for impedance matching, which will drive the load with desired level of output voltage. However this configuration has the important drawback of limited slew rate which. of course, degrades the performance of the circuit before it. namely the DAC.
Fig2.7he schematic of deglitching circuit
The deglitching circuit will provide special signals for switches, which in this case are PMOS transistors (section 3); the required levels of the outputs are 0 and 3.3V. These high levels are required by thc "cry high full-scale current p I 7 m A ) on load
termination I5 ohms and this implieslfouf,, = I,R,, cca 1.2V. That is why, using 1.2V transistor models for analog side is impossible. The solution is in this case to use 3.3V transistor models with voltage levels for switches greater than 2V (to have enough overdrive voltage for switches). One of the important roles is to make the interface between 0-1.2V voltage levels for digital side with 0-3.3V voltage levels, with a lower crossing point (fig3).
The glitch energy appears at code transitions (usually at inajor code transitions). In thermometer architecture these glitches are with minimum energy, but improper switches sizes, improper driver signals for switches, could he major sources of errors. Glitches limit the performances of DAC, and these are revealed in SFDR (spurious free dynamic range), SNDR (signal to noise and distortion ratio), with lower values. With the proposed
- deglitch circuit the worst case glitch occurs from transitions code 15 to 16 with 6.2 pV*sec.
The reason to achieve a lower crossing paint is to never turn-off completely both of transistor switches, because the current sources may come out of saturation, and it can take a long time for the current to settle again to the correct value. The output waveforms are planed in fig3 (out and ouln). The lowering of the crossing point can he implemented by making one of the rising or falling edge slower, but this results in asymmetrically outputs of DAC. The effect is increased amplitude of spectral line for the second harmonic frequency, and to provision of an offset error in differential output voltage. Another way is to delay one of the transitions. In this circuit a combination of both methods with a minimum offset error was used.
The circuit is in fact a latch with buffers (M6-13. 3 . 3 ~ transistors) that comcts the rising and falling edges to make possible signals with minimum rise and fall time. In this way the settle time is decreased. The transistors MI, M14, M5, h44 are 3 . 3 ~ transistors and MI, M14, MO, M3 are driven by the signal with 0-1.2V levels. and MO, M3 composes an inverter 1.2V supply. The ratio between pmos sizes and nmos size:; will achieve different rise and fall times with low crossing point as in kig3.
I.On,,_l Rm- .: -, I I d .: -","
Fig.) The waveforms for deglitching circuit
382
Another iechnique to increase the dynamic performances of this DAC srchitecture is to make rising and falling edges of driving signals, especially for MSB switches, as equal as possible, by taking into account the larger capacitance that h p to be driven by the outputs signals of the deglitching circuit for MSB switches in ccmparison with LSB switches (I_MSB=16 1-LSB). AS it is shown in fig4 the signals out and outn have a lower crossing point with almost equal rising and falling edges, more delay being added between them as compared to the signals out-latch and outn-latch.
-. --
.i Jn
.: ul r
Fig.4 Output waveforms plotted according to fig.?
I
Fig.5 Current cell schematic
2. PROPOSED CURRENT CELL Video standards imply doubly load termination 75 Ohms,
large full scale output current, higher clock frequency and low
3 83
DNL, INL (integral nonlinearity) errors. To get maximum performances under these conditions, a schematic for the current cell is shown in fig.5. All transistors used in this cell (except deglitching circuit) are 3.3V transistors, M2 and M3 represents the switches, MO and MI the unary current source.
Many trade-offs have to be accomplished when designing this block, for example the switches have to be large to lower the effect of their own parasitical resistance, but on the other hand, this will increase glitches amplitude, due to the . clockfeedthrough (parasitical coupling through Cgs of MO and MI for both edges of driving signals). The solution is to minimize the sizes of switches and to increase the output impedance for the current sources. In this work, for the current sources a single cascode stage was preferred. There f e many converters with a single transistor as the current source, using the switch in saturation region to increase the overall output impedance, especially for small full-scale currents.
In this design, a minimum possible size of the switches with maximum possible impedance for current sources in case of a large LSB current value (max 65.5 PA) was obtained.
Another important problem is matching of the unary current sources. Using 131, the investigations show that the area of the objects matching can characterize the variance of the stochastic relative matching errors. As it was shown in most of the articles related to matching behavior of CMOS transistors, the larger transistors have a better performances in matching parameters. So, to achieve a good matching, a special layout techniques was developed (double common centroid): This was also accomplished using the connection of several current sources in parallel. Sizing of current sources is difficult because of limited headroom (by the necessity of large full-scale currents). This limits the maximum size transistors and the limited output impedance of current sources that has to be achieved gives minimum limit. In fig.6 the transient simulations results for IOOMhr update frequency with RC extracts is presented. The glitch energy is about 6.5pV'sec.
~ 0 m Q s m n m ~ c o ~ w I o I p . n"rInADml0lol
. _ _ " - --ms - - I 1.- (I T I
3. LAYOUT CONSIDERATIONS
Maximum Update Rate Time Settling
SFDR (Foul=ZOMhz
In this paper a high performance full custom layout was achieved, with special design of switches; using common centroidstructure. This technique provides an equal dispersion of threshold voltage and equal C , for both transistors. The layout
of switches is isolated from both MSR current sources array and LSR array. Full layout view is for a single DAC unit shown in tig7. The matching of the current sources is extremely important and this will be accomplished using special layout techniques to compensate symmetrical and graded errors caused by the temperature, process, and electrical gradients with special switchibg techniques as in [4]; [SI, and [2] (double common centroid). These techniques require a complicated routing layout. Another complicated issue is that three DAC's must be on the same chip and these have to be matched with minimum area and power consumption. A maximum INL error around 0.8 LSR is considered as acceptable, but with very good DAC to DAC matching.
The realized DAC shows a good SFDR (tig8) behavior (for video frequency bandwidth) for 8 bits resolution with post-layout simulations of parasitical RC distributed extract using Spectre simulator bsim3v3 models, technology is 0.13vm n-well four metal /single poly.
4. CONCLUSION A high performance video-dac has been presented, based on
fully thermometer current steering architecture with 8 hits resolution, low glitch energy, at high fu l l scale currenL with extremely smaller area consumption per DAC unit (0.14 mm'). The presented current sources architecture is more complex than binary ,weighted current DAC with minimum size of transistors with complicated switching sequence that implies a difficult task to develop lull custom layout. However the performances obtained. under the condition of given application. justifq. all the efforts done. Future develoomcnts of entire RAMDAC chio
3.3V (analog supply) 500 Mhz
2.511s -4YdBc
Fig .7 Layout view of a single unit DAC
Area consumption per DAC unit
I
0.14 mm2(360,,m 390 v,n)
Fig.8 SFDR over the Nyquist window -4YdRc, signal tone=20Mhz, Fclock=500 MSis
Tablel. Performance Summary (for a single DAC unit cell)
Resolution I 8 bits Supply Voltage I I .2V (digital supply),
I -61.2dRc
Fclock=SMMhz) SFDR (Fout=lMhz
I Process 1 0.13pm n-well Sour
Fclock=500Mhz) Glitch energy 6.2 pV*sec
384
Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters
Ola Andersson
Reg no: LiTH-ISY-EX-3026
November 3, 1999
Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters
Thesis for Degree of Master of Science
Department of Electrical Engineering
Division of Electronics Systems
Ola Andersson
Reg no: LiTH-ISY-EX-3026
November 3, 1999
Supervisor: J. Jacob Wikner
Examiner: Mark Vesterbacka
DAC
SammanfattningAbstract
NyckelordKeywords
RapporttypReport: category
Licentiatavhandling
C-uppsatsD-uppsatsÖvrig rapport
SpråkLanguage
Svenska/SwedishEngelska/English
ISBN
Serietitel och serienummerTitle of series, numbering
URL för elektronisk version
TitelTitle
FörfattareAuthor
DatumDateAvdelning, Institution
Division, department
Department of Electrical Engineering
ISRN
ExamensarbeteISSN
x
LiTH-ISY-EX-
95-1
1-01
/lli
Electronics Systems
3026
Mismatch Modeling and Design of CMOS Current-Steering Digital-to-AnalogConverters
The requirements on today’s telecommunications equipment are very hard. Most of the signal processingis done in the digital domain, but the information has to be transferred with analog signals, and thereforeanalog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are crucial building blocks.In this report we concentrate on the matching properties of current-steering DACs. Because transistor-level simulations are time demanding, we need to approach the problems on a higher level of abstraction.A mathematical model of so called linearly graded mismatch has been developed and analyzed for a par-ticular DAC structure.A DAC structure that will reduce the influence of linearly graded mismatch has been developed, and twosets of DAC chips with different types of current switches has been implemented. Some design issues formixed mode applications in general, and especially DACs, are also discussed.
Kraven på dagens telekommunikationsutrustning är väldigt höga. Största delen av signalbehandlingensker digitalt, men överföringen av information måste ske med analoga signaler, och därför är A/D-om-vandlare och D/A-omvandlare viktiga byggblock.I den här rapporten koncentrerar vi oss på matchningsegenskaperna hos strömstyrda D/A-omvandlare.Eftersom simulering på transistornivå är tidskrävande måste vi angripa problemen på en högre abstrak-tionsnivå. En matematisk modell av så kallat linjärt varierande matchningsfel har utvecklats och analyser-ats för en speciell D/A-omvandlarstruktur.En D/A-omvandlar struktur som minskar inverkan av linjärt varierande matchningsfel har konstruerats,och två uppsättningar D/A-omvandlarchip har implementerats. Vissa konstruktionsfrågor rörande mixed-mode-tillämpningar i allmänhet, och D/A-omvandlare i synnerhet, tas även upp.
DAC, matching, mixed mode design, current source, CMOS, analog design
x
1999-11-03
Ola Andersson
Abstract
The requirements on today’s telecommunications equipment are very hard. Most of thesignal processing is done in the digital domain, but the information has to be transferredwith analog signals, and therefore analog-to-digital converters (ADCs) and digital-to-ana-log converters (DACs) are crucial building blocks.
In this report we concentrate on the matching properties of current-steering DACs. Be-cause transistor-level simulations are time demanding, we need to approach the problemson a higher level of abstraction. A mathematical model of so called linearly graded mis-match has been developed and analyzed for a particular DAC structure.
A DAC structure that will reduce the influence of linearly graded mismatch has been de-veloped, and two sets of DAC chips with different types of current switches has been im-plemented. Some design issues for mixed mode applications in general, and especiallyDACs, are also discussed.
Acknowledgments
I would like to thank my supervisor Tekn.Lic. J. Jacob Wikner for his invaluable help inintroducing me to the world of data conversion, teaching me how to use all the IT-tools andgiving me useful remarks on my work.
My deepest gratitude to Ericsson Components AB and Ph.D. Gunnar Björklund for givingme the opportunity to do this work.
Special thanks to my office colleagues Niklas Andersson and Pierre Dahlheim Lander,without you two the spirit of the office would not have been on the same high level. I alsothank Elmo for never complaining.
Finally I thank my fiancé, Helena, for always supporting me.
C Contribution to the NORCHIP Conference, Nov 1999 ................ 49
iii
iv
Abbreviations
Notation Description
Covariance between and
Variance of
ADC Analog-to-digital converter
ADSL Assymmetric digital subscriber line
CFT Clock feedthrough
DAC Digital-to-analog converter
DNL Differential non-linearity
DSL Digital subscriber line
FFT Fast Fourier transform
HDSL High data rate digital subscriber line
INL Integral non-linearity
LSB Least significant bit
MSB Most significant bit
SFDR Spurious-free dynamic range
SNDR Signal-to-noise-and-distortion ratio
SNR Signal-to-noise ratio
VDSL Very high data rate digital subscriber line
Cov X Y,( ) X Y
Var X( ) σ2X( )= X
v
Chapter
1
Introduction
Digital-to-analog converters (DACs) are very important building blocks in telecommunica-tions equipment. A large problem for DACs, and analog designs in general, is componentmismatch. Two components, e.g., transistors or capacitors, that ideally are supposed to beidentical, suffer from dissimilarities due to process variations.
This report is a presentation of a graduation work carried out at the department of Elec-trical Engineering, Linköping University, Sweden in cooperation with the Microelectron-ics Research Center (MERC), Ericsson Components AB, Kista, Sweden. This work can bedivided into three main parts:
1. Perform a literature study on how component mismatch can be modelled2. Make a behavioral-level model of a DAC and investigate how the mismatch
affects the performance of the DAC3. Use the knowledge achieved to implement a DAC on silicon where the
mismatch influence is decreased.
1.1 BACKGROUND
With the number of Internet users growing at a very high rate, the need for better and fast-er telecommunications equipment is increasing. Digital subscriber line (DSL) is one tech-nology for bringing high bandwidth information over ordinary copper telephone lines [1].The reason for wanting to use copper lines is that this infrastructure already exist. xDSLrefers to different variations of DSL, such as HDSL (high bit-rate DSL), ADSL (asymmet-ric DSL) and VDSL (very high data rate DSL).
Most of the signal processing is performed digitally because this is more accurate than ifanalog circuitry were to be used. However, digital data has to be transferred on a long dis-tance line using only analog signals, and therefore DACs and analog-to-digital converters(ADCs) are crucial building blocks, or even the bottle-necks in some applications.
There is good knowledge in how to make high-speed/low-resolution converters or low-speed/high-resolution converters. However, what is needed today for telecom applicationsis both high-speed/high-resolution converters.
1
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
1.2 BRIEF OVERVIEW OF THE WORK
In this section we present how the work has been carried out, and also briefly how the re-port is divided.
1.2.1 Background ResearchStudies of papers treating the subject of mismatch in CMOS processes in general, andDACs in particular, show that the parameter mismatch for CMOS current sources oftenshows an approximately linear geometrical dependence. We denote this type of mismatchlinearly graded mismatch. In chapter 2 we introduce DACs on a behavioral level, and aparticular type of DAC, the current-steering DAC, is presented.
1.2.2 High-Level ApproachBecause circuit-level simulations require a large amount of time, the problem has to be ap-proached on a higher level of abstraction. A mathematical model of the DAC was developedbased on the knowledge from literature treating the subject. The performance of the DACwas analytically examined using this model, and results were achieved in terms of DNL,INL, SFDR and SNDR. This part of the work is presented in chapter 3.
To verify the analytical results, the DAC model was also implemented in MatLab. The re-sults from the MatLab simulations are presented together with the analytical results inchapter 3.
The simulation results show a very good agreement with the analytical expressions devel-oped for describing the DAC performance due to linearly graded mismatch.
The text describing the actual MatLab simulations has been placed in appendix A, this isto emphasize the simulation results rather than the simulations themselves.
The theoretical part of the work also resulted in a paper accepted for publication at theNORCHIP conference in Oslo, Norway, November 1999. This paper is included in appen-dix C.
1.2.3 ImplementationTwo sets of DAC-chips were implemented. In chapter 4 some issues concerning the chipdesign are discussed, and special care is taken to the knowledge achieved about mismatchin the theoretical part of the work. Discussions about design methodologies and the Ca-dence design tools used to implement the DACs have been placed in appendix B.
2
Chapter
2
Introduction to DACs
2.1 INTRODUCTION
The requirements on today’s telecommunication circuits are in the order of 25MHz band-width and 14-bit resolution, or even more [1]. To meet these requirements, the design ofanalog and mixed-signal circuits becomes very hard. One of the bottle-necks is the inter-face between the digital signal processing circuits and the analog amplifiers and filterssending and receiving the signal. The interface consists of the digital-to-analog converter(DAC) and the analog-to-digital converter (ADC). In this report we concentrate on thematching properties and design issues of current-steering DACs most often used in tele-communications applications. In this chapter we will introduce the reader to the conceptof DACs.
2.2 BEHAVIORAL-LEVEL DESCRIPTION
In this section we describe the behavioral-level properties of DACs to be used in this re-port. A DAC performs a mapping of a digital signal onto an analog one. The ideal DAC isdescribed in section 2.3. However, in reality DACs suffer from non-idealities, and we there-fore need some measures to describe those non-idealities. We will define static, dynamicand frequency domain properties of the DAC.
2.2.1 Static PropertiesIn Fig. 2-1 below the real and the wanted output of a DAC is plotted as a function of theinput code. We denote the wanted output for a digital input is by , and thecorresponding real output . denotes the settled value of the non-idealDAC output, compare section 2.2.2. We define the deviation from the wanted value
, and we can now introduce the following performance mea-sures:
1. Differential Non-Linearity, DNL
(2-1)
2. Integral Non-Linearity, INL
(2-2)
X Awanted X( )Areal X( ) Areal X( )
d X( ) Areal X( ) Awanted X( )–=
DNL X( ) d X( ) d X 1–( )–=
INL X( ) DNL Y( )Y X≤∑=
3
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
The DNL value describes the deviation from an ideal step in the transition between thecodes and , and INL describes the overall deviation from the wanted output.
Deviations from the wanted transfer characteristics of the DAC can be divided into twomain groups, offset errors and gain errors. The offset error may be defined as the deviationfrom the wanted minimum output, marked in Fig. 2-1. Two types of gain errors, linearand non-linear, are illustrated in Fig. 2-2 below.
Because linear gain errors and offset errors do not affect the performance of the DAC, INLand DNL are often calculated with respect to a best-fit straight line,
. and are calculated using the least square method and
the real outputs of the DAC, further discussed in [2]. Better values of INL and DNL thanin Eq.(2-1) and Eq.(2-2) are now given by:
X 1– X
0 1 2 3 4 5 6 70
1
2
3
4
5
6
7Ideal (solid) and non−ideal (dashed) output of a DAC
Out
put v
alue
Input code X
Areal 3( )Awanted 3( )
d0
Fig. 2-1: Illustration of real and wanted output of a DAC
d0
Abest-fit X( ) kX Aoffset+=
0 200 400 600 800 1000 1200 1400 16000
200
400
600
800
1000
1200
1400
1600
1800
2000
Input code
Out
put v
alue
Illustration of linear and non−linear gain error
wanted output
non-linear gain error
linear gain error
Fig. 2-2: Illustration of linear and non-linear gain error
k Aoffset
4
Chapter 2 - "Introduction to DACs"
(2-3)
(2-4)
Eq.(2-3) and Eq.(2-4) are the definitions of DNL and INL that will be used in this report.Those properties are often given in the unit [LSB] ( [LSB]), which we also will use inthis report.
2.2.2 Dynamic PropertiesWhen switching the input code from one value to another, it takes a certain amount of timebefore the output reaches it’s final value, and thus the static properties are not enough todescribe the performance of the DAC. Fig. 2-3 below shows the qualitative behavior of theoutput when switching the input code, there is also a plot of an ideal step included for easycomparison
We can define the following measurements to describe the dynamic properties
1. Rise time,
The time it takes for the output to go from 5% to 95% of it’s final value2. Settling time,
The time it takes for the output to settle within 5% of it’s final value
The percentages given in the above definitions are often used, but they are not a standard,so the reader should not be surprised if other values are given in the literature.
When we have relatively small code transitions, the output can be well approximated witha linear system, and we have so called linear settling. However, for larger code transitionsthe output driving capability is a limiting factor. We define the slew rate as
DNL X( ) Areal X( ) Areal X 1–( )– k–=
INL X( ) Areal X( ) Abest-fit X( )–=
k 1=
Fig. 2-3: Ideal step (dashed) and real step response (solid)
0 5 10 15 200
0.2
0.4
0.6
0.8
1
1.2
time
outp
ut
tr
ts
tr
ts
5
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
3. Slew rate, SR
(2-5)
where is the output value.
The dynamic properties are strongly dependent on which codes are involved in the transi-tion, and are therefore difficult to model. In this work we limit ourselves to model the in-fluence of the static errors.
2.2.3 Frequency Domain PropertiesMost of the characterization of the DAC is done in the frequency-domain [3]. It is impor-tant that the wanted signal can be separated from the noise and distortion that also ap-pears on the output of a DAC. The DAC can be characterized by the amount of power inthe signal compared to the amount of power in the noise and the distortion. The measuresdefined below, are examples of such characterizations, which will also be used later in thisreport.
1. Signal-to-Noise Ratio, SNR
(2-6)
2. Signal-to-Noise-and-Distortion Ratio, SNDR
(2-7)
3. Spurious-Free Dynamic Range, SFDR
(2-8)
In the equations above is the signal power, is the noise power, isthe the distortion power, and the power of the largest distortion term. An example ofa signal spectrum is shown in Fig. 2-4 to illustrate those concepts.
Deeper discussions on DAC performance characterization can be found in e.g. [2] or [4].
2.3 THE IDEAL DACWe need to define what we mean with the word "ideal" when describing DACs. This is donein the sections below, where the performance of the ideal DAC also is discussed.
2.3.1 Definition of the Ideal DACIf a band limited signal is sampled with a sampling frequency, , that is larger than twotimes the bandwidth of the signal, the signal can be ideally reconstructed using sinc pulsesaccording to [5]
(2-9)
where is the value of the reconstructed signal at the time , is the value of thesampled signal at sampling instant , and we sum over all values of .
The sinc function is defined as
(2-10)
Since the reconstruction of Eq.(2-9) is not possible to implement, the sinc-function has tobe replaced by a function that does not have an infinite extension in time. Most often thesinc is replaced by a square pulse, as shown in Fig. 2-5 where the sinc also is plotted. Whenwe refer to the ideal DAC in this report, we mean a DAC where the sinc has been replacedby a square pulse, i.e., sample-and-hold elements are used at the output. This causes thesignal spectrum to be sinc weighted.
This definition of the ideal DAC does not really correspond to right meaning of the wordideal, since the reconstruction of the signal is indeed not ideal. It is instead a descriptionof what we want to achieve when designing DACs.
0 0.1 0.2 0.3 0.4 0.5
−140
−120
−100
−80
−60
−40
−20
0
Sig
nal P
ower
[dB
]
Normalized frequency
signal harmonic distortion termsSFDR
Fig. 2-4: Example of a signal spectrum.
f s
Xrec t( ) X n( )sinc f st n–( )n∑=
Xrec t( ) t X n( )n n
sinc x( ) πx( )sinπx
-------------------=
7
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
2.3.2 Behavioral-Level DescriptionFor an ideal DAC, as defined in section 2.3.1 the output is only dependent on the value ofthe digital signal at the sampling instant. The -bit digital word
is mapped onto the analog value
(2-11)
in Eq.(2-11) is a reference value, often an electrical voltage, current or charge.
2.3.3 Performance of the Ideal DACSince the output of the ideal DAC exactly follows the wanted staircase of Fig. 2-1, the idealDAC will have:
(2-12)
and
(2-13)
for all input codes.
Since the output of the ideal DAC only adopts discrete levels, we will have so called quan-tization noise. According to [2] the ideal -bit DAC has a SNR value of
dB (2-14)
when applying a full scale sinusoid on the input. For an ideal DAC the SFDR is also limitedby quantization noise, which is also dependent on the sampling rate.
2.4 CURRENT -STEERING DAC STRUCTURE
There are many types of DAC realizations [2, 6]. The current-steering DAC, as sketchedin Fig. 2-6a), is suitable for high-speed and high-resolution applications [7]. The basicstructure needs no feedback loops and no operational amplifier and hence the bandwidthis large. The power efficiency is almost 100% since all current is directed to the output,
Fig. 2-5: The sinc function (dashed) plotted together with the square pulse (solid) used instead.
time
NX bN 1– bN 2– … b1 b0, , , , =
A X( ) Aref bk2k
k 0=
N 1–
∑⋅=
Aref
INL ideal 0=
DNL ideal 0=
N
SNR 6.02N 1.76+=
8
Chapter 2 - "Introduction to DACs"
where it is terminated over a resistive load (typically 50 Ohms). The -bit DAC in Fig. 2-6a) is constructed by using binary-weighted current sources, . Each current sourceutilizes parallel unit current sources, . The bits choose which current sources toconnect to the output. is the least significant bit (LSB) and is the most significantbit (MSB), hence the total output current for an ideal DAC is given by (compare with Eq.(2-11))
(2-15)
where is the binary input code at the sampling instant.
In reality it is impossible to create unit sources that produce exactly the same current. The current sources will be unmatched, and therefore Eq.(2-15) do not hold, i.e., the
DAC is non-ideal. Instead we model the binary weighted current source of bit as a nom-inal current source, , in parallel with a error source, , as illustrated in Fig. 2-6b). Theoutput of the non-ideal DAC will now become
(2-16)
where
(2-17)
In the next chapter the matching errors, , are further discussed, and a study of a specialcase of matching errors, linearly graded mismatch, is presented.
Fig. 2-6: a) Current-steering DAC and b) unit current source with matching error ∆k.
b0 b1 bN-1
I0=Iunit I1=2Iunit IN-1=2N-1Iunit
Iout
∆k
bk
Ik
Iout,k
a) b)
NN Ik I k
2k I unit bib0 bN 1–
I out n( ) bN 1– n( ) 2N 1–⋅ … b1 n( ) 2⋅ b0 n( )+ + +[ ] I unit⋅ X n( ) I unit⋅= =
X n( ) X n( ) bN 1– n( ) … b0 n( ), , =n
I unitk
I k ∆k
I out n( ) bk n( )I out k,k 0=
N 1–
∑=
I out k, I k ∆k+ I unit2k ∆k+= =
∆k
9
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
10
Chapter
3
Modeling of the Influence of LinearlyGraded Mismatch
3.1 INTRODUCTION
Analog designs are often dependent on certain relations between devices used in the de-sign. Examples of such relations can be that two transistors should be identical or thatthere should be a certain relationship between their sizes. When fabricating the design,those relations will not be fulfilled due to imperfections in the fabrication process, causingso called matching errors. In this chapter we will describe the matching errors and howthey affect the performance of the current-steering DAC.
3.2 THE CMOS PROCESS
The most commonly used process in today’s integrated circuits is the complementary metaloxide semiconductor (CMOS) process [2]. The two types of transistors available in a stan-dard CMOS process are the NMOS and the PMOS. The corresponding circuit symbols aregiven in Fig. 3-1. A simplified view of the CMOS transistor is shown in Fig. 3-2.
gate (G)bulk (B)(substrate)
drain (D)
source (S)
S
D
G B
a) b)
Fig. 3-1: Circuit symbol of a) NMOS transistor and b) PMOS transistor.
11
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
For an NMOS device the substrate is of p-type, whereas the source and the drain are heavi-ly n-doped. For a PMOS device the substrate is of n-type, whereas the source and the drainare heavily p-doped. A deeper discussion on the physics behind the metal oxide semicon-ductor field effect transistor (MOSFET) can be found in e.g. [8], in this report we onlypresent the approximate relations between currents and voltages in a MOSFET.
3.2.1 Relations for NMOS TransistorsThe MOSFET has three different regions of operation; cut-off region, linear region, andsaturation region. What region is used is dependent on the different voltages of the tran-sistor. For the NMOS transistor the following relations hold approximately [2].
1. Cut-off region
(3-1)
2. Linear region and
(3-2)
3. Saturation region and
(3-3)
The threshold voltage, , can be determined using
(3-4)
The mobility , the oxide capacitance , , and are constants for thespecific process. The subscript indicates that the constant is specific for an NMOS de-vice. The channel length modulation factor is dependent on the transistor size, but isoften set to zero when less accuracy is needed. The width, , and the channel length, ,of the transistor are indicated in Fig. 3-2. The drain current, , and the different voltagesare defined in Fig. 3-3a).
gate of poly silicon
insulator of silicondioxide
source drain
substrate
L
drain
gate
source
W
a)
b)
L
Fig. 3-2: a) Side view and b) top view of a CMOS transistor.
vGS vT n,≤( )
iD 0≈
vGS vT n,>( ) vDS vGS vT n,–≤( )
iDµ0 n, Cox
2-------------------W
L----- 2 vGS vT n,–( ) vDS–( )vDS 1 λvDS+( )≈
vGS vT n,>( ) vDS vGS vT n,–>( )
iDµ0 n, Cox
2-------------------W
L----- vGS vT n,–( )2
1 λvDS+( )≈
vT n,
vT n, VT0 n, γ 2 ΦF n, vSB– 2 ΦF n,–( )+=
µ0 n, Cox VT0 n, γ ΦF n,n
λW L
iD
12
Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"
Even though the linear relation between and that is present in the linear region isnot present in the saturated region, transistors in analog designs are most often operatedin the saturated region. This is because the current is (almost) only dependent on one volt-age, , and therefore more easily controlled than then the current for a transistor in thelinear region. An exception to this is when the transistor is used as an analog switch, andthen operated in the linear or cut-off region.
3.2.2 Relations for PMOS TransistorsThe corresponding relations for the PMOS transistor are listed below.
1. cut-off region
(3-5)
2. linear region and
(3-6)
3. saturation region and
(3-7)
The threshold voltage for the PMOS transistor, , is determined by
(3-8)
The different process parameters are similar to those for the NMOS transistor. Here thesubscript indicates that the constant is specific for the PMOS device. The drain current,
, and the different voltages are defined in Fig. 3-3b)
3.2.3 Small-Signal EquivalentsWhen analyzing the small-signal response of CMOS circuits, linearized models, small-sig-nal equivalents, of the MOSFET are used. A simple small-signal equivalent of an NMOSis shown in Fig. 3-4 below.
The small-signal parameters in Fig. 3-4 are defined as
vDS
vBS
vGS
vSD
vSB
vSGiD
iD
a) b)
Fig. 3-3: Definitions of voltages and drain current in a) an NMOS transistor and b) a PMOStransistor.
iD vGS
vGS
vSG vT p,≤( )
iD 0≈
vSG vT p,>( ) vSD vSG vT p,–≤( )
iDµ0 p, Cox
2--------------------W
L----- 2 vSG vT p,–( ) vSD–( )vSD 1 λvSD+( )≈
vSG vT n,>( ) vSD vSG vT p,–>( )
iDµ0 p, Cox
2--------------------W
L----- vSG vT p,–( )2
1 λvSD+( )≈
vT p,
vT p, VT0 p, γ 2 ΦF p, vSB– 2 ΦF p,–( )+=
piD
13
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
stance
e to
(3-9)
(3-10)
The subscript denotes that the partial derivatives are evaluated in the quiescent (DCoperation) point.
In the saturated region, Eq.(3-9) and Eq.(3-10) become
(3-11)
and
(3-12)
3.3 PARAMETER MODELING
Generally a MOSFET-parameter, , can be modeled as a sum of one fixed and one ran-domly varying term; . The random part, , which causes mismatch to thecircuit, arises from many different random processes during the fabrication. As seen in [9]those error sources can be divided into two main groups
1. Short distance variations that can be modeled as spatial white noise (the correlation diis typically much shorter than the transistor length)
2. Long distance variations arising from a circular parameter distribution on the wafer dufabrication processes such as substrate fabrication and oxide growth.
A further analysis, given in [9], gives the following result for the variance of the parametermismatch:
(3-13)
In the above equation and are the transistor width and length, is the distancebetween the compared transistors, and and are constants (for the particular wafer)describing the short- and long-distance variations of parameter respectively. FromEq.(3-13) we can see that for good matching properties we should place the transistors asclose together as possible, and keep the product as large as possible.
G
S
D
r ds1
gds-------=gmvgs
+
-
vgs
Fig. 3-4: Simplified small signal equivalent of an NMOS transistor.
gm vGS∂∂iD
Q
=
gds vDS∂∂iD
Q
=
Q
gm µ0 n, CoxWL----- vGS vT n,–( )≈ 2µ0 n, Cox
WL----- iD=
gds λµ0 n, Cox
2-------------------W
L----- vGS vT n,–( )2 λiD≈=
PP P0 ∆P+= ∆P
σ2 ∆P( )AP
2
WL-------- Sp
2Dx
2+=
W L DxAP SP
P
WL
14
Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"
3.4 MISMATCH APPLIED ON DACS
In DACs implemented with binary-weighted current sources it is very important that thecurrent sources are closely matched in order to achieve high performance (e.g. linearity,SFDR, and SNDR). The impact of uncorrelated matching properties can be reduced by theuse of unit current sources. If a binary-weighted current source is constructed usingunit current sources in parallel the relative accuracy is improved with a factor [10], ifthe mismatch is uncorrelated.
When implementing a current-steering DAC the unit sources are placed in an array as il-lustrated in Fig. 3-5. A deeper discussion of the implementation is found in chapter 4.
The long distance variations due to parameter gradients give rise to deterministic match-ing properties. However since we do not know where on the wafer the particular chip isproduced, the gradient can have any direction unknown to us. This problem has been ap-proached in a few different ways, e.g. randomization techniques [11] and special layoutstyles. Fig. 3-5a) shows the principle of a layout style used to reduce the impact of param-eter gradients [10]. The current sources that are part of a particular bit are distributed
uniformly over the array of current sources. Even though every unit source has errors asdescribed previously, this type of layout tends to cancelate those errors slightly. Fig. 3-5b)shows a more straight forward type of layout. Since the unit sources for each bit are placedvery close to each other their errors are very much correlated and the total error for a par-ticular bit can be quite large. However, this kind of layout has some advantages concern-ing, e.g., wire routing.
3.5 LINEARLY GRADED MISMATCH
The mismatch of CMOS transistors has shown to have a certain geometrical dependencewhich we choose to call linearly graded mismatch. This type of mismatch and it’s influenceon the DAC type of Fig. 3-5b) is discussed in the following sections.
3.5.1 Mismatch ModelingThe unit sources are arranged in an array with sources in the x-direction andsources in the y-direction, indexed as in Fig. 3-6a). Although this is not a particularly gooddesign strategy, we now can form the binary weighted current sources as shown in the ex-ample of a 6-bit DAC in Fig. 3-6b), where .
KK
Fig. 3-5: a) Layout reducing gradient matching errors and b) straight forward layout
unit current sourceunit current source, part of MSBunit current source, part of MSB-1
a) b)
2M
2N M–
M 3=
15
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
We model the unit current sources in the same way as the binary weighted sources, hencea nominal current source in parallel with an error source (compare with Eq.(2-17))
(3-14)
Using the notation above we have:
(3-15)
Investigations of CMOS current sources [12] show that the deterministic part of the mis-match often show a linear distribution over the chip, i.e. the geometrical dependence of thecurrent sources can be well approximated with it’s first order Taylor expansion.
Neglecting the short distance variations and assuming that the matching errors are lin-early distributed over the chip area (current source array) we can express the error sourcesas
(3-16)
(equation of a plane) where and are constants describing the linearly graded match-ing properties of the unit source array. The terms and compen-sates for the fact that there are no unit sources with index or . We will usethe unit for all currents , and thus and will have the unit
. Combining Eq.(3-15) and Eq.(3-16) we achieve an expression for
(3-17)
From Eq.(3-17) we can see that the gradient in the x-direction, as could be expected, onlyaffects the LSBs. Due to the factor in Eq.(3-17) the largest errors will occur for theMSBs, provided that is not very large compared to , which probably is a valid as-sumption.
Fig. 3-6: a) Array of unit current sources with defined directions and positions.b) Assignment of unit sources to specific bits for a 6-bit DAC.
a) b)
I5
I4
I3
I2 I1 I0dummysource
i(-1,1)i(1,1)
i(1,-1)i(-2M-1,-2N-M-1)
xy
i a b,( ) I unit δ a b,( )+=
I k 2k
I unit⋅=
∆k δ a b,( )a b,( ):i a b,( ) I k∈
∑=
δ a b,( ) kx a12--- a( )sgn–
⋅ ky b12--- b( )sgn–
⋅+=
kx ky1 2⁄( ) a( )sgn 1 2⁄( ) b( )sgn
a 0= b 0=LSB[ ] 1 LSB[ ] I unit=( ) kx ky
LSB unit source⁄[ ] ∆k
∆k
kx 2M 1– 2k 1+– 2k 1–+( )⋅ ky 2N M– 1– 2 1––( )⋅( )–( ) 2k⋅ 0 k M 1–≤ ≤,
ky 2N M– 1–
2k M– 1+
2k M– 1–
+–( )⋅– 2k⋅ M k N 1–≤ ≤,
=
M 2k
kx ky
16
Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"
3.5.2 DC Properties Arising from Linearly Graded MismatchIn this section we will qualitatively describe the DC properties of the DAC using the defi-nitions of DNL and INL in Eq.(2-3) and Eq.(2-4). Since we are mostly interested in the fre-quency domain properties, we will not perform a deeper analytical examination of the DCproperties, but be rather satisfied with simulations showing the qualitative behavior.
The simulated DNL and INL for an 8-bit DAC is shown in Fig. 3-7. There is an error gra-dient only in the y-direction (compare Fig. 3-6a), with valueand the width of the unit current source array is given by . In Fig. 3-7a) we clearlysee that DNL is largest when turning on the MSB. The same holds for the simulation re-sult in Fig. 3-7b). The INL is largest for around , since the mismatch error in thisregion is the largest (about ).
In Fig. 3-8 we show the simulated DNL and INL when introducing a gradient error in thex-direction as well. The gradients are given by . As ex-pected these plots are very similar to those in Fig. 3-7. Even though we can see that theLSBs no longer are mutually matched, the most prominent errors are still those from
ky 0.001 LSB unit source⁄[ ]=M 4=
X 2N 1–
∆N 1–±
0 50 100 150 200 250−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
Input word
INL
INL for an 8−bit DAC with M=4, ky=0.001 and kx=0
Fig. 3-7: Typical a) DNL and b) INL plot for an 8-bit DAC with linearlygraded matching errors only in the y-direction.
50 100 150 200 2500
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Input word
DN
L
DNL for an 8−bit DAC with M=4, ky=0.001 and kx=0a) b)
50 100 150 200 250
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Input word
DN
L
DNL for an 8−bit DAC with M=4, ky=0.001 and kx=0.001
0 50 100 150 200 250−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
Input word
INL
INL for an 8−bit DAC with M=4, ky=0.001 and kx=0.001
Fig. 3-8: Typical a) DNL and b) INL plot for an 8-bit DAC with linearlygraded matching errors in both the x and y direction.
a) b)
kx ky 0.001 LSB unit source⁄[ ]= =M
17
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
MSB, MSB-1 etc.
3.5.3 SFDR due to Linearly Graded MismatchMost of the characterization of the high-speed DAC is done in the frequency-domain [3].Since the distortion of a converter is dependent on input DC and amplitude level, the in-formation on DNL and INL is insufficient. We have to find models for the frequency-do-main properties as well. When applying a full-scale sinusoid at the input of the DAC, theoutput current at the sampling instant, , can be written as
(3-18)
where is the signal frequency, is the sample or update frequency, is the signal’sDC level, is the sequence index, and is the error signal due to the linearly gradedmismatch. From Eq.(2-16) we have that the error signal can be written as
(3-19)
It can be shown that
(3-20)
Using Eq.(3-20) we can calculate the mismatch error for four different inputs
(3-21)
Using this information we approximate the error signal with a piece-wise linear signal,, as shown in Fig. 3-9. Making a Fourier series expansion on the approximated error
signal gives us
I out n( )
I out n( ) 2N 1– 2πf 0
f s----- n⋅ ⋅
sin⋅ e n( ) I DC+ +≈
f 0 f s I DCn e n( )
e n( ) bk n( ) ∆k⋅k 0=
N 1–
∑=
∆kk 0=
N 2–
∑ ∆– N 1–≈
e
0 X, 0 0 … 0 0, , , ,[ ] or 1 1 … 1 1, , , ,[ ]=
∆N 1–– X, 0 1 … 1 1, , , ,[ ]=
∆N 1– X, 1 0 … 0 0, , , ,[ ]=
=
e n( )
Fig. 3-9: Input signal (dashed) and approximative error signal (solid) plotted in different scales.
0 1 2 3 4 5 6−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
input signal
e n( )
∆N 1–
∆– N 1–
18
Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"
(3-22)
Besides , the largest coefficient is given by the 3rd harmonic, . Also, since wehave applied a full-scale sinusoid at the input, the signal amplitude is approximately
(3-23)
Combining Eq.(3-22) and Eq.(3-23) gives us the spurious-free dynamic range (SFDR) as
(3-24)
Using Eq.(3-17) for in Eq.(3-24) we get
(3-25)
Rewriting Eq.(3-25) in dB yields
dB (3-26)
Having achieved an analytical expression for SFDR, it would be nice if we somehow couldverify this with simulations. Fig. 3-10 and Fig. 3-11 show simulated values of SFDR as afunction of and respectively
e n( ) Ak 2πkf 0
f s-----n
whereAksink 1=
∞
∑0 k even,
∆N 1–4
πk------ 1 2
πk------–
k odd,
= =
A1 Ak A3
Asignal 2N 1–≈
SFDRAsignal
22⁄
A32
2⁄-----------------------≈ 9π2
4 3π 2–( )-----------------------
2
22 N 1–( )
∆N 1–2
-------------------⋅=
∆N 1–
SFDR9π2
4 3π 2–( )-----------------------
2
2N 1–
2M 1+
22 N 1–( )---------------------------
2
ky2–⋅ ⋅ 9π2
3π 2–---------------
2
22M
22N
--------- ky2–⋅ ⋅= =
SFDR 21.6 6M N–( ) 20 kylog–+≈
N M
Fig. 3-10: SFDR as a function of N for different values of M when ky=0.0001 and kx=0.
12 13 14 15 16 1730
40
50
60
70
80
90
100
SF
DR
[dB
]
Number of bits
SFDR as a function of N for different values of M, ky=0.0001 [LSB/(unit source)]
M=6
M=12
19
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
From those two simulations we can get the following “empiric” expression for SFDR:
dB (3-27)
This means that we have a verification of Eq.(3-26) as far as to the dependence of and. is a function of not yet determined.
In Fig. 3-12 the calculated value of SFDR is plotted as a function of together with sim-
ulated values for a 14-bit DAC with an array width of . We see a close agreementbetween calculated and simulated values for larger gradients, for smaller gradients thesimulated values are limited by the quantization noise, which is dependent on the FFTlength used in the simulations.
Fig. 3-11: SFDR as a function of M for different values of N when ky=0.0001 and kx=0.
6 7 8 9 10 11 1230
40
50
60
70
80
90
100
SF
DR
[dB
]
Number of bits in one row of the array
SFDR as a function of M for different values of N, ky=0.0001 [LSB/(unit source)]
N=17
N=12
SFDR K 6M 6N–+≈N
M K ky
Fig. 3-12: Calculated (solid) and simulated (dashed) values of SFDR as a function of ky for a14-bit DAC with M=8.
10−8
10−7
10−6
10−5
10−4
10−3
10−2
0
50
100
150
SF
DR
[dB
]
Gradient in the y−direction [LSB/(unit source)]
SFDR as a function ky, kx=0
10−4
64
64.5
65
65.5
ky
M 8=
20
Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"
3.5.4 SNDR due to Linearly Graded MismatchIn order to calculate the signal-to-noise-and-distortion ratio (SNDR) we need to find thepower of the error signal. We will do this in two different ways, starting with the most ac-curate statistical approach. Using Eq.(3-19) and defining , we get
(3-28)
When applying a full-scale sinusoid, the dominating covariance term, appearing twice inthe sum above, is
(3-29)
The error signals, , have the following probability functions:
(3-30)
Since we have the probability functions we can calculate the variance for each error signal,yielding
(3-31)
Since we want to use this equation to find SNDR as a function of , , and , weneed to write the :s as functions of those parameters. We find the expressions for the
:s in Eq.(3-17). However when we start manipulating those we find out that the param-eter gives us severe problems finding a neat expression for the variance of the error sig-nal. Assuming to be negligible we set it to zero in order to simplify our calculations,which is something we can justify with the simulation results in section 3.5.2. Using Eq.(3-17) we achieve:
(3-32)
Some algebraic manipulations on the above expressions give us:
(3-33)
We have the formula for a geometric sum
ek n( ) bk n( ) ∆k⋅=
Var e n( )( ) Var ek n( )( )k 0=
N 1–
∑
Cov ei n( ) ek n( ),( )i k,( ):i k≠∑
+=
Cov eN 1– n( ) eN 2– n( ),( )∆N 1–
2
48--------------–=
ek n( )
P ek n( ) x=( )12--- x 0 or ∆k=
0 otherwise
=
Var ek n( )( ) 12---
∆k2
22
------∆k
2
22
------+
⋅∆k
2
4------= =
N M kx ky∆k
∆kkx
kx
∆k
∆N 1–--------------
2N M– 1–
2k M– 1+
– 2k M– 1–
+( )2M 1+
22 N 1–( )-----------------------------------------------------------------------------------------------2k M k N 1–≤ ≤
2k 2
N M– 1–2
1––( )
22 N 1–( )----------------------------------------– 0 k M 1–≤ ≤
=
∆k
∆N 1–--------------
24
k N–16 8
k N–96– 16
k N–144+( ) M k N 1–≤ ≤
162
N2
M–
22N
-------------------
4k
0 k M 1–≤ ≤
=
21
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
(3-34)
This gives us the expression
(3-35)
In a similar way for the LSBs we get
(3-36)
Using these relations we arrive at
(3-37)
Now we can rewrite Eq.(3-28) as
(3-38)
We are now ready to express the power of the noise and distortion, , as
(3-39)
In Eq.(3-39) we have included , the power of the quantization noise, and also subtractedthe power of the error signal that appears at the signal frequency (compare with Eq.(3-22)). It is known that , and from Eq.(3-22) the value of follows. We can thuswrite Eq.(3-39) as
(3-40)
Using Eq.(3-17) and Eq.(3-23) we now get
(3-41)
In Fig. 3-13 SNDR is plotted in the same way as SFDR was in Fig. 3-12. As we can see fromthis figure there is a close agreement between the theoretical expression and the simulatedvalues. The dependence of and has been verified in the same way as for SFDR.
For small gradients the SNDR is determined by the signal-to-quantization noise ratio(SQNR)
Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"
We also see that at larger gradients when , Eq.(3-41) may be approximated by
dB (3-43)
An alternative method is to use the same approximation of the error signal as was the casefor the SFDR calculation. To find an approximate value of the power of the error signal weuse
(3-44)
where is the period of the error signal. With knowledge of the error signal approximationwe can rewrite Eq.(3-44) as
(3-45)
We can now express the power of the noise and distortion as
(3-46)
Using this value of , SNDR can be approximated with
(3-47)
or, approximating SNDR for larger gradients
dB (3-48)
10−7
10−6
10−5
10−4
10−3
10−2
0
10
20
30
40
50
60
70
80
90
SN
DR
[dB
]
Gradient in the y−direction [LSB/(unit source)]
SNDR as a function of ky, kx=0
10−4
60.8
60.85
60.9
60.95
61
Fig. 3-13: Calculated (solid) and simulated (dashed) values of SNDR as a function of ky for a14-bit DAC with M=8.
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
In Fig. 3-14 the SNDR approximation of Eq.(3-47) is plotted together with simulated val-ues, as in Fig. 3-13. As we can see from the simulations, Eq.(3-41) gives us a much betterapproximation of the SNDR than Eq.(3-47) did, on the other hand the latter was much eas-ier achieved and gives acceptably good results.
3.5.5 Simulated Signal SpectraThe influence of linearly graded mismatch on the performance of the current-steering DAChas been established in the previous sections. For completeness we also show typical sig-nal spectra arising from linearly graded mismatch. Fig. 3-15 shows the output signal spec-tra for the same input signal, but with different values of , is zero in all three.Onecan clearly see how the gradient in the y-direction give rise to harmonic distortion termsof odd order, which is typical for this kind of non-linearities.
Fig. 3-16 shows basically the same thing as Fig. 3-15, but here we have added a gradientin the x-direction. As expected from the discussion previously, appears as extra noise inthe signal spectrum.
3.6 CONCLUSIONS
In this chapter we have discussed mismatch of CMOS current sources and presented astudy of a special case of matching errors, linearly graded mismatch. The study was car-ried out for one particular way of choosing current sources from an array in a CMOS DAC,a technique known not to be good in suppressing linearly graded matching errors. Howev-er, the work presented can be seen as a proposed approach to the concept of linearly gradedmatching errors that can be applied on other layout styles. It is desirable to keep the layoutas simple as possible in order to keep the amount of time needed to design the DAC as lowas possible. Given expected process parameter variations from the vendor one can, on ahigh abstraction level, find how complex layout style is needed to reach the wanted perfor-mance, e.g. the layout style of Fig. 3-5a) will ideally reduce the influence of linearly gradedmismatch completely, but it is much more complex to design than the layout style of Fig.3-5b). If the latter is sufficient for the wanted application, it is preferred that it is used in-stead.
10−7
10−6
10−5
10−4
10−3
10−2
0
10
20
30
40
50
60
70
80
90
SN
DR
[dB
]
Gradient in the y−direction [LSB/(unit source)]
SNDR as a function of ky, kx=0
10−4
59.5
60
60.5
61
Fig. 3-14: Approximated (solid) and simulated (dashed) values of SNDR as a function of ky fora 14-bit DAC with M=8.
ky kx
kx
24
Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"
Singel−tone output from 14−bit DAC, M=8, kx=0.001, ky=0.001
Normalized frequency
Fig. 3-16: Signal spectra for different values of ky, when kx=0.001.
25
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
To get a more realistic model of the DAC one needs to introduce more non-idealities thanjust the linearly graded mismatch, e.g. short distance variations, wire resistance, finiteoutput impedance of current sources and circuit noise. Modeling of the mentioned non-ide-alities are discussed in [4]. A suggestion for future work is to combine those properties intoa DAC model to help DAC designers optimize their design on a high level of abstraction.
26
Chapter
4
Implementation of Current-SteeringDACs
4.1 INTRODUCTION
In the previous chapters the current-steering DAC has been described in a relatively ab-stract way concerning mismatch and geometrical structure, but we have not described howthe DAC is really implemented. In this chapter we describe in more detail the implemen-tation of two 14-bit DACs with two different types of current switches, and where the cur-rent sources are placed to decrease the influence of linearly graded mismatch as describedin chapter 3.
The DACs were implemented in a standard digital CMOS process with three met-al layers and two poly layers. The DACs were designed to operate at sampling frequenciesup to , using a supply voltage of .
4.2 THE IMPLEMENTED STRUCTURE
In this section we present the circuit structure of the design and the way of choosing unitsources from the array.
4.2.1 SegmentationSo far we have considered DAC structures where each bit is represented by a binary-weighted current source which is turned on and off when the bit is 1 and 0 respectively. Adisadvantage with this structure is a phenomenon called glitches, unwanted current peakson the output. Glitches occur when some current sources are switched on while others areswitched off. The worst case is the transition between and . During thistransition we might for a moment have the incorrect input (or some other incor-rect input) due to non-perfect timing of the switching signals.
To avoid glitches we can use segmentation, a transformation of the binary coded input codeto thermometer code. This transformation is illustrated for a 3-bit binary input in Table 4-1 below. We can see that during a code transition using thermometer code it will never oc-cur that some sources are switched on while others are switched off, which means that wewill have less glitches.
With an -bit binary word we will have a corresponding thermometer coded word ofbits. When we have , it is not suitable to have full segmentation, because
the thermometer coded word would then have bits. However, to avoidlarge glitches we can use segmentation on some of the MSBs. In this implementation we
0.35µm
88MHz 3.3 V
011…11 100…00111…11
N2N 1– N 14=
214 1– 16383=
27
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
have chosen the 5 MSBs for segmentation.
4.2.2 The Choice of Current SourcesThe way of choosing unit sources from the array described in chapter 3 has shown to bebad in suppressing linearly graded mismatch and should be seen as an example of howthose errors could affect the performance of DACs rather than how a DAC should be im-plemented. In the literature (e.g. [10]) layout styles have been proposed that would cancelthe linearly graded matching errors, however those are not very often easy to implement,and will have disadvantages in terms of wire resistance, wire routing etc. In this DAC im-plementation we have chosen to use a more simple, but yet effective way of choosing theunit sources in order to suppress graded errors.
We know from chapter 3 that the unit sources giving current closest to the ideal valueare those closest to the middle of the array, and the bits most often switched are the LSBs.Therefore we choose to place the sources corresponding to the LSBs in the middle of thearray as shown in Fig. 4-1 a) below. The unit sources are chosen as far to the left as possible
binary thermometer
b2b1b0 s7s6s5s4s3s2s1
000 0000000
001 0000001
010 0000011
011 0000111
100 0001111
101 0011111
110 0111111
111 1111111
Table 4-1: Example of segmentation
I unit
I0
I1
I3I2
I4
I6I5
I7
I8
a)
Fig. 4-1: Assignment of unit sources a) for the 9 LSBs and b) for the 5 segmented MSBs.
256 unit sources
non-segmented LSBss1
s2
s2s1
s31s30
s30s31
b)
28
Chapter 4 - "Implementation of Current-Steering DACs"
in each row, where also the switches are placed, in order to keep the wire resistance as lowas possible. The unused unit sources (white space in Fig. 4-1) are used for biasing the otherunit sources, as described in section 4.3.2. In order to decrease the influence of linearlygraded mismatch it is preferred that the sources are chosen in the middle of each row, butthen the wire resistance will increase, and a trade off between those two properties has tobe made.
The sources for the thermometer coded bits are chosen in a way developed for reducing theinfluence of linearly graded mismatch, as shown in Fig. 4-1b). Each of those sources usetwo rows of unit sources, one from the upper half and one from the lower half of the arrayequally spaced from the center in order to cancellate the gradient in the y-direction. Thegradient in the x-direction is already taken care of by the fact that we use an integer num-ber of rows. With exactly linearly graded mismatch this arrangement would totally erasethe mismatch for those bits. However, the mismatch is probably not exactly linearly grad-ed, and therefore we choose the thermometer bits most often turned off (s31, s30, ...) to con-trol the sources furthest away from the center of the array, since those are the sources thatmost likely have the largest mismatch.
4.3 DAC BUILDING BLOCKS
In this section the design of a few important building blocks are discussed. The analogparts are described at transistor level, but the digital parts are only described at a logiclevel since we want to emphazise on the analog issues of the DAC design.
4.3.1 The Current SourceThe currents from the unit sources are switched to a load resistance of . With a max-imum output swing of and 14 bits this means that the unit current will be
(4-1)
In order to achieve high resolution of the DAC, the output resistance of the current sourcesmust be very large.. The total output resistance is a function of the input which can bewritten as
(4-2)
where is the output resistance of one unit source. Eq.(4-2) is motivated by the fact thatwe have connected unit sources in parallel.
In Fig. 4-2 the implementation of two types of current sources are shown. The single tran-sistor current source in Fig. 4-2a) is the simplest possible current source, but the outputresistance of this current source, , is not large enough to reach high resolu-tion. In Fig. 4-2b) we have included a cascode transistor M2 which increases the outputresistance to
(4-3)
The increase of the output resistance is about a factor . In order to further increase theoutput resistance one could introduce even more cascode transistors, but then we will havea larger voltage drop over the current source, which would decrease the possible outputswing of the DAC. For this implementation we choose the single cascode current source ofFig. 4-2b), and reached an output resistance of for a unit source.
50 Ω1 V
I unit1
50 214
1–( )--------------------------- 1.22 µA≈=
X
Rout
r out
X---------=
r outX
rout 1 gds 1,⁄=
r out
gm 2,gds 2,------------ 1
gds 1,------------=
103
r out 150 GΩ≈
29
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
4.3.2 BiasingTo bias the single cascode current source we use some of the unit sources in the array notconnected to any of the switches to form a wide-swing current mirror [2], as shown in Fig.4-3. unit sources are used for the bias circuitry, and the current is therefore
. The cascode voltage, , is chosen to give as largeoutput swing as possible, keeping all transistors in the saturated region. Both and
are produced off-chip.
4.3.3 The SwitchIt is known that differential structures have many advantages [2], e.g. decreasing distor-tion etc., and therefore the DAC is made differential. The current sources are switched be-tween the terminals and as shown in Fig. 4-4. The simplest type of differential switchis constructed using two MOS transistors as shown in Fig. 4-5a), however this type ofswitch suffers from a phenomenon called clock feedthrough (CFT) [2]. When the switch isturned off the channel charge has to be removed, half of the charge will then go to the out-
Fig. 4-2: a) Single transistor current source and b) single cascode current source.
iout
iout
vbiasvbias
vcascode
a) b)
M1 M1
M2
1024 i refi ref 1024 1.22µA⋅ 1.25mA≈= vcascode
i refvcascode
iref
vcascode
1024 unit sourcesfor biasing
unit source
Fig. 4-3: Biasing the unit sources with a wide-swing current mirror.
I + I -
30
Chapter 4 - "Implementation of Current-Steering DACs"
put giving rise to an unwanted current peak. To reduce CFT we can use the so called dum-my switch of Fig. 4-5b), the dummy transistor works as a capacitor storing the channelcharge while the switching transistor is turned off, and returning it when the switchingtransistor is turned back on again. In order to store the right amount of charge, the dummytransistor has the same length, , as the switching transistor, but only half the width, .The switching signals and are further described in section 4.3.5. In this implemen-tation we have designed two chips, one using the simple switch and another using thedummy switch, in order to find which one works best.
4.3.4 Binary-to-Thermometer EncoderThe simplest form of binary-to-thermometer encoding is when a 2-bit binary code is trans-formed into a 3-bit thermometer code, something that we will call 2-3-encoding. One sim-ple way of carrying out this encoding is shown in Fig. 4-6a). Using this circuitry we caneasily achieve 3-7-encoding as shown in Fig. 4-6b), this method can be further extended toimplement a general encoding as shown in Fig. 4-6c).
I + I -
Q Q
Fig. 4-4: Differential switching of current sources.
L WQ Q
I+
Q
Q
I-
Q
Q
dummytransistors
switchingtransistors
I+
Q
I-
Q
switchingtransistors
a)b)
Fig. 4-5: a) simple differential CMOS switch b) differential CMOS dummy switch.
31
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
When the number of bits to encode is large, the depth of this encoding circuitry is alsolarge. For every additional bit to encode, the depth is increased with one gate, or in anactual implementation with two gates since an or and an and gate is implemented as a norand a nand gate with a following inverter. This means that for a large number of bits wewill have to reduce the clock frequency. To solve this problem we use pipelining, everystage of the circuitry is followed by a D-flip-flop, and therefore the signal only has to prop-agate through two gates on every clock cycle. Pipelining introduces a delay in the signal,so we have to delay the binary coded LSBs to the same extent in order not to have a mal-function of the DAC.
&
1≥b0
b1
s1
s2
s3
2-3-encoding
b0
b1
s1
s2
s3
1≥
1≥
1≥
&
&
&
b0
b1
b2
s1
s2
s3
s4
s5
s6
s7
N-(2N-1)-encoding
b0
bN-1
s1
s2
N1–
1≥
1≥
&
&
b0
bN-1
bN
s1
s2
N1–
s2
N
s2
N1+
s2
N 1+1–
a) b)
c)
Fig. 4-6: Implementation of a) 2-3-encoding, b) 3-7-encoding and c) general (N+1)-(2N+1-1)-encoding.
32
Chapter 4 - "Implementation of Current-Steering DACs"
4.3.5 Switching Signal GeneratorWhen switching a current source it is important that it is never turned off, or it will takesome time before the current settles at the right value when the current source is turnedback on again. Therefore the switches making up the differential switch as described insection 4.3.3 should never be open at the same time, and thus we need to ensure that wehave overlapping switch signals as in Fig. 4-7 below.
Those switching signals could be achieved using the circuitry in Fig. 4-8. The way the nandgates are connected ensures that the outputs are never low at the same time. In order forone of them to go low, the other has to be high.
With the set signal high, is high and is low, and with the set signal low, followsthe output of the D-flip-flop.
4.4 LAYOUT CONSIDERATIONS
In this section we discuss chip layout issues for the DAC.
4.4.1 The Overall StructureSince the DAC is a mixed analog digital structure special care has to be taken in the layoutof the circuits. From an analog viewpoint the digital parts can be seen as a high frequencytransmitter giving rise to noise in the analog circuitry through capacitive coupling on thechip. To avoid this to as large extent as possible we separate the digital parts from the an-alog and use guard rings around the analog circuitry to shield it from the digital parts. InFig. 4-9 the overall structure is shown. To avoid glitches it is important that the wires fromthe switch signal generator to the corresponding switch has the same length for all switch-es, and that the resistance of those wires is as low as possible to get short switching times,and therefore we place the switches as close to the switch signal generators as possible.The clock signal for the digital part is distributed using a tree structure as described insection 4.4.3.
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
4.4.2 The Unit SourceFrom chapter 3 we know that the design and matching properties of the unit sources arecrucial to the performance of the DAC. According to [13] metal coverage on MOS transis-tors gives very poor matching properties, and therefore we should avoid routing wires overthe current sources, or, if this is not possible, at least cover all sources in the same way.Fig. 4-10 shows a layout of a single cascode current source described in section 4.3.1. Thesource transistor M1 is made relatively long in order to suppress thermal noise, which isproportional to the transconductance of M1, , and therefore inversely proportional tothe square root of the length of M1. A long source transistors also means a small ,yielding a large output resistance. M2 is designed to have a large gain, , to yieldas large output resistance as possible.
The unit sources are arranged in an array with equally spaced sources. For reasons ofmatching it is important that all sources have the same geometrical boundary conditions,and therefore a frame of dummy (unconnected) sources is placed around the array.
4.4.3 Clock Signal DistributionThe pipelined structure of the digital circuitry means that there is a large capacitive load
SEGMENTATION
DELAY
SWITCH
SIGNAL
GENERATORS
SWITCHES
UNIT SOURCE
ARRAY
guard between analog anddigital parts
5 MSBs
9 LSBs 9 LSBs
31 bitsthermo-metercoded
digital parts
analog parts
Fig. 4-9: The overall structure of the 14-bit current-steering DAC.
gm 1,gds 1,
gm 2, gds 2,⁄
34
Chapter 4 - "Implementation of Current-Steering DACs"
for the clock to drive. It is also important for the function of the DAC that the clock signalsto the different flip-flops has approximately the same delay. Because of these two reasonsthe clock is distributed over the chip area with a tree structure as shown in Fig. 4-11 below.
Each inverter in the last stage will only have a small load to drive. If the wires betweentwo stages all have the same length, the delay will also be the same for all clock signalsfrom the output of the last stage.
4.5 THE FINAL CHIP
A plot of the whole DAC is shown in Fig. 4-12. The padframe which connects the circuit tothe outside of the chip is also included in the plot. When the chip is packaged, bondingwires attached to the pads connects the circuit to external pins of the chip, as sketched inFig. 4-13. For this implementation a 28 pin SOIC28 package is used.
The pads used differ depending on what their purpose is. In this chip four different kindsof pads are used.
1. VDD-pad, used for the upper supply voltage.2. GND-pad, used for the lower supply voltage or ground.3. Analog input/output pad.4. Digital input pad.
Common to all types of pads are the (relatively) large metal plates where the bonding wiresare attached. The first three types basically consist of a wire connected to the appropriate
vdd connection
gate of M1
gate of M2
output terminal
Fig. 4-10: Layout of single cascode current source
substrate connections toimprove performance
clock signals out
clock signal in
Fig. 4-11: Example of clock distribution for better buffering and equal clock delays
35
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
place, whereas the digital input pad is terminated with a relatively large buffer, as sche-matically shown in Fig. 4-14, in order to have well defined signals on the chip and gooddriving capability of the pad. The input pad also includes protective diodes and resistanceto ensure that the input voltage of the buffer does not reach too high or too low values, alsoshown in Fig. 4-14.
To cope with the large current peaks that might occur, capacitors with reservoirs of charg-es are connected between VDD and GND where there is chip area available. The digitalpart of the circuit is by no means optimized in size. It could be made much smaller, butsince there is a lot of chip area available, some distance is kept between building blocks tosimplify routing. The total size of the chip is approximately mm, containing al-most 45 000 transistors. Some chip data is given in Table 4-2.
2.7 2.7×
Fig. 4-12: Plot of the implemented DAC, including the pad frame
digital part
analog part
capacitors
2.7 mm
Fig. 4-13: Connecting the circuit with the outside world
bonding wires connectingthe pads to the pins
36
Chapter 4 - "Implementation of Current-Steering DACs"
The specified signal bandwidth for the DAC is , which implies a sample frequencyof at least . To improve the SNR we can use oversampling [2], i.e., we use a largersample frequency than to distribute the quantization noise over a larger frequen-cy range. The noise power appearing at frequencies above the signal band is then removedwith an analog low-pass filter. When using oversampling we operate the DAC ator .
Property Description
Supply voltage
Area core, with pads
Transistor count ~
Process
Resolution
Sample frequency
Table 4-2: Chip data for the implemented DACs
Buffer of inverters
PAD
protectioncircuitry
Fig. 4-14: Sketch of a digital input pad structure.
3.3V
1.7mm 1.2mm×( ) 2.7mm 2.7mm×( )
45000
0.35µm CMOS, 3 metal layers, 2 poly layers
14 bits
22MHz, 44MHz, 88MHz
11 MHz22 MHz
22 MHz
44 MHz88 MHz
37
"Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"
38
Appendix
A Using MatLab for Behavioral-LevelSimulations
A.1 INTRODUCTION
Due to the long simulation time, it is almost impossible to carry out transistor-level simu-lations of DACs in order to characterize the influence of mismatch. Therefore it is neces-sary to create behavioral-level models for the simulations. In this appendix we present howsuch simulations can be carried out using MatLab.
A.2 BRIEF MATLAB OVERVIEW
MatLab is a short-hand notation for Matrix Laboratory and is a technical computing envi-ronment for high-performance numeric computation and visualization. MatLab integratesnumerical analysis, matrix computation, signal processing and graphics. The basic dataelement in MatLab is the matrix, and MatLab is written to easily and quickly carry outmatrix operations.
MatLab also features a family of application-specific solutions called toolboxes. The tool-boxes contains collections of MatLab functions, called M-files, that extends the MatLab en-vironment to solve particular classes of problems. Examples of areas where toolboxes areavailable are control systems, signal processing, statistics, etc.
It is easy to create your own M-files using an ordinary text editor, such as emacs. The M-files basically contains a sequence of MatLab commands to be executed.
For further information on MatLab we refer to [14].
A.3 CREATING DAC MODELS USING MATLAB
In the models used, the DAC is represented by a -matrix containing the values of thebinary-weighted current sources given on the form , where is the cur-rent of the most significant bit and is the current of the least significant bit. This ma-trix is constructed from a matrix of unit source values where the mismatch is included. Thevalues of the chosen unit sources are summed, and the value of the binary weighted cur-rent source is achieved.
This way of representing the DAC on a high level of abstraction only allows us to modelthe influence of static non-idealities. Dynamic non-idealities, such as settling times andglitches, has to be approached in some other way.
A.4 CREATING INPUT AND OUTPUT SIGNALS FOR THE DACThe digital input signal is constructed using ideal A/D-conversion on the wanted outputsignal, e.g. a sine or a ramp. In MatLab this is done by transforming a row-matrix contain-ing the values of the wanted output into a matrix of ones and zeros where each row is thedigital representation of the corresponding element in the wanted output matrix, as de-fined below.
1 N×I N 1– … I 0, ,[ ] I N 1–
I 0
39
Appendix A - "Using MatLab for Behavioral-Level Simulations"
(A-1)
denotes the (wanted) analog value at sample instant , and is the :th bit of the cor-responding digital number, either or . This transformation is done using the M-filea2d2 [15], referred to in the code listings in section A.6.
The output signal of the DAC can now be achieved using simple matrix multiplication,which is easily done with MatLab.
(A-2)
Note that, even for an ideal DAC, and will differ, at least for some values of , sincethe transformation in Eq.(A-1) means a loss of accuracy.
A.5 ANALYZING SIGNALS IN THE FREQUENCY DOMAIN
A fast fourier transform (FFT) algorithm is included in the signal processing toolbox,which can be used to transform the output signal to the frequency domain. Because thesignal vectors used are of finite length (and are very short for simulation times reasons),the elements of the signal vectors have to be multiplied with a window function in order toyield good signal spectras. In this report all spectras are achieved using Hanning windows.Functions carrying out this, and estimating SFDR and SNDR were developed by Wikner[15].
A.6 M-FILE LISTINGS
In this section we present some of the M-files used for the behavioral-level simulations ofDACs with linearly graded matching errors.
A.6.1 createDAC.mThis function is used to produce a matrix containing the values of the different unit sourcesfrom an array with linearly graded matching errors.
function [current_sources] = createDAC(NOB, kx, ky, NOx, curr_nom)% current_sources = createDAC(NOB, kx, ky, NOx, curr_nom)%% createDAC returns an array of unit current sources with the nominal value% curr_nom and a determinstic graded error.% NOB is the number of bits to be realized, NOx is the number of% current sources in the x-direction (no. of columns in the array), kx and% ky is the mismatch [LSB/(unit source)] in the x and y direction% respectively.
a1
a2 …, ,[ ]
bN 1–1
bN 2–1 … b0
1
bN 1–2
bN 2–2 … b0
2
.
.
.
.
.
.
.
.
.
.
.
.
↔
ai
i bki
k0 1
output signal a1
a2 …, ,[ ]
bN 1–1
bN 2–1 … b0
1
bN 1–2
bN 2–2 … b0
2
.
.
.
.
.
.
.
.
.
.
.
.
I N 1– … I 0, ,[ ]T×= =
ai
ai
i
40
Appendix A - "Using MatLab for Behavioral-Level Simulations"
% find the needed number of current sources in the y-direction (rows in the% array)NOy = ceil(2^NOB/NOx);
% use the gradient in the x-directionx = 1:NOx;x = x*kx*curr_nom;x = x-mean(x);X = ones(NOy,1);X = X*x;
% use the gradient in the y directiony = 1:NOy;y = y*ky*curr_nom;y = y-mean(y);Y = ones(NOx,1);Y = Y*y;
% combine the influence of the gradients in the x- and y-direction into an% array of unit sources with linearly graded mismatchcurrent_sources = (X+Y’+curr_nom);
A.6.2 corr_choice.mThis function picks unit sources from an array given by createDAC.m and sums the valuesinto binary weighted current sources. The unit sources are chosen in a straight forwardmanor described in section 3.5.
function [sources, currents] = corr_choice(NOB, kx, ky, NOx, Ilsb);
% [sources, currents] = corr_choice(NOB, kx, ky, NOx, Ilsb);%% creates NOB binary weighted current sources by chosing, in a straight% forward way, unit sources from an array created with createDAC.% currents = [Imsb,...,Ilsb], sources is the array returned by createDAC.
x=0;y=1;for i=NOB:-1:1 for j=1:2^(i-1) x=x+1; if x > NOx x = 1; y =y+1; end currents(NOB+1-i) = currents(NOB+1-i)+sources(y,x); endend
A.6.3 INLest.mThis function estimates the INL with respect to a best-fit straight line for each digital in-put word and also returns a vector of input words for easy visualization with the MatLabplot function.
41
Appendix A - "Using MatLab for Behavioral-Level Simulations"
function [INL, inputword]= INLest(current_sources)
% function [INL, inputword]= INLest(current_sources)%% Returns the INL and the input word vector for a DAC defined by% it’s current source vector [Imsb ... Ilsb]. The INL is given in [LSB]% and the input word vector as [0 1 2 ... 2^N] (this is to make simple to% plot INL against input word)
% find the number of bitsN=length(current_sources);
% create the input ramp (digital)t=0:1:2^N-1;y=a2d2(t,N);
% create the output for a ramp inputout=(y*current_sources’)’;
%find a best-fit straight line to the outputsignal (linear regression)t_mean=mean(t);out_mean=mean(out);x1=t-t_mean;x2=x1.^2;Ilsb=sum(x1.*out)/sum(x2);ideal_out=Ilsb*x1+out_mean;
%calculate the INLINL=(out-ideal_out)/Ilsb;
%Make the input word vectorinputword=t;
A.6.4 DNLest.mThis function estimates the DNL with respect to a best-fit straight line for each digital in-put word and also returns a vector of input words for easy visualization with the MatLabplot function.
function [DNL, inputword]= DNLest(current_sources)
% function [DNL, inputword]= DNLest(current_sources)%% Returns the INL and the input word vector for a DAC defined by% it’s current source vector [Imsb ... Ilsb]. The DNL is given in [LSB]% and the input word vector as [0 1 2 ... 2^N] (this is to make simple to% plot DNL against input word)
% find the number of bitsN=length(current_sources);
% create the input ramp (digital)t=0:1:2^N-1;y=a2d2(t,N);
% create the output for a ramp inputout=(y*current_sources’)’;
42
Appendix A - "Using MatLab for Behavioral-Level Simulations"
% find a best-fit straight line to the outputsignal (linear regression)t_mean=mean(t);out_mean=mean(out);x1=t-t_mean;x2=x1.^2;Ilsb=sum(x1.*out)/sum(x2);
% calculate the DNLDNL=((out(2:length(out))-out(1:length(out)-1))-Ilsb)./Ilsb;
% Make the input word vectorinputword=t(2:length(t));
43
Appendix A - "Using MatLab for Behavioral-Level Simulations"
44
Appendix
B Integrated Circuit Design withCadence
B.1 INTRODUCTION
In this appendix we describe the different steps of integrated circuit (IC) design. The toolsused are products of Cadence Design Systems Inc., which are assumed to be the most com-mon tools when designing analog or mixed mode applications [16]. The design method de-scribed is so called full-custom design, i.e. all transistors and wires are placed manually,but there are also, at least for digital designs, a few high level design methods, using forexample VHDL, which might be preferred when larger designs are to be implemented.
Since IC is a large field, this appendix only serves as a brief presentation of the subject.For a more extensive presentation we refer to literature treating the subject, i.e. [17] or[18].
B.2 A BRIEF OVERVIEW OF THE DESIGN PROCESS
A flow chart of the design process when designing circuits with Cadence tools is shown inFig. B-1. This flow chart is, with minor modifications, valid for any kind of tools for full
custom VLSI design. As seen from Fig. B-1 there are three main design steps
1. Design of the circuit on a schematic level.2. Circuit layout.3. Netlist extraction from the circuit layout.
When designing on schematic level the design is iterated until simulations show that thecircuit works satisfactory.
Schematic
Extraction
Layout LVSDRC
Simulations
Fig. B-1: Design flow chart.
45
Appendix B - "Integrated Circuit Design with Cadence"
When the schematic is completed, a layout of the circuit has to be made, i.e., transistors,wires etc. have to be placed on the silicon surface. Design rule checks (DRCs) are carriedout on the layout to ensure that it is possible to manufacture the layout.
A netlist is extracted from the layout. This netlist is compared with the schematic netlistduring a layout-versus-schematic check (LVS). If the netlists match, the layout is finished,otherwise the layout has to be corrected.
The tools used to carry out the steps described in this section will be briefly presented inthe following sections.
B.3 SCHEMATIC EDITOR
As mentioned before, the first step in designing a circuit is usually to create a schematic.A schematic view of a CMOS inverter from the Cadence Composer schematic editor isshown in Fig. B-2a). In order for the circuit to be used as a subcell in a larger circuit, asymbolic view has to be created. A symbolic view of the CMOS inverter is shown in Fig. B-2b).
B.4 ANALOG ARTIST SIMULATIONS
The simulator in Cadence is called Analog Artist. It is easily invoked from the schematiceditor. A testbench is created in the schematic editor containing the circuitry to be testedand other needed parts such as supply voltage sources, input sources and loads. An exam-ple of a testbench for the CMOS inverter is shown in Fig. B-3.
Different types of simulations available in Analog Artist are, for example,
1. transient analysis,2. AC analysis,3. DC analysis.
The simulations also lets you sweep different parameters, e.g. transistor sizes and biasvoltages, in order to find the best possible values of those parameters.
The output of a transient analysis for the testbench of Fig. B-3 is shown in Fig. B-4.
a) b)
Fig. B-2: a) Schematic and b) symbolic view of an inverter.
46
Appendix B - "Integrated Circuit Design with Cadence"
B.5 LAYOUT EDITOR
Having iterated the design in multiple passes between the schematic editor and simula-tions, a good design has been found on the schematic level. Now it is time to make a circuitlayout. This is done with the Cadence Virtouso layout editor, a tool used to place geomet-rical shapes of different materials on the silicon surface. A layout of the inverter used asan example in this text is shown in Fig. B-5. There is also a DRC tool, which is used tocheck that the design obeys the design rules, e.g., that no wires or transistors are placedto close to each other and prevents the circuit to be correctly manufactured.
When the layout is finished, a netlist can be extracted. The netlist is then compared withthe schematic view to ensure that the layout really corresponds to the circuit you have sim-ulated earlier. From the extraction you can also find parasitic components, e.g., capaci-tances and wire resistance.
Fig. B-3: Testbench schematics for the CMOS inverter
Fig. B-4: Input (lower curve) and output (upper curve) for a transient analysis of a CMOSinverter.
47
Appendix B - "Integrated Circuit Design with Cadence"
Fig. B-5: Layout of the CMOS inverter.
48
Appendix
C Contribution to the NORCHIPConference, Nov 1999
49
Appendix C - "Contribution to the NORCHIP Conference, Nov 1999"
50
Modeling of the Influence of Graded ElementMatching Errors in Current-Steering DACs
K. Ola Andersson and J. Jacob Wiknerolaa, [email protected], Phone: +46-13-281721, Fax: +46-13-139282
Microelectronics Research Center, Ericsson Components ABDept. of E.E., Linköpings universitet, SE-581 83 Linköping, Sweden
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workerrorss thatmea-is dis-
idthigitalrface).
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e it isnaryrallelutput.otal
.
Abstract — In analog and mixed-mode circuits the matching between circuit elements iscial. For example, in binary encoded digital-to-analog converters (DACs) the matchbetween different bit weights can set the limit on the performance. Related to earliermodeling the influence of stochastic matching, the influence of graded element matchingon the performance of current-steering DACs is shown. Presented are calculated resultcorrelate very well with simulated results. As performance measures we use both staticsures as DNL and INL as well as frequency domain parameters as SNDR and SFDR. Thcussion can also be applied to other DAC structures, for example switched-capacitor.
1. INTRODUCTIONThe requirements on today’s telecommunication circuits are in the order of 25MHz bandwand 14-bit resolution or even more [1]. A crucial bottle-neck is the interface between the dsignal processing circuits and the transmitting/receiving amplifiers and filters. In the intewe also have the digital-to-analog converter (DAC) and analog-to-digital converter (ADC
In this paper we focus on the DAC, and especially the binary weighted current-steering DApresented in Sec. 2 and in [2, 3, 4]. In binary weighted structures, the matching error is mless setting the performance of the DAC. The matching errors are both of stochastic natudetermined by gradients in for example the oxide thickness and voltage drops over swires [5, 6]. In Sec. 3 we discuss the modeling of the mismatch error for a certain DAC toogy. This type of modeling has previously been reported in for example [4]. The DAC analin this paper has a very simple structure known to be bad in suppressing deterministicmatch, but the approach to deterministic mismatch that we present can be applied totypes of DACs and help us comparing different layout styles.
Mostly, wideband DACs are characterized by their behavior in the frequency domain [1]. Ecially we use the signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynrange (SFDR). Some important formulas determining the SFDR and SNDR have been dand they are presented in Sec. 5. In Sec. 4 we also briefly address the static measures inof the differential nonlinearity (DNL) and the integral nonlinearity (INL).
2. CURRENT-STEERING DAC STRUCTUREThe current-steering CMOS DAC, as sketched in Fig. 1a), is suitable for high-speed andresolution [2, 3, 7-8]. The basic structure needs no feedback loops and no operational amand the power efficiency is almost 100% since all current is directed to the output, wherterminated over a resistive load. The -bit DAC in Fig. 1a) is constructed by using biweighted current sources, . To improve matching, each current source utilizes paunit current sources, . The bits choose which current sources to connect to the o
is the least significant bit (LSB) and is the most significant bit (MSB), hence the toutput current is given by
(1)
where is the binary input code at the sampling instant
N NI k I k 2k
I unit bib0 bN 1–
I out n( ) bN 1– n( ) 2N 1–⋅ … b1 n( ) 2⋅ b0 n( )+ + +[ ] I unit⋅ X n( ) I unit⋅= =
X n( ) X n( ) bN 1– n( ) … b0 n( ), , = n
51
tegy,DAC
ize
itionalunit
current
rrent
e unitre nots.
The unit sources are arranged in an array with sources in the x-direction andsources in the y-direction, indexed as in Fig. 2a). Although it is not a very good design strawe now can form the binary weighted current sources as shown in the example of a 6-bitin Fig. 2b), where .
Actually, it is commonly known how to select unit current sources from an array to minimthe influence of gradient matching errors [7-8]. However, there is much less knowledge inhowthe errors really effect the output signal and the overall performance.
3. MISMATCH ERROR MODELINGThe mismatch error associated with a weighted current source, , is modeled as an addcurrent source with amplitude in parallel as shown in Fig. 1b). Further, we model thecurrent sources in the same way as the binary weighted sources, hence a nominalsource in parallel with an error source
(2)
With this notation we have:
and (3)
Assuming that the matching errors are linearly distributed over the chip area [5, 6, 7] (cusource array) we can express the error sources as
(4)
where and are constants describing the linearly graded matching properties of thsource array. The terms and compensate for the fact that there aunit sources with index or . We will use the unit for all curren
, and thus and will have the unit . Combining Eq(3) and Eq. (4) we achieve an expression for
Figure 1: a) Current-steering DAC and b) unit current source with matching error∆k.
b0 b1 bN-1
I0=Iunit I1=2Iunit IN-1=2N-1Iunit
Iout
∆k
bk
Ik=2k-1.Iunit
Iout,k
a) b)
2M
2N M–
M 3=
Figure 2: a) Array of unit current sources with defined directions and positions.b) Assignment of unit sources to specific bits for a 6-bit DAC.
a) b)
I5
I4
I3
I2 I1 I0dummysource
i(-1,1)i(1,1)
i(1,-1)i(-2M-1,-2N-M-1)
xy
I k∆k
i a b,( ) I unit δ a b,( )+=
I k 2k I unit⋅= ∆k δ a b,( )a b,( ):i a b,( ) I k∈∑=
δ a b,( ) kx a a( )sgn 2⁄–( )⋅ ky b b( )sgn 2⁄–( )⋅+=
kx kya( )sgn 2⁄ b( )sgn 2⁄
a 0= b 0= LSB[ ]1 LSB[ ] I unit=( ) kx ky LSB unit source⁄[ ]
∆k
52
ffectsro-
ted by
r and aerror
rror
seeFig.boutr ins
longer
nd
(5)
From Eq. (5) we can see that the gradient in the x-direction, as could be expected, only athe LSBs. Due to the factor in Eq. (5) the largest errors will occur for the MSBs, pvided that is not very large compared to , which probably is a valid assumption.
4. ERRORS IN THE CODE-DOMAINFirst, we use the differential nonlinearity (DNL) and integral nonlinearity (INL) to illustrahow graded mismatch error effects the output amplitude levels. DNL and INL are define
and (6)
where is the input code. Since in most cases we can neglect the influence of a dc errolinear gain error, the DNL and INL are calculated with respect to a best-fit line (absoluteis minimized) found using the least mean-square method and the actual output .
The simulated DNL and INL for an 8-bit DAC is shown in Fig. 3a) and b). There is an e
gradient only in the y-direction (compare Fig. 2a), with valueand the width of the unit current source array is given by . In Fig. 3a) we clearlythat DNL is largest when turning on the MSB. The same holds for the simulation result in3b). The INL is largest for around , where the mismatch error also is largest (a
). In Fig. 3c) and d) we show the DNL and INL when introducing a gradient errothe x-direction as well. The gradients are given by . Aexpected these plots are similar to those in Fig. 3a) and b). Even though the LSBs noare mutually matched, the dominating errors are still those from MSB, MSB-1 etc.
∆k kx 2M 1– 2k 1+– 2k 1–+( )⋅ ky 2N M– 1– 2 1––( )⋅( )–( ) 2k⋅= 0 k M 1–≤ ≤,
∆k ky 2N M– 1– 2k M– 1+ 2k M– 1–+–( )⋅– 2k⋅= M k N 1–≤ ≤,
M 2k
kx ky
DNLX I out X( ) I out X 1–( )– 1LSB–= INL X DNLxx X≤∑=
X
I out X( )
0 50 100 150 200 250−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
Input word
INL
INL for an 8−bit DAC with M=4, ky=0.001 and kx=0
Figure 3: Typical DNL and INL plots for an 8-bit DAC with linearly graded matching errors (a ab) only in the y-direction and (c and d) in both the x and y direction.
50 100 150 200 2500
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Input word
DN
L
DNL for an 8−bit DAC with M=4, ky=0.001 and kx=0a) b)
50 100 150 200 250
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Input word
DN
L
DNL for an 8−bit DAC with M=4, ky=0.001 and kx=0.001
0 50 100 150 200 250−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
Input word
INL
INL for an 8−bit DAC with M=4, ky=0.001 and kx=0.001c) d)
ky 0.001 LSB unit source⁄[ ]=M 4=
X 2N 1–
∆N 1–±kx ky 0.001 LSB unit source⁄[ ]= =
M
53
e theDNLwell.n as
l’s dcmis-
urces,
, ases us
have
s
5. ERRORS IN THE FREQUENCY-DOMAINMost of the characterization of the high-speed DAC is done in the frequency-domain. Sincdistortion of a converter is dependent on input dc and amplitude level, the information onand INL is insufficient. We have to find models for the frequency-domain properties asWhen applying a full-scale sinusoid to the DAC, the output current, , can be writte
(7)
where is the signal frequency, is the sample or update frequency, is the signalevel, is the sequence index, and is the error signal due to the linearly gradedmatch. Using the description of error sources from Fig. 1b) and considering all current sowe have that the total error signal can be written as
(8)
It can be shown that
(9)
Using this information we approximate the error signal with a piecewise linear signal,shown in Fig. 4. Making a Fourier series expansion on the approximated error signal giv
with for odd and 0 else. (10)
Besides , the largest coefficient is given by the 3rd harmonic, , and because weapplied a full-scale sinusoid at the input, the signal amplitude is approximately
(11)
Combining Eq. (10) and Eq. (11) gives us the spurious-free dynamic range (SFDR) as
(12)
Using Eq. (5) for in Eq. (12) we get
(13)
I out n( )
I out n( ) 2N 1– 2π f 0 f s⁄ n⋅ ⋅( )sin⋅ e n( ) I DC+ +≈
f 0 f s I DCn e n( )
e n( ) bk n( ) ∆k⋅k 0=N 1–∑=
∆kk 0=N 2–∑ ∆– N 1–≈
e n( )
0 1 2 3 4 5 6−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
Figure 4: Input signal (dashed) and approximative error signal (solid) plotted in different scale
input signal
e n( )
∆N 1–
∆– N 1–
e n( ) Ak 2πkf 0
f s-----n
sink 1=
∞∑= Ak ∆N 1–4
πk------ 1 2
πk------–
= k
A1 Ak A3
Asig 2N 1–≈
SFDRAsignal
2 2⁄A3
2 2⁄-----------------------≈ 9π2
4 3π 2–( )-----------------------
2 22 N 1–( )
∆N 1–2
-------------------⋅=
∆N 1–
SFDR9π2
4 3π 2–( )⋅----------------------------
2 2N 1– 2M 1+⋅22 N 1–( )--------------------------------
2ky
2–⋅ ⋅ 9π2
3π 2–---------------
2 22M
22N--------- ky
2–⋅ ⋅= =
54
value
ithulateduanti-
errorm thedone,et
n the
owern that
ction
Rewriting Eq. (13) in dB yields
(14)
The dependence on and has been verified in simulations. In Fig. 5a) the theoretical
of SFDR is plotted as a function of together with a simulated value for a 14-bit DAC wan array width of . We see a very good agreement between theoretical and simvalues for larger gradients, for smaller gradients the simulated values are limited by the qzation noise, which is dependent on the FFT length used in the simulations.
In order to calculate the signal-to-noise-and-distortion ratio (SNDR) we need to find thesignal power. We could use the same approximation of the error signal as before and susquares of the Fourier coefficients, but examining Eq. (10) we see that this is not easilyso a statistical approach is preferred. Using Eq. (8) and defining , we g
(15)
When applying a full-scale sinusoid, the dominating covariance term, appearing twice isum above, is
(16)
With a few minor approximations we also find
(17)
Now we can rewrite Eq. (15) as
(18)
We are now ready to express the power of the noise and distortion, , as
(19)
In Eq. (19), the power of the quantization noise is included, and also subtracted the pof the error signal that appears at the signal frequency (compare Eq. (10)). It is know
, and from Eq. (10) the value of follows. We can thus write Eq. (19) as
SFDR 21.6 6M N–( ) 20 kylog–+≈
M N
10−7
10−6
10−5
10−4
10−3
10−2
0
10
20
30
40
50
60
70
80
90
SN
DR
[dB
]
Gradient in the y−direction [LSB/(unit source)]
SNDR as a function of ky, kx=0
10−4
60.8
60.85
60.9
60.95
61
Figure 5: Theoretical (solid) and simulated (dashed) values of (a) SFDR and (b) SNDR as a funof ky for a 14-bit DAC with M=8.
10−8
10−7
10−6
10−5
10−4
10−3
10−2
0
50
100
150
SF
DR
[dB
]
Gradient in the y−direction [LSB/(unit source)]
SFDR as a function ky, kx=0
10−4
64
64.5
65
65.5
a) b)
kyM 8=
ek n( ) bk n( ) ∆k⋅=
Var e n( )( ) Var ek n( )( )k 0=
N 1–∑ Cov ei n( ) ek n( ),( )i k,( ):i k≠∑+=
Cov eN 1– n( ) eN 2– n( ),( ) ∆N 1–2 48⁄–=
Var ek n( )( )k 0=N 1–∑ ∆N 1–
232 140 4M N–⋅+( ) 105⁄⋅≈
Var e n( )( ) ∆N 1–2
32 140 4M N–⋅+( ) 105⁄ 1 24⁄–( )⋅≈
PND
PND Var e n( )( ) Pq A12 2⁄–+=
Pqf 0
Pq 1 12⁄= A1
55
mentDR islso
eringents.earlyd (e.g.ecteded to
per isroachbined
outputt can
r at
n,”
of
igi-
(20)
Using Eq. (5) and Eq. (11) we now get
(21)
In Fig. 5b) SNDR is plotted in the same way as for the SFDR. We see a very good agreebetween the theoretical expression and the simulated values. At small gradients, the SNdetermined by the signal-to-quantization noise ratio dB. We asee that at larger gradients when , Eq. (21) may be approximated by
(22)
6. CONCLUSIONSWe have derived formulas describing the frequency-domain performance of current-steCMOS DAC when applying linearly graded matching errors to unit current source elemCalculated and simulated results correlate very well. To decrease the influence of lingraded matching properties, different techniques and layout styles have been propose[7]). However, it is desirable to make the design as simple as possible, and given expparameter variations one can predict what type of technique or layout style that is needreach a certain goal in terms of DAC performance. The DAC structure analyzed in this parather naive. For example the lack of segmentation may increase glitches, but the appused to treat deterministic mismatch could also be applied to other structures and comwith models of other error sources such as random mismatch, wire resistance, and finiteimpedance we are able to find a very good model of current-steering DACs, a model thabe used to design high performance DACs without too much trial and error.
The authors would like to thank Niklas U. Andersson and Pierre Dalheim-LandeLinköpings universitet, Sweden, for their help.
7. REFERENCES[1] P. Hendriks, “Specifying communication DACs,”IEEE Spectrum, Vol. 34, No. 7, pp. 58-
69, July 1997[2] D.A. Johns and K. Martin,Analog integrated circuit design, John Wiley & Sons, New
York, NY, USA, 1997[3] R.J. van de Plassche,Integrated analog-to-digital and digital-to-analog converters, Klu-
wer Academic Publishers, Boston, MA, USA, 1994[4] J.J. Wikner and N. Tan, “Modeling of CMOS D/A Converters for Telecommunicatio
IEEE T. of Circuits and Systems II, May 1999[5] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching Properties
MOS Transistors,”IEEE J. of Solid-State Circuits, vol. 24, pp. 1433-39, Oct. 1989.[6] J. Bastos, et al, “Mismatch Characterization of Submicron MOS Transistors,”Analog
Integrated Circuits and Signal Processing, Vol. 12, pp. 95-106, 1997[7] H. J. Schouwenaars, et al, “A Low-Power Stereo 16-bit CMOS D/A Converter for D
tal Audio,” IEEE J. of Solid-State Circuits, Vol. 23, pp. 1290-1297, Dec. 1988.[8] T. Miki et al, “An 80 MHz 8-bit CMOS D/A Converter,”IEEE J. of Solid-State Circuits,
[1] T. Starr, J.M.Cioffi, and P.J. Silverman, Understanding Digital Subscriber LineTechnology, Prentice Hall PTR, Upper Saddle River, NJ, USA, 1999, ISBN 0-13-780545-4
[2] D.A. Johns and K.Martin, Analog Integrated Circuit Design, John Wiley & Sons, NewYork, NY, USA, 1997, ISBN 0-471-14448-7
[4] J.J. Wikner, Digital-to-Analog Converters for Telecommunication Applications,Linköping Studies in Science and Technology, Thesis no.715, 1998, 91-7219-277-1
[5] S. Söderkvist, and L.-E. Ahnell, Tidsdiskreta Signaler och System
[6] R.J. van de Plassche,Integrated analog-to-digital and digital-to-analog converters, Klu-wer Academic Publishers, Boston, MA, USA, 1994
[7] K. Lin, and C.H. Bult, “A 10b 250MSample/s CMOS DAC in 1mm2”, in Proc. of the1998 IEEE Int’l Solid-State Circuits Conf. (ISSCC’98), pp.214-15, San Fransisco, CA,USA, Feb 1998
[8] B.G. Streetman, Solid State Electronic Devices, Prentice-Hall Inc, Englewood Cliffs,NJ, USA, 1995, ISBN 0-13-436379-5
[9] M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, “Matching Properties ofMOS Transistors”, IEEE J. of Solid-State Circuits, vol. 24, no. 5, pp. 1433-9, Oct 1989
[10] C.A.A. Bastiaansen, D.W.J. Groeneveld, H.J. Schouwenaars, and H.A.H. Termeer“A 10-b 40-MHz 0.8 m CMOS Current-Output D/A Converter”, IEEE J. of Solid-State Circuits, vol. 26, no. 7, pp. 917-21, Jul 1991
[11] N.U. Andersson, and J.J.Wikner, “A Comparison of Dynamic Element Matching inDACs”, in Proc. of Norchip 1999, Oslo, Norway, Nov 1999
[12] H.J. Schouwenaars, D.W.J. Groeneveld, and H.A.H. Termeer “A Low-Power Stereo16-bit CMOS D/A Converter for Digital Audio”, IEEE J. of Solid-State Circuits, vol.23, no. 6, pp. 1290-7, Dec 1988
[13] H. Tuinhout, M.J.M. Pelgrom, R. Penning de Vries, and M. Vertregt, “Effects ofMetal Coverage on MOSFET matching”, in Proc. of the Int’l Electron Devices Meeting,pp. 735-8, San Fransisco, CA, USA, Dec.8-11, 1996
[15] Private communications, J.J. Wikner, Ericsson Components AB, 1999
[16] P. Dahlheim Lander, Design of an MSB Randomizer for Wide Band CMOS DAC,Final Work, Linköping University, Sweden, 1998, LiTH-ISY-EX-ET-0159
[17] S.M. Kang, and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design,McGraw-Hill, Singapore, 1996, ISBN 0-07-114423-4
[18] N.H.E. Weste, and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Per-spective, Addison-Wesley, USA, 1994, ISBN 0-201-53376-6
µ
Design of 12-bit 100-MHz Current-Steering DAC for SOC Applications
Chun-Yueh Huang Tsung-Tien Hou, and Chi-Chieh Chuang Department of Electronic Engineering
Kun Shan Universiv of Technology Yung-Kang, Tainan, 71 003 Taiwan, R.O.C.
Hung-Yu Wang Chip Implementation Center, National Applied Research
Laboratories, cyhun@,mail.ksut.edu.tw
Abstract
In this paper, we propose a 12-bit 100-MHz current-steering digital-to-analog converter (DAC) for system-on-a-chip (SOC) applications. We adapt the segmented architecture to design this DAC to obtain better perJ?ormances of LVL, Glitch energy, and monotonicity. The segmented architecture includes 7- MSBs which are decoded into 127 equally weighted current sources and 5-LSBs which are corresponding to binary-weighted current sources. Based on the TSMC 0.35um 2p4m CMOS technology, we use HSPICE to simulate the proposed DAC. The simulation results show that the proposed DAC has the following characteristics: INL < B.4LSB, DNL< f 0.25LSB, and settling time less than 9ns. The proposed converter’s spurious free dynamic ranges (SFDfi) for are larger than 80 dB and 65 dB at an update rate fc& lOOMHz and its output frequencies are I MHz and 49 MHz, respectively. The power consumption is 47 m W at the maximum conversion rate.
1. Introduction
In the applications of HDTV, video and modern communication systems, high-speed and high-accuracy digital-to-analog converters are indispensable components. In the past years, many researchers have devoted to developing the high-speed and high- accuracy DACs [ 1-91. While designing DACs for SOC applications, an important issue must be considered. We need to consider how to integrate analog circuits with memory and digital signal processing (DSP) circuits on the same chip, and use CMOS technology
This work was supported by the MOE Program for Promoting Academic Excellence of Universities, under Grant EX-93-E-FA09-5-4.
Taiwun, R. 0. C. ted@,tn.cic.edu.tw
117 0-7695-2403-6/05 $20.00 0 2005 IEEE
to fabricate the SOC. To design the high-speed and high-accuracy DACs to meet the requirement of SOC applications, a current-steering DAC architecture is particularly suitable for SOC applications, because it can be implemented by standard CMOS technology.
In this paper, we design a 12-bit 100-MHz current- steering DAC. In order to reduce glitch and to ensure monotonicity, the segmented architecture is used to design the DAC. The common-centroid layout approach is used to realize the layout of most significant bits’ (MSB) unary cells current source transistors to reduce the process graded error and symmetrical error.
2. Design of a current-steerign DAC
Figure 1 shows the block diagram of the proposed segmented DAC architecture. In this DAC, the segmented architecture consists of 7-MSBs and 5- LSBs, which are thermometer coded and binary weighted coded, respectively. The segmented current- steering topology is used to guarantee monotonicity for the MSBs and to improve the performance of DNL. The 7-MSB digits (bll * b5) are decoded by a thermometer decoder into 127 thermometer codes, and the 5-LSB binary digits (b4 - bO) are directly fed to the second D-latch array. Two D-latch array and clock driver are used to synchronize the DAC and to reduce glitch energy. In the current source array, there are 127 unary current cells and 5 binary weighted current cells. According to the digital inputs, the outputs of the second D-latch array from the 127 thermometer codes and 5 binary codes are used to determine the DAC output value by switching the currents of unary current source array and binary current source array into the output load (50 n), respectively.
For ease of understanding the design methodology, the basic components of the current-steering DAC are discussed in detail as follows.
0
CLK
D o 1
Figure 1. The block diagram of the proposed current- steering DAC
$j-M2 1
NOT3 NOT4
A. D-latch
The circuit diagram of D-latch is shown in Fig. 2. The D-Latch, which is the simplest digital storage element, is a samplehold circuit and can be used to keep the synchronization of control signals in the DAC. Basically, in the D-Latch, two cross-coupled inverters (NOTl and NOT2) are acted as a storage unit and two inverters (NOT3 and NOT4) as buffers. When CLK is high, transistors M 2 and M3 are turned on, and the input signal D through transistors M 2 and M3 are transmitted to latch output Q. The signal of Q is dependent on the value of input D. When CLK is low, transistors M 2 and M3 are turned off, and the Q of the D-latch will be dependent on the input value of D just before CLK is turned low.
Considering the circuit implementation, when CLK is high, the input signal through transistors M2 and M3 must dominate over the positive feedback through NOTl. In order to meet the above requirement, the widths of the transistors of NOTl must be designed as small as possible, i.e., at their minimum widths. With this condition, the input signal can correctly change the state of the D-latch.
B. Clock driver
In order to reduce the global clock timing skew, we need to develop a good clock distribution approach to align the switching signal with the D-latch array. In the DAC, the clock tree structure as shown in Fig.3 is used to improve buffering and equal clock delay to the D- latch array and to optimize the speed and clock edge
Figure 4. Iterative implementation of a thermometer decoder
C. Thermometer decoder
Basically, a binary code consisting of k bits is converted into a thermometer code of 2k-1 bits. Based on the iterative approach, a (k+l)-to- (2'+' -1) binary-to-thermometer decoder can be constructed by using a (&to- (2k -1) decoder as shown in Fig. 4, where there are (2' -1) AND gates and (2' -1) OR gates. In the proposed DAC, the input binary codes of 7-MSBs are converted into 127 bits thermometer codes. The total delay through the thermometer decoder is the propagation delay of six gates with inverter buffers at the output, The difference in the delay is small enough to guarantee over 100 MHz operation. All the decoded data are latched at the second D-latch array before driving the current switches.
118
...... . n . n n m n
D. Current cell
In the DAC, the current source cannot be completely turned off and therefore the switching signals have to be properly matched to improve the glitch performance. A proper switching scheme for the PMOS differential current switch is implemented by transistors M3 and M5 as shown in Fig.5. Two transistors M4 and M6 with self-bias are used to increase the output impedance of the current cell.
The output impedance of the current cell has a great influence on the specifications of INL (integral non- linearity) and SFDR [9,10]. The relationship between the impedance and the achievable INL specification is given by [ 101
T R AT2
where RL is the load resistor, runit is the LSB current, and N is the total number of unit current sources.
Considering the frequency dependency of the output impedance, the relation between the SFDR specification is given by [9]
NRL R,, =- 4s
where S is the ratio between the fundamental signal and the second harmonic component caused by the output impedance effect. According to Eq. (2), for a 12-bit current steering DAC, the ratio has to be at least equal to 72 dB. If the load resistor is a 50!2 double terminated cable and N is equal to 4095, the value for required output impedance Rout has to be at least lOOM !2 in the Nyquist frequency range. In order to make the output impedance of the current cell large enough, and to satisfy the specification of INL and SFDR, the cascade current source configuration and the cascade switching transistors as shown in Fig. 5 are used to design the current cell.
Figure 5 . The circuit diagram of a current cell
In Fig. 5 , the output impedance of the current cell Rout is approximately calculated as
Rout gm4gm3gm2ro4ro3ro2rol (3)
In the current cell, the device dimensions of the channel width W and the channel length L for M1-M2 and M3-M6 are 6.Y2.5 and 3/0.35 pm, respectively.
Next, when we implement the DAC layout, we have to think of some questions. For instance, the current cell will exist transistor matching errors, i.e., size errors, threshold voltage variations, supply and bias voltage variations, oxide thickness variations, output voltage variations, etc. In order to improve transistor matching errors, in the current source array, we use basic unit current sources from different positions to construct this array by means of common-centroid technique as shown in Fig. 6. This approach can reduce the problem of process graded and systematic errors, but it will increase the wire resistance and capacitance as well. The shaded area is the dummy cells for avoiding over etching of process.
Figure 6. The floor plan common-centroid technique of current source
E. Bias circuit
In Fig.5, the cascade current mirror in the current cell can be used to reduce short-channel effects and increase the output impedance, but it will limit the signal swings. In order to reduce this limitation, a wide-swing cascade current mirror bias scheme as shown in Fig. 7 is used to provide the accurate bias voltages for the current cells. In the bias circuit, the diode-connected transistors M1, M2, M3 and M8, M9, M10 provide a bias to transistor M4 and M12, respectively. The transistors M4 and M12 are used to increase the gate-source voltages of transistor M5 and M11 and control the drain-source voltages of transistor M5 and M11 in edge of saturation.
119
I ..
The above approach can reduce the variations in the drain-source voltage of M5 and M7 with changes in VDD, and hence can make the bias current rout more accurately equal to the reference current Im~. The reference current IREF depends on external resistor R and the device dimensions of the transistor M5. The value of IREF can be derived as follows
‘DLI = ‘REF + ‘GS5 (4)
where K = O.S,uu,C,W I L , V,, and VT are the transconductance parameter, the gate-to-source voltage, and the threshold voltage, respectively. Then, the gate- to-source voltage of V,,, can be rewritten as
Finally, we can use Eq. (4) and Eq. (6) to determine the reference current based on the resistor R and W/L of transistor M5.
M1
M 2
M3
Figure 7. The biasing scheme of the current cells
3. Simulation results
The layout of the proposed 12-bit lOOMHz current- steering DAC has been finished as shown in Fig. 8. This circuit is simulated by HSPICE based on TSMC standard 0.35um 2p4m CMOS process [ll]. The power supply is 3.3 Volts and the output load resistor is 50 SZ. The current of LSB is designed as 3 pA. The post layout simulation results show that the static performances of DAC in DNL and INL are less than
0.25 LSB and 0.4 LSB, respectively, as shown in Fig. 9 andFig. 10.
For the SFDR simulation, the converter is simulated at the condition of the update rate for a full-scale input signal with a fkequency of 1 MHz sine wave. Fig. 11 shows that the SFDR remains above 80 dB at the update rate of 100 MS/s. Furthermore, Fig. 12 shows that the SFDR is above 65dE3, for Nyquist fi-equency range simulation, in the condition of a full-scale input signal with a frequency of 49 MHz under the sampling rate of 100 MHz.
The settling time of the DAC is less than 911s. The power consumption is 47 mW at the maximum conversion rate. The summary of the performance of the proposed DAC is shown in Table 1.
Figure 8. The layout diagram of DAC
Figure 9. Post layout simulation for DNL of DAC
1 20
. . -, . , I I..
Table 1. Summary of the DAC performance
, . * .
4. Conclusion
. , " ~ . ~ . In this paper, a 12-bit 100-MHz current-mode digital-to-analog converter (DAC) for system-on-a- chip (SOC) applications is presented. The SFDR is larger than 65dB for a Nyquist fimdamental signal. Based on the TSMC 0.35um 2p4m CMOS technology, the proposed DAC is simulated by HSPICE. The post layout simulation results show that the proposed DAC has the following characteristics: INL,< kO.4LSB, DNL<3.25LSB, and settling time less than 9ns. The power consumption is 47mW at the maximum rate. The chip area is 6.9mm2. In the near hture, the chip will be fabricated. After finishing the chip fabrication and testing the chip's function, we will develop the corresponding Verilog-A model of DAC in SOC applications.
5. References
Figure 1 1. The SFDR for a 1 MHz signal at a 1 OOMHz update rate.
.. .. . . .. . . " . ... . .* . *
[l] J. Vandenbussche, G . Van der Plas, et al., "Systematic Design of High-Accuracy Current-Stecring D/A Converter Macrocells for integrated VLSI System", IEEE Trans. Circuit and Syst. II, vol. 48 NO. 3, March 2001.
[2] A. Torralba, R. G. Carvajal, J . Ramirez - Angulo and F. Munoz, "Output stage for low supply voltage, high- performance CMOS current mirrors," Electron. Lett. vol. 38 NO. 24 November 2002.
[31 A. Van den Bosch, M. Borremans et al., "A 12-bit 2OOMHz low glitch CMOS D/A converter," IEEE 1998 Custom Integrated Circuits Con$ (CICC), May 1998, pp. Figure 12. The SFDR for a 49MHz signal at a
IOOMHz update rate 249-252.
121
[4] B. J. Tesch and J. C. Garcia, “A Low Glitch 14-b lOOMHz DIA Converter,” IEEE J. Solid-state Circuit, Vol. 32, pp. 249-252.
[5 ] M. Gustavsson, J. J. Wilner and N. N. Tan, CMOS Data Converters For Communications. Boston, Kluwer Academic Publishers, 2000.
[6] C. H. Lin and K. Bult, “A lob 250Msmapleh CMOS DAC in lmm2,” in Proc. 1998 Int. Solid-state Circuit Con$ (ISSCC), pp. 214-215, Feb. 1998.
[7] C. H. Lin and K. Bult “A 10-b, 500-Msampleh CMOS DAC in 0.6 m 2 , ” IEEE J. Solid-state Circuits, Vol. 33, No. 12, Dec. 1998.
[8] A. Van den Bosch et al., “A 10-bit 1-Gsamplesls nyquist current-steering CMOS DIA converter,” IEEE J. Solid-state Circuits, ~01.36, pp. 3 15-324, Mar. 2001.
[9] A. Van den Bosch, M. Steyaert and W. Sansen “SFDR- bandwidth limitations for high speed high resolution current steering cmos d/a converter,” in Proc. IEEE Int. Con$ Electronics, Circuit and System (TCECS), Sept. 1999, pp. 1193-1196.
[lo] B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995. ISBN 0-7803-1093-4.
[l 11 R. Gregorian, An Introduction to Mixed- ,Signal IC Test and Measurement. New York, Oxford, 2001.
ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland
THE EXTRACTION OF TRANSISTOR MISMATCH
CONVERTER AS A TEST STRUCTURE PARAMETERS : THE CMOS CURRENT-STEERING D/A
A. Van den Bosch, M. Steyaert and W. Sansen
K.U. Leuven, Department of Electrical Engineering, ESAT-MICAS, Kard. Mercierlaan 94, B-3001 Heverlee, BELGlUM
e-mail : anne.vandenbosch @ esat.kuleuven .ac.be
ABSTRACT
Since transistor mismatch directly affects the performances of a broad class of analog CMOS devices such as comparators, A/D and D/A converters, it is of the utmost importance to determine these parameters for every available CMOS technology. Nowadays, this is done by processing and evaluating a large number of especially designed test structures that have no further use. This paper presents a technique to extract the transistor mismatch parameters from the performance of a simple current- steering CMOS D/A converter.
1. INTRODUCTION
Due to the “explosion” of the wireless telecommunication market a lot of effort is recently put in the integration of digital and analog blocks on one chip. However, the success of a mixed analog-digital system depends on the correct operation of every system component. The analog circuits have to be fully compatible with the digital technology with its trend towards higher operation frequency and higher accuracy. The matching parameters impose a limit on the highest attainable accuracy performance of an analog circuit in a given technology. During the fabrication process small variations will occur that result in a statistical variation of the transistor properties. This variation depends on the dimensions of the matched component and its biasing conditions. When only a limited amount of information is available, the analog designer has to introduce large safety margins to guarantee the required performance of the circuit leading however to an unnecessary power consumption and an operation speed reduction [ 11.
For the VLSI manufacturer, it is very important to be able to provide his customers with the necessary quantitative data of the matching quality of his technology. This can only be achieved by the use of dedicated test circuits that are especially designed for this purpose (low parasitics,
high measurement accuracy, . . .). Furthermore, i t is necessary to follow the evolution of the matching performance of the technology over different runs in time. This requires a test circuit that gives a good indication of the matching technology for a low cost. However, these circuits are of no further use to the manufacturer or the designer and therefor an alternative structure has been sought for. A high performant current-steering D/A converter is highly dependent on the matching quality of the technology. Furthermore, the evaluation of the D/A converter’s performance poses no problem since there exist standardized test procedures. In this paper, the D/A converter’s performance will be directly translated in the matching characteristics of the technology.
The paper is organized as follows. In the section 2 the test structures as they exist now will be shortly discussed. In the next section the D/A converter approach will be ‘ presented. In this section the architectural choice and the design of the D/A converter is discussed as well as the transistor mismatch extraction procedure. In section 4 some measurement results will be shown and evaluated. Finally, a conclusion will be formulated.
drdn m draln 1 dmlnZ
’- 4 4
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Fig.1 : example of the test structure approach [2]
2. TEST STRUCTURE APPROACH
Until now the test circuits are constructed using an array of about fifty to one hundred transistors with some additional
0-7803-5482-6/99/$10.00 02000 EEE
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digitallselection logic to be able to automate the measurements to a large extent [2,3]. The dimensions of
VTniUraM A*c-725>mv”m
l/sqrt(area) (l/um)
Fig.2 : the quadratic standard deviation of the threshold voltage in function of the inverse of the square root of the area of the measured transistors
the transistors are chosen in such a way that the
the transistors span a wide interval. By measuring a large number of chips, an accurate determination of the mismatch parameter coefficients A, and AVT of the Pelgrom equation[4] is possible. The test chip normally exhibits a large geometrical symmetry and consists of an array of identical cells. Furthermore, the chip area has to be kept as small as possible to reduce the cost.
In this paragraph the transistor mismatch parameters of the CMOS 0.5 Fm technology are extracted. The schematic of the used test structure is given in fig.1. The test chip contains 10 rows of 12 nM0S transistors with different sizes : W L - 0.810.5, 111.4, %, 1013.2, 20120, 3.2110, 2.810.5, 110.7, 0.8120, 2010.5 pmlpm. Fifty test chips were measured giving the results depicted in f ig2 and fig.3. In these figures, the ‘+’ indicate the results for the standard deviations extracted from the measurements and the ‘*’ give the mean value of the mismatch parameter coefficients.
Fig.3 : the quadratic standard deviation of the current factor in function of the inverse of the square root of the area of the measured transistors
The extracted values of the threshold voltage and current factor mismatch parameter coefficients are :
AvT = 1.3mVpm Ap =1.3%pm
As is mentioned earlier, these test chips have no other function than the mismatch determination of the technology and as such are a cost overhead to the manufacturer. Therefor, both designers as manufacturers are looking for alternative structures to determine the transistor mismatch parameters.
3. D/A CONVERTER APPROACH
3.1 ’ Choice of the D/A converter architecture
A current-steering DIA converter is based on an array of identical current cells. The achievable resolution ultimately relies on the matching properties of these cells which are determined by the used process and can only be improved by increasing the current source transistor sizes orland adjusting the bias voltages. The close relationship between the DIA converter’s performance and the transistor mismatch parameters makes this circuit the ideal process monitor.
An unary architecture is chosen because in this implementation every current source can be accessed separately while in a binary implementation the current sources are grouped bit by bit. Furthermore, this architecture has the extra advantage that it has good dynamic specifications.
The resolution of the D/A converter is chosen to be seven or eight bits so that enough measurements are available to be able to work with gaussian distributions when processing the data. Furthermore, such a DIA converter can also be used in applications in the area of e.g. video, HDTV and so on. This leads us to the major advantage of using a current-steering DIA converter as a test structure. This chip has further use, no silicon area has gone to waste. Furthermore, the chip area can be made in the order of a few mm2 which is considerably smaller than any test chip reported in literature. This enables the manufacturer to place it on every wafer having in this way a continuous monitoring of his technology.
3.2 Design issues for the D/A converter
In this paragraph, the design plan for a current-steering DIA converter will be shortly discussed. The circuit
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schematic for one unit current cell is depicted in fig.4. The design parameters of the D/A converter will be calculated for a yield estimation of 99.7 % and an output voltage swing of 1 Volt peak to peak into a 50 R load. This leads to a full scale drain-source current specification of 20 mb. (=IFS).
Fig.4 : the unit current cell and the biasing circuit
The dimensions of the current source transistors are determined by the following formulas :
(3)
Since the transistor matching parameters seem to improve for smaller gate-length technologies, the parameters of the 0.7 pm technology can be used in a first approximation for the design of a 0.5 pm D/A converter. Apart from the mismatch parameters, the gate overdrive voltage of the current source transistors has to be determined. An appropriate value can be found by making a trade-off between the settling time of the D/A converter and the chip area [5]. The optimal value for the gate-source voltage of the current source is then given by a value of approximately 1.6V. If the operation frequency of the D/A converter is of minor importance, the value of the overdrive voltage can be increased leading to the use of a smaller silicon area.
The values for the dimensions of the current sources (implemented in the 0.5 pm technology) for both the optimal gate overdrive voltage and for a larger value can be found in table 1.
3.3 Measurement and extraction procedure of the transistor mismatch parameters
The measurements of the D/A converter can be fully automated. A program has been written that drives the data
generator (HP80000) so that for different values for the (VGs-VT)cs the current at the output of the D/A converter will be measured (HP3457 multimeter) and
Table 1 : the current source dimensions for different values of the gate overdrive voltage for a DIA converter processed in the 0.5 km technology with 1, = 20 mA
stored. At this point, for every gate overdrive voltage of the current source transistors 2N-1 measured currents are available leading to 2N-2 transistor pairs (I,,I,+,) with i=l to 2N-1. Using MATLAB the values for the relative current difference (AH) and the relative current standard deviation o(AI/I) can be easily calculated. This gives us a curve as is depicted in fig.5.
I line fined through the measurement points /
l/(vGs-<T)z
Fig.5 : the quadratic relative standard deviation in function of the inverse quadratic gate overdrive voltage of the current source transistors
From the IDs-V~s characteristic, the formula for the relative current standard deviation is easily derived :
(4)
For large values of the gate overdrive voltage this formula simplifies to :
Using Pelgrom's equation a value for the current factor mismatch coefficient can then be calculated :
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On the other hand, for small values of ( V G S - V ~ ) ~ ~ the influence of the current factor is negligible and the relative unit current standard deviation is given by :
Since the characteristic of fig.3 is a straight line, a fitting of d(AI/I) calculated from the measurement data gives us the threshold voltage mismatch coefficient.
The distance term in Pelgrom’s equation can be neglected because the current sources are switched following an S pattern. The current source that in the layout is placed beside to the previous measured current source is measured next. Furthermore, to avoid the influence of edge effects dummy rows and columns are used in current-steering D/A converters. This guarantees the fact that all measured transistor pairs have identical surroundings.
3.4 Measurement Results
As an example a six bit current-steering D/A converter has been measured. The chip has been processed in a CMOS 0.5 pm technology. The results of the extraction procedure described in the previous paragraph are given in fig.6.
Fig.6 : the measured quadratic relative current standard deviation in function of the inverse of the quadratic gate overdrive voltage of the current sources
From this figure the following values for the mismatch parameter coefficients can be obtained using equations 6 and 8 :
These results are in good agreement with the results obtained from the test structures described in paragraph 2. This proves that the D/A converter can indeed be successfully used as a process monitor for mismatch.
4. CONCLUSION
In this paper the CMOS current-steering D/A converter has been presented as a test structure for matching purposes. Using a D/A converter as a test structure has a large cost advantage since no especially designed test structures will be necessary anymore. The time to implement the.se circuits and the silicon area they consume can now be used to design a chip (=DAC) that can be further used in e.g. telecommunication applications.
The extraction procedure of the transistor mismatch parameters has been described and is verified by comparing the measurement results of a six bit current- steering D/A converter and the results obtained from the classical test structures.
5. ACKNOWLEDGEMENT
The authors wish to thank Alcatel Microelectronics for their support.
6. REFERENCES [ I ] P. Kinget and M. Steyaert, “Impact of Transistor Mismatch
on the Speed-Accuracy-Power Trade-off of Analog CMOS Circuits”, Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), May 1996
[2] J. Bastos and al., “Mismatch Characterization of Small Size MOS Transistors”, Proceedings ofthe IEEE 1995 Int. Conf: , Microelectronic Test Structures, vol. 8, March 1995, pp.
[3] T. Serrano Gotarredona and B. Linares Barranco, “Cheap and Easy Systematic CMOS Transistor Mismatch Characterization”, Proceedings of the IEEE International Symposium on Circuits and System (ISCAS), California, June 1998
[4] M. Pelgrom, A. Duinmaijer and A. Welbers, “Matching Properties of MOS Transistors”, IEEE Journal of Solid State Circuiri, vol. SC-24, Oct. 1989, pp. 1433-1439
[5] A. Van den Bosch and al., “Modeling and Realization of High Accuracy, High Speed Current-Steering CMOS DIA Converters”, Accepted for publication in the Elsevier Measurement Journal
27 1-276
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Folded-Current-Steering DAC: An Approach to Low-Voltage High-Speed High-Resolution D/A Converters
Soheil Radiom Behzad Sheikholeslami Hamed Aminzadeh Reza LotfiIntegrated Systems Lab., IC-Design Lab., Integrated Systems Lab., Integrated Systems Lab.,
EE Dept. ECE Dept. EE Dept. EE Dept.Ferdowsi University University of Tehran Ferdowsi University Ferdowsi UniversityMashhad, I.R.Iran Tehran, I.R.Iran Mashhad, I.R.Iran Mashhad, I.R.Iran
soheil_radiom @ieee.org
Abstract- In this paper, a new topology for CMOS current In section II, the current-steering D/A converters, theirsteering DAC, i.e. folded current-steering structure, suitable basics and their conventional structure are described. Sectionfor low-voltage applications is presented. Using the folded III introduces the proposed folded structure. In section IVstructure, more voltage headroom will be available for the simulation results confirming the effectiveness of thecurrent-source devices increasing the output impedance of the proposed approach are presented following by conclusions incurrent sources. The DAC linearity is thus improved. Also this section V.novel topology improves the value of PSRR and output voltageswing without SFDR degradation and results in more constantload for current cell. Also a current-steering logic decoder with I VARIOUS CURRENT-STEERING TOPOLOGIESdifferential outputs is suggested. Besides, gain boosting is Current-steering DACs are based on an array of theapplied to increase the output impedance of current source. matched current sources that are switched to the output nodeThese techniques are used to design a 12-bit 200MS/s DAC based on the input digital code. Three different ways ofwith 1.5-V power supply and more than 72dB SFDR is implementation are available, namely binary, unary andachieved in all frequencies. Also Monte-Carlo simulations show segmented architecture. Each of the architectures will bethat the probability of an SFDR of more than 65dB is more briefly discussed.than 90% for an input frequency of 100MHz.
A. The Binary Weighted ArchitectureI. INTRODUCTION In the binary implementation, the binary digital inputThe recent growth in the market demand for VLSI codes directly control N binary-weighted current sources, i.e.
circuits and also the advance in implementing digital each switch conveys a current to the output node that is twiceintegrated circuits have made the interface between the larger than the current of the previous least significant bit.analog and digital parts of a system as one of the most This architecture suffers from the poor matchingchallenging blocks of the system to design. Applications in performance ofnon-equal current sources. Large glitches arethe area of video and wireless communications need DACs also expected in this structure.with high performance. For these applications, amongdifferent architectures, the current-steering configuration is B. The Unary Architecture ( Thermometer coded)frequently chosen due to its superior performance from the In the unary architecture, the current sources are switchedspeed, resolution and power consumption points of view. On to the output node based on the thermometer version of thethe other hand, designing high-speed high-resolution data input binary code. 2N -1 unit current sources, equal to ILSBconverters is more challenging with lower supply voltages, are switched. The matching performance is much better thanAlthough at low frequencies the output impedance and the binary architecture and the glitches are smaller and codemismatch between current sources have the main influence dependent; however the decoder complexity is added to theon linearity [1], in high-speed, high- resolution DACs, the circuit.most important parameter for evaluating the performance isSpurious Free Dynamic Range (SFDR) which is mostly C. Segmented Architecturelimited by finite output impedance, charge feedthrough,e thmajor carry glitches and spikes in common switch nodes and In order to employ the advantages of both architecturespower supply noise. the segmented topology is proposed, i.e. the binary
architecture is employed for less significant bits whereas the
unary structure for more significant bits. The degree of E. Conventional Structuresegmentation in a current-steering DAC has major influence In Fig.2 the conventional structure of a cell is shown.on both the structure ofthe converter and on its performance. Although one can use single-ended output for current-Segmentation rather than binary-weighted architecture is steering DACs, the use of differential output signal is moreoften used for improving DNL, glitch and SFDR favorable. Not only the common mode noise is attenuated,performance [2] at the expense ofexponential increase in the but also the output impedance requirement for each currentarea and much more complexity because ofthe thermometer cell is significantly reduced. To have high output impedancedecoder. A brief overview of advantages and disadvantages in the current sources for better performance, it's common toof each architecture is given in Tablel. use transistors with channel lengths much longer than the
minimum available length in the process. This results in aTable 1: Advantages and disadvantages of various architectures small W/L which in turn yields relatively large VGS. The
I D consequence ofthis choice is that, in order to bias the currentArchitecture N N Glitch Power Area Complexity source transistors in the saturation region which is required
L L to get high output impedance, the VDS of those transistorsBinary = |++ ++ ++ must be relatively large which limits the output swing. While
- u ± _ - + higher output impedance limits the swing, it has a majorUnary _ + ++ effect both on SFDR and on the linear behavior of the DAC
Segmented = + [4]. On the other hand, higher output impedance decreasesthe effect of input signal glitching on the performance ofthecurrent source. In this structure larger swing cause the
This also increases the power consumption and the voltage drops on switches and current sources becomerequired design time. Of course one should consider that smaller, so the operation region ofthem gets closer to linear,increasing the digital part will increase the digital noise and thus the performance degrades effectively. Also the outputalso time skews get bigger that mostly degrade the dynamic swing directly affects the load of the current source whichperformance. It is obvious that a good segmentation choice is causes degradation in its ideal performance.very important and of course application dependent. Yet the In order to overcome these issues, effective solutions arechoice is often based on experience rather than on founded ptdecisions [3]. We have chosen 6 bits for segmentation forour designed DAC.
D. DAC Building Blocks VDDFig. 1. shows the block diagram of the segmented D/A
converter. It consists of 6 bits in the binary and 6 bits in theunary sub-DACs. The thermometer decoder turns the binarycode into the thermometer code. The dummy decoder * * *compensates the delay of the thermometer decoder. Currentsources are implemented in this way for matching reasons.
B6 B7 l i
Thermometer Decoder
CLK Switch Matrix I H Latch
_ £ £||.
_~ *,(D___ III. PROPOSEDARCHITECTURE
f~~~~iIIllllllFig.3 shows the proposed architecture for current-ca ~~~~~~~~~~~~steeringDAC that considerably reduce the challenges
mentioned in previous section about conventional design.Figl. Block diagram of a segmented architecture Here transistors MFOLD provides a constant current. Thus the
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current ofthe load resistors is again proportional to the input Vdddigital code. However, there are several advantages.
As the drain-source voltage of the fold transistors can beadjusted, the headroom voltage on the switches and currentsources is increased, i.e. larger VDS for CS, CAS and switchtransistors are provided, so higher SFDR and more linearityas a result of increase in current source output impedance isobtained. Also, this increase in their VDS leads to better Gate of McaPSRR. On the other hand, increasing the output impedance Source of Mcaswill improve the performance of the current sources as welland make their behavior more robust against the data-dependent transitions caused by input signal variations onnode V, [5]. Moreover what transistor Mk does is to shield 'rthe critical node (Y) from loading effect of Rload and theeffect of the output voltage swing on the performance ofcurrent sources and thus to provide a more constant load for Fig.4. The applied gain booster for increasing output impedancecurrent cell. Also it reduces the effect ofinput code spikes onthe output nodes. VDD
Here the effect of charge feedthrough which seriouslydegrades the performance of conventional DACs [6] isconsiderably decreased in the output node as there is no CLK CLKdirect path to the output. So there is no need for the cascode VIP T_'_L__transistor above switches that was offered in [4] which limitsthe swing. Also here one can get more swing without SFDRdegradation as a consequence of any limitation on VDS ofcurrent cell transistors.
The CMFB used in the folded branch is for compensatingthe variations in various temperatures.
Another technique applied to the circuit is gain boostingwhich effectively increases the output impedance and leads Fig.5. Latch circuitto more SFDR and better linear behavior. For obtaining moregain the boosting amplifier of Fig. 4 is used in the circuit. Another proposed technique employed in the circuit is
using current-steering logic with differential outputs forbinary to thermometer decoder that significantly reduces theeffect of the decoder output voltage spikes in the circuit.
VDDFaster transitions push the spurious outputs to out-of-
band frequencies. Besides, fast switching can decrease thetransition energy. The charge injected by the capacitive
FVCMFB + coupling ofthe digital signals to the output is independent of1.I /1 I_ MFOLD the switching speed, but the time ofunbalanced switching is
reduced [3] and this is the reason of choosing NMOS0 * 0 0 yswitches here. Considering the fact that in the offered
-./-11-/ 1MK structure the direct path between input signal and output isF,,> r rl removed, the effect of glitch energy in the output node
IV\x I @ _ substantially decreases.
Lgdump out The circuit depicted in Fig.5 has been employed for theCAS 41-0 T tlatch circuit, previously proposed in [7].
IV. SIMULATION RESULTS, = The proposed DAC has been simulated using HSPICEusing BSIM3v3.1 model parameters of a 0.18-pim CMOS
Fig.3. Folded current steering cell process. DAC SFDR is depicted vs. output signal frequencyin Fig.6. The minimum value ofthe SFDR obtained for inputsignals with frequencies up to 100MHz is 72dB. The output
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swing is 1.2 Vp-p,djf with a 25-Q load and a power-supply V. CONCLUSIONvoltage of 1.5V. At 200 MSample/s the analog and digital In this paper, a new topology for current steering DACsparts consume 85mW. Monte-Carlo simulations considering was presented. This topology results in larger VDS onthe mismatches of the current sources show that the current-source transistors which causes higher outputprobability of an SFDR of more than 65dB for a Nyquist-frqecipti mor tha 900 impedance and as a consequence better performance andfrequenc input is more than90PSRR. Also this method provides constant load for current
cells and improves output voltage swing without SFDR
Resolution 12 degradation. Also the proposed techniques for the binary tothermometer decoder, using current steering logic with
Decoding Segmented (6+6) differential outputs, as well as gain-boosted current sources
Nyquist update frequency 200MS/s improve the circuit behavior considerably. Simulation resultsDifferential output signal 1.2Vpp of a 12-bit 200MHz DAC confirm the effectiveness of theSupply voltage 1.5V proposed techniques.Iload 25mA
SFDR up to Nyquist freq. > 72 dB
INL 1LSB ACKNOWLEDGMENT
DNL 0.7 LSB The authors would like to express their appreciation for
Total power consumption @ 85 mW Dr. Robert Neff and Dr.Ola Anderson for providing ongoingNyquist rate guidance.Technology 0.18prm CMOS
77 REFERENCES
[1] K.Doris, J.Briaire, D. leenaerts, M.Vertregt, A.van Roermund "A 12b76 - 500MS/s DAC WITH >70dB SFDR up to 120 MHz in 0.18um
CMOS," IEEE International Solid-State Circuit Conference 2005.75 - \ [2] Chi-Hung Lin and Klaas Bult " A 10-b 500-MSample/s CMOS DAC
in 0.6mm2," IEEE JOURNAL OF SOLID-STATE74 - \ CIRCUITS,VOL.33, NO 12 ,DECEMBER 1998.
[3] Jurgen Deveugele, Michiel Steyaert " A 10b 250 MS/s Binary-Weighted Current-Steering DAC," IEEE International Solid-State
a_ \; / , _+,Circuit Conference 2004.
72 - [4] A.Van den Bosch, M.Steyaert and W.Sansen "SFDR-BandwidthLimitation for high speed high resolution Current Steering CMOS
71 - D/A Converter,"[5] W.Schofield "A 16b 400MS/s DAC with <-8OdBc IMD to 300MHz
70 - and <-160dBm/Hz Noise Spectral Density," ISSCC Dig.Tech.papers,Feb.2003.
69 I_ I_ I_ I_ I_ I_I [6] Van Beek, K.Doris, J.A.Hegt and Van Roermund "Optimum3/64 7/64 11/64 15/64 19/64 25/64 29/64 31/64 Segmentation for high speed current steering Digital-to-Analog
Converters,"f/fs
[7] A.Van den Bosch, F.Borremans, Michel Steyaert , Willy Sensen " A10-bit 1-GSample/s Nyquist Current-Steering CMOS D/AConverter," IEEE JOURNAL OF SOLID-STATE
Fig.6 SFDR VS signal frequency. The sample rate is 200MS/s CIRCUITS,VOL36,No.3, MARCH 2001.
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Linköping Studies in Science and TechnologyThesis No. 715
Department of Electrical EngineeringLinköpings universitetS-581 83 Linköping
Sweden
ISBN 91-7219-277-1 ISSN 0280-7971Printed in Sweden by UniTryck, Linköping, 1998
thealogrs is
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Abstract
In telecommunication systems, most of the information processing is performed indigital domain, but the signal carrying the information must be transmitted using ansignals. Therefore, the use of digital-to-analog and analog-to-digital converteunavoidable.
The general basics of digital-to-analog converters are described in this thesis. A conation of behavioral-level, circuit-level, and layout-level descriptions, as well as demethodologies are presented. A thorough description of the design of a CMOS Nyqrate digital-to-analog converter chipset for wideband radio and VDSL applications,of a CMOS oversampling digital-to-analog converter for ADSL applications is givMeasurement results are presented as well as suggestions on how to improve pmance.
In these kinds of applications, it is the dynamic performance of the converters that dmines the quality of the device. Commonly, the characterization of the converters isin the frequency domain. We have focused on how static and dynamic propertieaffecting the output spectrum. In the thesis we present important work on how teffects are modeled and how they apply to a CMOS current-steering digital-to-anconverter structure as used in the Nyquist-rate chipset. It is shown how the output imance, matching, and noise are affecting the performance when changing fundamcomponent values of the circuit. This work has resulted in four publications, andresults can be used as a guide when designing high-resolution converters.
Since large mixed analog/digital circuits contain both complex analog and digital pit is important to be able to simulate and vary parameters on a higher behavioral-This makes it possible to use faster simulation tools to find structures near the optimWith time-consuming circuit-level simulations these structures are only verified. Tallows a faster design flow. Especially during the design of the oversampling convthis design strategy has been used and MatLab models have been developed.
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nd
Part A:Acknowledgment
I would like to thank my supervisor, Ph. D. Nianxiong Tan, for all the great help aencouragement he has given me. As he said, “... before you know how to drive a cafirst have to crash it some times ...”
The help with discussions and to make the working day more interesting, the wgroup, Electronics Systems at Linköping University, with our supervisor Prof. PhLars Wanhammar, is acknowledged. I would especially like to thank Mikael Gustavfor valuable discussions and great help. All the help from former Ph. D. studenElectronics Systems (former Applied Electronics) is acknowledged.
Very much thank you, the Ericsson people; Gunnar Björklund and Jan-Erik Ek(MERC, Ericsson Components AB), and Bengt E. Jonsson (Ericsson Radio AB). Thfor the great help with Cadence; Helge Stenström (Ericsson Radio AB), and for the ginto the mysterious world of measurements; Peter Pettersson (Ericsson Radio AB)
The work is financially supported by the Swedish National Board for Industrial aTechnical Development (NUTEK) and the Strategic Research Fund (SSF).
1.1.1 The DAC 51.1.2 The Telecommunication Situation 61.1.3 Higher-Level Design 8
1.2 Signals and Coding Schemes ................................................................... 91.2.1 Signal Definitions 91.2.2 Digital Numbers and Representation 10
1.4 The CMOS Transistor ............................................................................ 141.4.1 Operation Regions and Small Signal Characteristics 15
3.2 Influence of Output Impedance Variations ............................................ 45
3.3 Influence of Current Source Mismatch .................................................. 483.3.1 Deterministic Variations of the Mismatch 493.3.2 Stochastic Variations of the Mismatch 51
3.4 Influence of Circuit Noise ...................................................................... 54
3.5 Influence of Timing Uncertainties ......................................................... 57
4.1 Practical Design Considerations ............................................................ 594.1.1 Unit Current Sources 604.1.2 Current Switches 634.1.3 Segmentation of the MSBs 664.1.4 Digital Circuits 67
5.1 Digital Correction .................................................................................. 755.1.1 Intentional Pre-Distortion 755.1.2 Calibration and Trimming Techniques 77
5.2 Dithering ................................................................................................ 785.2.1 Randomization of Segmented Current Sources 78
Part C:Oversampling Digital-to-AnalogConverters for ADSL Applications
This thesis is divided into five parts and is outlined in Sec. 1.1. Except this introducand the conclusions’ part, the thesis consists of three major parts as described bel
1.1 Outline of the Thesis
The three major parts of the thesis describe the different stages of the research coing digital-to-analog converters (DACs) for telecommunication applications.
The first part,Part A: Overview: Digital-to-Analog Converter Design, introduces thereader to the background and problems concerning the DAC. We also give a brief detion of different signals, telecommunication standards, digital codes, and CMOS trators. The DAC as a black box is discussed and the ideal DAC with its propertiesbehavioral-level is presented. In this part the important static and dynamic performmeasures are discussed as well as frequency domain measures. This thesis part fuas a background and overall description of the DAC and is only elementary introdufor the reader that is already familiar with the concepts of digital-to-analog convers
1
CMOS Digital-to-Analog Converters for Telecommunication Applications
ide-pe ofow-
., cal-and
DACin co-for-
workpre-ance
-ighs thatdig-
pli-g Gaorning
nted.rds,
In Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applicationsthe wide-band DAC is presented. For very high data rate digital subscriber line (VDSL) and wband radio, wideband converters are needed. The “simplest” way to construct this tyDAC is to use a binary weighted source structure – a structure without feedback. Hever, to meet high performance specifications, certain improvement techniques, e.gibration, digital correction, etc., may be needed. This implies a certain redundancyfeedback. These issues are discussed in this part. The design of a 1.5V - 5V CMOSchipset for VDSL and wideband radio applications is presented. It has been doneoperation with Nianxiong Tan (GlobeSpan Semiconductor, Red Bank, NJ, USA,merly Ericsson Components, Kista, Sweden). Important contributions concerningon modeling and simulation on behavioral-level of the binary converter structure aresented. The results may be used to understand fundamental limitations of the performand to give a design guide in general.
Presented inPart C: Oversampling Digital-to-Analog Converters for ADSL Applications is the oversampling technique which offers possibilities to reach a very hdynamic performance. However, this technique also introduces some other problemhave to be analyzed. In this part, the design of a 3V - 5V CMOS 14-bit oversamplingital-to-analog converter (OSDAC) for asymmetric digital subscriber line (ADSL) apcations is presented. The design has been done in co-operation with Yonghon(ESDLab, KTH, Stockholm, Sweden) and N. Tan. There are important issues concesimulation on behavioral-level of the whole converter presented in this part.
The thesis is concluded in the Conclusions part.
1.2 Papers and Conference Contributions
In this section papers and publications with Wikner as author/co-author are preseFor overall background description of design, simulation, telecommunication standaetc., we use papers as
• N. Tan, J. Erlands, and J. J. Wikner, “Fully Differential Line Driver,” PendingSwedish Patent, [67].
• N. Tan and J. J. Wikner, “A CMOS Digital-to-Analog Converter Chipset forTelecommunications,” IEEE Magazine on Circuits and Devices, vol. 13, no. 5,pp. 11-16, Sept. 1997, [68].
• H. Träff and J. J. Wikner, “Snapshot Sampling for ultra-high speed dataacquisition,” Electronics Letters, vol. 33, no. 13, pp. 1137-9, June 1997, [72].
• J. J. Wikner and N. Tan, “Influences of Circuit Imperfections on the DynamicPerformance of DACs,” in Proc. of the 15th Norchip Sem., pp. 336-43, Tallin,Estonia, Nov 10-11, 1997, [75].
• J. J. Wikner and N. Tan, “Influences of Circuit Imperfections on thePerformance of DACs,” Analog Integrated Circuits and Signal Processing, tobe published, 1998, [76].
• J. J. Wikner and N. Tan, “Modelling of CMOS digital-to-analog convertersfor telecommunication,” in Proc. of the 1998 IEEE Int’l Symp. on Circuits andSystems, Monterey, CA, USA, May 31 - June 3, 1998, [77].
• J. J. Wikner and N. Tan, “Modelling of DACs for telecommunication,”Internal Report, Linköping University, Sweden, 1997, [78].
2
Introduction
1.3 Nomenclature, Acronyms, and Abbreviations
Notation Description
Fourier transform
Laplace transform
Set of real numbers
Step function,
Set of integer numbers
Transconductance parameter,
Oxide capacitance per gate area
Nyquist frequency,
Oversampling frequency,
Sampling or update frequency
Small-signal transconductance
Small-signal output conductance,
Boltzmann’s constant, pJ/K
Transconductance parameter,
Charge mobility
Fundamental electron charge, aC
Output resistance of the transistor,
Oxide thickness
ADC Analog-to-digital converter
ADSL Asymmetric digital subscriber line
BP Bandpass (filter)
CDMA Carrier division multiple access
CFT Clock feedthrough
DAC Digital-to-analog converter
DMT Discrete multi-tone
DNL Differential non-linearity
DSP Digital signal processor
DWMT Discrete wavelet multi-tone
FIR Finite-length impulse response
FFT§ Fast Fourier transform
Harmonic distortion given by the -th tone
F
L
R
u t( ) u t( ) 1 t 0≥0 t 0<
=
Z
β β K' W L⁄( )⋅=
Cox
f N f N f s 2⁄=
f OSR f OSR OSR f s⋅=
f s
gm
gds gds 1 r ds⁄=
k k 1.321=
K' K' µ0Cox=
µ0
q q 0.1602=
r ds r ds 1 gds⁄=
tox
HDk k
3
CMOS Digital-to-Analog Converters for Telecommunication Applications
Table 1-1: Constants, values and variables used in the thesis.
HDSL High data rate digital subscriber line
HDTV High definition television
HP Highpass (filter)
IIR Infinite-length impulse response
IFFT Inverse fast Fourier transformation
IMD Intermodulation distortion
INL Integral non-linearity
LP Lowpass (filter)
LSB Least significant bit
MSB Most significant bit
NTF Noise transfer Function
OFDM Orthogonal frequency division multiplexing
OSR Oversampling ratio
PAM Pulse amplitude modulation
PCM Pulse code modulation
PSD Power spectral density
THD Total harmonic distortion
SC Switched capacitor
SI Switched current
SFDR Spurious-free dynamic range
SNDR Signal-to-noise-and-distortion ratio
SNR Signal-to-noise ratio
STF Signal transfer function
VDSL Very high data rate digital subscriber line
Notation Description
4
mate-ven,igitald. Inusings andvery
d cir-
cation
ig-er ofeact
A Part A:Overview:Digital-to-AnalogConverter Design
1 Introduction
In this introductory part we describe and motivate the research background to therial presented in the thesis. An overall view of the telecommunication situation is giand especially the roles that the digital-to-analog converter (DAC) and analog-to-dconverter (ADC) play in the front-end and back-end of a transceiver are discussesome way, the digitally processed information has to be transmitted over a channelonly analog signals and a certain transmission technique. Therefore, the use of ADCDACs is unavoidable in telecommunication applications, and the converters maywell be the bottleneck of the whole system.
The research background, digital codes, xDSL standards, the CMOS transistor, ancuit noise are discussed in this chapter.
1.1 Research Background
We present a short background to the research focused on DACs for telecommuniapplications.
1.1.1 The DAC
At the behavioral-level the function of the DAC is a mapping function from a digital snal to an analog signal. The converter may be described by a black box with a numbinputs and outputs, Fig. 1-1, and a transfer function describing how the output will ron the input (1-1).
5
Part A: Overview: Digital-to-Analog Converter Design
, the
ude
t bit
-
sed
utputspecialerterd in
per-d andrtersults.
edun-. Cal-allerrob-smis-ationslowert. Then is
t bese the
nd ar, andand asig-
italided
nvert-
For a single ended output Nyquist-rate converter with an input word length of bitsamplitude level at the output for an offset binary code would be
(1-1)
where is the reference level for the least significant bit (LSB), , i.e., the amplit
value at the output when only the LSB is active, and is the most significan
(MSB) in the digital input word . Naturally, there are sev
eral ways to implement a converter of this kind [23, 37, 56, 58]. This is further discusin Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications.
Figure 1-1: The digital-to-analog converter as a black box.
The converter may also be constructed as a finite-state machine where the odepends on previous states of the converter. This is used in feedback strategies orassigned converters as for example an oversampling digital-to-analog conv(OSDAC) that uses pulse coded modulation (PCM) [11, 56]. It is further describePart C: Oversampling Digital-to-Analog Converters for ADSL Applications.
Future research will focus on how the signal information can be used to improve theformance of the converter. With feedback strategies the output of the circuit is sensewith that information we vary parameters controlling the transfer function of the conveand the performance may be improved. A use of redundancy can also improve the reBy extending the digital code into more bits and use a higher resolution we can use rdant parts of the converter to correct errors (non-linearities) that are generated [56]ibration techniques have been implemented in audio DACs which have a smbandwidth [11]. For wideband DACs where the bandwidth is large there might be plems with using feedback since it limits the bandwidth and reduces speed. Some transion schemes use time-slots during which no information is sent. For some calibrtechniques it may be possible to use samples of the generated output signal at arate than the transmission rate, i.e., using the time-slots where no information is senproblem still, is that the output of a DAC is analog and that the correction most oftedone digitally. In an implementation, extra analog-to-digital conversion that mighneeded for a specific correction technique should be avoided, since this may increacomplexity dramatically.
1.1.2 The Telecommunication Situation
A classical telecommunication system is divided into a transmitter, a channel, areceiver [26]. As shown in Fig. 1-2, the transmitter consists of a source, an encodea modulator. Correspondingly, the receiver consists of a demodulator, a decoder,sink. This thesis focuses on the modulator and especially the final circuits putting thenal on the channel; the digital-to-analog converters.
From a circuit designer’s perspective, we can divide the different blocks into digparts, mixed analog/digital, and pure analog parts. The digital part can further be divinto hardware and software components. For the mixed analog/digital part stands co
ers, filters, and amplifiers, which have to interact with each other. In the transmitterdigital code vectors are transformed into a proper analog representation and thenthe channel, which finally is reversely transformed by the receiver.
Figure 1-2: Classical view of communication system. The system can be divided into digital partsmixed analog/digital parts, and analog parts.
Mixed analog/digital circuits also introduce some additional problems [33], e.g., inference from the digital circuits on the analog circuits, noise from supply lines, etc.cial care has to be taken during design and simulation of these circuits.
Another approach is the so called coded modulation, where the source, encodemodulator are no longer optimized separately. Instead the ambition is to optimizewhole transmitter (and receiver) as one unit. This also implies new possibilities fodesign of mixed analog/digital parts, where new simulation and design methodolomay be used.
In this thesis we focus on the digital subscriber line standards [83-88], which commare referred to as xDSL which is the overall notation for several standards (or destandards) as ADSL, HDSL, VDSL, etc. The general structure of a transceiver for wband radio and very high data rate digital subscriber line (VDSL) is sketched in Figand a block view of a modem for asymmetric digital subscriber line (ADSL) is showFig. 1-4. Generally, the existing copper wire telephone nets are to be used for the xapplications, as is further described in Sec. 1.3.
Figure 1-3: Transceiver for VDSL applications.
Traditionally, video DACs have been used in telecommunication applications, sinctransmission speed for earlier applications has been low enough [17, 22, 52]. As themission speed increases as well as the number of users, the requirements on the conare much higher. The converters are specially designed, assigned for this specific
Source Encoder Modulator
Sink Decoder Demodulator
Channel
Digital Mixed Analog/Digital Analog
RF Analog
Filter
Digital
FilterDSP
Wideband
A/D
Analog
Filter
Digital
Filter
Wideband
D/ADSP RF
Mixed Analog/Digital System
7
Part A: Overview: Digital-to-Analog Converter Design
temiver,
tion.nnaplifi-
Somemea-theratiothecon-
erterual-
it, itioral-
r [1,d a1-5.
rent,e.g.,onlyand
hav-it- oron ofsim-edgesur-
tion. In the future we will probably see more specific circuits optimizing the whole syswith the converters, amplifiers, and filters at the front-end and back-end of the transcewith the goal to minimize a cost function as for example the overall power consumpThe ambition is also to be able to put the DAC and/or ADC directly on the line or anteto minimize the number of analog components, such as mixers, modulators, and amers [15].
Figure 1-4: Modem for ADSL applications over the existing telephone system.
We also see varying sensitivity to performance in different transmission schemes.allow more noise, but less distortion and vice versa. Among dynamic performancesures, we find the signal-to-noise ratio (SNR), the total harmonic distortion (THD),spurious-free dynamic range (SFDR), and the signal-to-noise-and-distortion(SNDR). It can be shown that in principle from a certain degree of non-linearity, it isSFDR that determines the SNDR and THD, and thereby the total performance of theverter.
For most telecommunication applications it is the dynamic performance of the convthat determines the quality of the transceiver [6]. The converter could limit the total qity of the transmission channel and be the bottleneck of the system.
1.1.3 Higher-Level Design
Due to the high complexity of a converter or in general, a mixed analog/digital circuis important to have good models. We now see more exhaustive models on behavlevel that are used in higher-level simulation tools as for example MatLab or simila48, 74, 80]. Simulations on circuit-level or layout-level are very time-consuming anfaster design flow can be achieved by using higher-level simulation methods, Fig.The models are verified using results from measurements and simulations.
Using a circuit-level description of the converter, the signal types used may be cure.g., current-steering DAC, voltage, e.g., resistor-string DAC, and/or charge,switched-capacitor DAC. On a higher level we do not have to consider signal types,the basic principle of the converter. In this way, the influence of noise, non-linearity,other circuit imperfections can be analyzed in a more fundamental way.
When designing analog circuits we have to consider all levels of the design. At beioral-level we can improve results by using different coding techniques and at circulayout-level the skills of experienced analog designers are used. The combinatiknowledge in behavioral-level simulation and design, and knowledge in layout-levelulation and design is very attractive. In this thesis we are trying to combine the knowlof the behavior of the converter with simulation, modeling, implementation, and mea
Line
Driver
Wideband
A/D
Analog
Filter
Analog
Filter
Wideband
D/A
AGC
Dig
ital
Fro
nt E
nd
Pot
sS
plitt
er SubscriberLine
Interface
Pots Interface
Mixed Analog/Digital System
8
.
t sig-
, dis-[37].
inu-time
m-n, ,
am-
two
ing, with focus on the use in telecommunication applications.
Figure 1-5: Behavioral-level design and simulation provides a faster design flow.
1.2 Signals and Coding Schemes
We define a signal as a current, charge, or voltage that carries information. Differennal types as well as different digital codes are presented in this section.
1.2.1 Signal Definitions
A signal can be divided into a number of groups depending on its properties, i.e.crete-time, continuous-time, discrete-amplitude, and continuous-amplitude signalsAs combinations of these we find the analog or the digital signal, Fig. 1-6.
Figure 1-6: Signals with a) analog and b) digital representation.
With ananalog signalwe understand a signal that is both continuous-time and contous-amplitude. The analog signal is described by a mapping function, , from the
point, , to the amplitude as
(1-2)
where and is the set of real numbers.
With a digital signal we understand a signal that is both discrete-time (uniform sapling) and discrete-amplitude. The digital signal is described by a mapping functio
from the discrete-time point, , to the amplitude as
(1-3)
where and , is the set of integer numbers, is the set of possible
plitude levels determined by the digital code used, and is the time period between
Specifications
Behavioral-LevelDescription &
SimulationCircuit-Level
Implementation
Layout-LevelImplementation
Circuit-LevelModels
Layout-LevelModels
Simulation &Verification
“Faster”Design
Flow
t
a(t) a(n)
na) b)
T
f
t A f t( )=
t A f t( )=( )→
t A, R∈ R
f
nT A f nT( )=
nT A f nT( )=( )→
n Z∈ A AL∈ Z AL
T
9
Part A: Overview: Digital-to-Analog Converter Design
[42].n this
of the
is ar
e
ffset
.which
rrent-
he
consecutive values.
1.2.2 Digital Numbers and Representation
There is a number of different codes with their special purpose and propertiesExamples on different codes are given in Table 1-1, they are also further described isection.
Assume that the digital number, , can be written as
(1-4)
where is the MSB and is the LSB. For signed digital numbers we refer to
as the sign bit. We only discuss the integer numbers in this thesis.
In anoffset binary code a number is given by
(1-5)
Using the offset binary code we cannot represent negative numbers. The rangecode is
(1-6)
In the thesis we focus on using offset binary codes. In current-steering DACs thisconvenient method, Chapter 4 inPart B: Nyquist-Rate Digital-to-Analog Converters foVDSL Applications.
Thesigned-magnitude codeuses the MSB as sign bit. indicates a positiv
number and a negative. The other bits indicate the magnitude as for an o
binary code. A number is given by
(1-7)
One effect is that there are two representations for the zero value; andThe signed-magnitude code also may have operand sign-dependent operationsintroduces extra control logic and computation time [42]. The range of the code is
(1-8)
The signed-magnitude allow though some special structures for binary weighted custeering DACs [56].
In aone’s complement code we define the number as
(1-9)
Also with this representation there is a situation with two zeros; and . T
X
X xN 1– xN 2– … x2 x1 x0, , , , ,( )=
xN 1– x0 xN 1–
X 2k xk⋅k 0=
N 1–
∑ x0 2x1 … 2N 1– xN 1–⋅+ + += =
0 X 2N 1–≤ ≤
xN 1– 0=
xN 1– 1=
X 1–( )xN 1– 2k xk⋅k 0=
N 2–
∑⋅=
0…00 10…00
X 2N 1– 1–( )≤
X xN 1–– 2N 1– 1–( )⋅ 2k xk⋅k 0=
N 2–
∑+=
0…00 1…11
10
.
l
efore
nted
qually
range of the code is
(1-10)
Table 1-1: Different types of digital codes.
The two’s complement codealso utilizes a sign bit in the MSB position. The digitanumber is given by
(1-11)
and the range of the code is
(1-12)
The two’s complement code has good properties for arithmetic operations and therused in several applications.
In the thermometer code, the number of ones in the code determines the represenumber. The number is given by
(1-13)
and in an order set we have that
(1-14)
The thermometer code is suitable for segmentation of sources, when a number of elarge sources is desired.
ValueOffsetBinary
Two’scompl.
One’scompl.
Signed-Magn.
Therm.
7 111 1111111
6 110 0111111
5 101 0011111
4 100 0001111
3 011 011 011 011 0000111
2 010 010 010 010 0000011
1 001 001 001 001 0000001
0 / -0 000 000 000 / 111 000 / 100 0000000
-1 111 110 101
-2 110 101 110
-3 101 100 111
-4 100
X 2N 1– 1–( )≤
X 2N 1– xN 1–⋅– 2k xk⋅k 0=
N 2–
∑+ x0 2x1 … 2N 1– xN 1–⋅–+ += =
2N 1–– X 2N 1– 1–( )≤ ≤
X xkk 1=
2N 1–
∑=
xk 1+ 1=( ) xk 1=( )⇒
11
Part A: Overview: Digital-to-Analog Converter Design
ts onnum-
thiss stillstan-
rans-ed toel ford data
demstween
rd forission
ed in
1.3 xDSL Standards
The telecommunication industry forms new standards to meet the requiremenhigher speed and the demands from more and more users. Naturally, there is a largeber of different standards for different applications. A few of them are described inthesis, although it should be emphasized that several telecommunication standardnot have found their final acceptance as a standard and they only work as de factodards.
All xDSL techniques are intended to be used on the existing copper wires and the tmission rate is highly dependent on the length of the wire [83]. There is a large neuse the already existing plain old telephone system (POTS) as an information channhigher speed, Fig. 1-7. The normal speech channel is separated from the high-speechannel with splitters, and the other information is handled by specially assigned moand switches [12, 83]. The channels using the xDSL techniques bridges the gap bethe local network and the broadband network.
Figure 1-7: Applications of the xDSL technique. The information from a broadband network istransferred to the local network via copper wires of the existing telephone net.
Since the transmission speed for ADSL can be around 6Mb/s, it is a suitable standainternet access, services as video-on-demand and similar. For VDSL the transmrates are even higher and therefore it may be used for broadband network.
Figure 1-8: Frequency domain characteristics of different xDSL techniques.
The frequency ranges for different standards are shown in Fig. 1-8 and summarizTable 1-2.
Table 1-2: Transmission rates for different standards.
Standard Transmission Rate [Mbit/s]
ADSL Downstream: 1.5 - 9 Upstream: 0.016 - 0.640
HDSL Both ways: 1.544 - 2.048
VDSL Downstream: 13 - 52 Upstream: 1.6 - 2.3
ADSL-Lite Downstream: 0 - 1 Upstream: 0 - 0.8
BroadbandNetwork
e.g., Radio,Fibre, etc.
LocalNetwork
Splitter
Telephone(Voice)
“existing”copper wires
POTS ADSLHDSL
VDSL
4.3k 1.1M 50M
f [Hz]
12
.
-toneM).ing
fromn thetedions
ined
areof ancyized
ratiothe
e 1-bout
The xDSL standards use modulation techniques as for example discrete multi(DMT), carrierless amplitude phase (CAP), and discrete wavelet multi-tone (DWTThe DMT technique is basically a version of orthogonal frequency division multiplex(OFDM). We briefly discuss the standards; ADSL and VDSL:
• Asymmetric digital subscriber’s line (ADSL)
The ADSL uses an asymmetric transmission scheme, since for most applicationsthe single user’s point of view, the downstream transmission speed is higher thaupstream, which is utilized in ADSL. With the DMT modulation the data is associawith a number of carriers. The carriers are individually orthogonal and are at the posit
(1-15)
where kHz and is an integer. The number of carriers used is determ
by the quality of the line and the mode of operation. If the line is perfect 249 tonesused in the frequency range from 25.875kHz to 1.104MHz. The output spectrumDMT signal with 240 tones is shown in Fig. 1-9. Shown in the figure is also the frequedomain specification according to the ANSI T1E1.4 working group [83] as summarin Table 1-3.
Figure 1-9: Output amplitude spectrum of a 240-tone DMT signal shown with frequency domainspecifications for the ADSL standard [83].
The number of bits associated with a certain carrier is given by the signal-to-noisewithin a 4.3125kHz bandwidth centered around the specific carrier. According tospecifications [82, 83], the SNDR has to be given (in dB) by
and (1-16)
where is the number of bits that can be associated with the carrier.
Since the ADSL specifications still are hard to meet, the ADSL-Lite standard (Tabl2) with reduced requirements has evolved. The reader can find more information athe overall ADSL techniques in [82-90].
f k k f 0⋅=
f 0 4.3125= k
104
105
106
107
−180
−160
−140
−120
−100
−80
−60
−40
ADSL Specifications
SNDR 3N 20+≥ SNDR 38≥
N
13
Part A: Overview: Digital-to-Analog Converter Design
egin-thewithind theand
om-tions
pro-rationTheipolar
ulk issilicon
rate isd the
Table 1-3: Specifications on the ADSL output spectrum.
• Very high data rate digital subscriber’s line (VDSL)
As for ADSL, the VDSL also uses an asymmetric transmission scheme, and in the bning, the VDSL standard evolved from the ADSL. However, the ambition is to reachsame data rate for the downstream as the upstream rate, since VDSL more is to usea larger network. The transmission schemes are basically, CAP, DMT, or DWTM, anfrequency range for the VDSL technique is from 300kHz to 700kHz (upstream)1MHz to 100MHz for downstream.
As for the ADSL, the standard is not really set and committees are trying to find a cmon standard. The VDSL is suitable for package handling as ATM, and the applicaare for example HDTV, internet access, etc.
The reader can find more information about the VDSL technique in [86-90].
1.4 The CMOS Transistor
In this thesis, we focus on the complementary metal oxide semi-conductor (CMOS)cess. The CMOS process is relatively simple and cheap as well as very high integof complex circuits is provided, hence suitable for low power and high-speed [57].vision is that the CMOS transistor soon will be able to reach the same speed as the bdevice.
The MOS device has four terminals; gate, source, drain, and bulk, Fig. 1-10. The bconnected to the substrate and the gate is separated from the substrate by a gateoxide layer.
Figure 1-10: Circuit symbols for the a) NMOS and b) PMOS transistor.
For the PMOS transistor we use heavily p-type doped source and drain. The substof n-type. For the NMOS transistor the source and drain are heavily n-type doped, ansubstrate is p-type doped.
Frequency Band [kHz] Upper Bound [dB] (f in kHz)
0 - 4
4 - 25.875
25.875 - 1104
1104 - 2208
2208 - 3660
3660 - 11040
97.5–
92.5– 21 f 4⁄( )log 2log⁄⋅+
36.5–
36.5– 36 f 1104⁄( )log 2log⁄⋅–
72.5– 24 f 2208⁄( )log 2log⁄⋅–
90–
G
S
D
B G
D
S
B
a) b)
14
.
ound.ond-on of
mallate-
arger
wer
ate-
tage,
r lin-
nsis-
the
h. The
sur-
1.4.1 Operation Regions and Small Signal Characteristics
Dependent on the voltage applied on the terminals, different operation regions are fIn this description we use the NMOS transistor and by inverting all voltages corresping results for the PMOS transistor are achieved. Also see Fig. 1-11a) for descriptivoltages.
Figure 1-11: NMOS a) circuit symbol and b) small-signal schematics.
In weak inversion (subthreshold region) the transistor is cut-off and only a very scurrent (leakage current) is flowing through the transistor. In strong inversion the gsource voltage, , is higher than the threshold voltage, , and a considerably l
current, , may flow from source to drain. When the drain-source voltage, , is lo
than the effective voltage, , the current is linearly dependent on the g
source voltage. When the drain-source voltage, , is higher than the effective vol
, the channel will become pinched-off, i.e., saturated, and the current is no longe
early dependent on the gate-source voltage. The drain current, , for the NMOS tra
tor in the different operating regions is approximately given by [37]:
• Cut-off region, :
(1-17)
• Linear region, and :
(1-18)
• Saturation region, and :
(1-19)
where is the channel length modulation factor, is the charge mobility, is
oxide capacitance per gate area, is the channel width and is the channel lengt
threshold voltage, , is given by
(1-20)
where is a constant given by the material, is the body-factor, and is the
face potential at strong inversion. The notations
gmbsvgs gmvgs gds
Drain (D)
Source (S)
Gate (G)
vgs
iDiD
vGS
vDS
vSB
a) b)
vGS vT
iD vDS
veff vGS vT–=
vDS
veff
iD
vGS vT<( )
iD 0≈
vGS vT>( ) vDS veff<( )
iDµ0Cox
2--------------- W
L-----
2 vGS vT–( ) vDS–( ) vDS 1 λvDS+( )⋅ ⋅ ⋅ ⋅≈
vGS vT>( ) vDS veff>( )
iDµ0Cox
2--------------- W
L-----
vGS vT–( )2 1 λvDS+( )⋅ ⋅ ⋅≈
λ µ0 Cox
W L
vT
vT VT0 γ 2 φF vSB+ 2 φF–( )⋅+=
VT0 γ 2 φF
15
Part A: Overview: Digital-to-Analog Converter Design
firstthe
hes),e (1-
11b),tor is
theneralasso-ular-
paci-by the
, , and (1-21)
are also used throughout the thesis.
It should be noted that the equations (1-17) through (1-20) are approximations of theorder. Short channels give rise to second-order effects that strongly may modifyresults derived by using the equations above.
In analog design we try to use the transistors in their saturated region (except switcsince the drain current is approximately only determined by the gate-source voltag19). This gives a better control over linearity and operation of the circuits [33].
We also need to know the small signal parameters of the MOS transistor, Fig. 1-which are derived in the quiescent point. The transconductance, , of the transis
defined as
(1-22)
In the linear and saturation regions the transconductance is
and (1-23)
The output conductance of the transistor, , is given by
(1-24)
which in the linear and saturation region is
and (1-25)
The influence of the source-bulk voltage also gives rise to a gain factor of
(1-26)
which in the different regions is
(1-27)
1.4.2 Parasitic Capacitors
A fundamental limit to the performance is the capacitive load at circuit nodes. WithMOS transistor a number of capacitors is associated, as shown in Fig. 1-12. In gethey are divided into three kinds, those associated with the depletion regions, thoseciated with the gate and the operation region, and finally those associated with irregities and unwanted overlaps in the geometrical structure of the MOS transistor.
When designing analog circuits it is necessary to analyze the influence of these cators carefully. Increasing the transistor sizes also increases the capacitors and there
K' µ0Cox= S W L⁄= β K' S⋅=
gm
gm
iD∂vGS∂
-----------Q
=
gm lin, β VDS⋅≈ gm sat, 2β I D⋅≈
gds
gds
iD∂vDS∂
-----------Q
=
gds lin, β VGS VT– VDS–( )⋅≈ gds sat, λ I D⋅≈
gmbs
iD∂vBS∂
-----------Q
gm
vT∂vSB∂
-----------Q
⋅= =
gmbs lin sat⁄,γ
2 2 φF VSB+( )1 2/------------------------------------------- gm lin sat⁄,⋅≈ η gm lin sat⁄,⋅=
16
.
tion
te is
ching, theclock
, cur-s. InThe
uency
dis-
, is
bandwidth of the circuit is affected. In Table 1-4 the capacitor sizes in different operaregions are summarized.
Figure 1-12: Capacitors associated with the terminals of the transistor,Cgs, Cgd, Csb, Cgb, andCdb.
Table 1-4: Variations of capacitors associated with the transistor in different working conditions.
The charges at and are changing when the switching voltage at the ga
changing. This forces extra charge to redistribute to the drain and source. When switanalog signals using digitally controlled switches, e.g., sample-and-hold circuitscapacitors may introduce glitches and current spikes in the analog signal. Thisfeedthrough (CFT) gives rise to noise and distortion in the analog signal [71].
1.5 Circuit Noise
We consider the noise to be an unwanted and, in principle, undeterminable voltagerent, or charge [20]. Noise is a fundamental limit to the performance of analog circuitDACs the signal-to-noise ratio (SNR) determines the resolution of the converter.noise is characterized by its power spectral density (PSD) as
(1-28)
where is the average normalized mean-square noise current and is the freq
variable. The shot noise, thermal noise, and noise (flicker noise) are brieflycussed:
• The shot noisePSD, arising when a dc current, , is applied to a pn-junctiongiven by
where is the fundamental electron charge.
• Thethermal noise PSD through a resistance, , is determined by
Operation region Gate-Bulk, Gate-Source, Gate-Drain,
Cut-off 0 0
Linear 0
Saturation 0 0
Cgs
Csb Cdb
Cgd
Cgb
S D
B
G
Cgb Cgs Cgd
CoxWL
CoxWL 2⁄ CoxWL 2⁄
2CoxWL 3⁄
Cgs Cgd
S f( ) i2
∆f------=
i2 ∆f
1 f⁄
I
S f( ) 2qI=
q
R
S f( ) 4kTR
----------=
17
Part A: Overview: Digital-to-Analog Converter Design
r theD of
lues
dis-tched
where is the Boltzmann’s constant and is the absolute temperature. FoCMOS channel we have an extra correction factor to the expression. The PSthe noise current through the drain of the transistor is given by
where is the transconductance of the transistor.
• Theflicker noise (or noise) PSD is determined by
where , , and are material-dependent variables. For and , typical va
are and .
For high-speed CMOS applications it is the thermal noise that is dominating. Forcrete-time circuits we also have to consider the concept of sampled noise or swinoise.
k T
S f( ) 83---kTgm=
gm
1 f⁄
S f( ) K fI a
f b-----⋅=
a b Kf a b
a 1≈ 0.8 b 1.3≤ ≤
18
2. The Ideal DAC
The37].thes of a
i.e.,enceWith
ete-fre-
dis-e fre-
infor-r as
2 The Ideal DAC
It is important to understand the properties of an ideal digital-to-analog converter.ideal reconstruction of a discrete-time signal is made by ideal lowpass (LP) filtering [In the time domain, this implies pulse amplitude modulation (PAM), i.e., weighting ofdiscrete-time values with sinc functions, Sec. 2.1. Due to the non-causal propertiesinc function, this operation is practically impossible to fulfil.
Further on, we discuss the resolution of an ideal DAC. If the resolution is limited,the number of bits in the converter is finite, the output signal is discrete-amplitude, hthere is a quantization noise in the output signal if the number of bits is large enough.an infinite number of bits, the noise and distortion disappear.
2.1 Discrete-Time Properties
The output of the DAC with a finite number of bits is a discrete-amplitude and discrtime signal. It is denoted where is the update cycle time or . The
quency spectrum of the output is given by
(2-1)
The spectrum is repeated over the frequency range, since
(2-2)
The amplitude spectrum is shown in Fig. 2-1. For a discrete-amplitude signal, ascussed above, there would be a noise floor, or even distortion terms, through out thquency range as well.
Figure 2-1: Discrete-time amplitude spectrum.
The generation of the continuous-time signal, hence the extraction of the wantedmation, from the discrete-time spectrum is performed with an ideal lowpass filteshown in Fig. 2-2. The frequency spectrum of the continuous-time signal, , is
where (2-3)
x nT( ) T T 1 f s⁄=
X ejωT( ) x nT( ) e jωTn–⋅n∀
∑=
X ejωT( ) X ej ωT 2π+( )( )=
−π 2ππ−2πejωT
|X(ejωT)|
X ω( )
X ω( ) T X ejωT( )⋅= ωT π≤
19
Part A: Overview: Digital-to-Analog Converter Design
litudetionct theed by
ency
Asthe
fre-
). Theuist
at theof
the
log
Figure 2-2: Ideal lowpass filtering with pulse amplitude modulation.
In the time-domain, (2-3) corresponds to the operation
(2-4)
where the discrete-time values are weighted with the sinc functions, i.e., pulse ampmodulation (PAM). This is however impossible to accomplish in a real implementasince the sinc function is non-causal. In the real case, the common way to reconstrusignal is to use sample-and-hold circuits on the output, hence the output is describpulse waves. Let be the reconstructed output signal as
(2-5)
where are the discrete-time values and is the step function. The frequspectrum of the reconstructed signal is
(2-6)
The amplitude spectrum of the sinc weighting function, , is shown in Fig. 2-3.is seen from the figure there is an attenuation of the original signal spectrum withinNyquist frequency band, . Images also occurs since is non-zero at
quencies above the Nyquist frequency and the discrete-time signal is repeating, (2-2images are removed or attenuated with an LP filter with cut-off frequency at the Nyqfrequency. To compensate the attenuation within the signal band, an anti-sinc filteroutput may be used as well. At the Nyquist frequency, , there is an attenuation
(2-7)
A simple approach to compensate the distortion is to use a filter, , that fulfils
approximate equation
(2-8)
in the frequency range .
The filter can be implemented in the digital domain at the input of the digital-to-anaconversion as well as using an analog filter at the output [7, 17, 30, 47].
−π 2ππ−2πejωT
|X(ejωT)|
x t( ) x nT( ) sinc f s t nT–( )( )⋅n∀
∑=
x t( )
x t( ) x nT( ) u t nT–( ) u t n 1+( )T–( )–[ ]⋅n∀
∑=
x nT( ) u t( )
X ω( ) F x t( ) 1 e jωT––jω
---------------------- x nT( ) e jωnT–⋅n∀
∑⋅= = =
ejωT
2---–
sinc ωT 2⁄( ) X ejωT( )⋅ ⋅ C ω( ) X ω( )⋅= =
C ω( )
f N f s 2⁄= C ω( )
f N
C 2π f N⋅( ) C π f s( ) 2 π⁄ 0.637≈= =
Has
Has ω( ) C ω( )⋅ 1≈
ω 2πf s
2-----⋅≤
20
2. The Ideal DAC
ussedon wey uni-tiza-theoise
, we
es agiven
the
Figure 2-3: Sinc weighting characteristics due to sample-and-hold elements.
2.2 Quantization and Discrete-Amplitude Properties
The representation of the digital code can be given in different ways, as was discin Sec. 1.2.2. Generally, we can chose whatever representation or mapping functiwant. In most cases, however, we use two different ways to represent the signal; bform or non-uniform quantization. The quantization give rise to noise, so called quantion noise. If the number of bits is small, distortion components are also visible inspectrum. In an OSDAC, where the number of bits often is small, the quantization nand distortion terms are highpass (HP) filtered. This is further discussed inPart C: Over-sampling Digital-to-Analog Converters for ADSL Applications.
Let the codes used by the -bit converter be given by the ordered set of codes
(2-9)
Each code is given by an ordered set of bits
(2-10)
Let the function describing the transfer function of the converter be given by
where is the amplitude level generated for the code . For a specific code,
denote the amplitude as
(2-11)
2.2.1 Quantization Types
In this thesis, we focus on offset binary code and uniform quantization which providregular quantization structure as sketched in Fig. 2-4a). Let the transfer function beby
(2-12)
where is the reference level and . Further, the reference level is
amplitude level for the LSB and the notation
πfs 2πfs 3πfs 4πfsω
|C(ω)|
0.64
1
N
X X0 X1 … X 2N 2–( ) X 2N 1–( ), , , , ∈
X xN 1– xN 2– … x1 x0, , , ,( )=
A X( )A X( ) X Xi
A Xi( ) Ai=
A Xi( ) Ai i Aref⋅= =
Aref i 0 … 2N 1–, ,≤
21
Part A: Overview: Digital-to-Analog Converter Design
hted
tudeum
sefulareveduni-
ter.
.
ouldthis
ight
nedthe
Each
tput
(2-13)
is also used. As described in equation (1-1) the output amplitude for a binary weigconverter is given by
(2-14)
where the result from (2-12) is applied. The maximum output amplitude is given by
(2-15)
Assuming that the input signal is statistically equal distributed over the whole amplirange, the uniform quantization intuitively provides a minimum error, hence a minimquantization noise.
Figure 2-4: Transfer function with a) uniform and b) non-uniform quantization.
When the signal is not equally distributed over the amplitude range it may be more uto use non-uniform quantization, Fig. 2-4b). With this method some amplitude levelsquantized with a larger error, but statistically a minimum quantization noise is achiesince the probability for these amplitude levels is lower. The output level using non-form quantization can be written as
(2-16)
where and is the set of possible amplitude levels of the conver
The non-uniform quantization may give rise to a more complex converter structure
2.2.2 Quantization Noise
The expected transfer function of an ideal converter using offset binary coding shbe a straight line from the minimum zero value; , to the maximum value (in
case); . Quantization noise, defined as the deviation from the stra
line, is introduced when the number of bits, , is finite. Note that the error is defiwithin the minimum and maximum amplitude levels. Assume that we sweep throughcodes, , consecutively as a function of time, i.e., sweeping a ramp, with period .
code are represented during a certain time interval given by . The true ou
Amax A X 2N 1–( )( ) A 2N 1–( ) 2N 1–( ) ALSB⋅= = =
A(Xi)
X XAk
Ak+1
A(Xi)
a) b)
Ak
Ak+1
A X( ) x0 A0⋅ x1 A1⋅ x2 A2⋅ … xN 1– AN 1–⋅+ + + +=
A Xi( ) Ai AL∈= AL
Amin 0=
Amax 2N Aref⋅=
N
Xi T
∆T T 2N⁄=
22
2. The Ideal DAC
on.
as the
n as
is given by a stairs function, Fig. 2-5, and can be written as
(2-17)
where is the amplitude level for the code , and is the step functi
The wanted output signal, , should be a ramp function, Fig. 2-5, as
(2-18)
‘
Figure 2-5: Transfer characteristics for an offset binary conversion and uniform quantization.
The quantization error as function of the time, shown in Fig. 2-6, is written as
(2-19)
We can now find the error r.m.s. value, , by using
(2-20)
It can easily be seen that the total r.m.s. error (over the time ) must be the same
r.m.s. error during half a single time period of , therefore (2-20) can be writte
(2-21)
which gives the r.m.s. value as
Atrue t( ) Ak u t k∆T–( ) u t k 1+( )∆T–( )– ⋅k 0=
2N 1–
∑=
Ak k Aref⋅= Xk u t( )
Awant t( )
Awant t( ) tT--- Amax⋅ t
T--- Aref 2N⋅( )⋅ t
∆T------- Aref⋅= = =
000 001 010 011 100101 110 111
7Aref
6Aref
5Aref
4Aref
3Aref
2Aref
Aref
Aout
X
Awant
Atrue
8Aref
Aerr t( ) Awant t( ) Atrue t( )–=
Aerr rms,
Aerr rms,2 1
T--- Awant t( ) Atrue t( )–[ ]2 td
0
T
∫=
T
∆T 2⁄
Aerr rms,2
Aref2
∆T 2⁄-------------- t
∆T-------
2td
0
∆T 2⁄
∫Aref
2
12----------= =
23
Part A: Overview: Digital-to-Analog Converter Design
ence aset
ica-refore
(2-22)
Figure 2-6: Quantization error as a) function of time and b) modeled as an error signal.Awant(t) is thewanted signal,Atrue(t) is the true output, andAerr(t) is the quantization noise.
Further, it is assumed that the noise can be considered to be signal-independent, hlarge number of bits and fine quantization. A sinusoidal of full amplitude for an offbinary code, i.e., dc value of and amplitude of
(2-23)
The r.m.s. value of the sinusoidal is
(2-24)
We define the peak signal-to-noise ratio (SNR) as
(2-25)
and in dB, this is approximately
(2-26)
For a small number of bits (2-26) has to be slightly corrected [56]. For telecommuntion applications the resolution should be high, hence a large number of bits and thethis consideration is not further discussed.
Several different measures are used to characterize the quality and performancedigital-to-analog converter. Different applications may request good linearity and nohard requirements on noise, and vice versa. For several telecommunication applicamulti-tone signalling system is used. In this case, for example the total harmonic dition may not give all the information we want about the quality of the DAC. We havefind other measures that determine the non-linearity and noise that are introduceirregularities of the converter.
The performance measures can be divided into two groups; static and dynamic me[28, 29, 56]. To the static performance we count the signal-independent values aserror, gain error, differential non-linearity (DNL), integral non-linearity (INL), monotnicity, etc. Dynamic performance is described by signal-dependent values as non-slewing, clock feedthrough (CFT), glitches, overshooting, etc.
Both static and dynamic properties can be investigated in the frequency domainStatic errors may give rise to distortion at frequencies that are multiples of the fundatal signal frequency. CFT gives frequency components in multiples of the Nyquistquency and glitches give higher frequency components, etc. We use the signal-toratio (SNR), total harmonic distortion (THD), spurious-free dynamic range (SFDR),nal-to-noise-and-distortion ratio (SNDR), and some more measures as powerful todetermine and characterize the DAC performance.
3.1 Static Measures
When a step is applied to the input of the DAC, hence digital bits are switching, thelog output will tune from the start value, , to the final value, , see Fig. 3-1. T
settling time, , describes the time between for example the 5% and 95% value o
ideal step value. The final value (after complete settling) is defined as the static valuehighest possible speed of the circuit is determined by the settling time, , which ma
signal-dependent and will in that case be referred to as non-linear slewing.
The static performance measures are given by the deviations from the wanted valu
and . The deviations are denoted, and , respectively, as shown in Fig
When the code is switching, clock feedthrough (CFT), glitches, overshoot, etc.,arise. CFT arises due to the capacitive coupling between the digital switching signathe analog output signal [71]. The glitch depends on how the internal switches arevidually skewed. It may be an erroneous code connected to the output for a short pof time. This is further described in Sec. 3.2.
Ai Ai 1+
Ts
Ts
Ai
Ai 1+ di di 1+
25
Part A: Overview: Digital-to-Analog Converter Design
avior
e
ea-sticalasures
e Fig.se
two
By using the known deviations, , we can characterize the performance and beh
of the converter.
Figure 3-1: True output signal compared with wanted output signal (dashed). The deviation from thstart-value,di, and the end-value,di+1, determine the static value of the specific code.Settling time is given byTs.
For a large number of bits, it may be inconvenient to find all static values by pure msurement, since the number of amplitude levels grows exponentially. Therefore statimethods can be used to find the deviation values and use them to derive static me[16].
3.1.1 Differential Non-linearity, DNL
As was discussed, a basic error definition is the deviation from the wanted value, se3-2. The differential non-linearity (DNL) indicates how non-linearly distributed theerrors are. Assume that the wanted output value for a certain code, , is
(3-1)
The true value generated by the converter for the same code is given by
(3-2)
The deviation is directly given by
(3-3)
The deviation is normalized with respect to the LSB value, from (2-13), as
(3-4)
and the deviation gets the unit “LSB”. The DNL, , is the difference between the
deviations at a certain code transition, , as
(3-5)
di
t
Aout
Ai+1
Ai
Glitch / CFT / Overshoot
di
di+1
Ts
Slewing
Xi
Awant Xi( ) Ai=
Atrue Xi( ) Ai˜=
di Atrue Xi( ) Awant Xi( )– Ai Ai–= =
ALSB
di
di
ALSB------------
Ai˜ Ai–
ALSB----------------= =
Di
Xi 1– Xi→
Di di di 1––Ai˜ Ai–
ALSB----------------
Ai 1– Ai 1––
ALSB------------------------------–
Ai Ai 1––ALSB
----------------------- 1–= = =
26
3. DAC Performance Measures
odes
ere
as-non-
um
ffsetdefineund
Note that in this case, and are the amplitude levels of two consecutive c
and the difference between them is ideally one LSB.
Figure 3-2: Possible errors in amplitude levels for a 3-bit DAC.
If all deviations are equally large, the DNL is for all code transitions, and th
will only be an offset error at the output. A basic observation is that if the DNL is increing, the deviations from the true code is also increasing and the transfer function islinear.
3.1.2 Offset Error
The offset error, , may be defined as the deviation from the wanted minim
value of the output.
(3-6)
In most configurations the converter is constructed with differential outputs where oerrors (between two channels) are cancelled, and it may in that case be useful tothe offset value, , as the average value of all deviations. The offset value is fo
by minimizing the expression for all , with the least square method as
(3-7)
which gives
(3-8)
The new deviation values are given by
Ai Ai 1–
000 001 010 011 100101 110 111
7Aref
6Aref
5Aref
4Aref
3Aref
2Aref
Aref
Aout
X
A4
d4
Di 0=
Aoffset
Aoffset d0=
Aoffset
di Aoffset– i
Aoffset∂∂ 1
2N------ di Aoffset–( )2
k 0=
2N 1–
∑ 0=
Aoffset1
2N------ di
k 0=
2N 1–
∑⋅=
27
Part A: Overview: Digital-to-Analog Converter Design
gained toger
s notent
with
utput
.1 in
ight
(3-9)
and the DNL values are not affected by this modification, see (3-5).
3.1.3 Gain Error
The gain error of the converter may influence the transfer function severely. Thecan basically be of two kinds, linear and non-linear, as sketched in Fig. 3-3. Comparthe wanted straight line, , the actual output deviates with a stron
slope (Fig. 3-3a) or with even higher order of non-linearity (Fig. 3-3b).
Figure 3-3: Characteristics of a) linear and b) non-linear gain error.
Linear gain error does not introduce extra distortion as long as the output signal iclipping or similar effects arise, compare with (2-14). The true output with a differslope and with offset error can be written as
(3-10)
where is the gain.
The non-linear gain error introduces distortion. The code can no longer be described
a binary offset code and the weights are no longer given by a factor as . The true ofor a non-linear gain can for example be given by
(3-11)
The non-linear errors may be reduced by using pre-distortion [54], see Sec. 5.1Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications.
3.1.4 Integral Non-linearity, INL
The integral non-linearity (INL) describes the overall deviation from a wanted straline. The INL values, , can also be calculated using the DNL values as
(3-12)
Using (3-4) and (3-5) the equation above is rewritten as
diˆ di Aoffset–=
Awant X( ) ALSB X⋅=
X X
Aout Aout
Awant(X) Awant(X)
Atrue(X)Atrue(X)
Atrue X( ) a X⋅ Aoffset+=
a
2i
Atrue X( ) a X⋅ b X2⋅ c X3⋅ … Aoffset+ + + +=
I i
I i Dkk 1=
i
∑=
28
3. DAC Performance Measures
ay bepensa-andendfirst
ential
ed as
east
tput
INL
d ifonic.o dif-
(3-13)
As was discussed in the previous sections, offset errors and linear gain errors mneglected since they do not necessarily degrade the performance. Therefore, comtion for offset and linear gain error gives a more understandable value of the INLDNL. The wanted straight line can be defined in two ways, either using the start andvalues as reference or using a best-fit straight line, which minimizes the error. Theguarantees a true zero code definition and the latter is more useful when using differstructures.
The deviation values are compensated as (3-9) but now the gain error, , is includwell
(3-14)
The gain and offset errors, and , are found by minimizing and using the l
square method as
(3-15)
and
(3-16)
If we assume a large number of bits, the following approximate values are found
(3-17)
(3-18)
The line expresses the best-fit straight line with respect to the true ou
values, . The compensated values, from (3-14), are used to find the DNL and
values as was given in equations (3-5) and (3-12).
3.1.5 Monotonicity
If the output amplitude level of the converter is increasing with increasing input anthere is a one-to-one mapping from the input to the output, the converter is monotOtherwise there is a situation when a specific output value may be represented by twferent input codes, see Fig. 3-4.
I iAi Ai 1––
ALSB----------------------- 1–
k 1=
i
∑Ai A0
˜–
ALSB-----------------
i ALSB⋅ALSB
------------------–di d0–
ALSB----------------= = =
a
diˆ Ai
˜ Aoffset a i⋅+( )– di Aoffset–( ) ALSB a–( ) i⋅+= =
a Aoffset
a∂∂ 1
2N------ di
ˆ 2
k 0=
2N 1–
∑ a∂∂ 1
2N------ Ai
˜ Aoffset a k⋅+( )–[ ]2
k 0=
2N 1–
∑ 0= =
Aoffset∂∂ 1
2N------ Ai
˜ Aoffset a k⋅+( )–[ ]2
k 0=
2N 1–
∑ 0=
Aoffset4
2N------ Ak
˜
k 0=
2N 1–
∑ 622N--------- k Ak
˜⋅k 0=
2N 1–
∑–≈
a1223N--------- k Ak
˜⋅k 0=
2N 1–
∑ 622N--------- Ak
˜
k 0=
2N 1–
∑–≈
Aoffset a X⋅+
Ai˜ di
ˆ
29
Part A: Overview: Digital-to-Analog Converter Design
oree-
ode.L
eter-nom-f theit the
r isut. For
or alarge.
litch
with
r the
Figure 3-4: Transfer function illustrating when monotonicity is not fulfilled (solid line).
Monotonicity implies that all DNL values have to be less than one LSB [56] as
LSB for all (3-19)
This also implies that the deviation from the best-fit straight line must never be mthan a half LSB [56], hence the converter is monotonic if the INL values fulfil the inquality
LSB for all (3-20)
Monotonicity can be improved by segmenting the bits, i.e., using a thermometer cThis is further discussed inPart B: Nyquist-Rate Digital-to-Analog Converters for VDSApplications.
3.2 Dynamic Measures
Especially for telecommunication applications it is the dynamic performance that dmines the quality of the converter. The dynamic performance is determined by pheenon such as glitching, skew, slewing, etc. This may also affect the static value oconverter but in general they do instead affect higher frequencies and therefore limbandwidth of the converter.
3.2.1 Glitch
Glitches occur when the time of switching between different bits in the converteunmatched. For a short period of time a false code could be represented at the outpexample if the code transition is
If the MSB is switching faster than the LSBs, the code may be present fshort time. This code represents the maximum value and hence the glitch would be
It is important to understand how the glitches may affect the performance. We use genergy as a measure of their impact.
We model the glitch as a pulse, Fig. 3-5, with a certain amplitude height, , and
a time duration, . The normalized average power, , of the glitch distributed ove
di
di+1
1 LSB
A
X
Di 1≤ i
I i12---≤ i
0111…111 1000…000→
11…111
Ag
Tg Pg
30
3. DAC Performance Measures
d by
is
ring
ease
ds onat there notge as
mes
shortest possible code duration, i.e., the update time interval, , is describe
(3-21)
Figure 3-5: Glitch modeled as a pulse with heightAg and durationTg.
Assume that the maximum peak glitch amplitude, i.e., the amplitude of the MSB,
(3-22)
which gives the maximum glitch power over one clock cycle
(3-23)
This should be compared with the power of the quantization noise, , (2-21), du
the same period of time
(3-24)
The power of the glitch should be smaller than the quantization in order to not decrthe SNR too much, hence
(3-25)
which gives a bound on the time duration of the glitch as
(3-26)
It should be noted that the glitches are naturally very hard to model since it depena short time and an error code that is hard to predict. It should also be mentioned therror generated by glitches may more or less randomly vary when code transitions arepeated periodically. The power of the glitch error is spread over the frequency rannoise, dependent on the probability for the excitation of the certain code transition.
The glitch impulse is also commonly specified by the glitch area, or its amplitude tithe duration-time, with the unit [9, 56].
Ts 1 f s⁄=
Pg Ag2
Tg
Ts------⋅=
t
Aj
Ak
Ag
Tg
A
Ag max, 2N 1– ALSB⋅=
Pg max, 22N 2– ALSB2
Tg
Ts------⋅ ⋅=
PQ
PQ
ALSB2
12------------=
Pg max, 22N 2– ALSB2
Tg
Ts------⋅ ⋅
ALSB2
12------------< PQ= =
Tg
Ts
3 22N⋅----------------<
pV s⋅
31
Part A: Overview: Digital-to-Analog Converter Design
dig-ghceire.ncy,
, they bethe on-ver the
. Thistaticrade
isingdig-
esis-
th de-utput
giv-
sign
impor-done
3.2.2 Clock Feedthrough, CFT
Due to capacitive coupling or Miller effect in switches (see Sec. 1.4.2) the clock (orital switching signals) will affect the analog output signal [71]. This clock feedthrou(CFT) will arise at both rising and falling edge of the switching signal, and it will forcharge to redistribute, hence a small current will flow in some direction in the analog wIn the frequency domain there will be a frequency component at the Nyquist freque
, since CFT occurs twice a clock period.
The CFT error may be modeled in a similar way as was done for glitches. NaturallyCFT is reduced when reducing the capacitive coupling. The transistor sizes mareduced to decrease the size of the parasitic capacitances. With smaller transistors,resistance increases and may degrade the result in other ways, i.e., voltage drop oswitch, etc.
3.2.3 Non-linear slewing
Signal-dependent capacitance and resistance give rise to the non-linear slewingimplies that for different signals there are different settling times and therefore the svalue may not be reached within one clock period, or at least the performance will degwith higher sampling frequency.
By modeling the converter as a first order RC model, the magnitude of the error arwhen switching from one code to another may be approximated. When switching theital input at the time , the output amplitude is given by
(3-27)
where is the wanted step and is the time constant determined by the r
tance and capacitance associated with the output of the converter. and are bopendent on the input code (and the output amplitude as well). Assume that the true ovalue should be found within one clock period, . The error at the output, , is
en by
For example, for an error less than 1%, , the clock period must be
This indicates the maximum speed of the circuit and it also gives a guide how to dethe circuit according to the specifications. It is further discussed in Sec. 3.5 inPart B:Nyquist-Rate Digital-to-Analog Converters for VDSL Applications.
3.3 Frequency-Domain Measures
Since in most cases we use the frequency domain to characterize the devices, it istant to have useful measures. In many applications the information extraction is also
f N f s 2⁄=
t0
Aout t0 t+( ) Aout t0( ) Astep 1 et
RC--------–
– ⋅+=
Astep τ RC=
R C
Ts d Ts( )
d Ts( )Aout Ts( ) Aout t0( )–
Astep----------------------------------------------- 1 e
Ts
RC--------–
–
= =
d Ts( ) 0.01<
Ts τ 100⁄>
32
3. DAC Performance Measures
efore,i-toneacterize
f the
cale
o be
tio
tude.
the
tude.
atio
in the frequency domain using FFT and IFFT operations.
Several standards for telecommunication applications use multi-tone signals. Therthe frequency domain measures are divided into single-tone, dual-tone, and multmeasures. It can also be seen that the single-tone measures are not enough to charconverters for multi-tone applications [28].
3.3.1 Signal-to-Noise Ratio, SNR
The signal-to-noise ratio (SNR) of the system is simply defined as the power ratio osignal and the noise within the Nyquist bandwidth.
(3-28)
where is the signal r.m.s. value and is the noise r.m.s. value. With a full-s
sinusoidal signal and quantization noise only, the SNR was derived in section 2.2 t
(3-29)
where is the number of bits.
3.3.2 Harmonic Distortion, HDk
The harmonic distortion with respect to the -th harmonic ( ) is the power ra
between the -th harmonic and the fundamental as
(3-30)
where is the amplitude of the -th harmonic and is the fundamental’s ampli
3.3.3 Total Harmonic Distortion, THD
Another measure of non-linearity is the total harmonic distortion (THD), which issum of all harmonic distortions from (3-30) as
(3-31)
where is the amplitude of the -th harmonic and is the fundamental’s ampli
3.3.4 Signal-to-Noise-and-Distortion Ratio, SNDR
When including the non-linearity with the noise, the signal-to-noise-and-distortion r(SNDR) is given
Part A: Overview: Digital-to-Analog Converter Design
nic,
e fun-
rgest
t the
s
DR.ll be
29).r of
ever
nesare
cies
ter-
s in
where is the amplitude of the fundamental, is the amplitude of the -th harmo
and is the noise r.m.s. value.
3.3.5 Spurious-Free Dynamic Range, SFDR
The spurious-free dynamic range (SFDR) is defined as the power ratio between thdamental and the second largest frequency component (except the dc)
(3-33)
where is the amplitude of the fundamental and is the power of the second la
component. The SFDR mostly determines the quality of the converter. Assume tha
maximum peak is one of the harmonics, . Then (3-31) is rewritten a
(3-34)
If the sum in expression (3-34) is small enough, the THD is determined by the SFUsing (3-32) we also see that if the distortion is larger than the SNR, also SNDR widetermined by the SFDR.
3.3.6 Effective Number of Bits, ENOB
When applying a full-scale sinusoidal to the DAC, the peak SNR is found from (3-By using the expression on SNDR (3-32) with (3-29) we derive the effective numbebits (ENOB) as
(3-35)
ENOB gives a hint on the performance of the converter. The ENOB value is howmostly used when characterizing the performance of ADCs.
3.3.7 Inter-Modulation Distortion, IMD
With inter-modulation distortion (IMD) we understand the distortion when several toare applied to the circuit. Assume that two tones with the frequencies and
applied to the converter. Intermodulation is given by the components in the frequen
(3-36)
where and are integer numbers, and further , , and . The in
modulation distortion is found by
(3-37)
where is the amplitude of the fundamental and is the amplitude of the tone
A0 Ak k
Brms
SFDRA0
2 2⁄Pmax-------------=
A0 Pmax
Pmax Amax2 2⁄=
THDAmax
2
A02
------------ 1Ak
2
Amax2
------------k maxpos≠
∑+
⋅=
ENOBSNDR 1.76–
6.02--------------------------------≈
f 1 f 2
k f 1⋅ m f2⋅+( ) mod f s 2⁄( )
k m k 0≠ m 0≠ f 1 f 2≠
IMDAk m,
2∑A0
2-------------------=
A0 Ak m,
34
3. DAC Performance Measures
nda-, see
c.),rtionistor-the
these.
nciesics at
st fac-ghtlytes a
the frequencies given by (3-36).
For some multi-tone applications the tone frequencies are multiples of a specific fumental frequency and hence the intermodulation terms will interfere with other tonesSec. 3.3.8 below.
3.3.8 Multi-Tone Power Ratio, MTPR
It is hard to find the distortion for multi-tone transmission schemes (DMT, OFDM, etsince tones often are multiples of a fundamental frequency. This implies that distoterms, harmonics, are added to true information carriers. A method to find out the dtion is to apply a number of tones (that are multiples of a fundamental, ), all with
same amplitude, . Some tones are left out, and the distortion terms that occur atpositions determine the quality and the multi-tone power ratio (MTPR) is defined as
(3-38)
This is also depicted in Fig. 3-6, where 25 tones have been applied. At two frequetones have been excluded. The non-linearity of the converter introduces harmonthese positions, and MTPR can be determined by the power of these harmonics.
Figure 3-6: Illustration of the impact of MTPR. Two tones are left out and the non-linearity can befound by observing the power of the tones appearing at the left-out positions.
3.3.9 Peak-to-Average Ratio, PAR
For multi-tone measurements we also use the peak-to-average ratio (PAR) or cretor. Since PAR describes the peak power to the average power ratio, it also slidescribes how the signal is distributed over the amplitude range. A low PAR indicamore uniform distribution. The PAR can be written as
(3-39)
ω0
A
MTPR A2 2⁄Power of tones at left-out frequency positions-------------------------------------------------------------------------------------------------------------=
0 0.1 0.2 0.3 0.4 0.5−120
−100
−80
−60
−40
−20
0
20
40
60
80
Spectrum of summed sines. (Non−linear converter).
Sig
nal p
ower
.
Normalized frequency.
MT
PR
PARAmax
2
Arms2
------------=
35
Part A: Overview: Digital-to-Analog Converter Design
a si-
e
DSLome
rms)er is
as an
verterand
itableations
ver-
where is the normalized peak power and is the signal r.m.s. value. For
nusoidal the since and where is the amplitud
of the sinusoidal.
3.4 DAC Comparison
The general consideration for telecommunication applications such as ADSL and Vis that the effective resolution of DACs should be around 12-14 bits, [27, 83]. For sapplications the effective number of bits does not have to be that high.
In Fig. 3-7 a sketched overview over DAC types found in the literature (in general te[2-79, 84, 85] vs. resolution and bandwidth. Since the resolution of the convertstrongly dependent on the bandwidth (and vice versa), the overview should be seenapproximation.
Figure 3-7: DAC types vs. speed and resolution.
Basically, it can be seen that Nyquist-rate converters are the most suitable constructures for high-speed telecommunication applications. For audio applicationslower-speed telecommunication applications the oversampling converter is a sustructure. The current-mode Nyquist-rate versions are suitable for high-speed applic[2, 3, 9, 13, 30-32, 39, 44, 49, 53, 61, 64-66, 68, 70] and voltage-mode oversampledsions for lower-speed applications [40, 46, 51, 59, 62, 79].
Amax2 Arms
PAR 2= Amax A2= Arms2 A2 2⁄= A
Oversampling DACsResolution
Bandwidth
Nyquist-Rate DACs
Audio
Current-Mode
Voltage-Mode
Video Telecommunication
20
200M16k 5M
12
(bits)
[Hz]
36
angency
ght-re also
d
io asoidal
B Part B:Nyquist-RateDigital-to-AnalogConverters forVDSL Applications
1 Introduction
The Nyquist-rate digital-to-analog converter is defined to have its signal frequency rfrom zero (dc) up to the Nyquist frequency, , with as the update freque
of the DAC [37, 56]. In Fig. 1-1 the amplitude spectrum is shown where the sinc weiing from sample-and-hold elements has not been considered. Images of the signal afound in the spectrum.
Figure 1-1: Amplitude spectrum within the Nyquist frequency range. The signal’s images are situateabove the Nyquist frequency. The quantization noise is equal over all frequencies.
The quantization noise within the Nyquist band determines the signal-to-noise ratdiscussed in the previous part of the thesis. With a normalized full-scale input sinus
f N f s 2⁄= f s
|X(f)|
ffs /2 fs
Quantization
Image
Noise
37
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
at a
wer
hasency
move
ide-high
er,rt con-mplens as
pectsant todif-d to
s andand
veral
(single-side peak at 0dB) the average quantization noise power, , is found
level of
(1-1)
From (1-1) we have the intuitive conclusion, that the higher bandwidth, , the lo
noise floor. The output from the converter when using sample-and-hold circuits alsoimages and attenuation of the signal spectrum due to the sinc weighting in the frequdomain as sketched in Fig. 1-2. Lowpass filters and anti-sinc filters can be used to reimages and reduce the distortion.
Figure 1-2: The output amplitude spectrum with images and the effect of sinc weighting.
In general the Nyquist-rate converter is required for wideband applications, e.g., wband radio, VDSL, etc., where oversampling techniques are impossible due to theclocking frequencies needed.
A brief description of different DAC structures is given in Chapter 2. The R-2R laddcharge-redistribution, and current-steering structures are discussed. This thesis’ pacentrates on the CMOS binary weighted current-steering DAC which provides a siand straight-forward structure suitable for high-speed telecommunication applicatiomentioned in Sec. 3.4 inPart A: Overview: Digital-to-Analog Converter Design.
In Chapter 3 we model the performance of a current-steering DAC. Important asconcerning output impedance, matching, and noise are discussed. It is very importhave a knowledge about the overall behavior of the circuit and how irregularities andferent circuit variations will affect the result. Therefore, the modeling results are useiterate the design of the converter using behavioral-level descriptions.
The design of a DAC chipset is presented in Chapter 4. Behavioral-level descriptionsimulations concerning the design is given, as well as results from circuit simulationsmeasurements.
From the design of the chipset as well as the modeling it can be concluded that sedifferent improvements may be done. Some of these are discussed in Chapter 5.
Qavg pwr,
Qavg. pwr 6.02N 1.76 10 f Nlog+ +[ ]–≈
f N
fs/2 fs 2fs
|X(ω)|
1
f
Images1st Nyquistband
38
2. Nyquist-Rate DAC Structures
moston thembere input
truc-hisarea
d and
harge-
torede Fig.
. The
g the
2 Nyquist-Rate DAC Structures
Various kinds of converter structures are used for different applications. They areoften trade-offs between area, power consumption, accuracy, and speed. We focusbinary weighted converter structure implemented in a CMOS process. This uses a nuof binary scaled elements that together generates the output value, dependent on thdigital code to the converter.
Most DAC solutions use a straight-forward approach. With some kind of feedback sture, e.g., calibration, trimming, etc., the effective resolution may be improved. Tmight however decrease the bandwidth of the converter, as well as increasing chipand design complexity. These aspects are further discussed in Chapter 5.
There is a limited number of DAC structures that are good candidates for high-speehigh-performance applications, see Sec. 3.4 inPart A: Overview: Digital-to-Analog Con-verter Design. The advantages and disadvantages of wideband converter types as credistribution, current-steering, and R-2R ladder, are discussed in this chapter.
2.1 Charge-Redistribution DACs
The charge redistribution DAC is a switched capacitor version, where the charge son a number of binary scaled capacitors is used to perform the conversion [37]. Se2-1 for an example of a 4-bit converter.
Figure 2-1: A 4-bit charge-redistribution DAC.
This switched capacitor version uses two non-overlapping clock phases, and
operation is determined by the discrete-time events controlled by the clocks. Durin
8C 4C 2C C
16C
C0
φ2
φ1
φ2
φ1
φ1
φ2
Vref
v0(t)
x3 x2 x1 x0
φ1 φ2
39
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
d no
The
rged
put
ose
pera-
ge.
ary
apac-
ver,hingthethe
cess,s and
2-2here
rent
rrent
par-
initializing phase; time point and clock phase , all inputs are shorted an
charge is found on the binary weighted capacitors. is the update time.
capacitor is charged with and is
charged with .
During clock phase and at time point , the binary weighted capacitors are cha
with the reference voltage, . The switches controlled by the digital in
, determine what capacitors to charge, i.e., the total charge on th
capacitors is given by
Since the capacitor is discharged and is connected to the input of the o
tional amplifier at this point, they will provide the binary weighted capacitors with charCharge conservation at the virtual ground state that
After one clock period, during clock phase and at time point , the bin
weighted capacitances are discharged and their charge is redistributed to the citor. This implies that
forcing the output voltage to be given by
which gives the wanted transfer function at the output.
This structure is insensitive to offset voltage and finite gain of the amplifier. Howeit is clear that the limitations of the converter is given by a number of factors: the matcof the capacitors, the switch on-resistance, the finite bandwidth of the amplifier limitperformance of the overall DAC. Noise is basically given by the noise and
influence of the noise is decreased with the switching used in Fig. 2-1.
2.2 Current-Steering DACs
The use of switched current sources is a straight forward approach in a CMOS prosince the construction of linear resistors and capacitors may be limited by the procestherefore, the current-steering DAC is a natural choice.
The general structure of a binary weighted current-steering DAC is shown in Fig.and discussed in [56, 66]. The switches are controlled by the input bits, , w
, and is the number of bits. is the LSB and the corresponding cur
source has the dc value . The source controlled by bit , i.e., the -th LSB cu
source, is formed by connecting LSB current sources (unit current sources) in
nT T 2⁄– φ2
T 1 f s⁄=
16C q16 nT T 2⁄–( ) 16C v0 nT T 2⁄–( )⋅= C0
q0 nT T 2⁄–( ) C0 v0 nT T 2⁄–( )⋅=
φ1 nT
Vref
X x3 x2 x1 x0, , ,( )=
qtot nT( ) X nT( ) C Vref⋅ ⋅=
16C C0
X nT( ) C Vref⋅ ⋅ C0 v0 nT( )⋅+ 16C v0 nT T 2⁄–( )⋅ C0 v0 nT T 2⁄–( )⋅+=
φ2 nT T 2⁄+
16C
q16 nT T 2⁄+( ) 16C v0 nT T 2⁄+( )⋅ X nT( ) C Vref⋅ ⋅= =
v0 nT T 2⁄+( ) X nT( )Vref
16----------⋅=
kT C⁄1 f⁄
xi
i 1 2 … N, , ,= N x0
I LSB xi i
2i 1–
40
2. Nyquist-Rate DAC Structures
.
elowmis-ther-ring ise the
fun-
mple-ed inuallyere
e of
ted
, the
oved.tancesLSBgh all
allel, hence the MSB current source therefore has the dc value
Figure 2-2: An N-bit current-steering DAC.
The output current, , of the DAC shown in Fig. 2-2 is given by
(2-1)
where is the digital input given by
(2-2)
The current-steering DAC has the advantages of being quite small for resolutions b10 bits and it may be very fast. The major disadvantage is its sensitivity to devicematch and glitching. To increase monotonicity and reduce the influence of glitches, amometer code can be used. This is further discussed in Sec. 5.2.1. The current-steesuitable for high-speed wideband applications when special care is taken to improvmatching of the converter.
Results from modeling of the current-steering DAC is given in Chapter 3 where thedamental impacts of matching error, output impedance, noise, etc., are discussed.
2.3 R-2R Ladder DACs
The R-2R ladder structure provides a structure suitable for processes capable of imenting linear resistances. The general structure of the R-2R ladder DAC is sketchFig. 2-3 and further discussed in [8, 25, 37, 56, 65]. The current sources are all eqlarge, , and the switches are controlled by the digital input, , wh
is the number of bits and is the MSB.
If the input is zero, and hence all , it is seen that the output resistanc
the ladder is . When terminating the output with to the voltage, the wan
transfer function is achieved and by determining the contribution from each sourceoperation of the converter is easily understood.
Due to the fact that the current sources are equally large, the matching can be imprThe resistors are however often non-linear and contains signal-dependent capaciyielding distortion. The ladder also introduces a time-delay between the MSB andwhich generates glitches and distortion. There is the same amount of current throu
I MSB 2N 1– I LSB⋅=
IMSB ILSB
xN-1 x0xN-2
Iout
Vref
I out
I out X( ) I LSB x0⋅ 2I LSB x1⋅ … 2N 1– I LSB xN 1–⋅+ + + I LSB X⋅= =
X
X x1 2 x2⋅ … 2N 1– xN 1–⋅+ + + 2k xk⋅k 0=
N 1–
∑= =
I 0 X xN 1– … x0, ,( )=
N xN 1–
X 0= xi 0=
2R 2R Vref
41
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
ltageages,
nent, and
urces
.3 areture.
intothe
vertedFur-
switches which makes the design of the switches simpler, however, the internal vonodes are swinging and therefore the current sources will have varying terminal volthence a poorer matching, further introducing distortion.
Figure 2-3: An N-bit R-2R ladder DAC.
One of the major advantages is that we only have a few number of different compotypes to implement, i.e., two resistor sizes, and , one current source size,
one type of current switch. This allows a more regular layout and since the current soall have the same size, trimming or calibration can be applied [8, .
2.4 Comparison
The properties of the different DAC structures described in Sec. 2.1 through Sec. 2approximately given in Table 2-1. The values are found from reported results in literaand data sheets from vendors [2, 3, 9, 13, 30-32, 39, 44, 49, 53, 61, 64-66, 68, 70]
Table 2-1: Comparison of performance for DAC structures for telecommunication applications.
One way to improve the overall performance is to combine different DAC structuresa hybrid DAC. Naturally a large number of hybrid DACs can be found. For exampleLSBs can be converted using a current-steering structure and the MSBs are conwith an R-2R structure, since the impact of matching errors are larger on the MSBs.ther improvements are discussed in Chapter 5.
IssueCurrent-Steering
Charge-Redistribution
R-2RLadder
Speed > 30MHz < 30MHz > 30MHz
Area < 12 bits < 12 bits > 10 bits
Accuracy < 12 bits > 10 bits > 8 bits
Noise
x0 x1 xN-1
R R R
R 2R 2R
I0 I0 I0
Iout
Vref
Vss
R 2R I0
8kT3
----------gmkTC------ 4kT
1R---
23---gm+
42
3. DAC Performance Modeling
ies.rfor-n the
se Cstem
tionsnt ord in
r inear-
andted
and
ener-issues) [75-
3 DAC Performance Modeling
It is important to know in advance how the converter will react on circuit non-idealitBehavior models of the DAC are used to find fundamental limits and possible pemance of the converter can be approximated. This gives indications on how to desigcircuit, how to identify bottle-necks, how to find possible improvements, etc.
It is also attractive to avoid time-consuming circuit-level simulations and instead uor MatLab models to do higher-level simulations of the whole converter and the syin which it is used [48, 68, 74, 80].
In Part A: Overview: Digital-to-Analog Converter Designthe different performancemeasures are given. Most characterization of DACs for telecommunication applicais achieved by using the frequency domain information [28, 29] of the measuremesimulation results, i.e., SFDR, THD, SNDR, MTPR, etc. This is further emphasizethis chapter.
Fundamental limits on the performance are set by three properties:
• Output impedance. The influence of a finite output impedance of the DAC, ogeneral; a finite output over termination impedance ratio strongly effects the linity of the converter.
• Matching errors. Since variations of the process force the oxide thicknessthreshold voltage, and , to vary over the die area, the binary weigh
sources become unbalanced which affects the linearity.
• Circuit noise. The fundamental limit on the performance is given by the SNRwe have to guarantee that the noise is below the quantization noise floor.
This thesis focuses on the Nyquist-rate binary weighted DAC, hence the sources gating the wanted output are binary weighted, as discussed in Chapter 2. The threementioned above are investigated for the current-steering converter type (Sec. 2.278]. In Fig. 3-1 we briefly sketch the main idea of this modeling.
Figure 3-1: Illustration of conflicts when choosing design parameters in a current-steering DAC.
tox VT
Iout
W/L
Rout
43
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
tput
gate
has toutputand
rs inindvels.
t
rs areepen-ands theand
andputtc.
num-hout
Linearity is affected by the output impedance , the noise is affected by the ou
current, , and matching is practically determined by the transistor size or
area . There is however a relation between the three properties and a trade-offbe done to find a solution that is meeting the specifications. When increasing the ocurrent with the ambition to improve the SNR, the output impedance is decreasingthereby the non-linearity increase, etc.
3.1 Influence of Amplitude Level Uncertainties
In the previous part of the thesis we focused on the DNL and INL to describe errothe conversion levels of the DAC’s transfer function, Fig. 3-2. It is also important to fout how the frequency domain measures are dependent on the errors in transfer le
Figure 3-2: Wanted transfer characteristics (dashed line) and with example of errors in differenconversion levels caused by the actual transfer characteristics (solid line).
If one assumes that the level errors of the transfer function caused by matching errofrequency-independent (which is not the case) the total error at the output is signal-ddent as well. This implies the non-linearity of the transfer function. Mainly, the SFDRthe SNR are used to characterize the converter. In principle, the SFDR determineTHD, SNDR, and MTPR if the converter is not too non-ideal, i.e., not too much noisenot too non-linear, compare with the formulae given inPart A: Overview: Digital-to-Ana-log Converter Design.
The SFDR can be deduced from DNL and INL values if the input signal is known,especially how the input signal is sweeping over all transfer function levels. If the insignal is not full-scale, all DNL values will not affect the linearity of the output signal, e
Basically, current sources used in a current-steering DAC is constructed by using aber of unit current sources (binary weighted) in parallel. This property is used througthe following sections.
Rout
I out W L⁄
WL
000 001 010 011 100 101 110 111
7Aref
6Aref
5Aref
4Aref
3Aref
2Aref
Aref
Output Level
CodeX
Errors or deviations
Actual transfer function
Wanted transfer functionAout
44
3. DAC Performance Modeling
ce ofoutputes areurce,
entsncenon-
out-
.
be arfor-t on theUsing
e
ts theigh-
e out-
g the
the
3.2 Influence of Output Impedance Variations
Using the current-steering DAC (Sec. 2.2), it is easily seen that the output impedanthe converter is signal-dependent, since any non-ideal current source has a finiteimpedance. Dependent on what code is applied, different numbers of current sourcconnected to the output. The whole DAC can briefly be modeled as a current soshown in Fig. 3-3, where the output is terminated with a load resistance .
Figure 3-3: Current source,IS(X), with finite output resistance,RS(X). The termination,RL, is signal-independent.
We only show the impact of output resistance, since the influence of capacitive elemstrongly affects the complexity of the modeling (Sec. 3.5). The finite output resistareduces the current delivered to the load. The current delivered to the load from aideal current source as well as the supply voltage is given by
(3-1)
where is the nominal current value in the current source given by (2-1), is the
put resistance of the current source, and is the load (or termination) resistance
From (3-1) it is seen, that if the output resistance were constant, there would onlyloss of gain and a dc current in the output signal, which would not degrade the pemance. However, as was discussed earlier, the total output resistance is dependennumber of sources connected to the output. This dependency give rise to distortion.a notation describing the code dependency, (3-1) can be rewritten as
(3-2)
where indicates the DAC’s digital input given by (2-2) and is th
code-dependent output conductance of the sources. It will be shown that this affecsecond harmonic strongly for reasonable high ratios of , for lower ratios also h
er order harmonics will be large in the output signal spectrum.
The termination resistance, , is assumed to be fixed and signal-independent. Th
put resistance, , and the output conductance, , are determined by studyin
DAC’s structure shown in Fig. 2-2. The output conductance, , is related to
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
. Theand
.
bits.
with
tion
litude,
sion
on is
term
number of parallel current sources that are currently connected to the output nodeoutput conductance associated with the LSB current source is assumed to be
therefore the output conductance of the -th LSB must be given by
The total output conductance, , of the converter is given by
(3-3)
where is the input code (offset binary code) given by (2-2), and is the number ofCombining (2-1), (3-2) and (3-3), we have
(3-4)
Assume that within the Nyquist band, the input signal, , is a full-scale sinusoidalan offset and can be written as
(3-5)
where is the deviation from an ideal sinusoidal due to truncation, i.e., quantiza
noise, is the normalized angular frequency, is a sequence index, and the amp
, is given by
(3-6)
since the input is an offset binary code. Combining (3-5) with (3-4) gives the expresof the current through the load resistance due to the current division.
(3-7)
The deviation, , is modeled as white noise and is neglected in (3-7). The notatisimplified by letting
and (3-8)
which gives the expression of the current through the termination load as
(3-9)
Since , then , and therefore
(3-10)
Using the relation in (3-10), a converging Taylor series can be used to rewrite thefrom (3-9) as
1 GLSB RL A 1 Ωk( )sin+[ ]⋅ ⋅ ⋅+--------------------------------------------------------------------------------–⋅=
e
K1A--- 1
GLSB RL⋅-----------------------⋅ 2
2N 1–---------------
RLSB
RL------------⋅= = L
11 K+-------------=
I L X( ) A ILSB GLSB VDD⋅+( ) K 1 L K⋅1 L Ωk( )sin⋅+-------------------------------------–⋅ ⋅ ⋅=
K 0> L 1<
L Ωk( )sin 1<
46
3. DAC Performance Modeling
nd by
com-
c as
) is
urce,, is
(3-11)
When determining the SFDR, the gain and dc level of the signal are neglected, ausing trigonometric formulae (3-11) becomes
(3-12)
where denotes a function containing the dc component and higher frequency
ponents that do not affect the SFDR and .
The SFDR is found as the power ratio between the fundamental and the harmoni
(3-13)
By substituting back and from (3-8) in (3-13) this becomes
(3-14)
When the impedance ratio and the number of bits, , are large, (3-14
approximated by
(3-15)
Express (3-15) in dB, we have
(3-16)
This gives a hint on how to choose the output impedance of the LSB current sowhen knowing the specified number of bits, . The average output resistance,
given by
(3-17)
Using (3-17) in (3-16), it is seen that the SFDR also can be expressed as
11 L Ωk( )sin+--------------------------------- L– Ωk( )sin[ ]n
n 0≥∑= =
1 L Ωk( )sin– L Ωk( )sin[ ]2n
n 1≥∑ L Ωk( )sin[ ]2n 1+
n 1≥∑–+=
11 L Ωk( )sin+--------------------------------- f Ωk( ) Ωk( )sin L 1 L 2⁄( )2n 2n 1+
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
thattios,floor,
noise
asingdou-
mpli-overthe
idth.
y for
eseover
isof sto-
atch
(3-18)
In Fig. 3-4 we show the simulated and calculated SFDR for a 12-bit DAC. It is seenthe calculated values fit the simulated curve very well. For high resistance ra
, the spurious tones are hidden in or below the average quantization noise
equation (1-1), and therefore the simulated curve is saturated, since peaks fromcomponents are higher than the spurious tones.
Figure 3-4: SFDR vs. resistance ratio when varying the output resistance of a 12-bit DAC.
The important aspect is that if the number of bits should be increased without decrethe SFDR, the output impedance for the unit current source has to be approximatelybled for each extra bit of resolution (3-16).
The influence of the output impedance may be minimized by using an operational afier at the output which has a very low input impedance, hence the output impedancetermination impedance is very large [37, 56]. However, in wideband applicationsoperational amplifier will limit the performance, due to its limited speed and bandw
3.3 Influence of Current Source Mismatch
Due to process variations the oxide thickness, , and threshold voltage, , var
different current sources. Naturally, it is important to lay out so that the influence of thvariations is minimized. The matching error can be modeled as a stochastic variationthe die area [9, 55, 71], which was also briefly mentioned inPart A: Overview: Digital-to-Analog Converter Design. To find a suitable model, first deterministic mismatchinvestigated, Sec. 3.3.1, and then the results are generalized to examine the impactchastic mismatch, Sec. 3.3.2.
For a current-steering DAC, the first, rather naive, approach is to model the mism
SFDR 20RDC
2N 1–2
---------------⋅
RL-------------------------------log 6 N 2–( )– 20
RDC
RL----------log 6+≈ ≈
RLSB RL⁄
102
104
106
108
0
20
40
60
80
100
120
SFDR vs. RLSB
/RL for a 12−bit DAC.
SF
DR
[dB
]
RLSB
/ RL
Simulated Value
Calculated Value
tox VT
48
3. DAC Performance Modeling
. 3-5.cted to
inputurce,
s used
rrent,tput
ur-
ource
the
fic
andmore
ue
,
,uare
error as a current source in parallel with the nominal current source, as shown in FigAll error sources can be summed and modeled as one error current source connethe output of the DAC.
Figure 3-5: Current sources with modeled mismatch.
The number of error sources connected to the output is determined by the digitalcode, . Since the mismatch error is considered to be fixed for a certain current sothe total error is signal-dependent and distortion is introduced.
The matching issue is also further discussed in Sec. 4.1.1 where the current sourcein the implementation of the Nyquist-rate DAC are discussed.
3.3.1 Deterministic Variations of the Mismatch
When neglecting the influence of the resistance ratios, the ideal nominal output cu, is given by (2-1) and dependent on the input code given by (2-2). An ou
current, , is given by the sum of the nominal current, , and the error c
rent, , caused by a deterministic error in some of the current sources.
(3-19)
Suppose in the simplest case that there is an error current, , in the current s
controlled by the -th LSB, we have
(3-20)
where is the relative current error in the -th LSB, and is the bit controlling
-th LSB. If for all inputs, , (i. e., the size of the error current in a speci
bit position, , is signal-independent), the total output current is
(3-21)
The error will have the characteristics of a pulsed signal, with different durationamplitude, depending on the error position, . It is seen that mismatch errors in the
significant bits (when is large) will affect the signal stronger, due to the term. D
to pulsed error currents in the MSBs, harmonics of odd order occur. The amplitude,
of such an error pulse in the -th LSB position, as found in (3-21), is given by
(3-22)
If the nominal output current is a sinusoidal as given in (3-5) with periodthe mismatch current associated with the MSB current source will be a periodic sq
IMSB ILSB
∆IMSB ∆ILSB
X
I out X( ) X
I out X( ) I out X( )
∆I X( )
I out X( ) I out X( ) ∆I X( )+=
∆I i X( )
i
I out X( ) I out X( ) ∆I i X( )+ I out X( ) I LSB 2i 1– δi X( ) xi⋅ ⋅ ⋅+= =
δi X( ) i xi
i δi X( ) δi= X
i
I out X( ) I out X( ) I LSB 2i 1– δi xi⋅ ⋅ ⋅+=
i
i 2i 1–
Ae i,
i
Ae i, δi I LSB 2i 1–⋅ ⋅=
M 1 Ω⁄=
49
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
hed
rce,
third
gnal
the
3-27)for-
roxi-iven7)
SB
ch ated in
rel-ow
the
wave with period and have a duration of (as the MSB current source is switc
to the output). The Fourier transform of the error current in the -th LSB current sou
, is approximately given by
(3-23)
where is the signal period and is the angular frequency variable, in (3-23)
describes the Dirac function. The normalized power of the largest harmonic, , (
order), found by letting in (3-23), is given by
(3-24)
Suppose a sinusoidal input with an amplitude given by (3-6), the normalized sipower can be written as
(3-25)
where is the amplitude of the signal, and is the number of bits. The power ratiosinusoidal (3-25) and the largest harmonic (3-24) is the SFDR given by
(3-26)
The approximation is true when is large. Expressing this in dB, we have
(3-27)
Since for square wave signals the third harmonic dominates the other harmonics, (is valid for errors in more significant bits. For errors in the least significant bits, themula is approximately true.
It is seen that for an increase of number of bits, , the SFDR is improved by appmately 6 dB, if the increase of the number of bits does not affect the mismatch in the gbit position. For a one per cent error, , in the MSB of a 14-bit DAC, (3-2
gives dB. It can also be seen from (3-27) that if there is mismatch in the M
( ) the SFDR is not depending on the number of bits, since the largest mismatthe MSB does not decrease with the increase of number of bits. This is also verifisimulations.
Shown in Fig. 3-6 is the simulation result for a 14-bit DAC. It can be seen that if theative error current in the MSB current source is , the simulations sh
dB. For smaller deterministic mismatch errors in the least significant bits,
error can not be modeled as contribution to the distortions. In this case the spuriousare hidden in the noise floor as shown in Fig. 3-6.
Figure 3-6: Deterministic variations of mismatch over bit positions in a 14-bit DAC. SFDR is shownas a function of the mismatch error bit position and size. For small errors the spurioutones are hidden in the noise floor.
3.3.2 Stochastic Variations of the Mismatch
In reality mismatch due to process variations are more or less of a stochastic natureBy using the results from Sec. 3.3.1, we can model the impact of stochastic mismawell. The errors are modeled as error current sources in parallel with nominal cusources as shown in Fig. 3-5. The stochastic error, , in the LSB current sour
assumed to be a normal distribution with a mean value, , and s
dard deviation given by . In the -th LSB source, LSB curre
sources are connected in parallel. Suppose all mismatch errors in each LSB currentare uncorrelated. Then, the mismatch error in the -th LSB current source, , ha
mean value
(3-28)
and standard deviation given by (uncorrelated sources)
(3-29)
One of the main issues is actually to find out how the correlation between two esources affects the result. Since the current sources generally are laid out close tother, the matching errors can be highly correlated. The mean value of the error socan in any case be neglected since its influence only give rise to a linear gain or o
24
68
1012
14
0
0.5
1
1.5
2
40
50
60
70
80
90
100
110
SFDR vs mismatch & bit position
Mismatch (%)
SF
DR
[dB
c]
δLSB
µLSB E δLSB 0= =
σLSB2 E δLSB
2 = i 2i 1–
i δi
µi E δkk 1=
2i 1–
∑
E δk k 1=
2i 1–
∑ 0= = =
σi2 E δi
k 1=
2i 1–
∑ 2
E δi2
k 1=
2i 1–
∑
2i 1– σLSB2⋅= = =
51
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
ourceing theatesana-
-th
hirdn in
, the
e dc
)
error.
The total error current due to the stochastic mismatch can be summed into one sand the expectation value of the total generated error power can be expressed by usequations from the previous section. If it is assumed that the third harmonic dominother harmonics, with (3-24) and (3-25), the expectation value of the SFDR can be
lyzed. Due to the summation of stochastic sources, the amplitude, , in the
LSB, for the third harmonic as was seen in (3-23) is
(3-30)
The normalized signal power is given by (3-25) and the normalized power of the tharmonic, , is derived, by summing the error current amplitudes as give
(3-30)
(3-31)
Noting that since and that the error sources are uncorrelated
expression in (3-31) is rewritten as
(3-32)
where the digital input signal, , was defined in (2-2). The mean value, , is thvalue of the sinusoidal and given by
(3-33)
Combining (3-32) and (3-33), we have
(3-34)
The expectation value of the SFDR can be derived by combining (3-25) and (3-34
2i 1– Ai i
Ai2
3π------ δLSB I LSB 2i 1–⋅ ⋅⋅=
E Pk 2= tot,
E Pk 2= tot, E xi Ai⋅i 1=
N
∑
E xi 2δLSB I LSB 2i 1–⋅ ⋅
3π----------------------------------------------⋅
i 1=
N
∑2
= = =
I LSB
3π 2⁄-------------
2
E xi 2i 1– δLSB⋅ ⋅i 1=
N
∑2
⋅=
xi xi2= xi 0 1, ∈
E Pk 2= tot, I LSB
3π 2⁄-------------
2
E δLSB2 xi
2 2i 1–⋅i 1=
N
∑⋅
= =
I LSB
3π 2⁄-------------
2
E δLSB2 x1 2x2 … 2N 1– xN⋅+ + +( )⋅ = =
σLSB2
I LSB
3π 2⁄-------------
2
E X ⋅ ⋅=
X E X
E X 2N 1–2
---------------=
E Pk 2= tot, I LSB
3π 2⁄-------------
2
σLSB2 2N 1–
2---------------⋅ ⋅=
52
3. DAC Performance Modeling
im-aluesom-
(3-35)
In dB, this becomes
(3-36)
Figure 3-7: Histograms showing the variation of the SFDR vs. mismatch for a 12-bit DAC. a)σLSB=1/128 b)σLSB = 1/512 c)σLSB = 1/1024 d)σLSB = 1/2056
Histograms, shown in Fig. 3-7, using 1000 FFTs of the output of a 12-bit DAC are sulated to find the expectation value of the SFDR. Each FFT uses 57643 points. The vare given for different mismatch error standard deviations (which are rather small cpared to a real process [4, 9]). The different SFDR expectation values found are
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
dard0%own
simu-lowr andalso
.s
irescur-
37].an thees, thes an
-5 or
the
It is seen that the SFDR is decreased with approximately 6dB for every time the standeviation is doubled. In the figures the yield of the circuits is shown as well. The 9yield implies that 90 per cent of the chips will have a better SFDR than the value shin the figures.
In Fig. 3-8 we see the comparison between the calculated values from (3-36) andlated values from histograms as shown in Fig. 3-7. The curves fit well together. Forvalues of error standard deviation the spurious tones are hidden in the noise flootherefore the curve is saturated. The simulation results from a 20-bit DAC arereported in [76].
Figure 3-8: Summary of the histograms for a 12-bit DAC compared with the calculated valuesExpectation value of SFDR vs. standard deviation for the mismatch error. For low errorthe simulated spurious tones are hidden in the noise floor.
To the matching error we can also include influence of voltage drops over internal was well as the influence of non-linear switches, etc. This also affects the value of therent fed to the output, hence can be modeled as matching errors.
3.4 Influence of Circuit Noise
The fundamental limit of the performance is the noise found in the output signal [The resolution of the converter is guaranteed as long as the circuit noise is less thaverage quantization noise. Using different processes and layout styles, or techniqunoise may influence the signals in different ways. However, we model the noise aerror current source in parallel with all unit current sources as described in Fig. 3more specific as in Fig. 3-9.
For an ideal -bit DAC, the SNR (determined by the quantization noise) overNyquist band is (in dB)
(3-37)
assuming uniform quantization steps and a full-scale sinusoidal input.
10−4
10−3
10−2
10−1
100
55
60
65
70
75
80
85
90
95
100
105
110Simulated and calculated mean value of SFDR.
Deviation in the LSB current
SF
DR
[dB
]
Calculated Value
Simulated Value
N
SNR 6.02 N⋅ 1.76+≈
54
3. DAC Performance Modeling
utedue is
he
ibed
corre-
re in
value
f the
dom-
Figure 3-9: Nominal unit current source,ILSB, with included noise source,ilsb.
With each unit current source (equal to the LSB current source) a normal distribnoise source, , is associated. Within a certain bandwidth, , the mean val
and its variance is given by . The expectation value of t
normalized total output noise power, , within the bandwidth, , can be descr
by the sum of all noise current sources. If we assume that the noise sources are unlated, the normalized total noise power can be described by
(3-38)
where is the mean value of the digital input, hence the number of sources that a
mean connected to the output. Assuming that is a full-scale sinusoidal, the meanis given by
(3-39)
where is the number of bits. Combining (3-38) and (3-39) gives the expression o
total normalized noise power, , as
(3-40)
The normalized signal power for the full-scale sinusoidal is given by
(3-41)
Combining (3-40) and (3-41), the SNR determined by the noise is expressed as
(3-42)
The approximation is valid when the number of bits, , is large. The SNR in dB is
dB (3-43)
For wideband CMOS DACs it is the thermal noise from the channel resistance that
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
e cur-
mall-
bothat the
en by
is
ed by
g thaturrent
wer,
SNR.
cur-from
ighurves
unit
inates other noise sources [37]. The power spectral density (PSD) of a thermal noisrent source as modeled in Fig. 3-9, is described by
(3-44)
where is the Boltzmann’s constant, is the absolute temperature, and is the s
signal transconductance of the current source transistor. Equation (3-44) holds forsingle transistor current sources and cascoded current sources if the impedancesource of the cascode transistors is very low. The unit current is approximately giv
(3-45)
where is the transconductance parameter, is the source-gate voltage, and
the threshold voltage. This also gives the linearized transconductance, , determin
(3-46)
Using the noise and transconductance definitions in (3-44) and (3-46) and assuminthe thermal noise in the transistors dominates, the noise spectral density in the unit csource is
(3-47)
If we assume a certain noise bandwidth of , the normalized total output noise po
, from the unit current source is
(3-48)
All the thermal noise associated with the switched current sources degrades theSubstituting the values from (3-48) into (3-43) gives the approximate expression
(3-49)
In Fig. 3-10 the simulated and calculated SNR for a 12-bit and a 14-bit DAC vs. therent through the unit current source, , are shown. In the simulations process data
Ericsson’s 0.6µm CMOS process were used. It can be seen from Fig. 3-10 that for hunit currents, the thermal noise is lower than the quantization noise. The simulated cfit well to the calculated values.
The formulae in this section give a guidance on how to choose the current of the(LSB) current source.
in2
∆f------ 8
3---kTgm≈
k T gm
I LSBβ2--- vSG vT–( )2=
β VSG VT
gm
gm 2β I LSB⋅≈
in2 ∆f⁄ 8
3---kT 2β I LSB⋅≈
BW
ilsb2
i lsb2 8
3---kT BW 2β I LSB⋅⋅ ⋅=
SNR 15 I LSBlog 3N 5WL-----
log– 10 BWlog– 1083---kT 2K'
log–+≈
I LSB
56
3. DAC Performance Modeling
erateat thedis-
one-w the
utitched
, the
out-first
e of
Figure 3-10: Simulated and calculated SNR vs. theILSB current for a) 12-bit and b) 14-bit DAC.
3.5 Influence of Timing Uncertainties
Timing uncertainties, skews between current switches of different positions gentemporary codes. These temporary codes may create a large current spike, glitch,output. If the current spike energy is input signal-dependent they may also introducetortion, but most often they appear as noise [28, 56]. It is very hard to model what errous codes that may temporarily arise on the output. Therefore, we briefly discuss hoconverter reacts on variations of settling time, as was discussed in Sec. 3.2.3 inPart A:Overview: Digital-to-Analog Converter Design. The output resistance and the outpcapacitance are signal-dependent, since the number of current sources that are swto the output are dependent on the input code which gives non-linear slewing.
Figure 3-11: Generalized view of the converter with output capacitance and resistance.
When the input switches from one code to a consecutive code
output will ideally be given by a step function. However, due to reactive parts of theput and load impedance, the signal will settle towards an end value. In Fig. 3-11 theorder model of the output of the DAC is shown. In this brief discussion, the influenca load capacitance is neglected.
The output current, , through the termination resistance, , is described by
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
. The
sig-
time
val-
alsoand
ax-
y be
tructmpli-
which with the initial conditions ( and ) gives
(3-51)
where
(3-52)
as from (3-2) with the assumption that the start value also has settled to its final valuetime constant is given by
(3-53)
where is the capacitor associated with the LSB current source. Obviously is
nal-dependent, and therefore the slewing is non-linear. The maximum value of the
constant is found when is maximal, hence when . For the maximum
ues at the output the slewing is more crucial, yielding a lower bandwidth. This isfound in measurements, since non-full-scale signals can give rise to a better SNRSFDR than a full-scale input signal. The result in (3-53) may be used to find out the mimum possible sampling frequency as well.
If the converter is well designed with respect to the output impedance, (3-53) maapproximated by
(3-54)
The knowledge about the time-constant gives the designer information how to consthe current sources in order to reach the specified update frequency. The error in atude level is determined by the time the signal is allowed to settle.
In this chapter we discuss the issues behind the design and implementation of a Cdigital-to-analog converter chipset for VDSL and wideband radio applications.chipset contains three generations of converters and the ad hoc specification is giTable 4-1.
Table 4-1: Specifications on the CMOS DAC chipset for wideband radio applications.
The first generation focuses on a low-voltage converter and is designed by N. TanThe second generation focuses on a wideband version and the third generation focuimproved matching for the wideband applications [68]. The design of the second getion converters is presented in this chapter and the target was to design a 14-bit conwith low power consumption, high-resolution, and high bandwidth. For the secondthird generation, also the knowledge from the modeling work as described in Chaphas been applied. We have however found out that matching was not considered prfor the second generation and this will also have a large impact on the achieved r(Sec. 4.3), especially the linearity of the converter.
The first and second generation converters have been measured and the third genis still to be measured. The structure used for all converters in the chipset is the custeering DAC as discussed in Sec. 2.2.
4.1 Practical Design Considerations
As was mentioned above, the knowledge about the fundamental limits given by beioral-level modeling, was used to design the DACs. Knowing how the output curaffects transistor sizes, output impedance, and noise, lets us choose a proper valu
The overall structure of the converters is given in Fig. 4-1. Naturally, we have threeferent parts of the converter:
Supply Voltage 1.5 - 5 V
Bandwidth 20 MHz
Update Frequency 50 MSps
Peak Output Current < 20mA
Power Dissipation < 20mW
Nominal Resolution 10 - 14 bits
Dynamic Resolution 8 - 12 bits
59
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
an
r and
fer-to
nce
kewd to
ted intors,o theoutputAC,
le cas--2. The
• The digital part consisting of clock, flip-flops stabilizing the digital input, andMSB segmentation part.
• The analog part consisting of an array of unit current sources.
• The mixed analog/digital parts consisting of current switches.
These issues are further discussed in the following subsections.
Figure 4-1: Overall structure of the converters in the chipset.
For the -th LSB, unit current sources from the array are connected togethe
their output is fed to the current switch controlled by the -th bit. The output is a difential current output and if the corresponding bit is a “1” or “0”, the current is routedthe positive, , or the negative output, . Differential signals will decrease the influe
of even harmonics (due to non-linearity) in the output.
The segmentation of the MSBs introduces a delay for the MSBs and to avoid sbetween the bits, a digital delay line is used for the LSBs. A clock tree is implementeget proper clock delay to all flip-flops controlling the current switches.
4.1.1 Unit Current Sources
The current source used in especially current-steering converters can be construcdifferent ways. A simple structure using a different number of PMOS cascode transisFig. 4-2, is used in the current source array. Also note that the bulk is connected tsame potential for all transistors. The use of cascode transistors increases theimpedance of the current source which affects the performance and linearity of the Das discussed in Sec. 3.2.
Two versions of the second generation chipset were designed. One containing singcode current sources and one containing double cascode current sources, see Fig. 4output resistances of the sources are given by and , respectively, as [78]
Flip-Flops Flip-Flops
Switches Switches
Delay MSBSegm.
M
N-M
Clock Tree Distribution
Dummy Sources
UnitCurrentSources
I+I -
bits
bits
Mixed Digital/Analog Parts
i 2i 1–
i
I + I -
RI RII
60
4. A CMOS DAC Chipset for VDSL Applications
(ap-
nsis-
(Sec.
r thecapac-ttling
by
c-
unitourceow-ter 5.
and (4-1)
where is the output current of the source, is the channel length modulation
proximately equal for all the transistors), is the transconductance parameter of tra
tor , and is a parameter given by the bulk-source connection of the transistor1.4.1 inPart A: Overview: Digital-to-Analog Converter Design).
Figure 4-2: Schematic view of PMOS current sources with a) single and b) double cascode.
According to (4-1), the output impedance of the double cascode is higher than fosingle cascode. However, there is one additional internal node, which increases theitive part of the output impedance and hence introducing extra poles and longer setime and therefore this constellation may degrade the performance.
Figure 4-3: Layout view of PMOS current sources with a) single and b) double cascode.
The transistors all have the same width, , and the lengths are given
, and , for the transistors M1, M2, and M3, respe
tively.
In the 14-bit DAC the binary weighted current sources were constructed by usingcurrent sources from the array by starting in one corner and use one unit current sfor the LSB, the next two attaching unit sources for the second LSB, etc. This will hever not give good matching properties and improvements will be discussed in Chap
RI 1 η+( )2β2
λ2 I src3 2/⋅
-------------------⋅≈ RII RI
1 η+( ) 2β3
λ I src⋅-------------------------------⋅≈
I src λ
βi
i η
M1M1
M2M2
M3IsrcIsrc
VDD
VDD
a) b)
a) b)
Outputs
Gates M1
M2
M3
M1
M2
W 2µm=
L1 8µm= L2 2µm= L3 1.2µm=
61
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
Fig.ether,d over
weretions
e
nit
or
r size,c. By
prox-
A part of the second generation array containing the unit current sources is given in4-4a). In the figure the internal nodes of the current sources are connected togincreasing the output capacitance of the sources. The connections are route
the M1 transistors, which influences the matching of the source transistors [73]. Thischanged in the third generation DAC as shown in Fig. 4-4b). The internal connecwere also removed to reduce the capacitance.
Figure 4-4: Part of current source array for the a) second and b) third generation DAC with doublcascode current sources.
For a 14-bit DAC with the peak output current of 20mA, the output current for the ucurrent source is
(4-2)
Consider the approximate drain current in saturation region for the PMOS transist
(4-3)
There are several components that are affected by matching errors, i.e., transistothreshold voltage, supply voltage, oxide thickness, bias voltage, output voltage, etdifferentiating (4-3) the influence of the matching errors can be seen as
(4-4)
When assuming that the deviation of the source-gate voltage is very small, (4-4) apimately becomes
(4-5)
The and matching are given by the following terms from (4-5)
and , respectively (4-6)
VDD
VDD Connections
ConnectedInternalNodes
Output
M1
M2
M3
over M1 transistors
VDD Connectionsmoved away
UnconnectedInternalNodes
Output
from M1
a) b)
I unit20
3–×10214 1–
-------------------- 1.22µA≈=
iDβ2--- vSG vT–( )2⋅≈
∆iDiD
--------- ∆ββ
------- 2∆VSG ∆VT–
VSG VT–-------------------------------+=
∆iDiD
--------- ∆ββ
------- 2∆VT
VSG VT–( )----------------------------–≈
β VT
∆ββ
-------2∆VT
VSG VT–-----------------------
62
4. A CMOS DAC Chipset for VDSL Applications
are
kept
outf theserentay belly beThis
0dB,
e is
urrentimplyrimaryof 3-ately
ant-
mayeed-of thealsoini-
iffer-itchesobilitymoreof an
From studies in the literature [4, 9, 55, 71], we know that the and matching
uncorrelated and that their variance is inversely proportional to the transistor area,
Since low power consumption and saturated transistors are wanted, is
low and therefore the expression (4-6) may be large.
From a geometrical point of view the term in (4-4) are dependent on the laystyle. Large transistors and special layout styles are used to reduce the influence okinds of mismatch, i.e., common-centroid and interdigitized layout styles. In the cursource array the matching errors between two neighboring unit current sources mstrongly correlated and therefore the binary weighted current sources should actuaconstructed by using unit current sources from different positions in the array [9, 39].may however increase wire resistance and capacitance.
If the SFDR of the converter should be guaranteed to be higher than for example 8equation (3-16) states that
(4-7)
With a 50Ω termination the bound on the output impedance of the current sourcfound to be
(4-8)
which is hard to accomplish. The output impedance is also dependent on the bias ccontrolling the source-gate voltage of the current source (4-1). These voltages are sgenerated using a cascoded current mirror and the reference current through the pside of the mirror is determined by a terminating resistance (at an approximate size5kΩ). The cascoded current source has an (simulated) output impedance of approxim
(4-9)
corresponding to an SFDR of 70dB for the 14-bit version, which is sufficient for the wed applications.
4.1.2 Current Switches
Naturally, the switch is crucial in a switched system. The properties of the switchaffect the transfer function and overall performance of the circuit. For example, in fback loops we have to be extra careful with parasitic capacitances and on-resistanceswitch, otherwise unwanted ringing or unstable circuits can arise. The switch maylimit the bandwidth of the system, since it basically is an RC-circuit. CFT must be mmized since extra noise and distortion are introduced [71].
The current switches are the mixed analog/digital circuit parts. In the converters a dential switch has been used, as shown in Fig. 4-5. For larger currents through the sw(MSBs), larger switches are needed. NMOS transistors are used since the charge mis higher than for the PMOS transistors, hence higher speed. The larger switch, thetransistors are connected in parallel, as illustrated in Fig. 4-5b). The conductanceNMOS switch is given by
β VT
WL
VSG VT–
∆β β⁄
RLSB RL 106 N 2–( ) 80+
20----------------------------------
⋅≥
RLSB 2GΩ≈
Rout 600MΩ≈
63
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
e,
olt-
ost
low-the
con-equal
oxi-
ltage
duc-
ce
ding
con-rgerger
(4-10)
where is the transconductance parameter of the transistor, is the gate voltag
is the threshold voltage, and is the drain voltage. As given in Fig. 4-5, the drain v
age is and is given by the switching signals, , whose amplitude m
often is the supply voltage (except for charge-pump versions as in the first generationvoltage DACs [64]). It is wanted to keep the conductance of the switch proportional tocurrent.
Figure 4-5: Differential current switch as a) circuit model and b) transistor implementation.
In principle, to keep the voltage drop over all switches and current sources nearlystant, hence proper matching simpler, the voltage node must be constant and
for all bits. For the -th LSB we let this node voltage be denoted and it is appr
mately given by
(4-11)
where is the output current of one unit current source, is the average vo
at the output, is the conductance of the switches, and is the output con
tance of the unit current source. Equation (4-11) is rewritten as
(4-12)
In order to keep the equal for all bits, must be equal for all bits, hen
(4-13)
where is the conductance of a certain unit switch, i.e., the switch correspon
to the LSB. This implies that the sizes of the switches must be chosen so that theirductance is increasing exponentially with higher LSBs. This will however give very laswitches for the MSBs and too large clock load as well as too high CFT due to the laMiller capacitance. A trade off has to be done.
Gsw β VG VT– VD–( )⋅≈
β VG VT
VD
VD VC= VG φ φ,
VC
VDD
VC
VDD
I+ I- I+ I-
Ii = 2i-1 IunitIi = 2i-1 Iunit
φφφφ
VC
i VC i,
VC i,2i 1– I unit⋅ Gsw i, VDC⋅ 2i 1– Gunit VDD⋅ ⋅+ +
Gsw i, Gunit 2i 1–⋅+---------------------------------------------------------------------------------------------------------------≈
The layout of the current switch for the LSB is shown in Fig. 4-6, where one of etransistors in parallel is used as switch for each channel. To achieve equal capacitivfor all switches, the number of NMOS transistors (eight) in the switches is the samall bits, although some of the transistors are shorted for LSBs, as shown in Fig. 4shielding ground plane around all switches is also used.
Figure 4-6: Layout view of a differential current switch.
The inverse switch signal is generated with a simple CMOS inverter. A better glitchformance can be found with a more proper switching scheme. When both switcheturned off at the same time, the voltage at the output of the current source, ,
increase and the glitch will be larger when one of the switches is turned on again. Tfore, it should be guaranteed that both switches are not completely off at the same[9, 71], as sketched in Fig. 4-7.
Figure 4-7: Wanted switching scheme for the differential current switch.
The possible switching voltage swing, , of the switches is determined by the m
imum threshold voltage of the NMOS transistors, , and the maximum output v
age, , since
(4-14)
For a standard process with a maximum output current of 20mA terminated with aΩload, the minimum switching voltage is approximately V. For the low-vo
age ( V) versions of the DACs a charge-pump circuit is used to increase
voltage swing of the switching signals to overcome these problems.
Current Input
Positive Output
Negative Output
ShieldingGround
Positive switch input
Negative switch input
Short
VC i,
Switch
VDD
0
Positive Switch Signal
Negative Switch Signal
Ampl.
time
Vs max,
VT max,
Vout max,
Vs max, Vout max, Vgs switch,+ Vout max, VT max,+>=
Vs max, 1.7≈
VDD 1.5=
65
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
bitstrans-
als,
s, Fig.witch
s theve to
s.
utrther
rgeantagetially
twotchesrying. 4-d bits,nce
e foronly
d bitsn, as
4.1.3 Segmentation of the MSBs
To improve monotonicity and reduce glitching, segmentation of the most significanthas been used in the design of the converters. A binary code consisting of bits is
formed into a thermometer code of bits and the new switch controlling sign
, are derived from the old by
(4-15)
Using the thermometer code we can use a number of equally large current source4-8. The layout can be more regular and current source sizes as well as current ssizes are equally large for the segmented bits. The digital circuitry that transformbinary code into the thermometer code introduces delay and therefore the LSBs habe delayed correspondingly long time as shown in Fig. 4-1.
Figure 4-8: Example of segmentation of two binary weighted sources into three equally large source
The current that will flow through one switch will be smaller than for the MSB withosegmentation and therefore a smaller voltage drop over the switches which fureduces the distortion.
When segmenting the four MSBs in the 14-bit DAC, they will turn into 15 equally lacurrent sources, each one containing 1024 unit current sources. This is also a disadvsince the number of switches, the extra introduced logic, and wires are exponengrowing with number of bits to segment.
The glitches are roughly dependent on how many bits that are switching betweenconsecutive values at the input. By setting up a cost function, i.e., the power of the glior the number of switching bits, we can examine how the power of the glitches are vawith the number of segmented bits. Simulation results for a 14-bit DAC, shown in Fig9, state that about 4-5 segmented bits give a large improvement. For more segmentethe improvement is not that high, and more digital circuitry is also introduced, hehigher complexity and power consumption.
The segmentation guarantees monotonicity (for the MSBs) and improved DNL sincan increasing input additional current sources are connected to the output. Whensome of the bits are segmented, the INL is not improved. Matching of the segmentemay further be improved by using randomization, averaging techniques, or calibratiodescribed in Chapter 5.
k
2k 1–
φa φb φc, ,[ ] φ1 φ2,[ ]
φa φb φc, ,[ ] φ1 φ2∧ φ1 φ1 φ2∨, ,[ ]=
I 2I I I I
φ1 φ2 φa φb φc
66
4. A CMOS DAC Chipset for VDSL Applications
ay
ogic
e.
he
, Fig.
’s
Espe-
volt-array
rrent
henceresis-ur-
Figure 4-9: Power of glitches as a function of the number of segmented bits in a 14-bit DAC.
4.1.4 Digital Circuits
The digital circuits implemented in the DAC are constructed in a straight forward wand they consist of
• logic performing the segmentation of the MSBs, as given in Sec. 4.1.3. The lfunctions are realized with unclocked CMOS circuits.
• digital delay of the LSBs consisting of four cascaded inverters in the delay lin
• flip-flops to stabilize the digital input, realized with clocked CMOS circuits. Tinput is aligned with a set bit as well.
• tree-formed clock distribution with buffers.
4.2 Chip Implementation
The whole layout of the second and third generation DACs was done with Cadence
4-11. The core size is approximately 2x2 mm2 and the chips were fabricated in Ericsson0.6µm CMOS process.
To improve the supply distribution to the current sources aVDD plane is covering the
whole array. This also improves the matching as was discussed in Sec. 4.1.1.
cially for CMOS current sources, where the current is controlled by the gate-sourceage, special care has to be taken. A true supply voltage for all current sources of thehas to be guaranteed [38].
Consider the example shown in Fig. 4-10. The currents, , generated from cu
sources implemented with transistors, are determined by the source-gate voltage,dependent on the supply voltage and should all be equally large. If we assume a wiretance, there will be a voltage drop over the supply line, , and the c
rents, , become non-equal since the gate-source voltages are different.
1 2 3 4 5 6 7 8 9 1046
47
48
49
50
51
52
53
54Glitch Power vs. number of segmented bits.
Number of segmented bits
Pow
er [d
B]
VT
I V i( )
VDD V1 … VN< < <
I V i( )
67
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
here-r thewn of
vicestrong.done
nalogusedC:
ichepen-good
Figure 4-10: Model of the voltage supply line connected to a number of current sources.
In high-performance circuits the reference current errors have to be very small. Tfore, we cannot distribute the supply along a single wire due to the voltage drop. Fosupply distribution it is also necessary to analyze the peak current to avoid breakdothe wires.
Figure 4-11: Chip layout of the third generation DAC.
In mixed analog/digital design, disturbances from the digital to the analog part (orversa) spread along supply lines and the substrate. The substrate coupling may beIt is therefore necessary to do careful designs with proper shielding, which may bein different ways [33], i.e., guard rings, grounding, etc.
At board level it is also needed to shield and separate the signals [20]. The chip apins are separated from the digital as far as possible. As well as grounding pins arein-between. The pin configuration of the chip is equal to the Analog Devices’ 14-bit DAAD9764 (member of the TxDAC series) and hence a 28-bit SOIC socket [84].
A good clock distribution is needed to minimize the influence of clock skew, whstrongly affects the performance of the converter. The energy of the glitches are ddent on the skew between the different bits. Shown in Fig. 4-12 are two examples onclock distribution that reduce the skew between different subcircuits.
VDD
I(V1) I(V2) I(VN)
V1 V2 VN
IDD
R R R R
CurrentSource Array
Interconnection
DigitalCircuitry
Wires
Current Outputs
Digital Inputs
Analog Inputs
68
4. A CMOS DAC Chipset for VDSL Applications
tos wasalyzed
sure-ratoris also
sing anverterure-
DCurthersolu-ble to
als.
uit-l cir-ircuitl cir-sis-
Figure 4-12: Clock tree structures to improve buffering and equal clock delay to the circuit.
4.3 Simulation and Measurement Results
When simulating the converter it is important to know what to simulate and howextract information about the device from the measurement and simulation data. Astated in the previous part, there are static and dynamic properties. These can be anin the time and frequency domain.
We can use different structures when measuring the DAC, depending on the meament equipment. The simple structure in Fig. 4-13a) uses a digital input stimuli geneand the analog output is analyzed using spectrum analyzers and oscilloscopes. Thisthe structure that have been used during the measurements of the chipset DACs.
Since some of the information about the converter under test has to be found by ularge number of measurements it may in some cases be useful to use a reference coto compare the output results instead, Fig. 4-13b-d). To perform a DNL or INL meas
ment of a 14-bit DAC with levels that has to be recorded, a reference Aas in Fig. 4-13d) is used. The digital data is recorded and analyzed by a computer, freducing time and complexity [16]. The reference converters have to have higher retion than the DAC under test and their performance behavior must be known to be aanalyze the result from the converter under test.
Figure 4-13: General measurement setups. a) Input is generated with a stimuli generator b) Input signis generated using an ADC c) Output is compared with a reference DAC d) The output iconverted back to an analog signal and can be compared with the original input signal
At the behavioral-level, MatLab or similar tools are used (Chapter 3), on the circlevel, Spice, Spectre or similar [43] are used. Since DACs are mixed analog/digitacuits mixed-mode simulations are performed. It may be necessary to partition the cinto digital and analog parts to increase the speed of the simulation [43]. The digitacuits may be simulated with event driven simulators, using simplified models for tran
Sub
circ
uits
Sub
circ
uits
Master Master
214 16384=
DAC DACADCTest Ref Test
DACTest
DACRef
DACTest
ADCRef
a) b)
c) d)
69
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
nalogitch-ay besing
ents-tone
e sig-erwiseo thatand
cies are. For
of a
signalpec-R is
Inving
tors. However, at the interface between the digital parts and analog parts the asignals may be affected by digital switches, e.g., current switches driven by digital swing signals. In order to analyze glitches, supply noise, substrate coupling, etc., it mpreferred to perform the whole simulation with a more accurate analog simulator ucontinuous-time models.
We will also divide the measurements into single-, dual-, and multi-tone measuremsince all necessary information about the converter may not be extracted from singlemeasurements [5].
4.3.1 Test Signal Generation
For single-tone measurements an update frequency that is relatively prime with thnal frequency is used to guarantee that all codes are used (for a full-scale tone). Othall information about the converter’s performance is not extracted. This ensures alsno distortion term is folded back and interferes with other frequency componentscausing errors in the measurement. For dual-tone measurements the signal frequenrelatively prime, and they are relatively prime with respect to the sampling frequencymulti-tone measurements we apply a number of tones with frequencies at multiplesfundamental frequency.
The test pattern has to be long and accurate enough, since irregularities in the inputcan give rise to odd phenomena. If the signal is clipped, this will affect the output strum, see Fig. 4-14. With a signal clipped at 99.5% of its maximum value, the SFDapproximately only 70dB for a 14-bit DAC, Fig. 4-14b).
Figure 4-14: Output amplitude spectrum from a 14-bit DAC with a) an unclipped signal and b) clippedsignal at 99.5% of its maximum value.
A signal that is not completely periodic will also give rise to distortion in the output.Fig. 4-15b) the amplitude spectrum of the output signal from a 14-bit DAC when leaout only one single sample of the whole period containing 1917 points is shown.
0 0.1 0.2 0.3 0.4
−60
−40
−20
0
20
40
60
80
Output of unclipped sinus
Mag
nitu
de [d
B]
Normalized frequency0 0.1 0.2 0.3 0.4
−60
−40
−20
0
20
40
60
80
Spectrum of clipped sinus (0.5%)
Mag
nitu
de [d
B]
Normalized frequency
a) b)
70
4. A CMOS DAC Chipset for VDSL Applications
d
divi-
num-
res-
nd
out-ntedsignalidal, ae
Figure 4-15: Output amplitude spectrum of a sinusoidal with a) full-length test vector and b) truncatetest vector.
For the discrete multi-tone (DMT) we use a signal equal to orthogonal frequencysion multiplexing (OFDM) where the signal, , should be given by
(4-16)
where is the complex value given by the code word assigned to the -th carrier.
is the spacing between the carriers, is the starting frequency, and is the
ber of carriers.
When simulating the DMT signal, the first approach would be to simply use the expsion where no information has been applied to the terms from (4-16)
(4-17)
where is a fundamental angular frequency, is the amplitude of each carrier, a
is the number of tones. This will however give rise to large peaks in the time-domainput, Fig. 4-16a). It gives non-equal distribution of the amplitude levels which is unwa[14, 50, 69], since the input codes are not used equally often and hence the outputis hard to analyze. Therefore, by adding a random variable (phase) to each sinusobetter crest factor is achieved. This also simulates random information applied to th
terms. The new approach gives the signal
(4-18)
0 0.1 0.2 0.3 0.4
−100
−80
−60
−40
−20
0
20
40
60
80
Output with truncated vector
Mag
nitu
de [d
B]
Normalized frequency0 0.1 0.2 0.3 0.4
−100
−80
−60
−40
−20
0
20
40
60
80
Output with full−length vector
Mag
nitu
de [d
B]
Normalized frequency
a) b)
y t( )
y t( ) 1
N-------- cn ejn∆ωt⋅
n N0=
N N0– 1–
∑=
cn n ∆ω
N0 ∆ω⋅ N
cn
y t( ) A kω0t( )sink 1=
K
∑⋅=
ω0 A K
cn
y t( ) A kω0t φk+( )sink 1=
K
∑⋅=
71
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
als,
pli-
st
ut sig-
t thetionbeen
s been
pply-ut ishar-uced
ly iss areen
where is uniformly distributed. Applying a random phase on the sign
gives a multi-tone signal that is better suited for simulation, see Fig. 4-16b). The amtude spectrum of the both signals, (4-17) and (4-18), is the same.
Figure 4-16: The output signal for a DMT system with a) fixed phase and b) random phase. The crefactor is improved by changing to random phase. Note the different scales.
These are some of the aspects that have to be considered when analyzing the outpnal. With an erroneous input signal the output cannot be trusted.
4.3.2 Measurement Results
Measurements have been done at Ericsson Radio AB, Kista-Stockholm, and adepartment of Physics and Measurements (IFM), Linköping University. As evaluaboard the Analog Devices’ AD976x-EB board has been used [84]. The results havecompared with the corresponding results from the Analog Devices’ DAC AD9764.
To characterize the performance of the converters mostly the frequency domain hastudied and the measurement results are briefly summarized in Sec. 4.3.3.
In Fig. 4-17a) we see the output spectrum for the 10-bit single cascode DAC when aing a full scale single-tone at supply voltage 3.3V. The signal frequency at the outpapproximately 3.43MHz and the update frequency is 20MHz. It is found that the thirdmonic is the one determining the SFDR to be 48dB. Harmonics of even order are reddue to the use of differential signals.
A dual-tone measurement result from a 14-bit double cascode DAC at 5V suppshown in Fig. 4-17b). The update frequency is 20MHz and the signal frequencieapproximately 3.43MHz ( ) and 3.51MHz ( ). The SFDR is 49dB and the IMD giv
by the frequency component is -54dB.
φk 0 2π,[ ]∈
0 0.02 0.04 0.06−200
−150
−100
−50
0
50
100
150
200Sines without random phase.
Sig
nal a
mpl
itude
.
Time.0 0.02 0.04 0.06
−50
−40
−30
−20
−10
0
10
20
30
40
50Sines with random phase.
Sig
nal a
mpl
itude
.
Time.
a) b)
f 1 f 2
2 f 1 f 2–
72
4. A CMOS DAC Chipset for VDSL Applications
4-bitely.
lly noto
enta-
the.
to
siticurces
canmea-
Figure 4-17: a) 10-bit single cascode DAC. 3.3 V supply. Single tone. 20 MHz clock frequency.b) 14-bit double cascode DAC. 5 V supply. Dual tone. 20 MHz clock frequency.
The SFDR vs. clock frequency for the single cascode 10-bit DAC, single cascode 1DAC, and double cascode 14-bit DAC is shown in Fig. 4-18a) through c), respectivIn the figures the results from both 3.3V and 5V supplies are shown.
4.3.3 Measurement Conclusions
There are some results found by observing the measurement results:
• During the measurements of the chipset we have seen that there are practicalarger variations of performance when changing the supply voltage from 5V3.3V.
• There are no larger variations between the single and double cascode implemtions, hence the output impedance of single cascodes is large enough.
• Matching errors that degrade the performance origin from:
→ Matching of current sources→ Voltage drop over internal wires→ Too high on resistance of the current switches
• The bandwidth is rather low indicating a high capacitive part at the output ofconverters, probably origins from the internal wires as described in Sec. 4.1.1
• Time-domain simulation results show low glitching behaviour, probably duegood clock distribution and segmentation of the MSBs.
The results can be improved by doing a more careful layout with respect to pararesistance and capacitance [33] as well as improving the matching of the current sowith a different assignment of unit current sources [9, 39].
From measurements of the 1.5V 10-bit DAC [64], we know that the performancefurther be improved with the same CMOS process. An SFDR over 60dB has beensured.
a) b)
73
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
it
Figure 4-18: SFDR vs. Clock frequency for the a) single cascode 10-bit DAC, b) single cascode 14-bDAC, and c) double cascode 14-bit DAC. (*) at 3.3 V supply. (o) at 5 V supply. Thesignal-to-clock frequency ratio is approximately 1/6.
0 5 10 15 20 25 30 35 40 45 50 5540
42
44
46
48
50
52SFDR vs. Clock Frequency. 10−bit DAC.3.3 and 5−V supply.
Clock Frequency [MHz]
SF
DR
[dB
]
0 5 10 15 20 25 30 35 40 45 50 55
40
42
44
46
48
50
SFDR vs. Clock Freq. 14−bit DAC (Single Casc.) 3.3 and 5−V supply.
Clock Frequency [MHz]
SF
DR
[dB
]
0 5 10 15 20 25 30 35 40 45 50 5540
41
42
43
44
45
46
47
48
49
50
51
Clock Frequency [MHz]
SF
DR
[dB
]
SFDR vs. Clock Freq. 14−bit DAC (Double Casc.) 3.3 and 5−V supply.
(49)
(44)
(49)
(42)
(49)
(42)
74
5. Improvements of the DAC Design
noise,is the
con-ve the
ted in
hing,
nalog
rity ofwaycom-
ad outata toband-d.
54].n of
erede con-
5 Improvements ofthe DAC Design
It has been shown that the performance of the converter is dependent on matching,and output impedance. In measurements (Chapter 4) it has also been found that itnon-linearity due to matching errors that limits the performance of the implementedverter chipset. In this chapter we present some techniques that can be used to improperformance of the wideband converters. Some of the techniques will be implemenfuture versions of the chipset.
The most common techniques to further improve the performance are
• Digital correction; calibration and trimming of sources, etc. [8, 10, 13, 54, 56]
• Dithering; randomization of segmented sources and dynamic element matcetc. [11, 24, 35, 56]
In some cases, a kind of an observer is needed. For the use in DACs it has to be aand it is therefore often hard to design due to its use in wideband applications.
5.1 Digital Correction
Naturally, the output of the current sources can be used to determine the non-lineathe converter. By using this information the digital input can be changed in such athat the non-linearity can be reduced, i.e., error compensation. This introduces moreplexity and in some cases even more noise since non-linearity components is sprelike noise. The digital correction needs some kind of feedback to change the input dcompensate for errors. This feedback loop slows down the converter and limits thewidth. Another drawback is, that some kind of analog-to-digital conversion is neede
5.1.1 Intentional Pre-Distortion
It is possible to eliminate some of the distortion by using intentional pre-distortion [Assume that the output signal of the converter, , should be a linear functio
the input, , as
(5-1)
With fine quantization, hence a large number of bits, the quantization error is considto be white noise and can therefore be neglected in this discussion. Suppose that thverter is non-linear of the first order and that the output amplitude can be written as
(5-2)
Aout X( )
X
Aout X( ) Aref X⋅=
Aout X( ) Aref X⋅ a X2⋅+=
75
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
t, ,
, if
orderroxi-
to the
Note that no delay skew is assumed in this simple model. Suppose that a new inpuwhich is described by
(5-3)
is applied to the input. By inserting (5-3) in (5-2), the output signal becomes
(5-4)
It is obvious that even more distortion components appear in the output. However
(5-5)
the influence of the component is eliminated. Therefore we have
(5-6)
If it is guaranteed that
and (5-7)
the SFDR is improved since the higher order harmonics are smaller than the firstharmonic as the example shows in Fig. 5-1, where the improvement in SFDR is appmately 27dB with pre-distortion.
Figure 5-1: Output amplitude spectrum from a non-linear DAC a) without and b) with pre-distortion.The improvement,∆SFDR, is approximately 27dB.
Note that for a sinusoidal input, we may have components that are folded back on
fundamental frequency, , and interference occurs.
X
X X b X2⋅+=
Aout X( ) Aref X⋅ a X2⋅+ Aref X b X2⋅+[ ]⋅ a X b X2⋅+[ ]2⋅+= = =
Aref X⋅ Aref b⋅ a+[ ] X2⋅ 2ab X3⋅ ab2 X4⋅+ + +=
Aref b a+ 0= b⇒ a Aref⁄–=
X2
Aout X( ) Aref X⋅ 2a2
Aref----------X3–
a3
Aref2
----------X4+=
a Xpeak2⋅ 2
a2
Aref----------Xpeak
3> a Xpeak2⋅ a3
Aref2
----------Xpeak4>
0 0.1 0.2 0.3 0.4
−100
−80
−60
−40
−20
0
20Output without predistortion
Mag
nitu
de [d
B]
Normalized frequency.0 0.1 0.2 0.3 0.4
−100
−80
−60
−40
−20
0
20Output with predistortion
Mag
nitu
de [d
B]
Normalized frequency.
∆SFDR
X3 X4 …, ,
76
5. Improvements of the DAC Design
rela-cir-of theher
or inthe
fromually
ver-speedw theinter-also
is the
atchthe
g (in
rged.
the
r willhen
the
age has
ongerr load)s alsor cer-
Intentional pre-distortion is most often only suitable for measurement, where it istively easy to distort the input signal. In a real chip implementation, digital squaringcuits are needed (5-3), as well as analog observers to determine the magnitudeactual non-linearity. This introduces more complexity to the design of the circuit, higpower consumption, etc.
5.1.2 Calibration and Trimming Techniques
The output of the converter can be modified by using additional current sources,fact an additional DAC. Using a method similar to the structure sketched in Fig. 5-2output current is changed using a compensating DAC. The error current resultingmatching errors in the original DAC can be reduced by adding or subtracting an eqlarge amount of current from the compensating DAC [56].
Figure 5-2: Use of extra current sources to compensate and calibrate errors.
This method will however require an observer that performs an analog-to-digital consion, which is undesired. An automatic compensating routine that works at the sameas the original converter is also needed. This implies that the observer must knoinput signal and hence it may be necessary to generate special calibration vectorsnally. This further slows down the converter and increases the complexity. It shouldbe noted that the compensating DAC cannot only be set for static errors, since itdynamic errors that determine the quality at higher frequencies.
Calibration or trimming techniques can be used to minimize the influence of mism[8]. The basic principle is that the source-gate voltage, , can be held by using
source-gate capacitance, , see Fig. 5-3. When switch and are conductin
the positions opposite to the ones shown in the figure), the capacitance, , is cha
The will now take a value corresponding to the reference current, , which is
wanted nominal output current of the current source. Mismatch errors of the transistonot affect the output current since is dependent on the reference current only. W
and are not conducting the is set by the charge on . However, due to
leakage currents and CFT the true value cannot be guaranteed, the source-gate voltto be refreshed at regular basis.
The advantage of this technique is that the matching errors of the transistors no laffect the result. Disadvantages are that additional switches are needed (hence largeand for high resolutions a large number of current sources have to be calibrated. Thiimplies that the calibration phase may take a long time, which may not be possible fo
Current Sources
Current Sources
Original DAC
Compensating DAC
Outputs have tobe observed.
Delay
Logic
VSG
Csg S1 S2
Csg
VSG I ref
VSG
S1 S2 VSG Csg
77
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
e cur-
th theust bes only
allyent.
e cur-ng tomber,d bygnal-urcesandomsweep-
re, the
tain applications. Still we also have to guarantee that the errors in switches, leakagrents, etc., are smaller than the original matching errors.
Figure 5-3: Circuit solution to calibrate the current sources at certain time points.
The technique can be used for the segmented MSBs, but than their mismatch wibinary weighted LSBs may be even worse, hence the reference current source mvery accurate. The technique is also suitable for R-2R ladder structures where there ia number of equally large current sources [8].
5.2 Dithering
The main principle of dithering technique is to smooth distortion into noise or generforcing matching errors (or similar) that generate non-linearity to be signal-independ
5.2.1 Randomization of Segmented Current Sources
When segmenting the sources of a current-steering DAC, a number of equally largrent sources is used. The digital input controlling the current switches correspondithese sources is a thermometer code. In the conventional design, the input nu
, is represented by using one specific current source, is representeusing two specific sources, etc. With this structure the matching errors are strongly sidependent. The digital circuit can be designed so that, at different times, different soare used to represent . The sources that should be used, can be chosen in a rway, using a pseudo-random binary sequence (PRBS), and they can be chosen bying through sources in a cyclic way, using the clock, see Fig. 5-4.
Figure 5-4: Randomization of bits. The matching error becomes uncorrelated with the signal.
The matching errors become more or less uncorrelated with the signal and therefo
Cgs
S1
S2IrefTo current
switches
Vbias
X 1= X 2=
X 1=
SegmentationCurrentSwitches
Binary Therm.
Randomizer
Input Code
78
5. Improvements of the DAC Design
urrent
each
to theseen
seg-
noisen the
d.
pen-y hardany
rtion
errors turn into noise instead of distortion. Assume that there are segmented c
sources. Each current source, , , has the same nominal size, . For
source a relative mismatch error, , is associated, hence
(5-8)
Without the randomization the relative error for the code (
number of “1”:s) would be
(5-9)
Hence the relative errors for the codes would be
The DNL and INL values are given by
and (5-10)
With randomization we have the same relative error for all codes as
(5-11)
since for each code all current sources are used equally many times (in mean) duerandom assignment of sources. Since all codes give the same error, this will only beas an offset error for all the segmented current sources
and for (5-12)
and hence the average DNL will be improved. The DNL error at the gap between themented MSB sources and the LSBs may increase. The INL values become
(5-13)
In the frequency domain the distortion terms are reduced to the cost of a higherfloor, Fig. 5-5. The increase of noise is dependent on the matching error sizes, . I
simulation a mismatch error with standard deviation of approximately 12% was use
For clock driven assignment of the sources, the errors may still be slightly signal-dedent, but the linearity errors are reduced. It should be noted that these results are verto predict and derive. The clock driven (cyclic shift) has the advantage of not needingrandom sequence. The output signal using this technique will still contain distoterms, they are however reduced to the cost of a higher noise floor.
K
I k k 1…K= I src
δk
I k I src 1 δk+( )⋅=
XM M 0011…11= = M
δXi1M----- δk
k 1=
M
∑=
X1 X2 X3 … XK, , , ,
δX1 δ1= δX2
δ1 δ2+
2-----------------= δX3
δ1 δ2 δ3+ +
3-----------------------------= … δXK
δ1 … δK+ +
K------------------------------=, , , ,
Di δi= I i Di∑ δi∑= =
Xi
δX1K---- δk
k 1=
K
∑=
D01K---- δ1 … δK+ +( )= Di 0= i 1≥
I i Di∑ D01K---- δ1 … δK+ +( )= = =
δk
79
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications
b)
AC.way asdedurrentparts.pplynd anted
cipleTheed as
ig. 5-nd be
filterh is
Figure 5-5: Output amplitude spectrum from 256 segmented sources a) without randomization andwith randomization.
In fact, the principle of randomization can be generalized to be used on the entire DThe current sources in a current source array are addressed basically in the samea RAM. To achieve a simple and regular layout, this forces digital circuits to be incluwith the current source in the array, since each current source has to have its own cswitch. This also increases the wire lengths and noise between digital and analogFor DAC structures with resolutions higher than 8-10 bits this technique is hard to adue to area and complexity. Hybrid versions use this digital control for the MSBs abinary weighted structure for the LSBs, very similar to randomization of segmesources.
Another technique is to use dynamic element matching (DEM) where the main prinis to divide the converter into a number of subconverters with a lower resolution.input to the subconverters are modified so that the matching errors (noise) is shapwell [24, 35]. Using the randomization technique, the noise floor is increased (see F5b). To reduce the noise floor within a certain signal band, the noise can be shaped amoved to other (higher) frequencies. This higher noise is filtered out by an analogat the output. However, this implies an oversampling converter structure, whicdescribed in the next part of the thesis,Part C: Oversampling Digital-to-Analog Convert-ers for ADSL Applications.
0 0.1 0.2 0.3 0.4−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Output without randomization
Normalized frequency
Mag
nitu
de [d
B]
0 0.1 0.2 0.3 0.4−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Output with randomization
Normalized frequencyM
agni
tude
[dB
]
80
l-to-tro-cks
pli-
ven
y
ith
,
]
C Part C:OversamplingDigital-to-AnalogConverters forADSL Applications
1 Introduction
In this part of the thesis we present an overall description of the oversampling digitaanalog converter (OSDAC) with theory and implementation. First we give a general induction to the principle of oversampling and in Chapter 2 a description of building bloassociated with an OSDAC. The design of a 3.3V-5V CMOS OSDAC for ADSL apcations is described in Chapter 3.
A Nyquist-rate converter has the peak SNR (within the Nyquist bandwidth), , gi
by dB. The sampling frequency, , for the OSDAC is given b
the oversampling ratio (OSR) and the original sampling frequency, , as
(1-1)
The quantization noise will now be given by the bandwidth determined by . W
a lowpass filter, Fig. 1-1, the signal within the wanted original bandwidth,
is filtered out and, ideally, the SNR within this frequency range is now given by [37
(1-2)
f N
SNR 6.02N 1.76+≈ f OSR
f s
f OSR OSR f s⋅=
f OSR
f N f s 2⁄=
SNR 6.02N 1.76 10 OSRlog+ +≈
81
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
ver-NRge arity.15-
con-, the
tro-nfor-s theildingpulset has
fewpling
SLhese
e the
The OSDAC can obviously be designed for low noise and high resolution if the osampling ratio is high due to the term: in (1-2). However, the increase of Sis still only 3dB for every doubling of the OSR and when increasing the dynamic ranhigher resolution of the DAC still is required to meet the specifications on the lineaIn a 14-bit DAC with an OSR = 4, the linearity of the converter must correspond to abit DAC [37].
Figure 1-1: Naive use of oversampling. The input signal is oversampledL (= OSR) times. Images thatoccur due to the oversampling is filtered out using the lowpass filter.
By using noise shaping with a modulator (Fig. 1-2), the linearity and the SNR of theverter may be improved significantly, as is further described in Chapter 2. In factimprovement in SNR is approximately given by (in dB)
(1-3)
where is the order of the modulator.
Figure 1-2: Oversampling DAC using modulation to improve linearity and signal-to-noise ratio.
The modulator is purely digital and it reduces the number of bits of the signal. This induces a higher quantization noise which is highpass filtered and the original signal imation is lowpass (or allpass) filtered. The reduced number of bits also relaxerequirements on the DAC used in the converter and hence the number of analog bublocks may be decreased. By reducing the number of bits to only one single bit, i.e.,code modulation (PCM), the DAC can be designed to be completely linear since ionly two threshold values [11]. Noise shaping is also referred to as sigma-delta (Σ∆) ordelta-sigma (∆Σ) modulation.
The ADSL standard as described inPart A: Overview: Digital-to-Analog ConverterDesignhas a bandwidth of approximately 1.1MHz [83]. Since the OSDAC contains anumber of analog elements, the oversampling ratio can be large. With an oversamratio of 32, the sampling frequency is approximately 71MHz for the OSDAC for AD(Chapter 3) and basically there are no bigger problems designing digital circuitry for tspeeds. The OSDAC is implemented in Ericsson’s 0.6µm CMOS process.
In this part we focus on and describe a behavioral-level design of an OSDAC whertrade-offs between different building blocks are highlighted and discussed.
10 OSRlog
DAC LPL
20 M⋅ 10+( ) OSRlog
M
DAC LPL Σ∆
82
2. Oversampling DAC Structures
6, 59,asic
,
.
ell
Sec.hich
ow
lter
signalat
f
g. 2-from
2 OversamplingDACStructures
Several different oversampling converter structures can be found [11, 37, 41, 46, 560, 63]. We show a general topology (Fig. 2-1) which is divided into a number of bbuilding blocks; interpolation filter, modulator,M-bit DAC, and analog filter.
Figure 2-1: General structure of the oversampling digital-to-analog converter. Interpolation filterModulator, DAC, analog lowpass filter (smoothing filter). The interpolation filter fulfilsthe oversampling of the signal and the modulator the reduction of bits in the circuit.
The input signal, , is given by bits at a certain clock frequency
An interpolation filter is used to increase the clock frequency to , as w
as filter out higher frequency components in the signal. This is further discussed in2.1. The interpolated signal, , is modulated by the modulator (Sec. 2.2) w
reduces the number of bits from to in its output signal . The DAC can n
be designed for bits and its output is lowpass filtered by the analog fi
(Sec. 2.4) which removes images and compensates for sinc weighting of the output. The DAC is a Nyquist-rate DAC with the Nyquist frequency . Note th
the linearity of the -bit DAC still has to correspond to bits.
Figure 2-2: Structure of the oversampling digital-to-analog converter when reducing the number obits to one.
When letting the modulator reduce the number of bits to only one single bit, see Fi2, the DAC can be replaced by a semi-digital FIR filter (Sec. 2.3), that both converts
bits @N f OSR
Interpol.Filter
bits @N f s
X1(kTs)Modu-lator
bits @M f OSR
X3(kTo)
DAC(M bits)
AnalogLP filterX4(kTo) Aout(t)
X2(kTo)
X kTs( ) N f s 1 Ts⁄=
f OSR 1 To⁄=
X2 kTo( )
N M X3 kTo( )
M X4 kTo( )
Aout t( ) f OSR
M N
X2(kTo)
bits @N f OSR
Interpol.Filter
bits @N f clk
X1(kTs)Modu-lator
1 bit @ f OSR
X3(kTo)Semi-digital
FIR filterAnalogLP filterX4(kTo) Aout(t)
83
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
igitalrentlesssta-
isd)
r with,
uencyh thelified
IR
3d).Fig.
f theunc-2-1
ften
a digital to an analog representation and filters the signal as well [34, 63]. The semi-dFIR filter can be considered to be a number of cascaded single-bit DACs with differeference levels. With this method the analog smoothing filter can be designed withcomplexity. However, the modulator must be designed more carefully with respect tobility since the loop gain is high.
Figure 2-3: Frequency spectrum for different stages of the oversampling with noise shaping. In thexample OSR=4. a) Original spectrum. b) Oversampling spectrum. c) Noise is shaped.Lowpass filtering the original signal e) Wanted output spectrum.
The amplitude spectrum of a signal at different stages in an oversampling converteOSR = 4 is shown in Fig. 2-3. The original signal within the Nyquist band,
Fig. 2-3a), is interpolated and the spectrum is repeated over the oversampling freqrange. The interpolating filters attenuate the images as illustrated in Fig. 2-3b). Witnoise shaping function the noise is attenuated at lower frequencies (< ) and amp
at higher frequencies ( ), Fig. 2-3c). A lowpass filter (semi-digital F
filter and analog LP filter) is used to filter out images and the amplified noise, Fig. 2-As is illustrated in Fig. 2-3e) the quantization noise is lower than for the original case,2-3a).
2.1 Interpolation Filters
The purpose of the interpolation filters is to interpolate and reduce the influence oimages (Fig. 2-3b) that arise due to the oversampling [21, 11]. The internal filtering ftion reduces the requirements on the next following building blocks as given in Fig.and Fig. 2-2. When implementing the interpolation filter, the oversampling is most odone in steps, i.e., multi-stage filters, as sketched in Fig. 2-4.
fsfs / 2
4fs = fOSR2fs = fOSR / 2
Shaped noise
Lowpass filtering
a)
b)
c)
d)
e)
fs / 2
Interpolationfiltering
f N f s 2⁄=
f N
f N f 0.5f OSR< <
84
2. Oversampling DAC Structures
s
tio,
ain
s or
less
ation
uc-
hich
Figure 2-4: Principle description of multi-stage interpolation filtering.
The oversampling ratio (OSR) is given by the individual oversampling ratios, , a
(2-1)
The interpolation function is described by
(2-2)
where is the output signal, is the input signal, is the oversampling ra
is an integer, and is the update time interval. In the frequency dom(2-2) corresponds to
(2-3)
The total transfer function, , of the filters in Fig. 2-4 is given by
(2-4)
where are the subfilters of the multi-stage filter. By using interpolation in stage
frequency masking techniques [36] the filters may be designed easier and with
complexity and less power consumption. A simple structure of a one-stage interpolfilter is shown in Fig. 2-5. It is an FIR filter with taps and the output is given by
(2-5)
The implementation of long filter coefficients may cost much and therefore filter strtures with simple coefficients are wanted.
Figure 2-5: General one-stage interpolation filter.
If the oversampling ratio is high, the interpolation filter has to be narrow banded wincreases the number of coefficients in the filters and the complexity [36].
Y z( ) H z( ) X z( )⋅ a0 a1z OSR– … aK 1– z OSR K 1–( )⋅–+ + +[ ] X z( )⋅= =
T/OSR T/OSR T/OSR
aK-1aK-2a2a1a0
x(nT)
y(nT)
85
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
pre-uan-
hpassoiseion
. The
n the
andtor,
output,d by aentedfirstfromd the
re
2.2 Modulator
Basically, the modulator in an OSDAC is designed to reduce the number of bits resenting the signal, i.e., to use a pulse code modulation (PCM). This implies that the qtization noise will increase, but the noise can be shaped in such a way that it is higfiltered. The transfer function from the noise to the output will be referred to as the ntransfer function (NTF) and for the signal we will refer to the signal transfer funct(STF). The STF is either an allpass or lowpass filtering function.
Generally, the modulator contains a feedback loop and IIR filters to shape the noisefeedback is of two kinds:
• Signal feedback (Sec. 2.2.1)
• Error feedback (Sec. 2.2.2)
The filters used in the modulator are different in the two structures. Dependent onumber of bits at the output the modulator structures are divided into two groups:
• Multi-bit modulators
• Single-bit modulators
In this thesis, we focus on the single-bit modulator, which has a large loop gaintherefore the stability must be carefully considered [56, 60]. In the single-bit modulaa certain value at the input is represented by the average value of the pulses at thehence the average duty cycle. Hence the maximum value of the input is representestable maximum output value on the output. The mean value of the input is represby a square waved signal with 50% duty cycle. In Fig. 2-6 the simulation result for aorder modulator using signal feedback (Sec. 2.2.1) is shown. The input is sweepinga value near the minimum amplitude to a value near the maximum (dashed line) anoutput signal is described by the square waves (solid line).
Figure 2-6: The average value of the output approximates the input signal. The simulation results aachieved with a first order signal feedback modulator.
0 50 100 150
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
Sequence Index
Nor
mal
ized
Am
plitu
de
Input Ramp and Output Signal.
86
2. Oversampling DAC Structures
n Fig.an-
Thistor is
filter
2.2.1 Signal Feedback Modulator
The signal feedback modulator uses the output signal to feed back [37], as shown i2-7. For a single-bit output, the output signal, , is equal to the MSB of the qu
tizer’s input, , and the quantization noise is .
Figure 2-7: Basic principle of a signal feedback modulator.
In the frequency domain, the input to the quantizer, , is given by
(2-6)
where is the output signal and can be written as
(2-7)
where is the error signal caused by the quantization. Therefore, we have
(2-8)
or
(2-9)
The signal transfer function, , is
(2-10)
and the noise transfer function, , is
(2-11)
The signal should be lowpass (or allpass) filtered and the noise highpass filtered.states the requirements on the filters and , and the order of the moduladetermined by the filter orders.
Assume that we want the STF to be described by a delay only, hence an allpass
(2-12)
and for the first order modulator the NTF is described by the highpass filter
(2-13)
y nT( )w nT( ) q nT( ) y nT( ) w nT( )–=
H(z)
G(z)
x(nT) y(nT)+
-
w(nT)
W z( )
W z( ) H z( ) X z( ) G z( ) Y z( )⋅–[ ]⋅=
Y z( )
Y z( ) Q z( ) W z( )+=
Q z( )
Y z( ) Q z( ) H z( ) X z( ) G z( ) Y z( )⋅–[ ]⋅+=
Y z( ) H z( ) X z( )⋅1 H z( ) G z( )⋅+------------------------------------- Q z( )
1 H z( ) G z( )⋅+-------------------------------------+=
STF z( )
STF z( ) H z( )1 H z( ) G z( )⋅+-------------------------------------=
NTF z( )
NTF z( ) 11 H z( ) G z( )⋅+-------------------------------------=
H z( ) G z( )
STF z( ) z 1–=
NTF z( ) 1 z 1––( )=
87
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
condthan
am-
Using the equations (2-10) through (2-13) the filters become
and (2-14)
For the second order modulator the NTF is
(2-15)
Using (2-12) and (2-15) in (2-10) and (2-11), the filters are set to
and (2-16)
In Fig. 2-8 the NTFs for the first and second order modulator are shown. The seorder modulator (dotted line) shows a better noise attenuation at lower frequenciesthe first order modulator (solid line).
Figure 2-8: NTF of a first order (solid line) and second order (dotted line) modulator.
The NTF for the second order modulator (when neglecting the sinc weighting from sple-and-hold elements) is
(2-17)
and its PSD is given by
(2-18)
G z( ) 1= H z( ) z 1–
1 z 1––----------------=
NTF z( ) 1 z 1––( )2=
G z( ) 2 z 1––= H z( ) z 1–
1 z 1––( )2-----------------------=
0 0.1 0.2 0.3 0.4 0.5−35
−30
−25
−20
−15
−10
−5
0
5
1st and 2nd order NTF. Signal Feedback.
Normalized Frequency
|NT
F(z
)|2 [d
B]
NTF f( ) 1 z 1––( )2z e
j 2π f f OSR⁄( )⋅ ⋅=
1 ej– 2π f
f OSR-----------⋅
– 2
= = =
4– ej– 2π f
f OSR-----------⋅
π ff OSR------------
sin2⋅ ⋅=
NTF f( ) 2 16 π ff OSR------------
sin4⋅ 2π ff OSR------------⋅
4≈=
88
2. Oversampling DAC Structures
, the
ation
n the
-20)
dB,for
od-37].
wn ine
.
where it is assumed that the OSR is high. Within the interesting frequency range,
noise power can be calculated by using the NTF and the known, original, quantiznoise error PSD
(2-19)
where is the reference step value. The total power of the shaped noise withi
Nyquist band is found by combining (2-18) and (2-19)
(2-20)
where
(2-21)
The signal’s normalized power is
(2-22)
which gives the SNR as the ratio of the signal power (2-22) and the noise power (2
(2-23)
From (2-23) it is seen that for each doubling of the OSR, the SNR is improved by 15corresponding to 2.5 bits. The improvement is approximately given by bits
each doubling of the OSR [56]. is the order of the modulator. For the single-bit mulator the linearity is also guaranteed since a single-bit DAC is used at the output [
2.2.2 Error Feedback Modulator
The error feedback modulator uses the quantization error to feed back [37], as shoFig. 2-9. The quantization error, , is given by the LSBs of th
input signal to the quantizer, , and the output signal is the MSB of
In the frequency domain, the quantization error signal is
(2-24)
and
f N
Sq f( ) 1f OSR------------
Aref2
12----------⋅=
Aref
Pnoise Sq2 f( ) NTF f( ) 2⋅ fd
f N–
f N
∫ Sq2 f( ) NTF f( ) 2 fd
f N–
f N
∫⋅= = =
1f OSR------------
Aref2
12----------
f N5
5------- 2π 1
f OSR------------⋅
4⋅ ⋅ ⋅ 2
60------ Aref
2 2π( )4
25-------------- 1
OSR5--------------⋅ ⋅ ⋅= =
f OSR OSR 2f N⋅=
Psignal12--- 22N 2– Aref
2⋅ ⋅=
SNR 10Psignal
Pnoise----------------
log 10
12--- 22N 2– Aref
2⋅ ⋅
Aref2 π4
60------ 1
OSR5--------------⋅ ⋅
----------------------------------------
log= = =
1032--- 22N 5
π4----- OSR5⋅ ⋅ ⋅
log 6.02N 1.76 12.90– 50 OSRlog+ +≈=
M 0.5+
M
q nT( ) y nT( ) w nT( )–=
w nT( ) y n( ) w nT( )
Q z( ) Y z( ) W z( )–=
89
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
hpassF is
dback
sta-f antors
(2-25)
which gives
(2-26)
Figure 2-9: Basic principle of an error feedback modulator.
The signal transfer function, , is
(2-27)
and the noise transfer function, , is
(2-28)
Since the signal should be lowpass or highpass filtered and the noise should be higfiltered, the requirements on the filters and are set. Assume that the STdescribed by a unity function
(2-29)
For the first order modulator the NTF is described by
(2-30)
and by using (2-29) in (2-28) with (2-30) we have
(2-31)
For the second order modulator the NTF is
(2-32)
and therefore
(2-33)
The feedback filters have practically the same structure as those for the signal feeconfiguration and the gain in SNR as function of the OSR is also the same.
2.2.3 Higher-Order Signal Feedback Modulators
For single-bit modulators the loop gain is high and for higher order modulators thebility has to be carefully investigated [11, 56, 60]. In Fig. 2-10 a general structure o
-th order modulator is shown. The filters are given by discrete-time integra(accumulators) as
W z( ) H z( ) X z( ) G z( ) Q z( )⋅–[ ]⋅=
Y z( ) H z( ) X z( )⋅ 1 H z( ) G z( )⋅–[ ] Q z( )⋅+=
H(z)
G(z)
x(nT) y(nT)+
-
-+
w(nT)
q(nT)
STF z( )
STF z( ) H z( )=
NTF z( )
NTF z( ) 1 H z( ) G z( )⋅–=
H z( ) G z( )
STF z( ) H z( ) 1= =
NTF z( ) 1 z 1––( )=
G z( ) z 1–=
NTF z( ) 1 z 1––( )2=
G z( ) z 1– 2 z 1––( )=
N A z( )
90
2. Oversampling DAC Structures
s are
filterlts of3.1.2.
g adis-
tors,sid-
e and
dis-noise
theal,passput
(2-34)
The coefficients and determine the NTF and STF.
Figure 2-10: General structure of a higher order modulator using signal feedback structure.
For a fourth order modulator the STF is given by
(2-35)
and the NTF is given by
(2-36)
where is the filter given by (2-34). The zeros of the NTF in (2-36) are
and (2-37)
and the :s are used to move the poles of the NTF to improve the stability. The pole
given by complex expressions and the overall complexity of the synthesis of thestructures increases dramatically with increased modulator order. Simulation resustability issues are also discussed for the implemented fifth order modulator in Sec.
2.3 Semi-Digital FIR Filter
For multi-bit modulators, the digital output signal is converted into an analog usinDAC with a smaller resolution than the input signal to the whole OSDAC. As wascussed inPart B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applicationsthelinearity is dependent on the reference currents in the DAC. For the single-bit modulathe output consists of only two levels and the DAC converting this signal can be conered to be completely linear since the two conversion levels determine a straight lintherefore no DNL and INL errors can occur [37].
Let be the output from the single-bit modulator. It can be considered to be acrete-time signal, i.e., pulse waves, and with a very good analog lowpass filter thecan be filtered out. This requires a high order analog filter which further increasescomplexity of the design. By using a semi-digital filter the modulator output sign
, can be filtered more or less digitally, and the requirements on the analog lowfilter are reduced. A semi-digital FIR filter structure is shown in Fig. 2-11, and its out
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
e.
s in aneralwill
the
mal-
rtioner-Long
e toLP),width
w-speedfilter
is given by
(2-38)
where is the number of taps in the FIR filter and is the clock cycle tim
The coefficients are generated with analog components, for example current sourcecurrent-steering version [45]. The output, , is a pulse-shaped signal since in gethe multiplication by the coefficients is done with sample-and-hold elements. Thisgenerate images that have to be filtered out by the analog smoothing filter.
Figure 2-11: K-tap FIR filter structure.
The number of coefficients in an FIR filter is inversely dependent on the width oftransition band [36], as
(2-39)
where is the normalized cut-off frequency of the passband and is the nor
ized stopband frequency. If the coefficients are signal-independent, naturally no distowill be introduced, only the filter’s transfer function will change if there are matchingrors in the current sources. With an FIR filter a linear phase is guaranteed as well.FIR filters naturally introduce a large delay through the shift register (Fig. 2-11).
2.4 Analog Smoothing Filter
The output of the semi-digital filter still contains images in the frequency domain duthe sample-and-hold elements. With an analog continuous-time lowpass filter (CTFig. 2-12, the images and noise at higher frequencies above the original wanted bandare attenuated.
Figure 2-12: Images and noise are attenuated using the continuous-time filter
In addition, in front of the continuous-time filter, also an additional discrete-time lopass filter (DT LP) can be used to attenuate the shaped noise, Fig. 2-13. For high-telecommunication applications, it can however be hard to design a discrete-time(switched-capacitor or switched-current) that meets the requirements.
y nT( ) a0 w nT( )⋅ a1 w nT T–( )⋅ aK 1– w nT K 1–( )T–( )⋅+ +=
K T 1 f s⁄=
y nT( )
T T T
aK-1aK-2a2a1a0
w(nT)
y(nT)
K1
∆ωT------------∼ 1
ωaT ωcT–---------------------------=
ωcT ωaT
CT LPFIR
92
2. Oversampling DAC Structures
n
queation.
theec-f theof the
ts ontionade-2-15.
d onusedhe
s
Figure 2-13: Images and noise are attenuated further by using a discrete-time filter (DT LP) betweethe FIR filter and the continuous-time filter (CT LP).
Naturally, the structure of the filters (Butterworth, Cauer, etc.) and circuit-techni(current-mode, voltage-mode, etc.) are dependent on the application and the specific
Figure 2-14: Filtering stages occurring in the OSDAC, illustrated in the frequency domain.
As is sketched in Fig. 2-14 there are actually three filtering functions occurring atback-end of the OSDAC; the semi-digital FIR filter, the sinc weighting of the output sptrum and the analog continuous-time lowpass filter. When determining the order oanalog filter, these aspects should be considered. If the OSR is high, the influencesinc weighting in the signal band is very low.
2.5 Trade-Off Discussion
As was mentioned previously, by choosing a good semi-digital filter the requirementhe analog lowpass filter may be relaxed significantly. Further, with good interpolafilters at the input, the requirements on the semi-digital filter may be relaxed, etc. A troff; complexity versus area, etc., has to be done. The basic idea is sketched in Fig.
Figure 2-15: Trade-off discussion between parts of the OSDAC.
To find the suitable trade-off the different building blocks are modeled and simulatea higher-level and at least a local optimum solution may be found with the models[1]. The circuit implementation will not give the same result, but it will be close to tlocal optimum found by behavioral-level modeling and simulation.
All the design issues can briefly be summarized for the different building blocks a
• Using higher orderinterpolation filter introduces
→ higher complexity, filter structures, filter orders, etc.→ higher power consumption→ decreased out-of-band noise (and attenuation of images)→ relaxed requirements on the modulator
CT LPFIR DT LP
fOSRfOSR/2
Sinc weighting
FIR Filter
Analog LP
fN
InterpolationFilter Length
ModulatorOrder
Semi-digitalFilter Length
Analog LPFilter Order
93
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
• Using higher ordersemi-digital FIR filter introduces
→ larger chip area→ larger delay through the filter→ higher sensitivity to coefficient errors→ larger glitches→ improved SNDR→ relaxed requirements on the analog continuous-time filter
• Using higher ordercontinuous-time filter introduces
All these issues have to be considered during the design, and one of the major prois to find a good cost function that should be minimized. It could for example be chip apower consumption, etc.
94
3. A CMOS Oversampling DAC for ADSL Applications
isab,on’s
leveland
ults4, the
theWe
nsfer
3 A CMOS OversamplingDAC for ADSL Applications
In this chapter the design of a 14-bit 3V-5V CMOS OSDAC for ADSL applicationspresented. The work is done by J. J. Wikner (Linköping University), Y. Gao (ESDLKTH), and N. Tan (GlobeSpan Semiconductor). The converter is fabricated in Ericss0.6µm CMOS process.
As a very important design issue, the simulation of the whole converter on higherwill be discussed. We show the impact of different filter orders (interpolation, FIRanalog), and how this applies to the ADSL standard.
In the following sections the building blocks of the OSDAC (Sec. 3.1), simulation res(Sec. 3.2), and the chip implementation (Sec. 3.3) are presented. Finally, in Sec. 3.drawbacks and the possible improvements of the implementation are discussed.
3.1 Practical Design Considerations
The whole OSDAC was simulated in MatLab with models for the individual parts ofconverter, i.e., interpolation filter, modulator, FIR filter, and analog smoothing filter.present a short description of each component.
3.1.1 Interpolation Filters
Cascade accumulators, shown in Fig. 3-1, were used as interpolation filter. The trafunction for the filter is given by
(3-1)
and the filter is given by
(3-2)
Figure 3-1: Interpolation filter structure used in the OSDAC.
H1 z( )
H1 z( ) z 1–z
----------- J
1 z 1––( )J= =
H2 z( )
H2 z( ) 1z 1–-----------
J z 1–
1 z 1––----------------
J= =
H1(z) H2(z)
X(z) Y(z)z-1
z-1
z-1
z-1
L
95
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
For
le on
,
n be
func-hed
ereesigne isncy
The exponent from (3-1) and (3-2) is set to in the different versions.
even higher :s the stability cannot be guaranteed in the simulations due to the po
the unit circle at dc level. The total transfer function of the interpolation filter,
describes a lowpass filtering and is given by
(3-3)
where is the oversampling ratio and . Using a series expansion, (3-3) carewritten as
(3-4)
and the poles in the expression are cancelled. The magnitude response of the filtertion (3-4) with is displayed in Fig. 3-2. The attenuation of the signal at (das
line) is approximately 3.9dB.
Figure 3-2: Magnitude response of the interpolation filter as in (3-4) withJ=1. The original Nyquistbandwidth is indicated with the dashed line.
In the final version of the OSDAC chip, no interpolation filter was implemented.
3.1.2 Modulator
In the OSDAC single-bit, signal feedback modulators of the fourth and fifth order winvestigated. They are designed by Y. Gao (KTH), and a closer description of the dof the fifth order modulator is presented in this section. The modulator’s structurshown in Fig. 3-3, it uses a 14-bit two’s complementary input at the freque
MHz.
J J 0 1 2, ,=
J
Hip z( )
Hip z( ) H1 zL( ) H2 z( )⋅ 1 z L––( )J z 1–
1 z 1––----------------
J⋅= =
L L OSR=
Hip z( ) 1 z 1– … z L 1–( )–+ + +( )J 1 z 1––( )J z 1–
1 z 1––----------------
J⋅ ⋅= =
z 1– z 2– … z L–+ + +( ) J=
J 1= f N
0 0.1 0.2 0.3 0.4 0.5−30
−20
−10
0
10
20
30
40Interpolation Filter Frequency Response
Normalized Frequency
Mag
nitu
de [d
B]
f OSR 1.104 64⋅ 71≈=
96
3. A CMOS Oversampling DAC for ADSL Applications
.
sig-
There are seven coefficients, and , with their values given by
, , , , , ,
Figure 3-3: Fifth order modulator structure.
The filters, , in Fig. 3-3, are discrete-time integrators with the transfer function
(3-5)
The NTF is given by
(3-6)
where from (3-5). From (2-37) the zeros of the NTF are
and (3-7)
Figure 3-4: Output amplitude spectrum of the modulator’s output without the complex NTF zerosThe input signal frequency is 431.25kHz and the sampling frequency is 70.66MHz.
The amplitude spectrum of the modulator’s output when applying a sinusoidal withnal frequency 431.25kHz is shown in Fig. 3-4. The SNDR is approximately 63dB.
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
noise
resultthe
l
ithf the
Fig.
With the parameters the SNDR is improved. The zeros further attenuate the
within the signal band and a sharper transition band is achieved. The simulationwhen applying a sinusoidal at a frequency of 431.25kHz is shown in Fig. 3-5 whereSNDR is found to be approximately 79dB.
Figure 3-5: Output amplitude spectrum with the two complex pairs of NTF zeros. The input signafrequency is 431.25kHz and the sampling frequency is 70.66MHz
The stability of the modulator was simulated using a root locus shown in Fig. 3-6. Wthe locus the limits of the feedback values, , are found and especially the gain o
feedback loop can be determined.
Figure 3-6: Root locus of the modulator when varying the feedback parameters.
The layout of the modulator is synthesized using COMPASS tools and is shown in
ai
100
101
102
103
104
105
−80
−60
−40
−20
0
20
40
60
80With a2 and a3
bi
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
98
3. A CMOS Oversampling DAC for ADSL Applications
were the
-8,the
a cur-ts of
[81]is
s only
3-7. The core size is approximately 1.2x0.8µm2.
Figure 3-7: Layout view of the fifth order modulator generated with COMPASS.
At a supply voltage of 3V and a clock frequency of approximately 71MHz, the podissipation of the core modulator is about 92mW. To save hardware and to reducpower dissipation the parameters have been scaled internally.
3.1.3 Semi-Digital FIR Filter
The FIR filter is of current-steering type [45, 63]. The principle is shown in Fig. 3where the single-bit output, , from the modulator is fed into a shift register andcontents of the shift register is used to control the current switches. For each switchrent source with the weight is associated, where the :s are the coefficien
the filter and is a unit current size.
Figure 3-8: Current-steering implementation of a semi-digital filter with coefficient lengthK.
The digital delay line or the shift register is constructed using dynamic CMOS gateswith help from Magnus Karlsson (Linköping University). The D-latch (Fig. 3-9c)formed by using a P-gate and an N-gate as shown in Fig. 3-9a-b). The D-latch use
w nT( )
ai I unit⋅ ai
I unit
D D Dw(nT)
y(nT)
a0Iunit a1Iunit aK-1Iunit
99
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
ple-
guar-n beig. 3-ence a
rrenters in
MOSd M2
e.
one single clock phase which simplifies the clock distribution. The outputs are commentary and hence suitable for controlling the differential current switches.
Figure 3-9: Schematic of a) P-gate and b) N-gate, and c) D-latch formed by a P-gate and N-gate.
The latches are sensitive to the capacitive load on the outputs. A constant load isanteed by letting all current switches be equally large. The layout of the D-latch camade rather compact. In the design of the FIR filter the latches have been laid out (F10) so that they are as wide as the current switches and the unit current source, hregular layout is possible.
Figure 3-10: Layout view of a D-latch including the 1) P-gate and 2) N-gate.
The coefficients as shown in Fig. 3-8 are created by using a number of unit cusources in parallel according to the same principle as in the design of the convertPart B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applicationsand thematching issues apply in the same way. In this implementation single cascode Ptransistors are used. The layout of a unit current source is shown in Fig. 3-11. M1 anare given by the sizes and [µm].
Figure 3-11: Layout view of a current source constructed by two PMOS transistors. M2 is the cascod
a) b) c)
VDDGND GND
D+
Q-
D-
Q+
clk
1)
2)
W L⁄( )1 2 8⁄= W L⁄( )2 2 2⁄=
VDDM1 M2 Output
Gates
100
3. A CMOS Oversampling DAC for ADSL Applications
z
entsents,equi-
Fig.ver-
istches,
r
real-e dif--13.
ar-ne ofigher
For the FIR filter, the cut-off frequency is approximately MH
and the attenuation in the stopband is approximately 17dB. The FIR filter coefficihave been generated with the Remez algorithm in MatLab. Since the original coeffici
, have been amplified and truncated to integer values, , there is no longer an
ripple in the stopband. Proper values are found as
(3-8)
where is an amplification value which determines the size of the truncation error. In3-12 the filter magnitude response for the original filter (219 taps) and the truncatedsion is shown. The FIR filter in the implemented version of the OSDAC uses
• 2390 effective unit current sources in 219 nonzero taps
• 152 unit current sources in the largest tap
A large number of unit current sources in the taps increases the accuracy, sincelarger, but it also generates a higher current which makes the design of current swiwires, supply, etc., harder.
Figure 3-12: 219 tap FIR filter magnitude response. Characteristics with and without truncated filtecoefficients are shown.
The switches are differential and therefore also negative filter coefficients can beized. For a current source corresponding to a negative coefficient the outputs of thferential switch is simply cross-connected to the OSDAC outputs, as shown in Fig. 3
All current switches in the OSDAC are equally large with eight NMOS transistors in pallel for each channel. This also ensures equal load for all D-latches. The layout of othe switches is shown in Fig. 3-14. NMOS transistors are used since they have htransconductance parameter (higher mobility).
f c 1.15 f N⋅ 1.27≈=
ai ai
ai Jmax ai
min ai-------------------⋅ 0.5 ai sgn⋅+=
J
J
0 0.5 1 1.5 2 2.5 3 3.5 4
x 107
−40
−20
0
20
40
60
80FIR Filter Amplitude Characteristics
Frequency
Pow
er [d
B] Increased
attenuation
Increased ripple in passband
in stopband
101
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
is the
s and
the
ge to
ting
ent)
Figure 3-13: Differential current switches in the FIR filter. Negative coefficients are realized by crossconnecting the outputs.
The on-resistance of the switches is given by the eight transistors in parallel
(3-9)
where is the transconductance parameter for one single NMOS transistor.
gate or switch voltage on the transistors, is the output node of the current source
is the threshold voltage of the transistors. Since the output node is varying with
signal, the source-bulk voltage, , varies as well. This forces the threshold volta
be slightly non-linear.
Figure 3-14: Layout view of differential current switch used in FIR filter.
The average output current, , of the FIR filter is given when the input is alterna
between “0” and “1” with a 50% duty cycle, as
(3-10)
hence the average power for one channel (standby for a zero input in two’s complemover a 50Ω load is given by
(3-11)
VDD
I+I-
I0 = a0Iunit I1 = a1Iunit IM = aMIunit
φMφMφ1φ0φ0 φ1
a0: PositiveCoefficient
a1: NegativeCoefficient
aM: NegativeCoefficient
GON 8β Vφ VT– VC–( )⋅≈
β Vφ
VC
VT
VSB
ShieldingGround
φ
φ
I+
I-
Ii
I out
I out I unit aiai odd∑ ai
ai even∑–
⋅ 1318I unit≈=
Pout I out2 50⋅ 86.86
6×10 I unit2⋅= =
102
3. A CMOS Oversampling DAC for ADSL Applications
t. For
istelyf
puted-case
ltert orderpo-utput
The output current of the unit current source is dependent on the reference currenthe case with we have from (3-10) and (3-11)
mA and mW (3-12)
The impulse response of the semi-digital FIR filter from a circuit-level simulationshown in Fig. 3-15. The output current of the unit current source is approxima
and the output is doubly terminated with 50Ω. Since the start-up phase o
the simulation was too long, the figure only displays 172 of 219 values.
Figure 3-15: Impulse response from a circuit-level simulation of the semi-digital FIR filter.
Since the currents originally were to be terminated with an operational amplifier (instage to the analog smoothing filter) with low input impedance, the total output impance of the FIR filter has not been investigated. The analysis is however similar to thewith the binary weighted sources in the Nyquist-rate converters.
3.1.4 Analog Smoothing Filter
As analog smoothing filter at the output a Butterworth LP filter or Chebyshev 2 LP fiis used since the ripple in the passband should be kept as small as possible. The firsLP filter is simply constructed by using an operational amplifier with and comnents, see Fig. 3-16. It is also wanted to use the circuit as an I/V converter. The ovoltage is given by
(3-13)
where
and (3-14)
I unit 1.65µA≈
I out 2.2= Pout 0.25≈
I unit 1.65µA≈
0 200 400 600 800 1000 12003.95
4
4.05
4.1
4.15
4.2
4.25
4.3
4.35
4.4
4.45Semi−digital filter impulse response
Diff
eren
tial o
utpu
t cur
rent
[mA
]
Time [us]
R C
Vout s( ) I in s( ) R1 sRC+--------------------⋅=
Vout s( ) V+out s( ) V-out s( )–= I in s( ) I +in s( ) I -in s( )–=
103
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
e for
age
mmas
p an-
dem-sultsfor
9)
0)
1)
=32.r thecon-cies
Figure 3-16: First order differential lowpass filter.
From the ADSL specification the cut-off frequency is given and therefore
(3-15)
We also know that the dc voltage drop over the resistance, , can not be too larg
low voltage applications. With an input dc current, , of 2.2mA and a maximum volt
drop of V, we have that
or (3-16)
This gives heuristically the size of the capacitance, , to
pF (3-17)
which is far too large to implement on chip since the area would be approximately 12
with today’s CMOS technology. Another filter structure, where the circuit is not usedan I/V converter, could be used as on-chip filter (see Sec. 3.4). However, no on-chialog filter was implemented in the fabricated OSDAC chip.
3.2 Simulation Results
Simulation results with different configurations are presented in this section. Theseonstrate how the trade-off between different parts affects the result. The simulation reare given in Fig. 3-17 through Fig. 3-21, showing the output spectrum of the OSDACthe following configurations:
• 219 tap FIR filter, no interpolation filters, no LP filter, (Fig. 3-17)
• 219 tap FIR filter, second order interpolation filter, no LP filter, (Fig. 3-18)
• 219 tap FIR filter, second order interpolation filter, first order LP filter, (Fig. 3-1
• 219 tap FIR filter, second order interpolation filter, third order LP filter, (Fig. 3-2
• 324 tap FIR filter, second order interpolation filter, third order LP filter, (Fig. 3-2
In all simulations a fifth order modulator is used and the oversampling ratio is OSRThe number of carriers of the DMT input is only 210. The carriers are distributed ovefrequency range from 86kHz to 992kHz with an equi-distance of 4.3125kHz. Idealditions allow 249 carriers according to the ADSL standard [83]. The cut-off frequen
R
C
C
RI+in
I-out
I+out
I-in V+out
V-out
RC1
2π 1.1046×10⋅
------------------------------------ 1449–×10≈=
R
I dc
Vdrop max, 1=
I dc R⋅ Vdrop max,< R 1 2.23–×10⁄< 455Ω≈
C
C 1449–×10 455⁄ 317≈=
104
3. A CMOS Oversampling DAC for ADSL Applications
ter-po-orthMHzin the
hownn ofltersto can-
of the filters are slightly above 1.104 MHz. The ripple in the passband is mainly demined by the FIR filter and the round-off errors of the coefficient truncation. The interlation filters are sinc filters as shown in Sec. 3.1.1. The analog filters are Butterwfilters as in Sec. 3.1.4. In Fig. 3-17 we see that the images from 1.104MHz to 2.208are very large and that the noise is not attenuated as much as wanted. The ripplepassband of the 210 carriers are around the specified level (-36.5dB).
Figure 3-17: Output spectrum without interpolation and analog filters.
By using a second order interpolation filter the images are slightly attenuated as sin Fig. 3-18. The noise is not affected since it origins in the modulator. The attenuatiothe noise by the FIR filter is not large enough. It is also seen that the interpolation ficause a quite large attenuation near the passband edge. The FIR could be designedcel this effect by having a higher gain near the passband edge.
Figure 3-18: Output spectrum with a second order interpolation filter and without analog filter.
103
104
105
106
107
−140
−120
−100
−80
−60
−40
−20ADSL Specifications
PS
D
Frequency
Images
Noise and
New ADSLSpecification
210 carriers
withinfN and 2*fN.
distortioncomponents.
103
104
105
106
107
−140
−120
−100
−80
−60
−40
−20ADSL Specifications
PS
D
Frequency
Drop, due tointerpolationfilter.
105
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
anduencyr.
is
d iswever
efully
By using the first order analog smoothing filter (Fig. 3-19) the noise is attenuatedthe images are slightly attenuated. We see an even larger attenuation of the high freqcarriers within the passband, due to the too low cut-off frequency in the analog filte
Figure 3-19: Output spectrum with second order interpolation filter and a first order analog filter.
With a third order analog filter (Fig. 3-20) the specification is still not met, the noisealmost attenuated to the specified level (-90dB).
Figure 3-20: Output spectrum with a second order interpolation filter and third order analog filter.
By increasing the FIR filter length to 324 taps the attenuation in the stopbanincreased, hence the noise is attenuated as seen in Fig. 3-21. The specification is hostill not met. There are hard requirements and the design of the filters has to be cardone.
103
104
105
106
107
−140
−120
−100
−80
−60
−40
−20ADSL Specifications
PS
D
Frequency
103
104
105
106
107
−140
−120
−100
−80
−60
−40
−20ADSL Specifications
PS
D
Frequency
106
3. A CMOS Oversampling DAC for ADSL Applications
paredet the
ntsrange
hoos-
then be
dropsigned.nte sup-
ltageires.
the
Figure 3-21: Output spectrum with a 324 tap FIR filter, second order interpolation filter, and a thirdorder analog filter.
It should be noted that the simulation results presented in the figures above are comwith a newer ADSL standard and the fabricated OSDAC has been designed to mespecification of an older ADSL standard. As was discussed inPart A: Overview: Digital-to-Analog Converter Design, the newer ADSL standard sets much tougher requiremeon the attenuation of higher frequency components and especially the frequencyfrom 1.104MHz to 2.208MHz.
It is easy to understand the complexity of the choices that have to be taken when cing the filter and modulator orders.
3.3 Chip Implementation
The final chip implementation includes (on-chip)
• A fifth order modulator
• A 219 tap FIR filter
During measurements, the effect of the interpolation filters will be generated withtest vector generator and as output analog filter a standard filter from a vendor caused. The layout view of the chips is shown in Fig. 3-22.
The design is similar to the implementation of the Nyquist-rate converters. AVDD planecoves the current sources has been used to decrease the influence of the voltagealong supply lines [38]. For each coefficient one row of current sources has been assUnused current sources are shorted byVDD. A shielding layer between the analog curresources and the digital delay line has been used as well. The chip is designed to havply voltages from 3V to 5V.
The chip also contains a number of decoupling capacitors to stabilize the supply voon chip, reducing the influence of parasitic inductance and resistance in the bond w
The modulator has been incorporated in the Cadence design via gdsII format fromCOMPASS design tool.
103
104
105
106
107
−140
−120
−100
−80
−60
−40
−20ADSL Specifications
PS
D
Frequency
107
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
nts of
tput
thetor.ance,.
f ther of
Figure 3-22: Layout view of the whole OSDAC with modulator and FIR filter included.
3.4 Improvements of OSDAC Design
The simulation results show that the implementation does not meet the requiremethe newer ADSL standard. Some general improvements can be done by using
• on-chip interpolation filters, perhaps FIR filters with around 20 taps.
• more suitable design of semi-digital FIR filter, reducing the number of taps.
• on-chip analog filter, needing technique to remove the dc current from the ouwithout introducing too much distortion.
We will briefly discuss the influence of changing the structure of the FIR filter andanalog LP filter. The specification on the SNDR is met with the fifth order modulaSome techniques for adaptive modulation [18] can be used to improve the performhowever, for higher order modulators the complexity of these techniques increases
3.4.1 Interpolated FIR Filter
The use of an interpolated FIR (IFIR) filter may be advantageous since the width otransition band, , can be made larger and therefore the numbe
non-zero taps can be reduced (2-39), hence less current sources, chip area, etc.
Modulator
FIR Filter
DecouplingCapacitors
Analog I/ODigital I/O
∆ωT ωsT ωcT–=
108
3. A CMOS Oversampling DAC for ADSL Applications
219
emez’er
ass-
m theout-harperf the
t theIR
But-omeame
noise
Assume that the original FIR filter, , has the following specification (2-39)
and
(3-18)
With an attenuation in the stopband of approximately 17dB the number of taps is
(Sec. 3.1.3). Using an IFIR filter, , with and . With
the same attenuation in the stopband, the number of taps is around 109 (from Ralgorithm in MatLab). In Fig. 3-23 this is illustrated with a filter interpolated at an ord
of eight, . The behavior within the passband is the same for both filters. The p
band of the IFIR filter is repeated over the frequency range and the shaped noise fromodulator will not be filtered out. Therefore, the attenuation of the analog filter at theput must be higher to remove these components and the transition band must be sas well. Not that the order of interpolation may not be too large, since the design ofollowing filters will be too hard.
Figure 3-23: IFIR filter (interpolation order = 8) vs. FIR filter. The behavior within the passband is thesame for both filters. The IFIR filter has an offset of 5dB to illustrate the function.
It can be seen from simulation results that the order of the analog filter (to still meeADSL specifications) is approximately proportional to the interpolation ratio in the IFfilter. In Table 3-1 the approximate filter orders are summarized. As analog filter, aterworth filter is used. It is seen that the specifications on the analog filter may becmuch tougher. It should also be noted that the delay through the IFIR filter still is the sas for the original FIR filter.
The noise transfer function of the modulator could also be designed to have lesswithin the passband images that arise due to the interpolation [41].
H0 z( )
ωcT 2π 1.15 f N f s⁄⋅ ⋅≈ 2.30π OSR⋅=
ωsT 2π 1.47 f N f s⁄⋅ ⋅≈ 2.94π OSR⋅=
H1 z2( ) ωcT 2.30f N≈ ωsT 2.94f N≈
H2 z8( )
0 5 10 15 20 25 30 35−60
−50
−40
−30
−20
−10
0
10
Mag
nitu
de [d
B]
Frequency [MHz]
Magnitude Response of FIR and IFIR filter
109
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications
thetors,3.1.4stance
a chip
d tolter
con-ust
Table 3-1: Analog filter order vs. the interpolation ratio of the IFIR filter.
To further simplify the design of the analog filter, the dc currents from the outputs ofFIR filter can be removed by using current sinks implemented with NMOS transisFig. 3-24. The ac currents are fed into the analog LP filter. As was discussed in Sec.the dc voltage drop over the resistance (Fig. 3-16) now can be removed and the resican be chosen to be larger, hence the capacitance can be made smaller (3-15) andimplementation may be possible.
Figure 3-24: Removing the dc current from the FIR filter output relaxes the complexity of the designof the analog LP filter.
As was briefly mentioned an additional switched-current (SI) filter could also be usefilter the signal [45, 71]. A frequency masking technique using an FIR filter and SI fi(which is discrete-time) would relax the specifications on the analog filter as well.
In the trade-off discussion it was also mentioned that the complexity and powersumption will increase with an interpolation filter and on-chip analog filter. This malso be considered when changing the structure of the OSDAC.
InterpolationRatio
Number ofTaps
Analog FilterOrder
1 219 3
2 110 4
4 55 5
8 28 7
16 14 8
Semi-digital FIR
LP
IDC IDC
Ipos Ineg Ipos,ac
Ineg,ac
110
alog
n
sam-
emen-atchingDR ofHz.logith
vert-Somed per-in thisy be
t-ratece is
ith ami-
ringgu-
ave aover
Conclusions
This thesis should be considered as an introduction to the design of digital-to-anconverters, and especially CMOS DACs for telecommunication applications.Part A:Overview: Digital-to-Analog Converter Designis a tutorial and elementary section. IPart B: Nyquist-Rate Digital-to-Analog Converters for VDSL ApplicationsandPart C:Oversampling Digital-to-Analog Converters for ADSL Applications, both a Nyquist-rateconverter chipset suitable for wideband radio and VDSL applications and an overpling converter for ADSL applications have been implemented and presented.
The Nyquist-rate converters have been measured and conclusions about the impltation and possible improvements have been presented. We have seen that the merrors are dominating other error sources. The converters have an approximate SF44dB at a clock frequency of 50MHz and a signal frequency of approximately 8.2MThis corresponds to roughly 7-8 bits of linearity. It could be compared with AnaDevices’ TxDAC series, which shows an SFDR of approximately 63dB (10-11 bits) wthe same measurement configuration.
We have also briefly discussed how to improve the performance of high-speed coners by using feedback structures, digital correction, and randomization techniques.of the ideas are also found in the literature, but implementations with good measureformance are not yet published. By making some changes to the DACs presentedthesis, for example another current source assignment, their performance maincreased significantly. The measurement results from the third generation NyquisDAC has not been included in this thesis. We believe however, that the performanincreased in this version, compared with the second generation.
One version of the Nyquist-rate DACs has also been successfully implemented wline driver designed by J. Erlands (Linköping University) and N. Tan (GlobeSpan Seconductor) to illustrate a back-end of a line transmitter for xDSL [19].
A chapter showing the contributions to modeling of the performance of current-steeCMOS Nyquist-rate converters is included. We have shown the impact of circuit irrelarities of the DAC on the frequency domain measures. From these results we hguide on how to design the circuit. This modeling can be extended to further cdynamic properties of converters.
111
Conclusions
d andwith
filterues toards.
foundcon-out-
l andof thenda-g the
espe-Mat-
Measurement results from the oversampling converter have not been presentetherefore some conclusions of the implementation are missing. The same issuematching of current sources can be applied to this converter as well, since the FIRwas implemented with unit current sources. Here, we have discussed some techniqfurther improve the performance to meet the specifications of the newer ADSL stand
We have discussed the important issues of simulating and measuring circuits. It isthat small errors in test vectors may generate large errors in the output signal of theverter. From this we conclude that it is important to have good input data to trust theput signal as well as be able to make the correct conclusions from this.
In general, we have pointed out the behavioral-level simulations as a very usefuimportant stage of the design. It is important that the designer is aware of all stagesdevelopment of the chip. By using good and simple models, it is possible to find fumental limits on the performance and therefore also be able to focus on improvincomponents that are bottlenecks in the systems. These higher-level simulation hascially been used during the design of the oversampling converter, where extensiveLab models have been developed.
112
to-l
and
/A)
n ofg
by
ive
References
[1] R. Baraniecki, P. Dabrowski, and K. Hejn, “Oversampling Sigma Delta Analog-Digital Converters Modeling Based on VHDL,”Analog Integrated Circuits and SignaProcessing, vol. 16, no. 2, pp. 101-9, June 1998
[2] C. A. A. Bastiaansen, D. Wouter, J. Groenewald, H. J. Schouwenaars,H. A. H. Termeer, “A 10-b 40-MHz 0.8-µm CMOS Current-Output D/A Converter,”IEEE J. of Solid-State Circuits, vol. 26, no. 7, pp 917-21, July 1991
[3] J. Bastos, M. Steyaert, and W. Sansen, “A High Yield 12-bit 250-MS/s CMOS DConverter,” inProc. of the IEEE 1996 Custom Integrated Circuits Conf. (CICC’96,pp. 431-4, San Diego, CA, USA, May 1996
[4] J. Bastos, M. Steyaert, A. Pergoot, and W. Sansen, “Mismatch characterizatiosubmicron MOS transistors,”,Analog Integrated Circuits and Signal Processin,vol. 12, no. 2, pp. 95-106, Feb. 1997
[5] M. Benkaïs, S. Le Masson, and P. Marchegay, “A/D Converter CharacterizationSpectral Analysis in ‘Dual-Tone’ Mode,”IEEE Trans. on Instrumentation andMeasurement, vol. 44, no. 5, p. 940-4, Oct. 1995
[6] I. Berggren, “Analog Front End for xDSL,”Private communication, EricssonTelecommunications AB, Sweden
[7] J. C. M. Bermudez, S. N. Filho, R. Seara, and L. Mayer, “A New Improved IteratMethod for Compensation of the (sin x)/x Frequency Response Distortion,” inProc.of the 1990 IEEE Int’l Symp. on Circuits and Systems (ISCAS’90), vol. 4, pp. 2793-6,New Orleans, LA, USA, May 1-3, 1990
[8] A. Biman and D. G. Nairn, “Trimming of Current Mode DACs by Adjusting Vt,” inProc. of the 1996 IEEE Int’l Symp. on Circuits and Systems (ISCAS’96), vol. 1, pp. 33-6, Atlanta, GA, USA, May 12-15, 1996
[9] S. Björklid, High Speed CMOS DAC for Direct Digital Signal Synthesis, Final Work,Linköping University, Sweden, 1998, LiTH-IFM-EX-742
1
References
ed
log
b.
r
ins
e,”
e-
g
s,”
V
s,71-
V
e
f ae
[10] S. Boiocchi, S. Brigati, G. Caiulo, and F. Maloberti, “Self-Calibration in High SpeCurrent Steering CMOS D/A Converters,” inProc. of the 2nd Int’l Conf. on ‘AdvancedA-D and D-A Conversion Techniques and their Applications’, pp. 148-52, London,UK, 1994
[11] J. C. Candy and G. C. Temes,Oversampling Delta-Sigma Data Converters, IEEE,New York, NY, USA, 1992, ISBN 0-87942-281-5
[12] Z.-Y. Chang, D. Macq, D. Haspeslagh, P. Spruyt, and B. Goffart, “A CMOS AnaFront End Circuit for an FDM-Based ADSL System,” inProc. of the 1995 IEEE Int’lSolid-State Circuits Conf. (ISSCC’95), pp. 330-1, 389, San Francisco, CA, USA, Fe1995
[13] S.-Y. Chin and C.-Y. Wu, “A 10-b 125-MHz CMOS Digital-to-Analog Converte(DAC) with Threshold-Voltage Compensated Current Sources,”IEEE J. of Solid-stateCircuits, vol. 29, no. 11, pp. 1374-80, Nov. 1994
[14] J. S. Chow, J. A. C. Bingham, and M. S. Flowers, “Mitigating Clipping NoiseMulti-Carrier Systems,” inProc. of the 1997 IEEE Int’l Conf. on Communication(ICC’97), vol. 2, pp. 715-19, Montreal, Canada, June 8-12, 1997
[15] P. Conway and D. Yu, “DAC design offers high-speed linear performancMicrowaves & RF, vol. 33, no. 8, pp. 95-96, 98, 100, 102, Aug. 1994
[16] M. D. Dallet, Contribution à la Caractérisation des Convertisseurs AnalogiquNumériques: Evaluation des Méthodes et Mise en Ouvre de Noveaux Procédés, Theseno. 1249, L’universite de Bordeaux I, France, Jan. 1995
[17] F. Dudek, B. M. Al-Hashimi, and M. Moniri, “CMOS Equaliser for Compensatinsinc(x) Distortion of Video D/A Converters,”Electronics Letters, vol. 33, no. 19,pp. 1618-19, Sept. 1997
[18] C. Dunn and M. Sandler, “Adaptive Sigma-Delta Modulation for use in DACElectronics Letters, vol. 32, no. 10, pp. 867-8, May 1996
[19] J. Erlands,Design of Low-Distortion High-Speed Line Drivers in a Standard 5CMOS Process for VDSL Applications, Final Work, Linköping University, Sweden,1998, LiTH-ISY-EX-1906
[20] P. J. Fish,Electronic Noise and Low Noise Design, Macmillan, Basingstoke, UK,1993, ISBN 0-333-57310-2
[21] N. J. Fliege,Multirate Digital Signal Processing: Multirate Systems, Filter BankWavelets, John Wiley & Sons, Chichester, West Sussex, England, 1994, ISBN 0-493976-5
[22] J. M. Fournier and P. Senn, “A 130-MHz 8-b CMOS Video DAC for HDTApplications,”IEEE J. of Solid-State Circuits, vol. 26, no. 7, pp 1073-7, July 1991
[23] J. E. Franca and J. C. Vital, “Low-Cost CMOS Algorithmic Digital-AnaloguConvertor for High-Frequency Applications,” inProc. of the 1990 IEEE CustomIntegrated Circuits Conf. (CICC’90), pp. 6.7/1-4, New York, NY, USA, 1990
[24] I. Galton, “Spectral Shaping of Circuit Errors in Digital-to-Analog Converters,”IEEETrans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44,no. 10, pp. 808-17, Oct. 1997
[25] P. E. de Haan, S. van den Elshout, E. A. M. Klumperink, and K. Bult, “Analysis oCurrent Mode MOST-Only D-A Converter,” inProc. of the 20th European Solid-StatCircuits Conf. (ESSCIRC’94), pp. 188-91, Ulm, Germany, Sept. 22-24, 1994
2
References
ases
face
wer
,
ion77,
oral
rs91-
ent-
/A
citor
a
[26] S. Haykin,Digital Communication, John Wiley & Sons, New York, NY, USA, 1988,ISBN 0-471-633775-0
[27] B. Hedberg, “Wideband Radio System,”Private communication, Ericsson RadioSystems AB, Sweden
[28] P. Hendriks, “Specifying Communication DACs,”IEEE Spectrum, vol. 34, no. 7,pp. 58-69, July 1997
[29] P. Hendriks, “Tips for Using High-Speed DACs in Communications Design“,IEEEElectronic Design, no. 2, pp. 112-8, Jan. 1998
[30] B. G. Henriques and J. E. Franca, “High-Speed D/A Conversion with Linear Phsinx/x Compensation,” inProc. of the 1993 IEEE Int’l Symp. on Circuits and System(ISCAS’93), vol. 2, pp. 1204-7, Chicago, IL, USA, May 3-6, 1993
[31] B. G. Henriques and J. E. Franca, “A High-Speed Programmable CMOS InterSystem Combining D/A Conversion and FIR Filtering,”IEEE J. of Solid-StateCircuits, vol. 29, pp. 972-7, no. 8, Aug. 1994
[32] B. G. Henriques, K. Kananen, J. E. Franca, and J. Rapeli, “A 10 Bit Low-PoCMOS D/A Converter with On-Chip Gain Error Compensation,” inProc. of the 1995IEEE Custom Integrated Circuits Conf. (CICC’95), pp. 215-8, Santa Clara, CA, USAMay 1995
[33] M. Ismail and T. Fiez,Analog VLSI: Signal and Information Processing, McGraw-Hill, New York, NY, USA, 1994, ISBN 0-07-113387-9
[34] C. Jansson,CMOS Signal Conditioned Sensor Arrays and A/D-D/A ConversTechniques, Linköping Studies in Science and Technology, Dissertation no. 31995, ISBN 91-7871-521-0
[35] H. T. Jensen and I. Galton, “A Low-Complexity Dynamic Element Matching DAC fDirect Digital Synthesis,”IEEE Trans. on Circuits and Systems II: Analog and DigitSignal Processing, vol. 45, no. 1, pp. 13-27, Jan. 1998
[36] H. Johansson,Synthesis and Realization of High-Speed Recursive Digital Filte,Linköping Studies in Science and Technology, Dissertation no. 534, 1998, ISBN7219-207-0
[37] D. A. Johns and K. Martin,Analog Integrated Circuit Design, John Wiley & Sons,New York, NY, USA, 1997, ISBN 0-471-14448-7
[38] B. E. Jonsson, “Design of Power Supply Lines in High-Performance SI and CurrMode Circuits,” inProc. of the 15th Norchip Sem., pp. 245-50, Tallinn, Estonia, Nov.10-11, 1997
[39] I. H. H. Jørgensen and S. A. Tunheim, “A 10-bit 100MSamples/s BiCMOS DConverter,”Analog Integrated Circuits and Signal Processing, vol. 12, pp. 15-28,1997
[40] P. Ju, K. Suyama, P. Ferguson Jr., and W. Lee, “A Highly Linear Switched-CapaDAC for Multi-Bit Sigma-Delta D/A Applications,” inProc. of the 1995 IEEE Int’lSymp. on Circuits and Systems (ISCAS’95), vol. 1, pp. 9-12, Seattle, WA, USA, April29 - May 3, 1995
[41] J.-W. Kim, B.-M. Min, J.-S. Yoo, and S.-W. Kim, “An Area-Efficient Sigma-DeltDAC with a Current-Mode Semidigital IFIR Reconstruction Filter,” inProc. of the1998 IEEE Int’l Symp. on Circuits and Systems (ISCAS’98), Monterey, CA, USA, May31 - June 3, 1998
3
References
”,
s,”
e-d
g
gd
00-
T-s
he
eir
,
/s
al
of
3-
[42] I. Koren, Computer Arithmetic Algorithms, Prentice-Hall, Englewood Cliffs, NJ,USA, 1993, ISBN 0-13-151952-2
[43] K. S. Kundert, The Designer’s Guide to Spice and Spectre, Kluwer AcademicPublishers, Boston, MA, USA, 1995, ISBN 0-7923-9571-9
[44] B. Leung, “BiCMOS Current Cell and Switch for Digital-to-Analog ConvertersIEEE J. of Solid-State Circuits, vol. 28, no. 1, pp. 68-71, Jan. 1993
[45] G. Liang and D. Allstot, “FIR Filtering Using CMOS Switched-Current Techniquein Proc. of the 1990 IEEE Int’l Symp. on Circuits and Systems (ISCAS’90), vol. 3,pp. 2291-3, New Orleans, LA, USA, May 1-3, 1990
[46] H. Lin, J. Barreiro da Silva, B. Zhang, and R. Schreier, “Multi-Bit DAC with NoisShaped Element Mismatch,” inProc. of the 1996 IEEE Int’l Symp. on Circuits anSystems (ISCAS’96), vol. 1, pp. 235-8, Atlanta, GA, USA, May 12-15, 1996
[47] T. Lin and H. Samulei, “A 200-MHz CMOS x/sin(x) Digital Filter for CompensatinD/A Converter Frequency Response Distortion,”IEEE J. of Solid-State Circuits,vol. 26, no. 9, pp. 1278-85, Sept. 1991
[48] E. Liu and A. Sangiovanni-Vincentelli, “Verification of Nyquist Data Converter UsinBehavioral Simulation,”IEEE Trans. on Computer Aided Design of IntegrateCircuits and Systems, vol. 14, no. 4, pp. 493-502, April 1995
[49] K. Maio, S. I. Hayashi, M. Hotta, T. Watanabe, S. Ueda, and N. Yokozama, “A 5MHz 8-bit D/A Converter,”IEEE J. Solid-State Circuits, vol. 20, no. 6, pp. 1133-7,Dec. 1985
[50] D. J. G. Mestdagh, P. Spruyt, and B. Biran, “Analysis of Clipping Effect in DMBased ADSL Systems,” inProc. of the 1994 IEEE Int’l Conf. on Communication(ICC’94), vol. 1, pp. 293-300, New Orleans, LA, USA, May 1994
[51] R. C. S. Morling, I. Kale, C. W. Tsang, S. J. Morris, G. Hague, and C. Foran, “TDesign of a Sigma-Delta Codec for Mobile Telephone Applications,” inProc. of the2nd Int’l Conf. on ‘Advanced A-D and D-A Conversion Techniques and thApplications’, pp. 11-47, IEE, London, UK, 1994
[52] D. G. Nairn, “A 130µW DAC for Low-Power Video Systems,” inProc. of the 1994IEEE Custom Integrated Circuits Conf. (CICC’94), pp. 511-14, San Diego, CA, USA1994
[53] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, “A 10-b 70-MSCMOS D/A Converter,”IEEE J. of Solid-State Circuits, vol. 26, no. 4, pp. 637-42,Apr. 1991
[54] A. Netterstrom, “Using Digital Pre-Distortion to Compensate for Analog SignProcessing Errors,” inProc. of the IEEE 1990 Int’l Radar Conf., pp. 243-8, Arlington,VA, USA, May 7-10, 1990
[55] M. J. M Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching PropertiesMOS Transistors,”IEEE J. of Solid-State Circuits, vol. 24, no. 5, pp. 1433-9, Oct.1989
[56] R. J. van de Plassche, Integrated Analog-to-Digital and Digital-to-AnalogConverters, Kluwer Academic Publishers, Boston, MA, USA, 1994, ISBN 0-7929436-4
[57] J. M. Rabaey,Digital Integrated Circuits: a Design Perspective, Prentice Hall,Englewood Cliffs, NJ, USA, 1996, ISBN 0-13-394271-6
4
References
/A
-bits
de
Data
t-
,
h-
g
or
0-
ata
of
[58] T. S. Rathore, “Optimised Weighted-Resistor Digital to Analogue Converter,”IEEProc. Circuits, Devices, and Systems, vol. 145, no. 3, pp. 197-200, June 1998
[59] T. Ritoniemi, V. Eerola, T. Karema, and H. Tenhunen, “Oversampled A/D and DConverters for VLSI System Integration,” inProc. of the 3rd Annual IEEE ASICSeminar and Exhibit, pp. P8/7.1-12, New York, NY, USA, 1990
[60] T. Ritoniemi, T. Karema, and H. Tenhunen, “Design of Stable High Order 1Sigma-Delta Modulators,” inProc. of the 1990 Int’l Symp. on Circuits and System(ISCAS’90), vol. 4, pp. 3267-70, New Orleans, LA, USA, May 1-3, 1990
[61] R. J. Romanczyk and B. H. Leung, “BiCMOS Circuits for High Speed Current MoD/A Converters,”IEEE J. of Solid-State Circuits, vol. 30, no. 8, pp. 923-34, Aug. 1995
[62] R. W. Stewart and E. Pfann, “Oversampling and Sigma-Delta Strategies forConversion,” Electronics & Communication Engineering Journal, vol. 10, no. 1,pp. 37-47, Feb. 1998
[63] D. K. Su and B. A. Wooley, “A CMOS oversampling D/A Converter with a CurrenMode Semi-Digital Reconstruction Filter,” inProc. of the 1993 IEEE Int’l Solid-StateCircuits Conf. (ISSCC’93), pp. 230-1, San Fransisco, CA, USA, 1993
[64] N. Tan, “A 1.5-V 3-mW 10-bit 50 MS/s CMOS DAC with Low Distortion and LowIntermodulation in Standard Digital CMOS Process,” inProc. of the 1997 IEEECustom Integrated Circuits Conf. (CICC’97), pp. 599 - 602, Santa Clara, CA, USAMay 1997
[65] N. Tan, “Design and Implementation of High-Speed Bipolar DAC,” inProc. of the15th Norchip Sem., pp. 320-7, Tallinn, Estonia, Nov. 10-11, 1997
[66] N. Tan, E. Cijvat, and H. Tenhunen, “Design and Implementation of HigPerformance CMOS D/A Converter,” inProc. of the 1997 IEEE Int’l Symp. onCircuits and Systems (ISCAS’97), Vol I. pp. 421-4, Hong Kong, June 9-12, 1997
[67] N. Tan, J. Erlands, and J. J. Wikner, “Fully Differential Line Driver,” PendinSwedish Patent, 1998
[68] N. Tan and J. J. Wikner, “A CMOS Digital-to-Analog Converter Chipset fTelecommunication,”IEEE Magazine on Circuits and Devices, vol. 13, no. 5, pp. 11-16, Sept. 1997
[69] C. Tellambura, “Upper Bound on the Peak Factor of N-Multiple Carriers,”ElectronicsLetters, vol. 33, no. 19, pp. 1608-9, 1997
[70] B. J. Tesch and J. C. Garcia, “A Low Glitch 14-b 100MHz D/A Converter,”IEEE J.of Solid-State Circuits, vol. 32, no. 9, pp. 1465-9, Sept. 1997
[71] C. Toumazou, J. B. Hughes, and N. C. Battersby,Switched-Currents: an AnalogueTechnique for Digital Technology, Peter Peregrinus, Stevenage, UK, 1993, ISBN86341-294-7
[72] H. Träff and J. J. Wikner, “Snapshot Sampling for Ultra-High Speed DAcquisition,” Electronics Letters, vol. 33, no. 13, pp. 1137-9, June 1997
[73] H. Tuinhout, M. J. M. Pelgrom, R. Penning de Vries, and M. Vertregt, “EffectsMetal Coverage on MOSFET Matching,” inProc. of the Int’l Electron DevicesMeeting (IEDM’96), pp. 735-8, San Fransisco, CA, USA, Dec. 8-11, 1996
[74] A. Vachoux, “Analog and Mixed-Signal Extensions to VHDL,”Analog IntegratedCircuits and Signal Processing, vol. 16, no. 2, pp. 185-200, June 1998
5
References
ic
e of
ors
mas
ing
ith
merlic
merlic
log
d
es,le-
s,
[75] J. J. Wikner and N. Tan, “Influences of Circuit Imperfections on the DynamPerformance of DACs,” inProc. of the 15th Norchip Sem., pp. 336-43, Tallinn,Estonia, Nov. 10-11, 1997
[76] J. J. Wikner and N. Tan, “Influences of Circuit Imperfections on the PerformancDACs,” Analog Integrated Circuits and Signal Processing, To be published.
[77] J. J. Wikner and N. Tan, “Modelling of CMOS Digital-to-Analog Converters fTelecommunication,” inProc. of the 1998 IEEE Int’l Symp. on Circuits and System(ISCAS’98), Monterey, CA, USA, May 31 - June 3, 1998
[78] J. J. Wikner and N. Tan, “Modelling of DACs for Telecommunication,”InternalReport, Linköping University, Sweden, 1997, LiTH-ISY-R-1983
[79] X. Xu, G. C. Temes, and R. Schreier, “The Implementation of Dual-Truncation SigDelta D/A Converters,” inProc. of the 1992 IEEE Int’l Symp. on Circuits and System(ISCAS’92), vol. 2, pp. 597-600, San Diego, CA, USA, May 1992
[80] L. Ye and H. W. Carter, “Analog Behavior Modeling and Processing usAnaVHDL,” Analog Integrated Circuits and Signal Processing, vol. 16, no. 2,pp. 173-80, June 1998
[81] J. Yuan and C. Svensson, “New Single-Clock CMOS Latches and Flipflops wImproved Speed and Power Savings,”IEEE J. of Solid-State Circuits, vol. 32, no. 1,pp. 62-9, Jan. 1997
[82] “American National Standard for Telecommunications – Network and CustoInstallation Interfaces – Assymetric Digital Subscriber Line (ADSL) MetalInterface,” in draft American National Standard for Telecommunications, ANSIT1.413, Aug. 1995
[83] “American National Standard for Telecommunications – Network and CustoInstallation Interfaces – Assymetric Digital Subscriber Line (ADSL) MetalInterface,” in draft American National Standard for Telecommunications, ANSIT1E1.4/97-007R6, Jan. 1998
[84] URL: “www.analog.com/product/Product_Center.html”, Data Sheets, AnaDevices, USA
[85] URL: “www.maxim-ic.com/efp/DAconv.htm”, Data Sheets, Maxim IntegrateProducts, Sunnyvale, CA, USA
[86] URL: “www.t1.org/t1e1/_e14home.htm”, Technical Subcommittee T1E1, InterfacPower & Protection of Networks, American National Standard for Tecommunications
[87] URL: “www.xdsl.com”, Information site, TeleChoice, Northglenn, CO, USA
[88] URL: “www.adsl.com”, Information site, ADSL Forum, Fremont, CA, USA
[89] URL: “www.aware.com”, Information site, Aware, Bedford, MA, USA
[90] URL: “www.itu.int”, Information site, ITU Telecom Information Exchange ServiceSwitzerland
6
Licentiate ThesesDivision of Electronics Systems
Department of Electrical EngineeringLinköpings universitet
Sweden
Andersson K.-G.: Implementation and Modeling of Modular Digital SignalProcessors, Linköping Studies in Science and Technology, Thesis No. 608, 1997
Melander J.: Design of SIC FFT Architectures, Linköping Studies in Science andTechnology, Thesis No. 618, 1997.
Widhe T.: Efficient Implementation of FFT Processing Elements, LinköpingStudies in Science and Technology, Thesis No. 619, 1997.
Johansson H.: High-Speed Recursive Digital Filters, Linköping Studies in Scienceand Technology, Thesis No. 620, 1997
Karlsson Rudberg M.: System Design of Image Decoder Hardware, LinköpingStudies in Science and Technology, Thesis No. 657, 1997.
Gustavsson M.: Analog Interfaces in a Digital CMOS Process, Linköping Studiesin Science and Technology, Thesis No. 662, 1997.
Karlsson M.: Distributed Arithmetic: Design and Applications, Linköping Studiesin Science and Technology, Thesis No. 696, 1998.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004 159
Mismatch and Dynamic Modeling of Current Sourcesin Current-Steering CMOS D/A Converters:
An Extended Design ProcedureMiquel Albiol, José Luis González, Member, IEEE, and Eduard Alarcón, Member, IEEE
Abstract—This paper presents an improved modeling of the ef-fect of random mismatch and current source transient switchingbehavior on the performance of current-steering CMOS digital-to-analog converters (DACs). The work considers two current sourcecell topologies, namely a simple cell and a cascoded cell, obtainingthe relation of transistors design parameters to the static and dy-namic models. On the one hand, a mismatching statistical anal-ysis is applied to all the transistors of the current source circuit,which allows to define design expressions relating the circuit pa-rameters to the DAC specifications without the need of arbitrarydesign margins or Monte Carlo simulations. On the other hand,improved analysis of the current source switching characteristicsprovides a more realistic modeling of the relation between transis-tors sizes and output current settling time. By including these twoimproved models into the usual design procedure, circuit sizing foroptimum settling time and proper static behavior can be obtainedanalytically, reverting in smaller current source area, and, hence,in an overall DAC area reduction.
MODERN broad-band communication integrated circuitsrequire as fundamental subcircuits digital-to-analog
converters (DACs) exhibiting both high speed and high reso-lution [1]. Wide bit-count DACs working at sampling clockfrequencies in the range of hundreds of megahertz will continueto be required, hence dictating Nyquist-rate data conversion, asfor instance to convert digital bitstreams into continuous-timesignals prior to up-conversion mixers preceding RF transmittersin wireless systems or to drive digital cable communicationsmodems. The development of future mobile communicationsystems (including both third–generation (3G) terminalsand basestations) as well as the prospective use of ubiqui-tous communication systems will continue the trust towardhigh-performance DAC conversion stages.
A CMOS current-steering DAC is the usual choice for thistype of application since that topology best suits the aforemen-
Manuscript received January 31, 2003; revised September 30, 2003. Thiswork was supported in part by the Spanish MCYT and EU FEDER programunder Project TIC2001-2337 and Project TIC2001-2157-C02-01. This paperwas recommended by Guest Editors A. Rodríguez-Vázquez, F. Mediero, andO. Feely.
The authors are with the Electronic Engineering Department, PolytechnicUniversity of Catalunya (UPC), Barcelona 08034, Spain (e-mail: [email protected]).
Digital Object Identifier 10.1109/TCSI.2003.821287
Fig. 1. Current-steering DAC architecture.
tioned requirements. Fig. 1 shows a typical block diagram of an-bit current-steering DAC. The input word is segmented into
the least significant bits (LSBs) that switch a binary weightedarray and the most significant bits (MSBs) that con-trol the switching of a unary current source array. The inputbits are thermometer decoded to individually switch each of the
unary sources. A dummy decoder is placed in the binaryweighted input path to equalize the delay. A latch is placed justbefore the switch transistors of each current source to minimizetiming errors. Latches and switches are grouped in a separatedarray placed between the decoders and the current source arraysin order to isolate these noisy digital circuits from the sensitiveanalog circuits that generate precise currents.
Since all current sources have the same circuit topology, onlythe sizes of their transistors are scaled from a basic currentcell circuit (usually the LSB current source) according to theirweights. Fig. 2 shows the two most usual topologies for the cur-rent source cell circuit. The basic circuit includes the currentsource transistor CS and two complementary switch transistors(SW and ), as shown in Fig. 2(a). Some cases require an ad-ditional cascode transistor (CAS) in series with the CS transistorto increase the cell output impedance and improve node isola-tion, as shown in Fig. 2(b). Bias voltages for transistors CS andCAS are common to all current sources. Complementary con-trol signals for SW transistors of both current sources are gener-ated by the corresponding latch and output driver circuits. TheHIGH level of these signals is adjusted in such a way that the SWtransistor in the ON state is actually operating as a first cascodetransistor. If the CAS transistor is used, it operates as a secondcascode transistor that further increases the output impedance of
160 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004
Fig. 2. Current source cell topologies. (a) Basic unary current source. (b)Cascoded unary current source.
the current source. This impedance boosting is needed in orderto fulfil requirements for high-resolution high-bandwidth cur-rent-steering DACs [2].
DAC performance is specified both through static parameters,namely integral nonlinearity (INL), differential nonlinearity(DNL), and parametric yield, as well as dynamic parameters,namely glitch energy, settling time, and spurious-free dynamicrange (SFDR) [3]. Static performance is mainly dominatedby systematic and random mismatch errors. Systematic errorscaused by process, temperature, and electrical slow variationgradients are almost cancelled by proper layout techniques [4].Random errors are determined solely by random mismatch dueto fast process variation gradients.
The design of a DAC is carried out at three levels: architec-ture design, circuit design, and physical design. In the usual de-sign procedure, the degree of segmentation ( over ) is de-cided at the architecture level by combining static and dynamicspecifications and overall minimum area requirements [5]–[7].Subsequently, the basic current cell circuit (usually the LSB cur-rent source) is designed by determining the sizes and bias volt-ages for the different transistors and the voltage levels requiredfor the switches’ control signals. Most of the DAC static anddynamic performance is determined by the performance of thebasic current source cell. The circuit design of the rest of thecomponents within the DAC architecture is mainly influencedby speed requirements. The digital binary-to-thermometer de-coder must be fast enough so that the converter speed is solely
limited by the current sources settling time. Latches should alsobe designed to be fast enough whilst their output driver shouldbe sized to generate the desired levels for the switches’ controlsignals, which are determined during the current cell circuit de-sign procedure. The timing of these control signals is also ofutmost relevance to minimize the glitches at the DAC output byavoiding both complementary SW transistors to be switched OFF
simultaneously during the output transition [8]. Finally, speciallayout techniques [4], [9] are applied to floorplan the differentDAC architecture components, especially the current source ar-rays, so as to compensate for systematic mismatch errors andisolate the sensitive analog section from the digital section.
This work focuses on the current cell design procedure. Twomain contributions are presented. The first one, presented inSection II, is an extended modeling of random mismatch ef-fects which considers statistical variations in all the transistorsof the current source circuit and studies how they impinge uponthe overall DAC static performance. The second contribution ofthe work, presented in Section III, addresses the dynamic mod-eling of current source switching transient behavior, extendingthe previous work of [11]. The model presented in this sec-tion allows us to properly describe the dynamic performanceof the DAC and calculate a realistic settling time. In Section IV,those models are embedded within a complete design procedurefor the optimum sizing of the current source cell of high-speedhigh-accuracy current-steering DACs. Finally, Section V pro-vides the conclusions of the work.
II. STATIC PERFORMANCE
Static and dynamic performances of current-steering DACsare mostly determined by the current sources accuracy, nonin-finite output impedance, and switching time. In the following,the dependencies of the DAC static performance on the cur-rent sources’ accuracy and output impedance constrained by thetransistors’ operating region are presented. Afterwards, the im-plications of those static and statistical constraints in the sizingdesign procedure of the current cell circuit are presented andcompared with other previously published approaches.
A. Current Source Accuracy
The transistor CS of Fig. 2 sets the cell’s current. Based on thestatistical mismatch model of [12], a relation exists between theCS transistor area, its overdrive voltage, and its relative accuracy(we will refer in the following to the LSB current source)
(1)
where is the cell’s current, and are the CStransistor width and length, respectively, and aremismatch process constants for the transistor large signal gainand threshold voltage, respectively, is the CS overdrivevoltage, i.e., , where is the CS gate-to-sourcevoltage and is the threshold voltage, and is thevariance of the current source value due to random mismatch.
ALBIOL et al.: MISMATCH AND DYNAMIC MODELING OF CURRENT SOURCES IN CURRENT-STEERING CMOS DACS 161
The aspect ratio of the CS transistors is determined bythe drain current and the overdrive voltage according to theMOSFET saturation drain current expression
(2)
The CS transistor dimensions are univocally determined oncethe overdrive voltage is chosen and vice versa, according to (1)and (2). The INL of a set of theoretically equal manufacturedDACs is a statistical process that depends on process variations.Systematic mismatch is addressed at the physical design phase.If only random mismatch is considered, the worst case INL, freeof offset and gain errors, is found at the mid code in the DACstatic transfer function. In this case, the INL error for an -bitDAC is due to the combination of LSB current sources(independently of the DAC segmentation1 ). The LSB currentsource minimum relative accuracy required to achieve a certainINL upper bound with a given statistical yield, as a function ofthe DAC resolution, is [10], [13]
(3)
where is the inverse cumulative normal distribution,and is the percentage of manufactured DACs with an INLsmaller or equal than the upper bound .
B. Current Source Output Impedance
The small-signal output impedance for thecurrent source topology of Fig. 2(a) is given by
(4)
where is the small-signal transconductance andis the drain-to-source small-signal resistance. The labels
are used here and in the rest of the paperas accompanying subscripts or superscripts to indicate the tran-sistor to which the parameters, voltages, or other expressionsrefer.
For the topology of Fig. 2(b), the outputimpedance is given by
(5)
Since the drain current is a value fixed by the DAC spec-ifications, the only degree of freedom available to design thetransconductances is either the overdrive voltage or the aspectratio
(6)
1This is due to the fact that a source of value k LSBs is actually obtained bycombining k sources of LSB value in parallel, instead of a single source withtransistors k times wider than the LSB source transistors.
The drain-to-source impedance, considering channel lengthmodulation, is expressed by
with (7)
where is the channel length modulation parameter, thedrain-to-source saturation current, is a technology constant[14], is the drain-to-source voltage, and is the built-injunction potential, which is also a technology constant.
Combining (4), (5), and (7) and expressing thedrain-to-source voltages as function of node voltages (SW andCAS gate bias voltage, and the output node minimum voltage
, which is the worst case for output impedance) yields
(8)
for the topology and
(9)
for the topology.The optimum SW and CAS gate bias voltages concerning the
output impedance are found by differentiating (8) and (9) withrespect to and . For the topology, the SWgate bias voltage that maximizes output impedance is found as
(10)
whereas for the topology the SW and CASgate bias voltages that maximize output impedance are
(11)
C. Analysis of the Current Source Circuit TransistorsOperating Region
Despite the fact that the overdrive voltage in (1) shouldbe maximized to minimize the CS area, it should be smallenough to allow the other transistors (SW and CAS if present)to work in saturation (the region in which higher outputimpedance is obtained) in any situation.
1) Simple Current Cell : Applying the MOSFETsaturation condition to all transistorsin the current source of Fig. 2(a) leads to the definition of a
162 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004
voltage range in which the SW gate bias voltage must be kept inorder to allow both CS and SW transistors to work in saturation
(12)
A solution exists for (12) if and only if the difference betweenthe upper and lower bounds is positive (i.e., the lower bound forthe SW gate voltage is smaller than the upper bound
. This determines an upper bound for the addition of thetwo transistors’ overdrive voltages
(13)
Resuming the saturation constraint of (12), note that the mid-point between the upper and lower bounds for the SW gate biasvoltage corresponds to the optimum voltage that maximizes thedc output impedance found in Section II-B
(14)This is not a coincidence, since this optimum SW gate voltage
places the operating point of both SW and CS transistors at thesame voltage distance from the triode region.
If there are no other criteria for choosing the overdrive volt-ages, such as dynamic output impedance, settling time, etc., itwould be interesting to choose the combination of overdrivevoltages that leads to the minimum area solution. This usu-ally corresponds to an SW transistor with minimum length andwidth, from which the SW overdrive voltage is derived, and themaximum CS overdrive voltage that verifies (13), provided thatthe corresponding CS transistor width and length obtained from(1) and (2) satisfy the technology minimum size constraint. Bydoing this, the operating points of both transistors are found justat the limit between the triode and the saturation regions.
In the previously published current source sizing procedure[10], which is representative of the usual design process for thistype of DAC, only the mismatch error of the current source tran-sistor is considered. Hence, an arbitrary safety margin isintroduced as follows in the saturation constraint (13) to preventthe transistors to enter triode region due to process variations:
(15)
If not only the mismatch errors of the CS transistor, but alsothe switches and additional cascode transistors mismatch errorsare taken into account, the overall basic current cell circuit canbe optimized without introducing that arbitrary safety margin.Alternatively, this safety margin can be found by performingparametric Monte Carlo simulations. The model that will be pre-sented in the following avoids either the arbitrary design marginor the time-consuming Monte Carlo simulations.
In order to include the effects of process variations in thesaturation condition of (12), the statistical variation of the twobounds for the SW gate bias voltage is modeled by means of anormal distribution. The variance of the upper and lower boundsis found, first by expressing these bounds as a function of the
random variables of the circuit that appear when mismatchingeffects are taking into account:
(16)
and subsequently by calculating the partial derivatives of theseexpressions with respect to each one of the random variables(that are considered independent). In this way, the variance ofthe upper bound for the SW gate voltage that guarantees satu-ration when random mismatch effects are taken into account isfound as
(17)
Similarly, the variance of the lower bound yields
(18)
In (17) and (18), only node voltages (except biasing gate volt-ages), current values, and load impedance have been consideredas being random variables affected by mismatching. In order totake into account also die-to-die process variations, the worstcase process parameter values (min or max) should be used in-stead of the typical ones. In the case of , the only param-eter affected by die-to-die process variations is the SW thresholdvoltage ( is always the same assuming that the full-scaleDAC output value is adjusted to eliminate offset and gain er-rors). Therefore, the minimum SW threshold voltage should beused. In the case of , the variation of the SW and CSthreshold voltage compensate for each other, as they appear in(16) with opposite sign. Therefore, only the die-to-die variationof the affects the lower bound and the worst case is theminimum value for that process.
To find an appropriate value for the SW gate voltage, theupper bound must be larger than the lower bound in a given per-centage of the cases expressed by . Fig. 3 illustratesthis tradeoff. To accomplish that the saturation constraint is ful-filled with a given probability , the optimum of theSW gate voltage found in (10), which is now the mean value ofa random variable, has to verify that
(19)
ALBIOL et al.: MISMATCH AND DYNAMIC MODELING OF CURRENT SOURCES IN CURRENT-STEERING CMOS DACS 163
Fig. 3. Graphical representation of the constraint (19).
which can be expressed also by the following equation:
(20)
which is the same as
(21)
Here, since only one half of the normal distribution has tobe considered, , where isrelated to the previously defined INL by
(22)
because the worst case of the bounds variance for the severalcurrent sources of the DAC is found in the LSB current source(since its area is the smallest of all the current sources), and itstwo complementary SW transistors must be inside both of thebounds with the same probability.
The expression of (21) represents a saturation constraintmore realistically than (15) for the CS and SW current cellcircuit, where an arbitrary safety margin was included. Thesafety margin appearing in (21) is not arbitrary nor needs tobe found using parametric Monte Carlo simulation. It canbe related to other circuit parameters and mismatch process
parameters using (17) and (18), which enables us to include(21) in an analytical optimization process.
2) Cascoded Current Cell : Applying theMOSFET saturation condition toall transistors in the current source of Fig. 2(b) leads to the def-inition of two voltage ranges, one for the SW gate bias voltage,and another for the CAS gate bias voltage as shown in (23) atthe bottom of the page.
The mid-points of the above voltage ranges also correspondto the optimum SW and CAS gate voltages, respectively, thatmaximize the current source output impedance found in Sec-tion II-B for this topology. Each range has two bounds, and thesefour bounds can also be expressed as a function of the randomvariables of the design when random mismatch errors are con-sidered. The variance of the bounds can be estimated in the sameway as that in Section II-C1. Using the same criteria as in the
topology case, we have
(24)
which in this case of the topology lead to twosaturation conditions
(25)
The equations in (25) are analytical expressions that dependon circuit and mismatch parameters. They will be used in the
(23)
164 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004
design procedure of Section IV for the optimum sizing of thecurrent cell topology.
D. Implications of the Extended Static PerformanceConstraints in the Design Procedure
In this subsection, the extended modeling of the mismatcheffects presented in Sections II-A–C (including the optimumoutput impedance biasing) are related to the circuit sizing for thetwo topologies. The occupied area saving that is obtained in thedesign by using the proposed extended modeling is contrastedwith previous design approaches.
1) Simple Current Cell : In the case of thetopology, (1) and (2) leave only one degree of freedom for
the CS transistor, namely the overdrive voltage (which univo-cally determines the CS gate bias voltage). The SW transistorthen introduces four more design variables: , , over-drive voltage, and gate bias voltage. For the SW transistor theoverdrive voltage and the width to length ratio arealso related by the current value, so only two of them are reallyfree parameters. The optimum SW gate bias voltage (i.e., the ON
gate voltage for the switch transistors) can be calculated using(10) as a function of the overdrive voltages, so only two de-grees of freedom are left: the SW area and its overdrive voltage.The three degrees of freedom left for the overall circuit are con-strained by the saturation condition of (21). They can be usedto optimize other criteria, as for example the dynamic perfor-mance, as will be shown in Section III.
In order to compare the proposed saturation statistical modelwith the literature, a usual assumption is made which is thatthe minimum area current cell is a prior target (which corre-sponds to the worst case mismatch). In this sense, minimumarea CS and SW transistor are chosen, and only the SW tran-sistor overdrive voltage is left as a variable. By doing this, theSW transistor must have either minimum length or minimumwidth, depending on its overdrive voltage. The maximum CSoverdrive voltage (its minimum area) is found as a function ofthe SW overdrive voltage using (21). Therefore, the SW over-drive voltage is the only degree of freedom left. Fig. 4 comparesthe saturation conditions of (15) and (21) for a 12-b DAC de-signed in a standard 0.35- m process with a specifications sim-ilar to [10] and other smaller safety margins. Fig. 4(a) depictsthe maximum CS overdrive voltage and Fig. 4(b) shows the min-imum CS and overall current cell area. Both graphs are repre-sented against the SW overdrive voltage assuming a minimumcurrent cell area requirement. The smallest area achieved by ap-plying the extended modeling and the saturation constraint of(21) is almost a 70% of the smallest area that will be obtained ifthe arbitrary safety margin of 500 mV used in [10] is considered,this indicating that the latter approach is notably pessimisticconcerning process variations effects. The use of smaller safetymargins leads to a reduction in the smallest area obtained, asshown in Fig. 4(b). However, even for a safety margin as small as150 mV, the extended modeling approach yields a better result.
2) Cascoded Current Cell : In the caseof the topology, the CS has also one degreeof freedom left. The four degrees of freedom of each one of thetwo other transistors (SW and CAS) are reduced to two degreesof freedom for each one, using the current value expression and
(a)
(b)
Fig. 4. Comparison between sizing results using (a) the proposed extendedmodeling and (b) previous sizing approaches with safety margins.
optimum gate bias voltage expressions of (11). The saturationconditions of (25) constrain the available design space in a sim-ilar way as (21) for the basic current cell. If minimum currentcell area is imposed, the maximum CS overdrive voltage and CSminimum area can be represented against CS and CAS overdrivevoltages as discussed in [15].
III. DYNAMIC PERFORMANCE
The dynamic performance of a segment current steering(SCS) DAC is mainly dependent on two characteristics of thecurrent sources: settling time and dynamic output impedance.Another contribution that will also be included in the designprocedure of Section IV is clock-feedthrough to the outputs,which is an important contribution to glitch energy. In thissection, however, we will concentrate in the analysis of thesettling time for switched current sources, by extending thework presented in [11] to find the relation of this settling timeto the current cell circuit parameters. Next the dynamic outputimpedance modeling is reviewed.
A. Settling Time Modeling
Following the same approach as in Section II, first the simpletopology of Fig. 2(a) will be analyzed, followed by an analysisof the cascoded topology of Fig. 2(b).
1) Simple Current Cell : During the switchingprocess of a steered current source, two phases may be distin-guished, as discussed in [11]. During the first phase, the two
ALBIOL et al.: MISMATCH AND DYNAMIC MODELING OF CURRENT SOURCES IN CURRENT-STEERING CMOS DACS 165
complementary control signals drive one of the switch transis-tors from OFF to saturation whilst its complementary is driven inthe opposite direction. This first phase of the switching processends when both of the control signals attain their final value.During the second phase, only the voltages at the switch tran-sistors drains (node in Fig. 2(a) and the common source (node
in Fig. 2(a) vary until they achieve their steady state values. Ifthe complementary control signals slopes are fast enough com-pared to the dynamic response of the current source nodes al-most all the complementary output nodes transient takes placein the second phase of the current sources switching process,which is analyzed in the following.
The switching output voltage waveform is obtained by ap-plying an incremental small-signal analysis around the steadystate and node voltages at the end of the second phase( and ) and output current . This analysis uses thefollowing small-signal and node voltage initial conditions:
(26)
The small-signal output voltage waveformfound by the analysis is [11]
(27)
where is the pole associated with the output node , thepole associated with the internal node , and is the ratio be-tween the small-signal initial charge at the internal node andat the output node at the beginning of phase 2. In the deriva-tion of (27), the following simplifications have been performed:
; . The poles andinitial charge ratio are related to the circuit parameters and ini-tial conditions through
and
(28)
where and are the parasitic capacitances at nodesand , respectively, and is the SW transistor small-signaltransconductance. It should be noted that .
Fig. 5 represents the current source output node tran-sient waveforms obtained with (27) for a given value of
and different values of , where hasbeen normalized to , and the time has been normalizedto . This waveforms have been obtained for a 12-b cur-rent-steering DAC using standard 0.35- m process parameters.Considering that the settling time is the time needed by theoutput voltage to reach its final steady state value within anaccuracy of volts, it is concluded from Fig. 5 that there
Fig. 5. Current source switching transient waveforms for the CS + SW
topology.
Fig. 6. Optimum as a function of poles quotient for a 12- and 10-b DAC.
exists an optimum value for that minimizes the settlingtime, for a given and . In the figure, has been set to0.5 LSB.
Two important conclusions are extracted from the previousanalysis.
1) There exists an optimum value of for everyratio that minimizes the settling time. This optimum isachieved through the appropriate design of the latch andits output driver circuit. The traditional design practicehas been hitherto to design this control signals with acrossing point in which one of the transistors enters in sat-uration just when the other enters OFF state [8]. However,this is not necessarily the optimum case, because a smallovershoot will help to speed-up the output settling time ofthe D/A converter, as has been shown above. For the il-lustrative 12-b DAC used to plot Fig. 5, and provided thatthe usual criterion of minimizing the overshootis used, the time needed for the output voltage to settle(point b) is almost 6 times larger than when the optimum
is used (point a).2) The model of (27) allows the quantitative estimation of
the settling time. It is a more accurate model than previousones [10], which consider the settling time to depend juston the minimum of the two poles, or , withoutcoupling.
The optimum waveform presents a negative overshootingthat is equal to (note that in Fig. 5 has been also nor-malized to ). No closed-form analytical expression exists for
, but it is relatively easy to solve it numerically with the use of
166 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004
Fig. 7. Optimum settling-time for the CS + SW topology.
differentiation, and considering that the optimum is found whenequals at the instant for which (27) is minimum:
(29)
Fig. 6 shows the optimum value of as a function offor and (12- and 10-b DAC, respec-tively). The figure also depicts the following boundary conditionthat must verify for overshooting to exist [11]:
(30)
Fig. 7 shows the optimum settling time against andP_X/O obtained for 12-bits DAC and typical 0.35-CMOStechnology parameters, assuming that the optimum is used.
2) Cascoded Current Cell : In this case,the circuit model used to estimate the output transient responseis shown in Fig. 2(b). An analysis equivalent to that done for the
topology leads to the following result in the Laplacedomain:
(31)
where andare the additional pole and initial conditions coeffi-
cients due to the additional internal node in Fig. 2(b). In thetime domain, the small-signal output voltage waveform derivedfrom (30) corresponds to
(32)
with
Fig. 8. Effects of theY node in the optimum settling time for theCS+CAS+SW topology.
(33)
where an additional pole ratio is defined.In this case, an additional component exists on the transient
response, which satisfies .The additional component effect is difficult to evaluate
either analytically or graphically since considering it togetherwith and implies too many degrees of freedom. Fig. 8shows the influence of the additional component on the esti-mated settling time as a function of and , for a rea-sonable value of and optimum , extracted froman actual 12-b SCS DAC designed on a 0.35- m CMOS tech-nology [16].
B. Dynamic Output Impedance Modeling
The current-steering DAC SFDR performance is strongly de-termined by the output impedance of the current sources [1], [2],as expressed by the following expression:
SFDR (34)
where is the output load to LSB cur-rent source output impedance ratio, and are thedc component and ac amplitude, respectively, of the sinusoidal( and ). For proper spec-tral performance, the SFDR has to be greater than the signal-to-quantization-noise ratio, which is 86 dB for a 14-b DAC or 74dB for a 12-b DAC. This implies a minimum output impedancerequirement. Output impedance SFDR requirements are easilyfulfilled for low-frequency signals, but when signal frequency isdeep in the megahertz band parasitic capacitances of the currentsource strongly degrade its output impedance and, consequently,the SFDR performance of the DAC is worsened.
In Section II-B, it was mentioned that the current sourceoutput impedance could be estimated using (4) and (5), for thesimple and cascoded current cell, respectively. This is true forslow variations of the output voltage. In [2], it is shown thatin the case of the simple current cell topology the effect of thenondesired capacitances may be modeled by adding a pole anda zero to (4) and two poles and two zeros to (5) in the case of the
ALBIOL et al.: MISMATCH AND DYNAMIC MODELING OF CURRENT SOURCES IN CURRENT-STEERING CMOS DACS 167
cascoded current cell. This yields to the frequency-dependentoutput impedances of (35) and (36), shown at the bottom ofthe page. In the frequency band of interest (up to Nyquist),the zeros do not affect dynamic output impedance because
for reasonable transistor sizes.
C. Implications of the Settling Time and Dynamic OutputImpedance in the Design Procedure
In this subsection, the settling time and dynamic outputimpedance dependencies on circuit poles and initial conditionsare related to the transistors sizes and other circuit parameters.
1) Simple Current Cell : Fig. 7 depicts theestimated optimum settling time as a function of and
, assuming that the optimum is obtained by the propersynchronization of the switches’ control signals. From Fig. 7,the intuitive rule that maximizing both poles leads to lowersettling time is quantitatively confirmed. In order to maximize
, a minimum-length SW transistor should be used. The SWtransconductance increases as the square root of the SW tran-sistor width, but gate-to-source capacitance increases linearly,thus a minimum-width SW transistor also maximizes . Onthe other hand, a minimum-width CS transistor minimizes theCS drain capacitance, therefore minimizing . A minimumwidth for the CS implies that it must have the maximum CSoverdrive voltage that guarantees saturation for all transistors(Section II-C). In most cases, however, the influence of the SWand CS transistors’ width on can be neglected. This capac-itance is dominated by the interconnect capacitance betweenthe CS and SW transistors in actual circuits, as each transistoris placed in a different array and their interconnections usuallyare large enough to dominate the node parasitic capacitance.Furthermore, a minimum-width SW transistor also maximizes
by minimizing its drain and overlap capacitances. Thisis specially significant for high segmentation ratios, where agreat number of switch drains are connected together at theoutput node. Apart from the benefits to the settling time, theclock-feedthrough is reduced if the SW gate and drain overlapcapacitances are lowered, which occurs when the SW width isminimum.
The main design implication extracted from the previous dis-cussion is that a minimum-length and -width SW transistor andminimum-width CS transistor (maximum overdrive voltage) isthe optimum choice for settling time. However, the effect of SWand CS width should be evaluated for every particular case, es-pecially when node and parasitic capacitances are not dom-inated by the SW capacitances. In this latter case, increasing
the SW width will increase its transconductance without signif-icantly affecting and , although the clock-feedthroughwill be compromised.
The previous analysis applies to the OFF–ON switching branchof the current source. If the same criterion is considered in theanalysis of the complementary ON–OFF switching branch, theconclusion is that during the second switching phase the time re-sponse of the complementary output node exclusively dependson .
Concerning the dynamic output impedance requirement, inthe case of the simple current cell , a minimum-length SW transistor allows minimizing . Even if intercon-nect capacitance dominates, it is not worth increasing the SWtransistor length to attempt to decrease the output impedancezero down to the pole frequency, as this compromises settlingtime and dramatically increases the current cell area and, conse-quently, the overall DAC area. Choosing the minimum area forthe CS transistor allows to minimize CS array area and, thus, theinterconnect capacitance. Furthermore, a minimum CS widthwill also reduce node capacitance.
2) Cascoded Current Cell : The sameconclusions of Section III-A1 and design implications of Sec-tion III-C1 are applicable to with respect to and
. A minimum-length and -width SW transistor and min-imum-width CAS transistor (instead of CS) are optimum forthe settling time. This is especially true if it is taken into ac-count that a small interconnect capacitance exists between SWand CAS transistors in actual circuits. In this sense, the CAStransistor not only increases current cell dc output impedance,but also improves settling time performance. Concerning the in-fluence of the additional node , as discussed in Section III-A2and from Fig. 8, it is clear that only when is low enough and
is high is the settling time compromised. This situation is notcommon, since the smaller is, the smaller will be, asopposes voltage variations at node . In general, for reasonablevalues of , , and , and reasonable voltage variations atthe internal nodes, pole does not effectively affect the set-tling time.
As far the dynamic output impedance is concerned, the sameargument than in Section III-C1 may be applied to the SW andCAS transistors length. Also, minimum CS area is the bestchoice for output impedance bandwidth. Finally, minimumCAS width leads to better performance, as it minimizes nodes
and capacitance. Minimum transistor dimensions pro-duce maximum bandwidth for output impedance and SFDRperformance, apart from minimizing DAC area. Note that if thedominant pole is , adding one or more extra
(35)
(36)
168 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004
Fig. 9. Current sources design procedure flow for current-steering DACs.
cascode transistors between CAS and SW may improve SFDRbandwidth performance without compromising settling time,although the overall DAC area is increased (especially if wetake into account that a lower CS overdrive voltage will needto be chosen).
IV. DESIGN PROCEDURE
In Sections II and III, the DAC current sources’ static, dy-namic, area, and statistical models have been presented. Perfor-mance requirements are related to the DAC design specifica-tions, such as number of bits, linearity (INL and DNL), sam-pling frequency, spectral performance, yield, area, and tech-nology [1].
On the basis of the models presented in Sections II and III, acurrent cell design procedure can be derived for both the simple
and cascoded current cell topolo-gies.
Fig. 9 shows the design procedures for the two topologies.The starting point includes design specifications and tech-nology parameters. For the two topologies there are basicallytwo targets driving the optimization process (indicated withitalics in the figure), namely minimize current cell area andminimize settling time. Note that in the cascoded topology theminimum settling time target is coincident with the optimumclock feedthrough and driver’s load target, whereas for thesimple current source topology (left part of the figure) thesettling time optimization has some negative impact on theclock-feedthrough (because of the required increase in the SWtransistor width). Hence, two alternatives are shown in this casedepending on whether glitch energy or sampling frequencyis priorized. Intermediate results of the design procedure are
enclosed within the boxes. The design criteria used to derivethe intermediate results are shown by the arrows. Note that, ingeneral, the design procedures do not require the segmentationratio to be chosen previously, at least not until the driver andlatches are designed. The only exception is the case in which theoutput node capacitance needs to be estimated with precision(this design path is indicated in Fig. 9 with an asterisk). Theproposed design procedure is closed and provides as a finalresult the complete sizing of the DAC current source circuits.
V. CONCLUSION
This work provides an extended design procedure for cur-rent-steering DACs through the static and dynamic study of twousually considered current source circuit cells. On the one hand,an extended mismatch statistical study which takes into accountrandom variations in all the transistors of the current source cellsyields an improved analytical static model. This refined modelpermits us to tighten the required biasing margins without re-sorting to arbitrary margins, which, given the design space ofthe DAC, results in notable area reductions. Conditions for op-timum gate bias voltages concerning output resistance are ob-tained as well. On the other hand, an extension of the switchingtransient behavior is discussed, and its relation to transistor pa-rameters is discussed. As a consequence of the extended staticand dynamic modeling, an improved DAC design procedure ispresented. By applying the design method to a particular tech-nology and DAC specifications, comparisons with previous de-sign approaches clearly indicate that the improved modeling ofmismatching and dynamics effects presented in this work allowto reduce the area and improve the settling time of the DAC.The results of this paper may ease the automatization of the
ALBIOL et al.: MISMATCH AND DYNAMIC MODELING OF CURRENT SOURCES IN CURRENT-STEERING CMOS DACS 169
circuit design of future current-steering DACs with improvedperformance.
REFERENCES
[1] M. Gustavsson, J. Wikner, and N. Tan, CMOS Data Converters for Com-munications. Boston, MA: Kluwer, 2000.
[2] A. Van den Bosch, M. Steyaert, and W. Sansen, “SFDR-Bandwidthlimitations for high speed high resolution current steering CMOS D/Aconverters,” in Proc. IEEE Int. Conf. Electronics, Circuits and Systems(ICECS), Sept. 1999, pp. 1193–1196.
[3] P. Hendriks, “Specifying communication DAC’s,” IEEE Spectrum, pp.58–69, July 1997.
[4] Y. Cong and R. L. Geiger, “Switching sequence optimization for gradienterror compensation in thermometer-decoded DAC arrays,” IEEE Trans.Circuits Syst. II, vol. 47, pp. 585–595, July 2000.
[5] J. Vandenbussche, G. Van der Plas, W. Daems, A. Van den Bosch, G.Gielen, M. Steyaert, and W. Sansen, “Systematic design of high-accu-racy current-steering D/A converter macrocell for integrated VLSI sys-tems,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 300–309, Mar. 2001.
[6] C. H. Lin and K. Bult, “A 10.b, 500-Msample/s CMOS DAC in 0.6mm ,” IEEE J. Solid-State Circuits, vol. 33, pp. 1948–1958, Feb. 1998.
[7] J. L. González and E. Alarcón, “Clock-Jitter induced distortion in high-speed CMOS switched-current segmented digital-to-analog converters,”in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS’01), May 2001,pp. I512–I515.
[8] H. Kohno, Y. Nakamura, A. Kondo, H. Amishiro, T. Miki, and K.Okada, “A 350-MHz 8-bit CMOS D/A converter using delayed drivingscheme,” in Proc. IEEE 1995 Custom Integrated Circuits Conf., 1995,pp. 211–214.
[9] G. A. M. Van der Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert,and G. Gielen, “A 14-bit intrinsic accuracy Q random walk CMOSDAC,” IEEE J. Solid-State Circuits, vol. 34, pp. 1708–1718, Dec. 1999.
[10] J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, “A 12-Bit in-trinsic accuracy high-speed CMOS DAC,” IEEE J. Solid-State Circuits,vol. 33, pp. 1959–1969, Dec. 1998.
[11] T. Miki, Y. Nakamura, K. Okada, and Y. Horiba, “Transient analysis ofswitched current sources,” IEICE Trans. Electron., vol. E75-C, no. 3,pp. 288–295, Mar. 1992.
[12] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matchingproperties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, pp.1433–1440, May 1989.
[13] A. Van den Bosch, M. Steyaert, and W. Sansen, “An accurate statisticalyield model for CMOS current-steering D/A converters,” in Proc. IEEEInt. Symp. Circuits and Systems (ISCAS), May 2000, pp. IV105–IV108.
[14] A. J. David and K. Martin, Analog Integrated Circuit Design. NewYork: Wiley, 1997.
[15] M. Albiol, J. L. González, and E. Alarcón, “Improved current-sourcesizing for high-speed high-accuracy current steering D/A converters,”in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Bangkok, Thai-land, May 2003, pp. 837–840.
[16] M. Albiol, “Design and implementation of a high-performancedigital–analog converter in 0.35 m CMOS technology for communi-cations applications,” Master’s thesis, Barcelona Telecommun. School(ETSETB), Univ. Politècnica de Catalunya (UPC), 2002.
Miquel Albiol received the M.Sc. degree in electricaland electronics engineering from the Universitat Po-litecnica de Catalunya, Barcelona, Spain, in 2002. Heis currently working toward the Ph.D. degreee at thesame university.
After working as a Design Engineer for theBroadcasting Department of Mier Comunicaciones,Barcelona, for 2001–2002, he is currently workingfor the Space Department of the same company inthe frame of the SMOS ESA project. His currentresearch interests include the areas of analog and
mixed-signal microelectronics with particular interest in digital-to-analogconversion and RF circuits.
José Luis González (M’99) received the Diplomain telecommunication engineering from the RamonLlull University (URL), Barcelona, Spain, in1992 and the M.S. degree in telecommunicationsengineering and the Ph.D. degree (with honors) inelectronic engineering, both from the PolytechnicUniversity of Catalunya (UPC), Barcelona, in 1994and 1998, respectively.
He is currently a full-time Associate Professor withthe Department of Electronic Engineering, Telecom-munication Engineering School of Barcelona, UPC.
During 1999, he spent a semester at the Electrical and Computer Science De-partment, University of Arizona, Tucson, with a Fulbright fellowship, and hecollaborated with the Motorola Wireless Infrastructure Group, Phoenix, AZ, inthe investigation of noise effects on D/A converters for communications. His re-search interests include VLSI design, mixed-signal and RF integrated circuits,and noise problems. He has authored or coauthored 26 scientific papers in jour-nals and conference proceedings and one book chapter.
Dr. González received the Doctoral Excellence Award for his Ph.D. thesisfrom the Polytechnic University of Catalunya in 2001. His thesis work has beenpublished in the book Analysis and Solutions for Switching Noise Coupling inMixed-Signal IC’s (Boston, MA: Kluwer, 1999).
Eduard Alarcón (S’96–M’01) received the M.S.(with national honors) and Ph.D. (with honors)degrees in electrical engineering from the UniversitatPolitecnica de Catalunya, Barcelona, Spain, in 1995and 2000, respectively.
From 1995 to 1997, he was awarded a researchfellowship from the Catalan Government. Duringthe period 1997–2000, he was an Assistant Professorwith Department of Electronics Engineering,
Telecommunication Engineering School of Barcelona, where he becamefull-time Associate Professor in 2000. During the period August 2003 toJanuary 2004, he is holding a visiting appointment at the COPEC center,University of Colorado, Boulder. He has participated in five Spanish nationalresearch projects. His current research interests include the areas of analog andmixed-signal microelectronics with particular interest in current-mode design,theoretical aspects of fuzzy control, integrated switching dc–dc converters, andnonlinear controller VLSI implementations. He has authored or coauthoredmore than 50 scientific papers in journals and conference proceedings and twobook chapters.
Dr. Alarcón was recipient in 1998 of the Myril B. Reed Best Paper Award atthe IEEE Midwest Symposium on Circuits and Systems for a research paper ona mixed-signal reconfigurable neuro-fuzzy processor. He is the invited co-ed-itor of a special issue of the Analog Integrated Circuits and Signal ProcessingJournal devoted to current-mode circuit techniques and co-organizer of a spe-cial session on “New trends in switching power converters toward circuit inte-gration” at ISCAS’03.
MODELING OF THE IMPACT OF THE CURRENT SOURCE OUTPUT IMPEDANCE ONTHE SFDR OF CURRENT-STEERING CMOS D/A CONVERTERS
A behavior-level model of a thermometric DAC with acceptablecomplexity and sufficient accuracy is presented in this paper. Theimpact of the current sources’ internal poles on the SFDR is de-scribed in the model. With this model, the sensitivity of the SFDRto some unideal factors such as the parasitic capacitors in the inter-nal point, and the variation of the internal points’ voltages, can beobserved directly. Furthermore, this model can be used for the ver-ification of the possible solutions for the output impedance prob-lem, and is therefore necessary for future work.
1. INTRODUCTION
In order to improve the Spurious Free Dynamic Range (SFDR) ofa high-accuracy, high-speed DAC, all the limitations have to be in-vestigated carefully. The current source’s limited output impedanceat high signal frequency is one of the most serious factors that im-pact the SFDR [1]. Normally, it’s very time-consuming or nearlyimpossible to simulate such an impact by a spice-like simulator.
In this paper, a model with sufficient accuracy and acceptablecomplexity is presented. The nonideal parameters, such as theparasitic parameters, the crossing point voltage of the switchingcontrol signals, the limited output resistance of the transistors, areincluded in this model, so that their impact on the SFDR can beobserved directly from the results of the simulation.
Our simulation results are consistent with the results of ref-erence [1]. Moreover, the impact of the variation of the internalpoints’ voltages, which can be controlled by adjusting the cross-ing point voltage of the switching control signals, on the SFDR issimulated. The results show that decreasing the absolute value ofthis deviation cannot always increase the SFDR, and its impact onthe SFDR is actually quite small.
In section 2, the mathematical model used in our simulationis proposed. The modeling work and the simulation results arepresented in section 3. At last, the conclusions are given in section4.
2. MATHEMATICAL ANALYSIS
2.1. The Model Used in Reference [2]
The transient behavior of a switched current source (shown in Fig.1(a)) is proposed in the reference [2]. The model for analysis isshown in Fig. 1(b).
Vb
o
g3
Internal node X
V (t)V (t)g2
R
V (t)
+
x
V (t)o
(a) The schematic of acurrent source
x
x
oC
g0
o
o0
b
V (t)
CI
V
R
V (t)
+
o
V
(b) the model for analysis
Figure 1: The schematic of current sources and the model for anal-ysis in reference [2]
When the current source is turned on, the output voltage canbe expressed as[2]:
vo(t) = vo0
»exp (−P1t) − γP2
P1 − P2exp (−P1t)+
γP2
P1 − P2exp (−P2t)
–(1)
where,
P1 =1
RoCo(2)
P2 =gm
Cx(3)
γ =vx0Cx
vo0Co(4)
gm is the transconductance of the switching transistors.In equation (1), vo(t) is the difference between the output volt-
age and its final value. vo0 is the initial value of vo(t), physicallyit’s the output difference between the two sampling cycles. Sim-ilarly, if we define vx(t) as the difference between the voltage ofthe internal node and its final value, vx0 is defined to be the initialvalue of vx(t). The value of vx0 is decided by the crossing pointof the two control signals (vg2(t) and vg3(t) in Fig. 1(a)) and iscontrollable.
2.2. The Extended Model
In the previous model, the transition behavior of the DAC is con-tained in the two parameters vo0 and vx0. The output conductancesof the transistors are approximated to zero in this model. So thisis not enough to predict the impact of the output impedance on theDAC’s SFDR, which has been proved to be one of the main factorsthat limit the SFDR of a DAC [1]. We will extend the mathemat-ical model to take the output resistances into consideration in thissection, and then in section 3 we will get the behavioral modelbased on the results obtained.
The model used is shown in Fig. 2. The left box in the figureis the model of the current sources which are switching on duringthe current sampling cycle, and the right box is the model of thecurrent sources which were already switched on at the beginningof the current sampling cycle. Those current sources which remainoff are neglected since their transconductances are very small, evenwhen the signal frequency is high.
+
V (t)o
+
Co
Ro
I (t)2 I (t)4
g m4
V
C
b
1
V (t)1
I1
o2
V (t)
g
g
g o1
o4g
g o3I3
C2
2
The current sources switching on The current sources switched on
A B
m2
Figure 2: Extended model for analysis
In this figure, Ro and Co are the load resistance and capacitorrespectively. Vo(t) is the DAC’s output voltage. Take the circuitsin the left box as an example. They describe all the current sourcesthat are switching on during the current sampling cycle. gm1 andgo2 are the total transconductance and the total output conductanceof the switching transistors respectively. I1 is the total DC currentof the current sources, go1 is the total output conductance of thecurrent source transistors, and C1 is the total parasitic capacitanceat the internal node. V1(t) is the voltage of this node. The mean-ing of the parameters in the right box are the same, except thatthey describe all the current sources that have switched on at thebeginning of the current cycle.
When some of the current sources are switching on, Vo(t),V1(t) and V2(t) are changing towards their new final values VoF ,V1F and V2F respectively. Assuming the final current passing theVoltage-Controlled Current Source (VCCS) in both the boxes areI2 and I4 respectively, their transient current can be expressed as[2]:
I2(t) = I2 − gm2 [V1(t) − V1F ] (5)
I4(t) = I4 − gm4 [V2(t) − V2F ] (6)
Applying these results, the node equation with respect to theoutput node is:
where Vo0, V10 and V20 are the initial values of vo(t), v1(t) andv2(t) respectively. Physically, they are the difference of the initialvalues of Vo(t), V1(t) and V2(t) from their final values. Theywill be calculated in section 2.4. With symbolic analysis tools, theoutput voltage vo(t) can be obtained from equations (19), (20) and(21).
2.3. Some Special Cases
Some special boundary cases still need to be considered.When all the current sources are switched off at the beginning
of the current cycle, the circuits in the right box of Fig. 2 don’texist. The circuits equations then become:
When no current source is switched on at both the beginningand the end of the current cycle, the circuits can be simplified intoan R-C network, and:
Vo(s) =Vo0
s + go/Co(26)
2.4. The Initial Conditions
In order to obtain the output voltage vo(t), the initial values Vo0,V10 and V20 have to be calculated. These initial values are the de-viations of the voltages at the beginning of the current cycle fromtheir final values.
At the beginning of the current cycle, only the current sourcesin Fig. 2’s right box are on. The circuits for calculating the voltageat the output node are shown in Fig. 3(a), where the cascode cur-rent source is simplified into an ideal current source and an outputresistance ro34:
ro34 = 1/go3 + 1/go4 + gm4/(go3go4) (27)
The output voltage at the beginning of the cycle can be obtainedas:
Vo(0) = Vbro34
Ro + ro34− I3
ro34Ro
ro34 + Ro(28)
Ro
Vb
oV (0)
I r3 o34
(a) At the beginning ofthe cycle
Ro
I3 + I1
Vb
o
ro34 //ro12
V ( )
(b) At the end of the cycle
Figure 3: The schematics for the calculation of the initial values ofthe output voltage
At the end of the cycle, the current sources in both boxes ofFig. 2 are on. The circuits are shown in Fig. 3(b). The outputvoltage is:
Vo(∞) = Vbro34‖ro12
Ro + ro34‖ro12− (I1 + I3)
(ro34‖ro12)Ro
r034‖ro12 + Ro(29)
wherero12 = 1/go1 + 1/go2 + gm2/(go1go2) (30)
With equations (28) and (29), the initial value of vo(t) can beobtained:
Vo0 = Vo(0) − Vdiff − Vo(∞) (31)
where Vdiff is the difference between the voltage at the end of thelast cycle and the ideal voltage when time is approaching infinity.It describes the fact that the ideal final value can never be reached.
The value of V10 is decided by the crossing point of the twocontrol signals (Vg2(t) and Vg3(t) in Fig. 1(a)), and is control-lable.
For the current sources which are always on during this cycle,the deviation of their internal point (point B in Fig. 2) is caused bythe deviation of the output point. Since Ro 1/go3, we can get:
V20 =Vo0
1 + gm4/(go3 + go4)(32)
3. MODELING WORK
With the mathematical model described in section 2, a behavioralmodel of the DAC can be obtained. Fig. 4 shows the flow chartof the program. In our program, all the parameters are extractedfrom the simulation results of a real design[3], except the parasiticcapacitance in the internal node. For simplification of the model,the simulation results below are based on the assumption that theparasitic capacitance at the internal node of every current sourceis the same. The total parasitic capacitance depends on the area ofthe current sources block and can be estimated. In our case, theestimated value is about 40 pF.
Calculate the parameters of thecircuits
Calculate the output signal in thissampling cycle
Calculate the output signal in allthe sampling cycles, and get thewhole output signal
and do the FFT analysis
For every sampling cycle,
sources that have been on andthat will be switched on
Apply the window function
Calculate the SFDR value forthat input frequency
calculate the number of current
Figure 4: The flowchart of the behavioral model
Fig. 5(a) shows the output signal of the DAC. Fig. 5(b) is theresult of the FFT analysis. The SFDR can be obtained by calculat-ing the difference between the amplitude of the signal frequencyand the amplitude of the second largest value in the frequencyspectrum.
Doing the same calculation for different signal frequencies, weget the SFDR-fsig curve as shown in Fig. 6(a). We see from thisfigure that when the signal frequency is higher than a value (whichis quite low), the SFDR will decrease with increasing signal fre-quency at a slope of about -20dB/dec, until it reaches a relative
0 2 4 6 8 10 12
x 108
0.3
0.2
0.1
0
0.1
0.2
0.3
Time (s)
Out
put V
olta
ge (
v)
The Output of the DAC
fsig
=9MHz
(a) The time-domain outputsignal of the DAC
0 1 2 3 4 5 6 7 8 9 10
x 104
160
140
120
100
80
60
40
20
0
20
40
Frequency (KHz)
Pow
er D
ensi
ty (
dB)
The Power Spectrum Deisity of the Output Signal
(b) The frequency-domainoutput signal of the DAC
Figure 5: The simulation results for one input signal frequency
high frequency. This result is consistent with the bode diagram ofZimp described in Fig. 3 of the reference [1].
103
104
105
106
107
108
70
75
80
85
90
95
100
105
110
V10
= 0.0465V
Ctot
=40pF
Simulation Result: Internal Poles Included
signal frequency: Hz
SF
DR
: DB
(a) The SFDR-fsig curve
1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 166
68
70
72
74
76
78
80
82
84
v10
(V)
SF
DR
(dB
)
The SFDR v10
Curve
fsig
=29MHz
Ctot
=40pF
(b) The SFDR-V10 curve
101
100
101
102
70
75
80
85
90
95
100
Ctot
(pF)
SF
DR
(dB
)
The SFDR Ctot
Curve
fsig
=29MHz
v10
= 0.0465V
(c) The SFDR-Ctot curve
Figure 6: The simulation results
Changing the control signals will cause a deviation of the in-ternal points (point A in Fig. 2). Designers can control the valueof v10 by controlling the crossing point of the control signal [4].Naturally, it will be interesting to observe the relation between theSFDR and the value of this deviation. Fig. 6(b) shows the simu-lation results. Two conclusions can be drawn from these results.Firstly, when the deviation changes, the variation of the SFDR isquite small; Secondly, when the deviation is negative (this is thenormal case), reducing the absolute value of the deviation will de-crease the SFDR. In our behavioral model, the glitches caused bythe feedthrough of the signal frequency are not considered. So in
a real converter, the SFDR might not really decrease. But still wecan expect that the SFDR won’t increase a lot by optimizing thecrossing point of the control signals.
Another interesting relation is the relation between the SFDRand the total parasitic capacitance. This is shown in Fig. 6(c). Wesee that, when the total parasitic capacitance is bigger than 2pF,the SFDR will decrease with increasing total capacitance valueat a rate of -20dB/dec. This is because the pole of the outputimpedance is reduced when the value of the parasitic capacitor isincreasing, thus the SFDR will be reduced to lower value at thegiven signal frequency.
4. CONCLUSIONS
The impact of the current source output impedance on the SFDR ofcurrent-steering CMOS D/A converters is simulated in this paper.The results show that the limited output impedance can really limitthe DAC’s SFDR property seriously.
One possible solution to this limitation is to reduce the para-sitic capacitance by reducing the area of the current sources. Inorder to achieve enough accuracy with smaller area, calibration ortrimming is necessary. Recent published paper shows this trend[5] [6].
The variation of the internal points’ voltages is also includedin the model, and their impact on SFDR is also investigated. Theresults show that the SFDR cannot improve a lot by adjusting thisparameter.
5. REFERENCES
[1] A. Van den Bosch, M. Steyaert and W. Sansen, “SFDR-Bandwidth Limitations for High Speed High ResolutionCurrent Steering CMOS D/A Converters,” in InternationalConference on Electronics, Circuits and Systems, vol. 3,pp. 1193-1196, Sept., 1999
[2] T. Miki, Y. Nakamura, K. Okada and Y. Horiba, “TransientAnalysis of Switched Current Sources,” IEICE Trans. Elec-tron, vol. E75-C, pp. 288-296, Mar. 1999
[5] Y. Cong and R. Geiger, “A 1.5V 14b 100MS/s Self-Calibrated DAC,” in IEEE ISSCC 2003 Session 7/Dacs ANDAMPs/Paper 7.2.
[6] J. Hyde, T. Humes, C. Diorio, M. Thomas and M. Figueroa,“A 300-MS/s 14-bit Digital-to Analog Converter in LogicCMOS,” IEEE J. Solid-State Circuits,vol. 38,pp. 734-740,May. 2003.
Department of Electroscience
Master of Science Thesis Henrik Hassander & Christian Lindholm
in cooperation withAcreo AB
February 2004
Modelling and implementation of a10-bit 80 MSPS current-steering DAC
with internal bandgap referencein a 0.18 µm CMOS process
Abstract A 10-bit quadrature differential digital to analog converter has been designed in a 0.18 µm CMOS process. This DAC is a part of the SoCTRix project at Acreo. There has been a large effort put into MATLAB modelling of DAC behaviour and errors. A design flow was built up to systemize and simplify the layout work. To minimize external components, a bandgap was implemented in the same design. The main design goal was to reach high linearity while keeping power consumption low. A secondary goal has been to keep the total chip area low. In an effort to make the DAC commercially viable it has been designed to give a high yield.
1
2
Preface This thesis work has been carried out at Acreo AB in Lund. The thesis is part of our Master of Science degree from Lund Institute of Technology – LTH, Lund University. We would like to thank our advisors Karl Norling from Acreo, Martin Anderson from Department of Electroscience, LTH and all co-workers at Acreo. We would also like to thank our examiner at LTH, Jiren Yuan.
5 Modelling of errors in a current-steering DAC................... 21 5.1 Causes of errors in current-steering DACs ..................................................21
5.1.1 Output impedance vs. SFDR................................................................21 5.1.2 Output impedance vs. gain error..........................................................21 5.1.3 Mismatch vs. SFDR.............................................................................22 5.1.4 Mismatch vs. INL ................................................................................22 5.1.5 Influence of noise on circuit performance ...........................................23 5.1.6 Influence of graded errors on performance..........................................23 5.1.7 Mismatch calculations .........................................................................24
5.3.1 Simulating the nominal case ................................................................25 5.3.2 Simulating the impact of reduced matching ........................................27 5.3.3 Simulating the impact of switching schemes.......................................28 5.3.4 Simulating the impact of limited output impedance ............................30
6 System implementation ...................................................... 31 6.1 System description .......................................................................................31 6.2 Implementation of sub-circuits ....................................................................32
7 Results and conclusion ....................................................... 49 7.1 The complete system....................................................................................49 7.2 Challenges of system simulations................................................................49 7.3 Simulation results.........................................................................................50 7.4 Conclusions..................................................................................................50 7.5 Possible improvements for future development ..........................................51
Wireless communication systems today require more and more digital signal processing. But somewhere along the line of a transmitter or a receiver there is a radio signal, an analog signal. This requires the use of a digital-to-analog converter in a transmitter or an analog-to-digital converter in a receiver. These communication systems are often mobile and thus require all of the circuits involved to have low power consumption. In IC manufacturing today, the trend is to keep shrinking the processes as much as possible. For digital circuits this is a good thing since it means smaller circuits with lower power consumption. For analog circuits however it is starting to become a bit of a problem. The smaller the process becomes the more the power supply voltage is lowered. This means that the signal headroom is decreased and the number of circuits that are possible to implement are reduced. In this thesis a DAC was designed in a 0.18 um process at Acreo AB in Lund. MATLAB models were developed to study the behavior of current-steering DACs and how different errors affects the performance. An internal reference in the form of a bandgap has also been implemented. The actual design was created and simulated in Cadence custom IC design tools.
2.1 Design goals
The goal is to design a quadrature 10-bit DAC with good linearity and low power consumption. The architecture chosen was a current-steering DAC, more information on this later on. The load was decided to be 60 Ω with a full-scale differential current of 10 mA(each output supplying 0 to 5mA). This equates to a differential voltage swing of 600 mV. The filter following the DAC set these requirements. The requirement on update rate was set to 80 MSPS.
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10
3 Theory
3.1 DAC Theory
The digital to analog converter converts a discrete time signal with discrete amplitude to a continuous time signal with discrete amplitude. In the case where the digital word is binary and there is a given voltage (or current) reference, the output is
∑=
−=N
kk
krefout bVV
12 ( 3.1 )
where the vector b is the binary word and N is its length (the DAC’s resolution). The minimum voltage change on the output, corresponding to a change of 1 LSB, is
Nref
LSB
VV
2= ( 3.2 )
The maximum output signal can be calculated from equation ( 3.1 ). The decimal value is
NN
k
k −
=
− −=∑ 2121
( 3.3 )
which gives the maximum output voltage
LSBrefMAX VVV −= ( 3.4 )
These equations give us the output as shown in Figure 3.1, where the input signal is a 2-bit ramp from 00 to 11.
Figure 3.1 Digital to analog conversion with a 2-bit DAC.
3.2 Performance measures
Due to nonlinearity, noise, mismatch, power supply etc, the output signal is not ideal. The unit used when defining the following errors is LSB.
3.2.1 Offset error The output when the input vector, B, is 0 is defined as the offset error, Eoffset [1].
11
( )0=
≡BLSB
outoffset V
BVE ( 3.5 )
3.2.2 Gain error The gain error is defined as the output deviation from the ideal output with a full-scale input, minus the offset error.
( ) ( ) offsetN
BLSB
outgain E
VBVE
N
−−−≡−=
1212
( 3.6 )
The offset and gain errors are described graphically in Figure 3.2.
Figure 3.2 DAC gain and offset errors.
These two errors are disregarded when describing differential and integral nonlinearity errors.
3.2.3 Differential Nonlinearity The difference between each output step of a real and an ideal DAC is the DNL error. The vector of DNL errors is
( ) ( )120
11−≤<
−−−≡
NBLSB
outoutB V
BVBVDNL ( 3.7 )
The vector’s maximum is often used in specifications to show the worst-case error.
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Figure 3.3 Transfer curve with errors on the left, and the DNL vector on the right.
3.2.4 Integral Nonlinearity The INL errors are calculated as the deviation from a straight line, which is adapted to the transfer curve. The line could be between the start and end points of the curve, or calculated with some kind of linear regression. As for the DNL, the vector’s maximum is often used to specify the INL.
Figure 3.4 INL errors compared to a straight line between start and end points.
The equation for the INL vector is
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( ) ( )120
_
−≤≤
−≡
NBLSB
fitoutoutB V
BVBVINL ( 3.8 )
where Vout_fit is the straight line from zero to full-scale. If the DNL and INL formulas are combined we get an expression for DNL and INL.
1−−= BBB INLINLDNL ( 3.9 )
∑=
+=B
kkB DNLINLINL
10 ( 3.10 )
3.2.5 Monotonicity A DAC has monotonic behaviour if the output always increases with an increasing input. Monotonicity is guaranteed if the maximum INL error is smaller than 0.5 LSB and the DNL error less than 1 LSB. The non-monotonicity often occur when the input is changed from “01…1” to “10…0” in binary weighted DAC’s.
3.2.6 Glitches If there is skew between the input bits or the clock, glitches can occur. For example, if an input word is changed from “1000” to “0111” and the MSB is slower than the other bits. Then the input is “1111” before it changes to “0111”. The LSB step will begin with a peak and then settle to the desired voltage.
3.2.7 Settling time Since the output is a step and there is always parasitic capacitance, it needs time to settle within the error margin (usually 0.5 LSB). The time it takes will limit the maximum number of samples per second.
3.2.8 Signal-to-Noise and Distortion Ratio SNDR is the most important dynamic specification. It depends on the resolution of the DAC and most of the other errors such as mismatch, nonlinearity, clock jitter, noise and settling time. SNDR can be calculated with equation ( 3.11 ), where VQ_RMS is a LSB and Vdist_RMS is the distortion.
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
++=
RMSdistRMSnoiseRMSQ
RMSout
VVV
VSNDR
_2
_2
_2
_log20 ( 3.11 )
3.2.9 Spurious Free Dynamic Range SFDR is the ratio between the signal amplitude and the largest spurious tone of the output signals’ spectrum.
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Figure 3.5 Frequency spectrum showing SFDR.
3.2.10 Resolution The resolution is defined as the number of analog levels. Which is 2N for a converter with N physical input bits. However, this does not say anything about the actual performance of the DAC.
3.2.11 Accuracy The absolute accuracy of the converter is the difference between the ideal and the actual performances, where the offset, gain and nonlinearity errors are included. Relative accuracy is the absolute accuracy without the gain and offset errors.
3.2.12 Effective Number Of Bits A converter with N-bits resolution has most likely not an accuracy of N effective bits. When calculating the ENOB, the formula for the maximum SNR with a quantized input signal is used [1].
76.102.6 += NSNR ( 3.12 )Distortion is added to the noise, which results in the equation for ENOB.
02.676.1−
=SNDRENOB ( 3.13 )
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4 DAC Architecture
4.1 Choice of architecture
There are four different architectures that are suitable for the required sampling rate.
The pipelined converter would need to use 10 fairly fast operational amplifiers for 10-bit operation. These would consume a lot of power to operate at the speeds required. The output from the pipelined converter is voltage and would therefore have to be converted into current in order for the next stage to work. The R-2R and resistor string architecture have the same basic flaw. It does not make efficient use of the power. This is caused by the fact that here is always a current flowing through the resistive network. It is also hard to match the resistors for 10-bit accuracy without a significant penalty in either area or power. This leaves only the current steering architecture, which is chosen because it is possible to reach 10-bit accuracy at the required speed.
4.2 Current-Steering DACs
The basic principle of a N-bit current-steering DAC is N current sources connected in parallel. The digital input word controls which source that is connected to the load. A larger digital word gives more current sources in parallel that results in a larger output signal. One big advantage with this architecture is that almost all current goes through the output, and that makes this architecture power efficient. This type of converter is also superior when it comes to high-speed D/A converters. A 1-bit differential converter is shown in Figure 4.1. The complementary input signals make the current pass through the left or the right output. The differential voltage on the output is
( )NPLout IIRV −= ( 4.1 )
Figure 4.1 A 1-bit current-steering DAC with current source and digital input b.
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The power losses for this type of converter come from generating the bias and synchronization of the input signal. This also means that the power consumption will scale fairly well with the update frequency since the power consumption in a digital net is proportional to the frequency.
4.2.1 Thermometer code A way, different from the binary, to represent a digital word is with thermometer code.
Decimal Binary Thermometer
0 000 0000000
1 001 0000001
2 010 0000011
3 011 0000111
4 100 0001111
5 101 0011111
6 110 0111111
7 111 1111111
Table 4.1 Decimal numbers coded with binary and thermometer code.
The number of bits required for the thermometer code is
12 −= BNTN ( 4.2 )
where NB is the number of binary bits. This results in a larger amount of hardware when there is a large word-length. However, the thermometer coded D/A converter also has positive qualities. For example, if a binary number changes from “100” to “011” there may be a glitch. If the same change is done with the thermometer code it just changes one bit, and this glitch problem is gone and the DNL errors are reduced. If the converters current sources have different current, the “011” level might give more current than the “100” level, which means that the converter is non monotonic. This is impossible with a fully thermometer coded current-steering converter because the number of active current sources always increases with the input, and this guarantees monotonicity.
4.2.2 Thermometer-Binary segmentation Due to fast increasing number of inputs for high accuracy fully thermometer coded DACs, it is common with segmented converters [2] where the LSBs are binary and the MSBs thermometer coded. A segmented DAC is used to get most of the advantages with fewer of the disadvantages from both coding techniques. Below are some positive and negative things about thermometer and binary coding.
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Thermometer Positive
• Low glitch energy • Monotonicity • Small DNL errors
Negative • Digital decoding with more area and power consumption • Increased number of control signals
Binary Positive
• Low digital power consumption • Smaller area • Small number of control signals
Negative • Monotonicity not guaranteed • Larger DNL errors
The price in digital power and area was rather small compared to the benefits of smaller glitch energy and DNL errors, so a split with 8 thermometer and 2 binary bits was chosen for this DAC. This results in a thermometer unit current, It, equal to four binary units, Ib. One can either represent the thermometer unit as 1 current source with 4 times the binary unit current, 2 sources with 2 times the unit current or 4 unit sources. With 1 source, the standard deviation for the transistor mismatch on a wafer is
( )σ4,4mN ∈ ( 4.3 )and with 4 sources of the same size as above
( ) ( )σσ 2,44,4 2 mmN =∈ ( 4.4 )
Therefore it is better to use 4 thermometer sources because the required matching is decreased, and it is easier to apply different layout techniques such as common-centriod. It is also easier to match the sources because they are the same size as the binary sources and they will have the same bias.
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5 Modelling of errors in a current-steering DAC
In this chapter the cause of some of the errors causing performance degradation will be discussed. Some approximate formulas for estimating performance are shown. Both static and dynamic errors are taken into consideration. A MATLAB model of a current steering DAC is shown. Some simulation results from this model are presented.
5.1 Causes of errors in current-steering DACs
5.1.1 Output impedance vs. SFDR The limited output impedance of the current source will cause an error in the output signal. This is caused by the fact that the output impedance is dependant on how many current sources that are on at any given time. This will cause a signal dependent current sharing between the load and the output impedance of the current source. It can be shown [3] that the output voltage as a function of time can be written as below:
( )
impL ZtN
R
ItNtV
)1)(sin(2)1)(sin(+
+
+=
ωω
( 5.1 )
where I is the current through one current source, RL is the load resistance, Zimp is the output impedance of one current source and N is the total number of current sources. By doing a taylor series expansion and identifying the harmonics it’s possible to decide the influence of Zimp on SFDR. The series expansion was done in maple for both the single-ended case and the differential case. In Appendix A the complete maple code can be seen for both cases. In the single-ended case the SFDR is dependant on the second order harmonic, which is the dominant overtone. In the differential case, assuming perfect matching, the second order harmonic is cancelled and the SFDR is dominated by the third overtone. The ratio between the signal and the second order harmonic in the single-ended case is, according to [3], approximately given by:
impL
imp
ZN
R
ZN
SFDR24
+= ( 5.2 )
For a 10-bit converter SFDR should be at least 60 dB. In this case with RL=60 Ω this would mean that Zimp would have to be at least 15.3 MΩ in the desired frequency range. In the differential case an output impedance of 455 kΩ is enough to meet the demands. A demand that is much easier to meet, especially if high frequency operation is desired.
5.1.2 Output impedance vs. gain error Since the current is shared between the load and the output impedance of the current source array a gain error will occur. The size of this error is decided by how many
21
current sources are on and the value of the load resistor. The worst case occurs when all current sources are conducting. The full-scale gain error is easily determined by the following equation:
impL
imp
in
out
ZR
Z
VV
+=
1023 ( 5.3 )
The only problem with this simple equation is that it doesn’t take the frequency dependence of Zimp into consideration. Since the frequency behaviour of Zimp is hard to determine analytically one has to rely on simulations for this.
5.1.3 Mismatch vs. SFDR Variations in the manufacturing process causes mismatch between current sources. This means that there will be a variation in current over the area of the chip. A detailed analysis has been performed in [2] and the result is shown below
2log1034
3log20 unitNSFDR σπ−+⎟
⎠⎞
⎜⎝⎛≈ ( 5.4 )
where σunit is the mismatch between current sources, for instance 4% mismatch means that σunit equals 0.04. This is only an approximate equation because it only takes the mismatch in the MSBs into account. But it gives an idea of what to expect and it can be used to calculate an approximate demand on mismatch. For an average SFDR of 65 dB in a 10-bit DAC less than 4.2 % mismatch is required.
5.1.4 Mismatch vs. INL The mismatch also affects the DC performance. The mismatch causes each current source to deliver a slightly different current. This causes non-linearity in the transfer function. To determine the tolerable mismatch based on INL performance the following equation can be used [4]
NCII
221
=σ with ⎟
⎠⎞
⎜⎝⎛ +=
25.0_ yieldnorminvC ( 5.5 )
where σI/I is the standard deviation of a unit current source, N is the number of bits, inv_norm is the inverse cumulative normal distribution and yield specifies the percentage of DACs with an INL below ½ LSB. Figure 5.1 shows the yield plotted versus the current source mismatch.
Figure 5.1 Yield versus mismatch.
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In a 10-bit DAC this means that the matching has to be around 0.5% to get a reasonable yield.
5.1.5 Influence of noise on circuit performance There are basically two types of noise on the output of the DAC. One is thermal noise from the load resistor. The other one is the noise from the current sources. The thermal noise for a resistor is given by the formula below:
BWkTRVrms ⋅= 4 ( 5.6 )
where k is Boltzmann’s constant, T is the temperature, R is the resistor value and BW is the noise bandwidth. The noise from the current source is harder to analyze analytically and therefore has to be computed from simulations. These noise sources should be compared with the quantization noise. The quantization noise exists because the input signal is quantized. The general formula for calculating the SNR caused by quantization noise is given below.
dBNV
V
SNR N
LSB
ref
76.102.6223log20
12
22log20 +=⎟⎟⎠
⎞⎜⎜⎝
⎛=
⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛
= ( 5.7 )
In order to calculate the total SNR of the DAC one has to add up all noise sources. The formula will then look like below
⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛
+⋅+=
22
1023412
22log20
IunitLOADLSB
ref
VBWkTRV
V
SNR ( 5.8 )
where VIunit is the RMS noise voltage from one current source. When the noise level is the same as the quantization noise level a 3 dB loss in SNR occurs and if the noise level is half that of the quantization noise the loss in SNR is 1 dB.
5.1.6 Influence of graded errors on performance In the above analysis the mismatch errors are assumed to be uncorrelated. This is not entirely true in a real implementation. The fabrication process causes linear graded errors. These can be caused by a linear graded thickness in gate-oxide for instance. There are also symmetrical errors caused by resistance in interconnect wires on chip. In addition to these errors there are also parabolic errors that emerge during manufacturing. All these errors degrade the performance of the DAC. To lessen the impact of these errors a hierarchical symmetric switching scheme is used as described in [5]. The basic concept is to switch the current sources so that they as a group cancel the linear and symmetrical errors. An illustration of this can be seen in Figure 5.2 below.
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Figure 5.2 Illustration of the hierarchical symmetric switching scheme.
First current source 1 is switched on and then when number 2 is switched on it cancels out the symmetrical error. Number 3 and 4 cancel their symmetrical error in the same way and together with 1 and 2 they cancel the graded error as well. As described earlier each thermometer coded current source is divided into four separate current sources. This means that there will be four arrays of 255 current sources. Each one of these arrays has their current sources placed according to the switching scheme above. To further reduce the impact of gradients a common-centroid layout scheme is used, meaning that all current sources will have a common centre. This is accomplished by mirroring the four arrays about the centre. This method works well to cancel linear gradients but does less to cancel parabolic gradients.
5.1.7 Mismatch calculations The mismatch model used was described in [6]. The reason for using this model is the fact that it has been verified by measuring on a large amount wafers so that the results are reliable. The model takes the VT and β mismatch into account where β = µCoxW/L is the current factor. The VT mismatch is modelled as follows:
WLA
VV VT
T
T 0
0
0 =σ ( 5.9 )
and β as
WL
A 0β
βσβ
= ( 5.10 )
where AVT0 and Aβ are process dependent constants. This is where problems arise. To find out what value these constants have. In the best case the value of these constants are supplied by the manufacturer. If they are not one has to resort to approximations. Fortunately the constants are mostly dependent on the process technology (gate size) and not so much on the particular manufacturer. In a current-steering DAC the mismatch of interest is that between current sources. The formula below describes the mismatch in current in relation to VT and β mismatch:
2
2
20
02
2
2
)(4
ββσσσ
+−
=TGS
T
d
d
VVV
II ( 5.11 )
From this formula the current mismatch can be calculated given the size of the transistor and its bias point (overdrive voltage).
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5.2 MATLAB model
To study the impact of all the errors above together a MATLAB model was created. The model consists of three files DAC.m which is the model of the DAC, swmatris.m which generates the matrix for the switching scheme and run_DAC.m in which simulation parameters are entered. The code for these files can be seen in Appendix B. At first an ideal ADC is used to create the input signal to the DAC. Some noise is added to the input signal of the ADC to avoid spurious tones in the final spectrum. Parameters like those described above are fed into the model. These include noise, gradients and output impedance for instance. A current source matrix is created in MATLAB using the data on gradients and random errors (mismatch). An example of how this matrix may look can be seen in Figure 5.3 below.
Figure 5.3 Distribution of current in sources depending on the location on chip
What it shows is the current distribution as a function of the location on chip. To create the output current the currents from the different current sources are added according to input signal and switching scheme. The current is then converted into a voltage taking the limited output impedance into account. Finally the noise is added to the output signal. A spectrum of the output is created using an FFT. The spectrum can then be analyzed to calculate dynamic performance such as SFDR, SNDR and ENOB. The advantage of MATLAB simulations as opposed to circuit simulations is speed. MATLAB simulations are many times faster than a circuit simulator. This makes it possible to run many simulations and look at yield figures.
5.3 MATLAB simulations
During all simulations the sample frequency was kept at 80 MHz, the input signal was an 11 MHz sine wave (or ramp in the case of INL and DNL simulations). The current source output impedance has a value of 8 MΩ if nothing else is stated. The noise applied was extracted from cadence simulations and inserted into the model. The linear and parabolic gradients were arbitrarily chosen to a value that seems reasonable since there was no data available on such errors.
5.3.1 Simulating the nominal case The figures below were simulated with a current source mismatch of 0.5 % and using a hierarchical symmetric switching scheme. To look at yield figures 10000 simulations were run and the result was plotted as a histogram.
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Figure 5.4 Output spectrum.
Figure 5.5 SFDR.
Figure 5.6 ENOB.
Figure 5.7 INL.
Figure 5.8 DNL.
In Figure 5.4 a typical output spectrum from one of these simulations can be seen. Figure 5.5 shows the number of DACs with a certain SFDR. Up to around 72 dB it looks like normal distribution. After that there is a significant peak in number of DACs. This is caused by the fact that the SFDR is limited by other factors than mismatch. This causes the normal distribution to peak around 72.5 dB because there is another spurious tone that is larger than the one caused by mismatch and noise. Figure 5.6 shows the ENOB yield. It behaves more like normal distribution since it’s dependent on SNDR, which is integrated over the entire spectrum and therefore more dependent on noise and mismatch. Figure 5.7 and Figure 5.8 shows the static performance in form of INL and DNL respectively. They also behave like normal distributions although slightly skewed toward a lower value.
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5.3.2 Simulating the impact of reduced matching In the next following figures the impact of increased mismatch is shown by changing current source matching from 0.5% to 1.5%.
Figure 5.9 Output spectrum.
Figure 5.10 SFDR.
Figure 5.11 ENOB.
Figure 5.12 INL.
Figure 5.13 DNL.
In Figure 5.9 the output spectrum is shown. It shows that there are a bit more and larger spurious tones than before. Figure 5.10 shows the SFDR and it can be seen that the result is still skewed toward a higher value but there are more DACs at lower values. What is also interesting to note from this figure is that some DACs actually have better SFDR than at 0.5 % mismatch. This is due to the fact that in a few cases the mismatch actually cancels the effect of gradients. The ENOB plot in Figure 5.11 shows the same behaviour.
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Figure 5.12 and Figure 5.13 showing INL and DNL shows more of a deterioration in performance when mismatch increases. Not very many of the DACs are below the wanted level of 0.5 LSB INL. At 1.5 % mismatch the equation ( 5.5 ) shown earlier predicts that only 70 % of the DACs will be below 0.5 LSB INL. The simulations suggest that it’s even fewer than that. This is most probably caused by the gradients which aren’t taken into account in equation ( 5.5 ).
5.3.3 Simulating the impact of switching schemes The next step is to study the impact of the switching scheme. For the results below the current source matching is decreased to 0.5 % again. Instead of using the hierarchical symmetric switching scheme the current sources are just placed in increasing order so that the first current source resides in the upper left corner and the second one is one step to the right an so on. The current source matrix still comprises of four quadrants laid out in a common-centroid manner. From now on this will be referred to as the conventional switching scheme.
Figure 5.14 Output spectrum.
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Figure 5.15 SFDR.
Figure 5.16 ENOB.
Figure 5.17 INL.
Figure 5.18 DNL.
As can be seen from the spectrum in Figure 5.14 the second harmonic overtone becomes dominant and other spurs have also increased in amplitude. This is caused by gradients that are not cancelled well in the conventional switching scheme. Since a common-centroid layout is used the linear gradients are perfectly cancelled, the parabolic gradients however, are not. From Figure 5.15 showing SFDR it can be seen that the mean value has gone from around 72.5 dB to around 56 dB. That equates to a loss of 16.5 dB in SFDR. Looking at Figure 5.16, showing the ENOB, a significant loss in performance is seen here as well. It has gone from 9.8 bits to 8.8 bits, which equates to a loss of 6 dB in SNDR so it is not as bad as the SFDR. In Figure 5.17 and Figure 5.18 where INL and DNL are shown it can be seen that the INL has gone from around 0.5 LSBs to 2.9 LSBs. This is also caused by the fact that gradients aren’t cancelled well in the conventional switching scheme. The DNL however is not any different with this switching scheme. This is easily understood since DNL is the difference between two adjacent current sources. This means that the error is not that big since the distance between two sources is fairly small which means that the change in current caused by gradients will be fairly small as well.
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5.3.4 Simulating the impact of limited output impedance Another interesting simulation that can be done is testing the impact of output impedance. By lowering the output impedance in the model to 455 kΩ and looking at the output spectrum. Figure 5.19 below shows the spectrum from this simulation.
Figure 5.19 Output spectrum.
The spectrum clearly shows that the third harmonic overtone is now the dominating one as expected from the previous calculations. SFDR is around 60 dB, also expected from the calculations above.
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6 System implementation
6.1 System description
Since the DAC is meant for a zero IF transceiver, with the data stream modulated on quadrature I and Q carriers, there are actually two DACs on the same chip. A functional diagram of the DAC can be seen in Figure 6.1.
Figure 6.1 Functional diagram of the DAC.
The input signal passes through the input DFFs to make sure that the signal is in synch with the clock. It is then split up so that 2 bits are passed directly to the latches and 8 bits go through the binary-to-thermometer decoder. The binary-to-thermometer decoder generates 255 control signals, which are then put in to the latch network. From the latches the 2 binary bits are fed to their respective switch and the 255 control signals go into their switches. The switches are connected to the current sources. The main matrix consists of 1020 thermometer current sources and 3 binary current sources. When it comes to the thermometer coded current sources there are 4 sources connected to each switch. The binary switches have 1 and 2 current sources for their respective bits. The switches are placed outside the current source matrix to avoid interference between digital and analog parts. To ensure that the control signals arrive to the switches at the same time a clock tree is used to distribute the clock signal. The two DACs have a common reference for better matching between the two. The reference consists of a bandgap reference that generates a voltage, which is fed to the voltage-current converter. The bandgap has a control signal that allows an external reference to be used. This feature is realised by having a switch in series with the bandgap output, which allows the bandgap to be disconnected from the voltage-current converter. The voltage-current converter utilizes an external resistor to generate the reference current. The reason for this is that an off-chip resistor has better tolerance and less temperature dependency. It also gives the opportunity to measure
31
the voltage in that node. Since both input and output voltages from the voltage-to-current converter are measurable the offset voltage in it can be calculated.
6.2 Implementation of sub-circuits
The sub-circuits in this chapter are tested under widely varying conditions. The first step is usually to test on a schematic level. When a working circuit is made on the schematic level a layout is created. From this layout the parasitic resistances and capacitances are extracted. A simulation is done to see that the layout version behaves the same as the schematic or at a level that is acceptable. To make sure that the final fabricated circuit will work it is tested in the corners of the process. A corner is defined as a worst case of sorts. It can be either a high/low temperature or some maximum/minimum value specified in the process from the manufacturer or a minimum/maximum supply voltage. The manufacturer guarantees that all process variables will be within a certain interval and the corner defines the end point of this interval. The process corners in this report are specified as typical, ff, ss, sf and fs where typical is as the name implies the typical case. The rest are defined as where a transistor N- or P-MOS is either fast or slow. For example ss means that both N- and P-MOS are at their slowest. On top of this there is usually a worst-case corner as well. In an amplifier this is usually ss, maximum temperature and minimum supply voltage because this will give a minimum amount of voltage swing and slowest performance.
6.2.1 Current source The main task for the current source is to provide a constant current over the entire frequency and output voltage range. This means that the output impedance should be as large as possible.
6.2.1.1 Theory In its simplest form a current source for a differential current-steering DAC might look like in Figure 6.2 below.
Figure 6.2 A simple current source.
The top transistor PM0 is the current source and PM1 and PM2 are the switches. The signals driving the switches are complementary so that only one of the two switches is on at any given time. The problem with the simple current source is its limited output impedance. The output impedance can be increased by cascoding the current source. In Figure 6.3 a cascode current source is shown.
32
Figure 6.3 A cascoded current source.
In order to bias this current source and get the maximum possible voltage swing available on the output, a wide-swing architecture is used [1]. It works by biasing PM0 so that its drain-source voltage is as close to the minimum voltage possible without going into the triode region. In order to achieve this the bias circuit shown in Figure 6.4 is used.
Figure 6.4 Bias generation circuit.
6.2.1.2 Implementation The size of the current source transistor is determined by mismatch calculations. It has to have a certain area to achieve the required matching as described in section 5.1.7. The size of the cascode is determined by simulations to achieve maximum output impedance. The cascode will also have some impact on matching but the exact numbers are hard to determine. The switches are made as small as possible to reduce glitches on the output. One difference from the theory above is the fact that there are four current sources connected to each switch for layout technical reasons. When it comes to the bias circuitry there are some differences from the theory above. Since there are only four bias circuits per DAC, because of area and power constraints, each bias circuit is loaded by 255 current sources. To keep the reference voltages stable the current in each bias circuit is 8 times the current in one current source. This lowers the output impedance of the bias circuit. To further help keeping the voltage stable both Vb1 and Vb2 are decoupled to VDD_A. The reason for connecting the decoupling capacitor to VDD instead of GND is that the output current is determined by Vgs-PM0, which is referred to VDD.
6.2.1.3 Results Shown in Figure 6.5 is the result from a simulation on output impedance. In order to achieve 10-bit performance the output impedance in one current source has to be larger than 455 kΩ. The smallest unit is four current sources connected through one switch and that is what has been simulated. This means that in the figure below the
33
value has to be above 113,75 kΩ in order to achieve 10-bit performance. This is true for all frequencies below 635 MHz. Which means that theoretically this is the limit on the analog bandwidth. This limited output impedance causes a gain error at higher frequencies as described earlier. In Table 6.1 the gain error in % can be seen versus frequency. Another important parameter when it comes to the current source is the amount of noise that one current source produce. As describe earlier in section 5.1.5 the noise level has to be lower than the quantization noise. Simulations show that one current source has about 303 nV RMS noise. Using equation ( 5.8 ) one can calculate the SNR of the DAC. The load resistor is 60 Ω and differentially this equates to a voltage noise of 8.9 µV RMS with a bandwidth of 40 MHz. The quantization noise has a value of 169 µV RMS with a 600 mV full-scale voltage. Putting these numbers into the equation for SNR yields a value of 61.94 dB, which is very close to the theoretical maximum of 61.96 dB.
Figure 6.5 Output impedance versus frequency.
Output frequency [MHz] Gain error [%]
1 0.02
8.125 0.2
16 0.38
32 0.77
64 1.53
128 2.95
256 5.66
Table 6.1 Gain error versus frequency.
34
6.2.2 The binary-to-thermometer decoder
6.2.2.1 Theory A systematic approach of the binary to thermometer decoder is based on a 2-bit converter [7]. To increase the number of binary inputs, a new logic level is added for each extra bit. Truth tables and De Morgan’s laws are used between every stage to find the optimum number of gates.
Figure 6.6 A 2-bit inverting binary to thermometer decoder.
This results in an arbitrary equation for every level of even or odd binary bits. The equations are shown below. The left equation is for even, and the right for odd bits. N is the number of binary bits, and tx inside the brackets is the output from the previous stage.
⎪⎪⎩
⎪⎪⎨
⎧
−≤<−⋅
−=
−<≤+
=−
−−
−−
−−
− 1212,
12,
120,
112
11
11
1NN
Nx
NN
NNx
x
xbt
xb
xbt
t
N
( 6.1 )
⎪⎪⎩
⎪⎪⎨
⎧
−≤<−+
−=
−<≤⋅
=−
−−
−−
−−
− 1212,
12,
120,
112
11
11
1NN
Nx
NN
NNx
x
xbt
xb
xbt
t
N
( 6.2 )
This method makes it easy to automatically generate a schematic with the desired number of inputs.
Figure 6.7 Even respectively odd binary number of inputs at schematic level.
35
6.2.2.2 Design A SKILL script was written to generate the decoder schematic. The script can be found in Appendix C. When adding an input bit, it gets a large fan-out, . In this 8-bit converter the binary MSB’s were buffered to compensate for the increasing rise and fall time.
12 −N
Verilog-XL produces a verilog netlist when a simulation is executed, and that netlist was used to import the design into Silicon Ensemble. The matrix signals must be rearranged somewhere between the Flip-Flops and switches to fit our switching scheme. To facilitate the layout work, the output pins placements were changed in SE. By combining GDS and DEF-exports from SE, the design was imported back to Cadence Virtuoso for DRC, extraction, LVS, simulation and some post route optimization [8].
Figure 6.8 Design flow for the binary to thermometer decoder.
6.2.2.3 Results The simulated maximum delay through the decoder was 645 ps on a schematic level, which is more than enough with our clock strategy. Since there is a delay of 50 ps between the clock to the flip-flops and the latches the actual delay will be 695 ps. This delay sets the DAC’s highest update rate to 720 MHz. The extra delay is there to make sure that the latch is in its non-transparent mode when new data is clocked in. The flip-flop is triggered on the positive edge and the latch is in its transparent mode when the clock is high and in its latched mode when the clock is low.
36
Figure 6.9 The decoder’s maximum tolerated delay at 80 MSPS.
6.2.3 Latches
6.2.3.1 Theory A matrix of latches is used to synchronize all thermometer-coded bits with the binary ones. The output bits are differential and connected to the switch array. The outputs are designed to switch on one side before it switches off the other because we want to keep the current sources from turning off during switching. The outputs intersect just above zero volts since the switches are made with PMOS transistors.
Figure 6.10 Desired outputs from the latches.
8 bits converted to thermometer code and 2 binary bits results in 257 latches, which will dominate the total digital power consumption. This, combined with the desired intersection point of the outputs, made it impossible to use standard cells.
6.2.3.2 Design The latch is based on a modified clocked SR-flip-flop [9]. The set and reset inputs are replaced with data and inverted data, D and DN in Figure 6.11 below.
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Figure 6.11 Schematic of the latch.
The first inverters have slow N and fast P-transistors to delay signals with rising edges, and the last inverters buffers the outputs. NM8 and NM9, the clock transistors, are minimum size to reduce clock feed through. The buffers also contribute to this. The current source matrix layout sets the switch array height, which is equal to the height of the latches to simplify their connections. There are 32 rows of latches in the array, the same as the switches and current sources. Since there are 8 thermometer and 2 binary bits, it results in 8 latches per row, and one row with an extra latch. To prevent skew between the outputs of this large block, a clock tree was implemented.
6.2.3.3 Results The output delays when receiving a positive edge from the clock tree are shown in Table 6.2. The arrows stand for rising or falling edges of the signal.
clk ↑ t [ps]
D ↑ 225
DN ↓ 163
D ↓ 216
DN ↑ 291
Table 6.2 The maximum output delay without clock tree.
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The switch is on when Vg drops below 180 mV, which is the maximum required intersection point. This was achieved at all corners. See Table 6.3.
Intersection point [mV] VDD [V]
T [°C]
Typical ss sf fs ff
0 6 4 30 4 9 1.65
110 17 11 68 7 26
0 9 6 44 5 14
27 12 8 52 6 17 1.8
110 25 17 86 11 36
0 13 9 56 6 19 1.9
110 30 22 100 13 44
Table 6.3 The intersection points at all process and environmental corners.
There is clock feed through when data is stored on the latch. The first inverter reduces this spike by 23.4 dB. And the buffer decreases it with 17.3 dB.
39
6.2.4 Bandgap reference
6.2.4.1 Theory The basic idea behind a bandgap reference is to create a stable voltage reference independent of process variations and temperature. The basic principle of the bandgap is to use a forward biased diode (base-emitter junction) as a base for the reference voltage. Because the voltage over the base-emitter junction has a negative temperature coefficient one has to compensate for this by adding a voltage that is proportional to absolute temperature (PTAT). The PTAT is realized by amplifying the voltage difference between two forward biased junctions biased at different current densities. Figure 6.12 below shows the conventional bandgap architecture in a CMOS process. Although independent bipolar transistors are not available in CMOS, well transistors with their collector connected to the substrate (ground in a p- substrate) usually are.
Figure 6.12 The conventional bandgap architecture.
It can be shown [1] that to get a zero temperature coefficient at some temperature T the following demand must be met:
( ) ( ) 01ln1ln1 0
1
2020
0
=⎟⎟⎠
⎞⎜⎜⎝
⎛−⎟
⎠⎞
⎜⎝⎛−+⎟⎟
⎠
⎞⎜⎜⎝
⎛+−=
∂∂
− TT
qkm
JJ
qkKVV
TTV
GBEref ( 6.3 )
where T0 is the reference temperature, VBE0-2 is the base emitter voltage for Q2 at the reference temperature, K is a factor dependent on the different current densities, k is Boltzmann’s constant, q is the elementary charge and m is a temperature constant approximately equal to 2.3. By solving ( 6.3 ) and identifying Vref it can be shown that:
( )q
kTmVV Gref0
00 1−+=− ( 6.4 )
where VG0 is the bandgap voltage of silicon at 0 K (equal to 1.206 V). In the case where T0 = 300 K this implies that:
VVref 24.10 =− ( 6.5 )
for zero temperature dependence. Which is basically the bandgap voltage plus a correction term for second order effects, hence the name bandgap reference for this type of reference. The problem with the conventional bandgap is that in a 0.18 µm process the 1.24 V output voltage referred to ground leaves little headroom to the supply voltage, which normally sits at 1.8 V. In the DAC, the bandgap reference voltage is fed to a voltage-
40
to-current converter, which creates the reference current for the current sources. Since getting this converter to work with an input voltage that close to the supply voltage is fairly hard it is desirable to have an output voltage from the reference that is closer to ground. For reasons stated above the architecture chosen for the bandgap is a low-voltage one [10]. The advantage with this kind of architecture is that it gives a larger margin to the supply voltage. Another nice feature of this architecture is the fact that the output voltage is easily changed.
6.2.4.2 Implementation The low voltage architecture implemented is shown below in Figure 6.13. The basic principle of this architecture is the same as for the conventional one. It uses two junctions biased at different current densities. Since PM1 and PM3 are biased equally and are of the same size the current through Q0 and Q1 is identical. To get a different current density through Q0 and Q1 transistor Q1 is made larger than Q0. Practically, this is solved by paralleling a number of identical devices. The output voltage from the bandgap can, according to [10], be written as:
⎟⎟⎠
⎞⎜⎜⎝
⎛+=
52
03 R
dVR
VRV ff
ref ( 6.6 )
where Vf0 is the voltage over Q0 and dVf is the voltage over R5. For a more detailed description of the bandgap see [10]. As seen from ( 6.6 ) the output voltage is only dependent on the ratio between the resistors and not on the absolute value.
Figure 6.13 Schematic of the low-voltage bandgap architecture.
Other things that can be noticed in the schematic are the three rightmost transistors that work as a startup circuit for the bandgap. It is simply made up of an inverter where PM5 has a small W/L ratio and NM1 has a fairly large W/L ratio. If Vref is lower than the threshold voltage for NM1 the inverter output will go high which will turn on transistor NM5. NM5 pulls the gate voltages on PM1, PM2 and PM3 low, which force the bandgap to reach its normal bias point. When the output reaches its nominal value the inverter will go low and turn off NM5 and the bandgap returns to its normal operation. Another detail to be noted is C0, which sits there to stabilize the circuit.
41
With this type of circuit in an on-chip environment it’s hard to analytically calculate the values of the resistors. This is because the resistor values are also dependent on temperature. To solve this problem the optimizer function in cadence was utilized. It works by giving it a number of variables to sweep and a few demands to meet. In this particular case the values of R4 and R2 were set and R5 and R3 were swept. The demands to meet were set as an absolute value as close to 500 mV as possible and Vref-max –Vref-min lower than 300 µV from 0 to 110º C. During the layout phase a few things were taken into consideration. Since the ratios between the resistors sets the output voltage and also affects the temperature stability it’s important that the resistors are well matched. To assure adequate matching the resistors were divided into unit blocks of similar size. These unit blocks are then distributed evenly over the total area that the array of resistors consumes. To ensure that the matching is adequate after all the unit blocks are connected together one has to consider the impact of parasitic resistance. The parasitic resistance comes from interconnect wires and contacts. The resistor array has been laid out so that the relative error caused by parasitic resistance is the same for all resistors. The bipolar transistors also have to be well matched. To ensure good matching a common centroid layout scheme was used. By placing Q0, which is a single transistor, in the middle and the individual blocks that make up Q1 around it a square matrix with a common centre for both Q0 and Q1 was created. An outer ring of dummy transistors ensures that all transistors have an equal surrounding environment.
6.2.4.3 Results Simulations were run over the specified temperature range of 0-110 ºC to verify its function. In Figure 6.14 below the output voltage vs. temperature can be seen in the typical case with a supply voltage of 1.8 V. Simulations were also run in the different process corners and different supply voltages to make sure that the bandgap operates properly under worst case conditions. The results of these simulations can be seen in Table 6.4 below. For future reference it was also interesting to see how low the supply voltage could go before the output strays to far from the nominal value. The result of this can be seen in Figure 6.15 below. The conclusions that can be drawn from this figure is that the bandgap works very well down to around 1.2 V supply voltage. The influence of power supply noise was investigated by looking at the power supply rejection ratio, PSRR. The simulation was run with an external capacitor of 470 pF through a model of the bond wire. A plot of PSRR versus frequency can be seen in Figure 6.16. The PSRR is good at low and medium frequencies. At low frequencies because the opamp gain is high there and the feedback loop will eliminate a lot of the noise. At medium frequencies the capacitor on the output will attenuate the noise. At high frequencies it’s very hard to eliminate the noise because the external capacitor’s effectiveness is limited by the bond wire. Finally a test was made to see how long it takes for the output voltage to stabilize after power on. The simulation was done with an off-chip capacitor with a value of 470 pF. This value was chosen because up to this value the increase in PSRR is notable. Any larger than this provides very little gain in PSRR and only increases startup time. The result is shown in Figure 6.17 below. The first part of the curve is where the startup circuit is still on and provides extra current to charge the external capacitor. Around 350 mV the startup circuit deactivates and the capacitor is charged with a constant current.
42
Figure 6.14 Reference output voltage versus temperature.
Corner VDD [ V ] Absolute
resistance variation
Vout @ 27 °C
[mV]
∆Vout for 0 –110 °C
[mV]
∆Vout/(Vout @ 27 °C)
[%]
Power consumption
@ 27 °C [µW]
typical 1.65 -15 % 502.4 0.73 0.15 166
typical 1.8 -15 % 502.3 0.85 0.17 185
typical 1.9 -15 % 502.2 0.9 0.18 199
typical 1.65 0 % 500.3 0.33 0.066 160
typical 1.8 0 % 500.2 0.28 0.056 179
typical 1.9 0 % 500.2 0.3 0.060 193
typical 1.65 + 15 % 499.0 0.64 0.13 156
typical 1.8 + 15 % 498.9 0.57 0.11 174
typical 1.9 + 15 % 498.9 0.53 0.11 187
ss 1.9 -15 % 502.2 0.9 0.18 195
ff 1.9 -15 % 502.2 0.9 0.18 201
sf 1.9 -15 % 502.3 0.9 0.18 202
fs 1.9 -15 % 502.1 0.9 0.18 193
Table 6.4 Output voltage and relative error in different process corners.
43
Figure 6.15 Output voltage versus supply voltage.
Figure 6.16 PSRR versus frequency.
Figure 6.17 Transient response during startup.
44
6.2.5 Voltage-to-current converter
6.2.5.1 Theory Since the reference has a voltage output and a current reference is needed for the current sources a design is needed to convert between the two. Figure 6.18 below shows the basic concept behind the converter [11].
Figure 6.18 Schematic of voltage-to-current converer
The same basic function could be performed using only the transistor and resistor. However it would not be as accurate and not as temperature stable. The simple circuit would have a transfer function like below:
inm
ref VRgR
I ⎟⎟⎠
⎞⎜⎜⎝
⎛+
=/1111 ( 6.7 )
So what the opamp in the above figure does, is to work as a gain-boost for the transistor and it essentially increases the transconductance of the overall circuit so that the transfer function looks like below instead:
in
m
ref V
RgAR
I
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⎟⎟⎠
⎞⎜⎜⎝
⎛++
=1111
11 ( 6.8 )
where A is the open-loop gain of the opamp. If the gain is large enough it can be approximated by:
RVI in
ref = ( 6.9 )
so that the current is only dependent on the input voltage and the resistor value.
6.2.5.2 Implementation In this design the opamp was realized with a folded-cascode architecture [11]. The advantage of this is that the converter is fully functional down to 0 V input voltage. In Figure 6.19 the schematic of the converter is shown.
45
Figure 6.19 Schematic of the complete voltage-to-current converter
The purpose of the converter is, as stated, to generate the reference currents for the DAC. Each DAC needs 8 reference currents since the bias is distributed over the chip. Since there are two DACs the total number of currents needed is 16. In Figure 6.19, only three of these are shown. To generate all these currents the output current from the converter is mirrored through PM11 and PM12 down to NM20, which forms a current mirror with the 16 output transistors. The capacitor on the output of the opamp is there to stabilize the circuit. Since Vout is fed to an off-chip resistor it will have to pass through a bond-wire. This will make the whole circuit susceptible to instability by decreasing the phase margin. It is therefore important to make the capacitor slightly larger than it would be with an on-chip resistor.
6.2.5.3 Results Important things to check for in a design like this are stability, linearity and temperature stability. In Figure 6.20 below the AC response is shown. Phase margin in this figure is around 82º. With a model of the bond wire and external parasitic capacitance connected to Vout, phase margin is degraded to around 75º leaving plenty of margin for unforeseen effects. Linearity in this case means how well the output current tracks the input voltage. The easiest way to verify this is by looking at the output voltage versus input voltage since the voltage over the resistor determines the output current. The results of this can be seen in Figure 6.21. The converter is linear within 0.5% from 100 mV to 850 mV. The error around its intended working voltage of 500 mV is 0.02%. The degradation in performance at lower and higher voltages is caused by lower loop-gain in the opamp when its output voltage comes closer to the supply. Temperature versus out current if plotted in Figure 6.22. It shows that the output current changes around 90 nA from 0-110ºC. This equates to a 0.2 % change in output current.
46
Figure 6.20 Bode plot of the voltage-to-current converter
Figure 6.21 Output versus input voltage
Figure 6.22 Reference current versus temperature
47
6.2.6 Voltage-to-current converter bias circuitry
6.2.6.1 Theory The opamp used in the V-I converter is a folded-cascode architecture. This means that it needs four different bias voltages. Two for the current source on the N- and P-side respectively and two for the cascodes on each side. The bias net used is depicted in Figure 6.23 below.
Figure 6.23 Schematic of the bias circuitry.
This type of bias circuit is called stable transconductance [1]. This is because it keeps gm of the transistors in the opamp stable regardless of supply voltage, process and temperature variations. It works by stabilizing the transistors transconductance to the resistors conductance as shown in [1].
6.2.6.2 Implementation The four rightmost transistors work as a startup circuit. The startup circuit is necessary because the bias circuitry has two stable states, one being its normal operating region the other being zero current. R0 is the resistor that stabilizes the transistor transconductance. In this case it’s realized with an on-chip resistor. It could be realized with an off-chip resistor but the external parasitics can cause oscillation. The disadvantage to using an on-chip resistor is the fact that its value is dependant on temperature and that its absolute value will have a large variation. The temperature coefficient is fairly low and shouldn’t be a problem though.
6.2.6.3 Results The performance aspects of interest can only be tested together with the V-I converter. If it works the way it’s supposed to it shouldn’t have any effect on the performance of the V-I converter.
48
7 Results and conclusion
7.1 The complete system
A layout of the complete system can be seen in Figure 7.1 below.
Figure 7.1 Layout of the complete chip
The bandgap reference and voltage-to-current converter resides in the middle of the chip. On each side of it there is one DAC, one for the I-channel and one for the Q-channel as described earlier. The lower part of the DAC is the current source matrix. The part above that, that resembles an arrow, is just the interconnect wiring from the matrix to the switches. The next part above that consists of switches, latches, digital decoding net and DFFs. Everything outside the main layout consists of decoupling capacitors.
7.2 Challenges of system simulations
The complete quadrature DAC and bandgap ends up being around 19000 transistors. This makes simulations on the complete system fairly difficult and mostly time consuming. It is not too difficult on a schematic level but the results provided from it are not good enough to accurately predict the final chip behavior. This is because parasitics in interconnect wires and circuits to a large extent determine the performance of the system. The problem encountered when trying to simulate with extracted parasitics is that it is extremely time consuming. Another problem is the fact that the layout of the complete system is so complex that the extraction tools can not do an extraction of the whole chip. The only way to get somewhat accurate results is by running the most critical blocks with extracted parasitics and less critical blocks in schematic.
49
Another difficulty during the final stages of simulation is the impact of bond wires on performance. This is mainly because there are no good models for the bond wires and a small change in the model leads to large changes in performance.
7.3 Simulation results
The DAC was tested with the specified load of 60 Ω at 80 MSPS. The input signal was an 11 MHz sine wave. The outcome of this simulation can be seen in Figure 7.2.
Figure 7.2 Differential sine wave current output.
As can be seen from this plot the response is fairly controlled with some minor glitches before a transition. The simulation was done without bond wires for reasons explained earlier. Estimated power consumption is around 22 mW for both DACs and bandgap reference. Of these 22 mW 2mW is consumed in the digital parts and 20 mW is consumed in the analog parts. The power wasted in the pads is not included in this figure.
7.4 Conclusions
Is has been shown that it’s possible to design a 10-bit DAC in a 0.18µm CMOS process. It has been shown that there are three limits on the update rate of the converter and one of them will decide the final update rate. The first limit is output impedance, which places a limit on the highest output frequency that can be reproduced without too much distortion. This doesn’t really limit the update rate unless operation up to Nyquist is wanted. In this converter the maximum output frequency is limited to 635 MHz, which, if operation up to Nyquist is desired, limits the update frequency to 1.27 GHz. The second limit is imposed by the digital net because of its delay. The data from the digital net must be available within half a clock cycle. The delay through the digital net is 695 ps, which limits the update rate to 720 MHz. Another limiting factor is the slew-rate of the output or settling time. The DAC has to settle before the next step is taken. The settling time is around 2 ns, which limits the update frequency to 500 MHz. Finally there is actually one more limit on
50
update frequency that is much harder to decide. That is the one caused by noise on supply lines and ringing on the output both of which are caused by bond wires. The biggest challenge is to accurately model all errors that are not shown in a circuit simulator such as noise and mismatch. There are also many other unknown factors that might degrade performance such as substrate coupling, crosstalk between digital and analog and the impact of bond wires.
7.5 Possible improvements for future development
The most probable cause of error in the chip is power supply noise. Preliminary simulations show that noise from the digital supply can get coupled over to the output signal. So in future versions some way of isolating the digital supply from the analog parts might have to be implemented. Measurements will show how much of a problem this really is.
51
52
8 Measurements
8.1 Introduction
All measurements have been performed with a single-ended load of 50 Ω and a full-scale current of 5 mA. During dynamic measurements the differential signal was converted to a single-ended signal using a balun. The output signal was analyzed using a spectrum analyzer. During the static measurements the differential-to-single-ended conversion was done with a precision opamp and the output was measured with a multimeter.
8.2 Static measurements
To verify the function of the bandgap reference its output voltage was measured on two different chips. The nominal output was 500 mV. On one chip it was measured to 499 mV and the other was measured to 511 mV. INL and DNL were measured by using a ramp as input signal to the DACs. The results are presented below:
Figure 8.1 I-DAC DNL Figure 8.2 Q-DAC DNL
Figure 8.3 I-DAC INL Figure 8.4 Q-DAC INL
53
As can be seen DNL is within ±0.4 LSB and INL within ±0.6. Due to noise during the measurements the measured results are slightly pessimistic. To make more accurate measurements it would have been preferable if one could have taken the mean value of several measurements instead of just one. Due to time constraints this was not possible, however, a short measurement series was done by taking the mean value of 4 measurements on each level for the first 100 data values. It could be seen that the performance was slightly better than the one presented above.
8.3 Dynamic measurements
To determine the DACs dynamic performance SFDR, THD, SNDR and ENOB were measured. The results from these measurements can be seen below:
SFDR [dBc] @ fsignal [MHz]
40 [MSPS] 80 [MSPS] 125 [MSPS] 175 [MSPS]
0.756 78 77 77
1.7 73 73 73 73
3.3 73 72 71
5.5 67 68 69 67
7.3 65 70 68
9.7 60 69 67 63
13 57 66 65
17 54 62 65 62
22 61 61
37 55 54 58
47 57
61 52 52
86 49
Table 8.1 Measured SFDR performance at different update rates
THD [dB] @ fsignal
[MHz] 40 [MSPS] 80 [MSPS] 125 [MSPS] 175 [MSPS]
0.756 -72.2 -71.4 -71.0
1.7 -67.4 -70.8 -69.2 -68.0
3.3 -68.0 -68.4 -66.9
5.5 -64.6 -63.9 -61.9
7.3 -62.7
9.7 -60.0
Table 8.2 Measured THD performance at different update rates
54
Figure 8.5 ENOB versus signal frequency
From Table 8.1 and 8.2 it can be seen that the performance is good for all but the highest frequencies. Figure 8.5 shows the ENOB versus signal frequency at 80 MSPS. It can be seen that the performance is good all the way up to 22 MHz. There were some problems during the measurements with the equipment used. Due to the fact that the clock from the pattern generator deteriorated the performance an external clock source was used. The external source triggered the pattern generator, which sent the data to the DAC. It proved to be difficult getting this to work perfectly due to the internal delay of the pattern generator. This might have caused some deterioration of the measured performance.
55
Below some typical output spectrums are presented:
Figure 8.6 Measured output spectrum at 80 MSPS with a 9.7 Mhz input signal
Figure 8.7 Measured output spectrum at 80 MSPS with a 22 Mhz input signal
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9 References
[1] David A. Johns and Ken Martin, ”Analog Integrated Circuit Design”, John Wiley & Sons Inc, ISBN 0-471-14448-7.
[2] Mikael Gustavsson, J. Jacob Wikner and Nianxiong Nick Tan, “CMOS Data Converters for Communications”, Kluwer Academic Publishers, 2000, ISBN 0-7923-7780-X.
[3] A. Van den Bosch, M. Steyaert & W. Sansen “SFDR-Bandwidth limitations for high-speed high-resolution current-steering CMOS D/A converters”, in Proc. IEEE Int. Conf. Electronics, Circuits and Systems (ICECS), Sept. 1999, pp.1193 –1196.
[4] Anne Van den Bosch, Marc A. F. Borremans, Michel S. J. Steyaert and Willy Sansen, ”A 10-bit 1-Gsample/s Nyquist Current-Steering CMOS D/A Converter”, IEEE Journal of Solid-state Circuits Vol. 36, March 2001.
[5] Yasuyuki Nakamura, Takahiro Miki, Atsushi Maeda, Harufusa Kondoh and Nobuharu Yazawa, ”A 10-b 70-MS/s CMOS D/A Converter”, IEEE Journal of Solid-state Circuits Vol. 26, April 1991.
[6] Marcel J. M. Pelgrom, AAD C. J. Duinmaijer, Anton P. G. Welbers, ”Matching Properties of MOS Transistors”, IEEE Journal of Solid-state Circuits Vol. 24, October 1989.
[7] K. Ola Andersson, Niklas U. Andersson, Mark Vesterbacka, and J. Jacob Wikner, “A 14-Bit Dual Current-Steering DAC”, SSoCC, 2003.
[8] H. Hassander and C. Lindholm, ”Simulering, layout och verifiering av mixed-mode-kretsar i Cadence”, Del av rapport i IC-projekt – Electroscience LTH , Maj 2003.
[9] Jan M. Rabaey, “Digital Integrated Circuits a Design Perspective”, Prentice Hall International, 1996, ISBN 0-13-394271-6.
[10] Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa, Shigeru Atsumi and Koji Sakui, ”A CMOS Bandgap Reference Circuit with Sub-1-V Operation”, IEEE Journal of Solid-state Circuits Vol. 34, May 1999.
[11] Johan H. Huijsing, “Operational Amplifiers Theory and Design”, Kluwer Academic Publishers, 2001, ISBN 0-7923-7248-0.
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58
Appendix A
The following pages shows the Taylor expansion done in Maple. The first one is the single-ended case and the other one is the differential. Single-ended: //The output signal as a function of gimp=1/Rl > f:=N*Ir*(x+1)/(2*gl+gimp*N*(x+1));
//Taylor expansion to the 5th order > tay:=mtaylor(f,x,5);
//Replace x with sin(wt) to be able to identify harmonics > tayt:=subs(x=sin(wt),tay);
//Break out all terms containing sin or cos > tayc:=combine(tayt,trig);
//Calculate the coefficient for cos*(2wt) which is the //second harmonic > HDS:=coeff(tayc,cos(2*wt));
//Calculate the coefficient for sin(wt) which is the //signal > A:=coeff(tayc,sin(wt));
59
//Set the demand on SFDR to at least 60 db > Q:=simplify(HDS/A)=.001;
Here are the MATLAB programs that were written to simulate the function and the impact of different errors on the DAC. function [SFDRar,nobbar,maxinl,maxdnl,Itot]= DAC(nSample,Fsamp,Fsig,overtoner,noit,funk,sv); %ADC %Ramp if (funk==1) data = [0:1:1023]; end %Sin if (funk==2) w = 2*pi*Fsig; tid = [0:nSample-1]./Fsamp; brus = 0.3*rand(size(tid)); data = round(1023*(1+sin(w*tid))/2+brus); end %OFDM if (funk==3) Fsig=(312.5e3:312.5e3:26*312.5e3); w=2*pi.*Fsig; tid=[0:nSample-1]./Fsamp; phi=2*pi*rand(26); sig=zeros(26,nSample); for i=1:26 sig(i,:)=0.07807*sin(w(i)*tid+phi(i)); end sigtot=sum(sig); brus = 0.3*rand(size(tid)); data = round(1023*(1+sigtot)/2+brus); end %DAC Rimp = 8e6;%Vid 20 MHz Rl= 60; N =1023; Iref=5e-3/N; sd=0.502/100; gradient=4/400; gradpolx=5/400; gradpoly=5/400; Lnoise=6.3e-6; Inoise=3.03e-7; %Konventionell symmetrisk matris %i=1; %for k=1:16 % for l=1:16 % imatris(k,l)=i;
63
% i =i+1; % end %end %Generera hierarkiskt switchad matris [imatris]=swmatris; %Generera gradienter t=[-1:2/31:1]; xpolgrad=-gradpolx*t.^2-gradpolx; ypolgrad=-gradpoly*t.^2+gradpoly; xgrad=[0.5-gradient:2*gradient/31:0.5+gradient]+xpolgrad; ygrad=[0.5-gradient:2*gradient/31:0.5+gradient]+ypolgrad; for k=1:32 for l=1:32 gradmat(k,l)=xgrad(k)+ygrad(l); end end %Sortera strömmatrisen så att koordinaterna för källa 1 ligger först i vektorn ims for k=1:255 [a,b]=find(imatris==k); ims(k,:)=[a,b]; end imsp=ims; imsn=flipud(ims); %Starta iterationsprocessen for j=1:noit %Generera strömkällor Irefs=Iref+Iref*sd*randn(32,32); Ibin=Iref+Iref*sd*rand(1,3); Ibinp=Ibin; Ibinn=fliplr(Ibinp); Itot=Irefs.*gradmat; %Spara strömmatrisen if (sv==1) save strom_matris Itot else load strom_matris end %Generera brus Noisetot=sqrt(N*Inoise^2+2*Lnoise^2)*randn(size(data)); %Räkna fram total ström genom att räkna fram varje summa av strömkällor Iutsump=zeros(1,1024); Iutsumn=zeros(1,1024); for i=1:4:1020 for k=1:3 Iutsump(i+k)=Iutsump(i+k-1)+Ibinp(k); Iutsumn(i+k)=Iutsumn(i+k-1)+Ibinn(k); end
64
rowp=imsp(fix(i/4)+1,1); colp=imsp(fix(i/4)+1,2); rown=imsn(fix(i/4)+1,1); coln=imsn(fix(i/4)+1,2); %Summera källorna enligt common-centroid (varje kvadrant flippad %så att enskilda källor får gemensamt centrum) Iutsump(i+4)=Iutsump(i)+Itot(rowp,colp)+Itot(rowp,33-colp)+Itot(33-rowp,33-colp)+Itot(33-rowp,colp); Iutsumn(i+4)=Iutsumn(i)+Itot(rown,coln)+Itot(rown,33-coln)+Itot(33-rown,33-coln)+Itot(33-rown,coln); %Summera källorna utlagda likadant (ingen rotation av kvadranter) %Iutsump(i+4)=Iutsump(i)+Itot(rowp,colp)+Itot(rowp,17-colp)+Itot(17-rowp,17-colp)+Itot(17-rowp,colp); %Iutsumn(i+4)=Iutsumn(i)+Itot(rown,coln)+Itot(rown,17-coln)+Itot(17-rown,17-coln)+Itot(17-rown,coln); end for k=1022:1024 Iutsump(k)=Iutsump(k-1)+Ibinp(k-1021); Iutsumn(k)=Iutsumn(k-1)+Ibinn(k-1021); end for i=1:length(data) Ioutp(i)=Iutsump(data(i)+1); Ioutn(i)=Iutsumn(1024-data(i)); end %Räkna ut utspänningen voutp= (2*Ioutp)./((2/Rl)+(1/Rimp)*2*data); voutn= (2*Ioutn)./((2/Rl)+(1/Rimp)*(2046-2*data)); Idiff=Ioutp-Ioutn; vdiff=voutp-voutn+Noisetot; Vref1=max(vdiff)-min(vdiff); Vref=600e-3; %Utför analys av resultatet beroende på vilken test som körts if funk==1 A=[ones(size(data))', data']; yfnutt=vdiff'; c = A\yfnutt; inl=(vdiff'-A*c)./(Iref*Rl); for m=1:length(data)-1 dnl(m)=(vdiff(m+1)-vdiff(m)-2*Iref*60)/(Iref*60); end maxdnl(j)=max(abs(dnl)); MaxDNL=maxdnl(j) maxinl(j)=max(abs(inl)); MaxINL=maxinl(j) SFDRar=0; nobbar=0; j end matrX=[1:32]; matrY=[1:32]; if funk==2 fullfft;
65
FOM nob1=FOM(63:67); SFDRvar=FOM(44:48) figure(1) SFDRvar=str2num(SFDRvar); SFDRar(j)=SFDRvar; nob1=str2num(nob1); nobbar(j)=nob1; maxinl=0; maxdnl=0; j end if funk==3 fullfft; FOM nobbar=0; SFDRar=0; maxinl=0; maxdnl=0; end end
66
function m=swmatris(); m=zeros(4,8); mtmp=zeros(8,8); i=1; for j=1:4 m(i,j)=256 - 4*(j-1); end for k=1:4 m(i,j+k)=m(i,j) + 4*(k-1)-1; end for i=2:4 for j=1:8 m(i,j)=m(1,j)-64*(i-1); end end m2=flipud(m) - 16; mtmp=[m;m2]; mtmp4=fliplr(flipud(mtmp)); mtmp1=fliplr(flipud(mtmp4)) - 2; mtmp2=fliplr(mtmp1) - 30; mtmp3=fliplr(flipud(mtmp2)) - 2; m=[mtmp1 mtmp2 ; mtmp3 mtmp4];
67
clear; nSample=4096; Fsamp=80e6; Fsig=11e6; overtoner=9; noit=100; Vref=600e-3; funk=2;%1=Ramp 2=Sinus 3=OFDM save_yes=1;%1=Skapa och spara stromkallor [SFDR,ENOB,maxinl,maxdnl,Itot]=DAC(nSample,Fsamp,Fsig,overtoner,noit,funk,save_yes); matrX=[1:32]; matrY=[1:32]; %figure(1) %surf(matrX,matrY,Itot); matrX=[1:noit]; matrY=[1:noit]; if funk==1 figure(2) hist(maxinl,50); xlabel('INL [LSB]'); ylabel('Number of DACs') figure(3) hist(maxdnl,50); xlabel('DNL [LSB]'); ylabel('Number of DACs') end if funk==2 figure(2) hist(SFDR,50); xlabel('SFDR [dB]'); ylabel('Number of DACs') figure(3) hist(ENOB,50); xlabel('ENOB [Number of bits]') ylabel('Number of DACs') end
68
Appendix C
This is the SKILL code used to generate the binary-to-thermometer decoder schematic. procedure(bin2term(nbr) ;_Oct 9 03 chrli 87 cvSch = geGetWindowCellView(window(44)) ;schematic window number INV = geGetWindowCellView(window(27)) ;inverter window number NAND = geGetWindowCellView(window(28)) ;NAND window number NOR = geGetWindowCellView(window(29)) ;NOR window number NA = 0.375 ;These values are the location of the NB = 0.125 ;symbols’ pins NYx = 1.25 NYy = 0.25 IYx = 0.75 IYy = 0.1875 IA = 0.1875 nbr = nbr – 1 ;nbr from above is the number of binary inputs x = 0 old_x = 0 wireID = 0 for( i 1 nbr nbrElements = expt(2 i) - 1 if( (mod(i 2) > 0) ;Checks if it is an odd then ;or even stage for( k 1 nbrElements dbCreateInst(cvSch NOR nil list(x (1-k)) "R0" 1) ) dbCreateInst(cvSch INV nil list(x -nbrElements) "R0" 1) for( k 1 nbrElements dbCreateInst(cvSch NAND nil list(x (-nbrElements - k)) "R0" 1) ) else for( k 1 nbrElements dbCreateInst(cvSch NAND nil list(x (1-k)) "R0" 1) ) dbCreateInst(cvSch INV nil list(x -nbrElements) "R0" 1) dbCreateInst(cvSch INV nil list(old_x -nbrElements) "R0" 1) for( k 1 nbrElements dbCreateInst(cvSch NOR nil list(x (-nbrElements - k)) "R0" 1) ) ) ; ** if mod ** if( (i > 1 ) ;Check where to connect wires then ;And them connecting them for oldNbr = expt(2 i) – 1 ;the entire stage for( k 0 (oldNbr - 1 ) x1 = old_x + NYx x2 = x y1 = -k + NYy y2 = -k + NA
69
if( (k == (expt(2 (i - 1)) - 1)) then x1 = x1 - (NYx - IYx) y1 = y1 - (NYy - IYy) ) ; ** if k ** schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) ) ; ** for k ** nbrE = expt(2 (i + 1)) - 1 for( k 0 (nbrE - 1) x1 = x x2 = x - 0.25 y1 = -k + NB y2 = y1 if( (k == oldNbr) then y1 = -k + IA y2 = y1 ) ; ** if k ** schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) ) ; ** for k ** x1 = x - 0.25 x2 = x1 y1 = NB y2 = (-nbrE + 1) + NB schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) for( k 0 (nbrElements - 1) x1 = old_x + NYx x2 = x y1 = -k + NYy y2 = -(nbrElements + 1) + NA - k if( (k == ((nbrElements - 1) / 2)) then x1 = old_x + IYx y1 = -k + IYy ) ; ** if k ** schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) ) ; ** for k ** x1 = x x2 = -2 y1 = -((nbrE - 1) / 2) + IA y2 = y1 id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) id = car(id) sprintf(data_in "data_in<%d>" i) xL = x2 yL = y1 + 0.0625
70
schCreateWireLabel(cvSch id (xL:yL) data_in "lowerLeft" "R0" "fixed" 0.1 nil) ) ; ** if i ** if( (i == nbr ) then nbrE = expt(2 (i + 1)) - 1 x2 = x + NYx + 1 for( k 0 (nbrE - 1) x1 = x + NYx y1 = -k + NYy y2 = y1 if( (k == ((nbrE - 1) / 2)) then x1 = x + IYx y1 = -k + IYy y2 = y1 ) ; ** if k ** id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) id = car(id) sprintf(data_out "data_out<%d>" k) xL = x2 - 0.75 yL = y1 + 0.0625 schCreateWireLabel(cvSch id (xL:yL) data_out "lowerLeft" "R0" "fixed" 0.1 nil) ) ; ** for k ** ) ; ** if i ** if( (i == 1) then x1 = 0 x2 = -0.25 for( k 0 2 y1 = -k + NB y2 = y1 if( (k == 1) then y1 = -k + IA y2 = y1 ) ; ** if k ** schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) ) ; ** for k ** x1 = x2 y1 = NB y2 = NB - 2 schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) x1 = 0 x2 = -2 y1 = NA y2 = y1
71
id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) id = car(id) xL = x2 yL = y1 + 0.125 schCreateWireLabel(cvSch id (xL:yL) "data_in<0>" "lowerLeft" "R0" "fixed" 0.1 nil) y1 = IA - 1 y2 = y1 yL = y1 + 0.125 id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) id = car(id) schCreateWireLabel(cvSch id (xL:yL) "data_in<1>" "lowerLeft" "R0" "fixed" 0.1 nil) x1 = -0.5 x2 = 0 y1 = NA y2 = NA - 2 schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) ) ; ** if i ** old_x = x x = expt(i 3) + 4 ) ; ** for i ** msb = expt(2 (nbr + 1)) - 2 x = old_x x1 = x + 5 x2 = x1 + 2 y1 = -(msb / 2) + IA y2 = y1 id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0625) id = car(id) sprintf(data_out "data_out<%d:0>" msb) xL = x1 yL = y1 + 0.125 ;The next rows puts bus-labels ;on the right place schCreateWireLabel(cvSch id (xL:yL) data_out "lowerLeft" "R0" "fixed" 0.15 nil) x1 = -4 x2 = x1 - 2 id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0625) id = car(id) msb = nbr sprintf(data_in "data_in<%d:0>" msb) xL = x2 yL = y1 + 0.125 schCreateWireLabel(cvSch id (xL:yL) data_in "lowerLeft" "R0" "fixed" 0.15 nil) ) ; ** procedure bin2term **
72
Linköping Studies in Science and TechnologyThesis No. 976
STUDIES ON PERFORMANCELIMITATIONS IN CMOS DACS
K Ola Andersson
LiU-Tek-Lic-2002:49
Department of Electrical EngineeringLinköpings universitet, SE-581 83 Linköping, Sweden
Department of Electrical EngineeringLinköpings universitetSE-581 83 Linköping
Sweden
ISBN 91-7373-452-7 ISSN 0280-7971
Printed in Sweden by UniTryck, Linköping, 2002
i
AbstractThe digital-to-analog converter (DAC) is a bottle neck in broadband communica-tion systems. High update rates are required in combination with high accuracy.In this work, we study factors that limit the performance of current-steeringDACs, focusing on the linearity properties of DACs for telecommunication appli-cations like digital subscriber lines (DSL).
There are many different sources of nonlinear behavior in current-steering DACs.Static errors dominate the low-frequency behavior, whereas the high-frequencybehavior is dominated by dynamic errors. The static errors are mainly caused bymismatch between components and finite output resistance in the current sources.The dynamic nonlinearity caused by parasitic capacitance in transistors and wiresis of special interest in this work. Two closely related types of models of thisdynamic nonlinearity were developed.
The linearity requirements on the converters for high-speed telecommunicationapplications can be hard to meet using a straightforward approach. Various meth-ods for improving the linearity of DACs are studied in this work. Some of themethods, like dynamic element matching (DEM) and a novel differential DACarchitecture, rely on redundant coding to improve the linearity. Two methods uti-lizing models of the dynamic nonlinearity caused by the parasitic capacitance inthe current sources were also developed. One of the methods utilizes a feedbacksimilar to delta-sigma modulation to spectrally shape the distortion. The othermethod is a type of predistortion where the input is modified in order to yield animproved output that is closer to the desired output, compared with using theoriginal input.
CMOS technology is popular for implementation of integrated circuits. Twomain advantages of CMOS, compared with, e.g., bipolar technology, is low costand the possibility of designing circuits with relatively low power consumption.
ii
CMOS is also the preferred technology for implementing large systems on a sin-gle chip with both analog and digital blocks. Three different current-steeringCMOS DACs were developed in this work, and are presented in the thesis. Mea-surement results show close resemblance with the simulation results obtainedfrom the developed models.
iii
AcknowledgmentsMany people deserve my gratitude for helping me during the years. First of all Ithank my supervisor, Prof. Mark Vesterbacka, for his guidance.
Dr. J Jacob Wikner, has taught me a lot about data conversion, mixed signaldesign, IT tools, and other things that have simplified my work. All help fromhim, M.Sc. Niklas U Andersson, and Dr. Mikael Karlsson Rudberg, all from Infi-neon Technologies Wireless Solutions Sweden (former Ericsson Microelectron-ics), is greatly appreciated.
I also thank Dr. Gunnar Björklund and M.Sc. Magnus Hägglund for supportingmy work during the years I spent doing research at Ericsson Microelectronics.
I appreciate the help and inspiration from all my colleagues at Ericsson Micro-electronics and Electronics Systems, Linköping University.
Finally, I thank my family, especially my wife Helena, for their support.
The work was financially supported by the Microelectronics Research Center(MERC) at Ericsson Microelectronics and the Center for Industrial InformationTechnology (CENIIT) at Linköping University.
3.4.1 State-space model of a current-steering DAC . . . . . . . . . 35Modeling of nonideal DAC components 35Circuit-level model of the DAC 38Simulations 42
3.4.2 A low-complexity model . . . . . . . . . . . . . . . . . . . . . . . . . 44A simple DAC model 45Model structure 46Simulation of the low-complexity model 48
1 IntroductionStrict requirements are imposed on the transmitting and receiving circuits forbroadband communication. A bottle neck in these communication systems is thedata converters, i.e., digital-to-analog converters (DACs) and analog-to-digitalconverters (ADCs). In this work we study performance limitations in DACs forhigh-speed applications. This chapter is an overview of the work and an introduc-tion to the thesis. In Sec. 1.1 we give a brief introduction to the analog front end(AFE) in which the DAC is an important building block. The different parts ofthe thesis are outlined in Sec. 1.2. The author’s scientific contribution to the areais outlined in Sec. 1.3, and the publications related to this thesis are listed inSec. 1.4. This chapter ends in Sec. 1.5 with a list of abbreviations used through-out the thesis.
1.1 The analog front end
Among the technologies that have emerged in recent years for broadband tele-communication are the different digital subscriber line (DSL) technologies. Asimplified view of a typical AFE used in digital subscriber line (DSL) applica-tions is shown in Fig. 1.1. There are a number of blocks with different functions.The multi-tone input signal to the DAC is constructed with an inverse fast Fouriertransform (IFFT) circuit, which is one of the digital signal processing (DSP)blocks. The DAC converts this signal to an analog signal which is the input to thefollowing analog transmitting circuits, consisting of lowpass (LP) filters and aline driver. The line driver is an amplifier with good driving capability used tofeed the signal into a twisted-pair copper wire. In the receive path there is areceive amplifier, whose output is connected via an LP filter to an ADC convert-
Introduction
2
ing the analog data to digital. The digital data is processed by a fast Fourier trans-form (FFT) circuit to determine the correct points in the different constellations,as will be discussed in Sec. 2.1.1.
1.2 Outline of the thesis
Below follows a brief outline of the different parts of the thesis.
Chapter 2 is an introduction to DACs in general and to their application in tele-communication. The requirements imposed on the DACs are presented and moti-vated. The performance measures that will be used throughout the thesis arepresented, as well as some terminology.
Chapter 3 deals with behavioral-level modeling of errors occurring when fabri-cating current-steering DACs in complementary metal oxide semiconductor(CMOS) technology. The errors that are studied are, e.g., caused by componentmismatch and parasitic components.
In Chapter 4 we use the models developed in Chapter 3 to develop and analyzemethods aiming for improving the linearity of DACs. The methods include cali-bration and biasing techniques, as well as predistortion and techniques based onredundant coding.
Three different current-steering CMOS DACs were developed in this work. Theimplementations are presented in Chapter 5 together with measurement resultsand discussions on the implementation of various building blocks. The work isconcluded in Chapter 6.
Figure 1.1 AFE for DSL applications.
DSP blocks
DAC
ADC
LP
LP
A
A
channel
line driver
receive amplifier
AFE
Scientific contribution of the author
3
1.3 Scientific contribution of the author
The text on DACs in telecommunication applications in Chapter 2 is intended asa background and introduction to the topic. The modeling of nonideal compo-nents discussed in Chapter 3 is a compilation of known models and modelsdeveloped by the author. The modeling of the influence of graded matchingerrors presented in Sec. 3.3.1 is original work of the author, along with all of thework presented in Sec. 3.4 regarding dynamic errors.
The discussions on error correction and compensation in Chapter 4 is also a com-pilation of known methods and methods developed by the author. The calibrationscheme presented in Sec. 4.1.1 is original work of the author. The remaining partof Sec. 4.1 discusses distributed biasing and dynamic element matching, whichare priorly known methods that have been implemented in two of the DACs pre-sented in Chapter 5. The techniques for reducing the impact of dynamic errorspresented in Sec. 4.2 were developed by the author.
The implementations of DACs presented in Chapter 5 were all designed in coop-eration with Niklas U Andersson and Dr. J Jacob Wikner. The DAC presented inSec. 5.5 was designed mainly by the author, the DAC in Sec. 5.6 mainly byNiklas U Andersson, and for the DAC in Sec. 5.7 the work was evenly distributedbetween the author and Niklas U Andersson. Dr. J Jacob Wikner has supervisedthe design work and provided some sub circuits and scripts useful for designautomation.
1.4 Publications related to the author
Publications, patents, and a tutorial, authored or coauthored by the author, relatedto the work presented in this thesis are listed below in chronological order foreach category.
1.4.1 Conference publications[1] K.O. Andersson and J.J. Wikner, “Modeling of the influence of graded
element matching errors in CMOS current-steering DACs,” Proc.NORCHIP Conference, pp. 399-404, Oslo, Norway, Nov. 8-9, 1999.
[2] K.O. Andersson and J.J. Wikner, “Characterization of a CMOS current-steering DAC using state-space models,” Proc. 43rd Midwest Symposiumon Circuits and Systems (MWSCAS’00), pp. 668-671, Lansing, MI, USA,Aug. 8-11, 2000.
Introduction
4
[3] K.O. Andersson, N.U. Andersson, and J.J. Wikner, “Spectral shaping ofDAC nonlinearity errors through modulation of expected errors,” Proc.IEEE International Symposium on Circuits and Systems (ISCAS’01),vol. 3, pp. 417-420, Sydney, Australia, May 6-9, 2001.
[4] N.U. Andersson, K.O. Andersson, J.J. Wikner, and M. Vesterbacka,“Models and implementation of a dynamic element matching DAC,” Proc.NORCHIP Conference, pp. 155-160, Kista, Sweden, Nov. 12-13, 2001.
[5] K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner, “Adifferential DAC architecture with variable common-mode level,” Proc.IEEE International Symposium on Circuits and Systems (ISCAS’02),vol. 1, pp. 113-116,Scottsdale, AZ, USA, May 26-29, 2002.
[6] K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner,“Combining DACs for improved performance,” Proc. 4th IEEInternational Conference on Advanced A/D and D/A ConversionTechniques and their Applications, Prague, Czech Republic, June 26-28,2002.
[7] M. Vesterbacka, K.O. Andersson, N.U. Andersson, and J.J. Wikner,“Using different weights in DACs,” Proc. 4th IEE InternationalConference on Advanced A/D and D/A Conversion Techniques and theirApplications, Prague, Czech Republic, June 26-28, 2002.
1.4.2 Journal publication[8] N.U. Andersson, K.O. Andersson, J.J. Wikner, and M. Vesterbacka,
“Models and implementation of a dynamic element matching DAC,” toappear in Kluwer International Journal of Analog Integrated Circuits andSignal Processing, Special Issue: Selected Papers from the NORCHIP2001 Conference.
1.4.3 Patents[9] K.O. Andersson, “Improved current-steering D/A conversion,” Swedish
patent 0000731-0, 2000.
[10] K.O. Andersson, “Current Steering DAC”, pending Swedish patent, 2001.
[11] K.O. Andersson and J.J. Wikner, “Digital-to-analog converter having errorcorrection,” pending Swedish patent, 2002.
Abbreviations
5
1.4.4 Tutorial[12] J.J. Wikner, N.U. Andersson, K.O. Andersson, and M. Vesterbacka,
Compilation of error prevention and correction techniques for DACs,Tutorial IEEE 7th Int. Conf. on Electronics, Circuits, and System(ICECS’01), Malta, Sep. 2, 2001.
1.5 Abbreviations
Below is a list of the abbreviations used in the thesis.
ADC Analog-to-digital converter
ADSL Asymmetric digital subscriber line
AFE Analog front-end
CMOS Complementary metal oxide semiconductor
CO Central office
CPE Customer premises equipment
DAC Digital-to-analog converter
DCVS Differential cascode voltage switch
DEM Dynamic element matching
DMT Discrete multi-tone
DNL Differential nonlinearity
DSL Digital subscriber line
DSP Digital signal processing
ECH Echo canceled hybrid
ENOB Effective number of bits
FDM Frequency division multiplexing
FFT Fast Fourier transform
FIR Finite impulse response
FRDEM Full randomization dynamic element matching
GPIB General purpose interface bus
IFFT Inverse fast Fourier transform
INL Integral nonlinearity
LP Lowpass
Introduction
6
LSB Least significant bit
LTI Linear, time invariant
LVDS Low voltage differential signalling
MSB Most significant bit
MTPR Multi-tone power ratio
OSR Oversampling ratio
PC Personal computer
PCB Printed circuit board
POTS Plain old telephone service
PRDEM Partial randomization dynamic element matching
PSD Power spectral density
QAM Quadrature amplitude modulation
RF Radio frequency
SFDR Spurious-free dynamic range
SNDR Signal-to-noise-and-distortion ratio
SNR Signal-to-noise ratio
THD Total harmonic distortion
VDSL Very high speed digital subscriber line
WLAN Wireless local area network
7
2 DACs inTelecommunication
The main emphasis in this thesis is on the linearity of current-steering DACs. Thework is focused on converters for telecommunication applications, and this chap-ter is an introduction to DACs in general, and their application to telecommunica-tion. We start by outlining the set of signals the DACs are intended for, andillustrate the importance of high linearity in the intended applications. As appli-cation examples we use digital subscriber line (DSL) environments. The idealDAC is presented on a behavioral level, along with some important performancemeasures used to describe the degree of deviation from the ideal DAC.
2.1 The DSL Environment
Among the technologies that have emerged in recent years for broadband tele-communication are the different DSL technologies, e.g., asymmetric DSL(ADSL) and very high speed DSL (VDSL) [1, 2, 3, 4]. Common to these tech-nologies is their use of existing twisted-pair copper wires, originally intended forthe plain old telephone service (POTS), as a medium for transmission. One rea-son for this is that because the wires already exist, the cost for establishing theinfrastructure is considerably lower compared with, e.g., communication overoptical fibers where new lines have to be routed.
A typical DSL system is outlined in Fig. 2.1. The terminal on the user side, orcustomer premises equipment (CPE) side, is connected to the central office (CO)side with twisted-pair copper wires. The backbone network of the telecommuni-cation operator connecting the different CO stations is typically a high-speedoptical fiber link. DSL cannot be made available in every existing POTS node,
DACs in Telecommunication
8
since the attenuation of signals in copper wires is rather high for the frequencybands used. The maximum physical distance between the CPE and the CO sidefor ADSL is approximately 5.5 km. Over this limit the possible data rate is dra-matically reduced. This is due to the common use of so called loading coils onsuch long lines to improve the voice band properties of the line. As a side effectthese loading coils increase the attenuation for frequencies above the voice band[1].
In Fig. 2.2 we show the frequency bands used in ADSL, which is a standard thathas been well established and is widespread today. The range of frequenciesbelow 4 kHz is reserved for POTS. The frequency range between 30 and 138 kHzis used for upstream communication, i.e., data sent from the CPE side to the COside. Data is sent in the reverse direction, downstream, in the frequency rangebetween 138 kHz and 1.104 MHz. A guard band is present between the POTSband and the ADSL downstream band. The information in ADSL is transmittedusing a discrete multi-tone (DMT) signal. The ADSL version described here isknown as frequency division multiplexing (FDM) ADSL [1, 2, 3, 4], where theupstream and downstream bands are separated. There is also a version calledecho-canceled hybrid (ECH) ADSL, where the upstream and downstream bandsoverlap. ECH ADSL requires echo cancellation to separate transmitted data fromreceived data [1, 2, 3, 4].
The downstream capacity (up to 9 Mb/s) is larger than the upstream capacity (upto 1 Mb/s) since the desired rate for downloading data in some applications, e.g.,video-on-demand, is larger than the corresponding uploading rate [4], hence theterm asymmetric. In VDSL on the other hand, the communication is symmetric,i.e., the same data rate is available in both directions.
Figure 2.1 Overview of DSL system.
CPE
CPE
CPE
CO CO
CPE
CPE
Backbone
The DSL Environment
9
The maximum signal bandwidth in ADSL is about 1 MHz. In other types of tele-communication and data communication, e.g., VDSL and wireless local area net-work (WLAN), the corresponding bandwidths lie around 10 MHz, and in futurecommunication standards the bandwidths may be even higher.
2.1.1 Signals and modulation in ADSL
As mentioned earlier, ADSL uses a DMT signal for data transmission. For exam-ple, in the downstream band the data is sent on 224 carriers between 138 kHz and1.104 MHz. Generally, a DMT signal, , can be expressed (in the time-domain) as
. (2.1)
It should be noted that, with the notation used in (2.1), some of the tones musthave zero amplitude in ADSL, since their frequencies are in the POTS band orthe guard band (or in the wrong ADSL band for FDM ADSL).
To each carrier there is an associated quadrature amplitude modulation (QAM)constellation [3] given by the values of and . The bits that are to be transmit-ted are divided into different constellations. The number of bits modulated on
Figure 2.2 Frequency bands used in FDM ADSL.
0 4 30 138 1104Frequency [kHz]
Frequency bands in FDM ADSL
PO
TS
guar
d ba
nd
AD
SL
upst
ream
AD
SL
dow
nstr
eam
Y t( )
Y t( ) ai i ω0 t⋅ ⋅( )sin bi i ω0 t⋅ ⋅( )cos+i 1=
K
∑= =
r i i ω0 t⋅ ⋅ φi+( )sini 1=
K
∑=
ai bi
DACs in Telecommunication
10
each carrier is not fixed, but is determined during training sequences and dependson the quality of the transmission link for the corresponding frequency band. InFig. 2.3(a) a 16-QAM constellation is shown, and the point of the constellation tobe transmitted determines the actual values of and .
Distorted signals
When the signal is sent from the transmitter to the receiver it will be distorted.Sources of signal distortion are, e.g., attenuation in the twisted-pair wire and non-linearities in the transmitting circuits. Here we examine the impact on the QAMconstellation for different types of distortion using simulations in Matlab. Thesimulations are performed using discrete time signals. Seven tones with angularfrequencies for have been used, and to each ofthese tones there is a 16-QAM constellation as illustrated in Fig. 2.3(a). As anexample we investigate how the constellation for the tone with is affectedby distortion. For the remaining tones we choose random values of andwith rectangular distribution, and for each such random combination we considerall possible combinations of and . The constellations plotted in Fig. 2.3 arethe results of 100 stochastic outcomes.
First we examine how the constellations are affected by a linear distortion. Lineardistortion affects each carrier by a signal independent phase shift and a signalindependent attenuation (or possibly amplification). Hence, the constellation ofthe linearly distorted carrier is a rotated and scaled copy of the original constella-tion, as illustrated in Fig. 2.3(b). The linear distorter is a simple finite impulseresponse (FIR) filter given by . Since there is aone-to-one mapping from the original constellation to the distorted constellation,the original constellation can be restored once the attenuation and the phase shiftis known.
The constellations for signals that are distorted by a simple nonlinearity,, are shown in Fig. 2.3(c). It can be seen that there is no
longer a one-to-one mapping between the original constellation and the distortedconstellation. The location of the received point is depending on the amplitudesand phases of the other tones as well. When the nonlinearity becomes moresevere, the clouds of points start to overlap and errors occur in determining theoriginal location of the transmitted point.
With these simple examples we have illustrated the importance of high linearityin all parts of the transmission link. Noise added to the signal will have similareffects on the constellations as a nonlinearity, so there are also requirements onthe noise margins.
ai bi
Ωn n π 8⁄⋅= n 1 2 … 7, , ,=
n 3=ai bi
a3 b3
y n( ) 0.5 x n( )⋅ 0.1 x n 1–( )⋅+=
y n( ) x n( ) 0.2 x3 n( )⋅+=
The DSL Environment
11
2.1.2 DAC requirements
Since the copper wires used in DSL were initially intended for POTS, which is anarrowband communication technology, strict requirements are imposed on thetransmitting and receiving circuits in order to achieve broadband communicationover these lines. General requirements on a DAC for DSL applications, which wewill use as a guideline throughout this thesis, can be found in Table 2.1.
Table 2.1 General DAC requirements for DSL and similar applications.
−1.5 −0.5 0.5 1.5
−1.5
−0.5
0.5
1.5
Original constellation
a
b
−1.5 −0.5 0.5 1.5
−1.5
−0.5
0.5
1.5
Linearly distorted constellation
a
b
−1.5 −0.5 0.5 1.5
−1.5
−0.5
0.5
1.5
Nonlinearly distorted constellation
a
b
DACs in Telecommunication
12
A comment on the requirements is that 12-bit DACs are commonly used in FDMADSL, whereas ECH ADSL often requires 14 bits of accuracy [1]. For someemerging communication standards the bandwidths are much higher than inTable 2.1 [5].
2.2 The ideal DAC
In this section we introduce the ideal DAC and the notation for digital signalsused throughout the thesis.
2.2.1 Representation of digital signals
The input to the DAC is a digital signal, that we denote . The parameterdenotes the sample (or update) instant. We will use the notation for both thevector form representation
(2.2)
and for the integer value
, (2.3)
since they easily can be distinguished by the context. The binary valued signalsare the individual bits of the digital word , and is the weight asso-
ciated with bit . The weights depend on what coding scheme is used. For exam-ple, in the binary-coded case we have that , whereas for all inthe thermometer-coded case. These two types of codes are common in data con-version, and are more thoroughly described in Sec. 5.3.1. We use the notationfor the inverse of , and denotes with all individual bits inverted.
Throughout this thesis we represent the weights, , as positive numbers. Thatis, we treat digital numbers and signals as positive. In the DSP blocks, digital sig-nals are generally expressed as signed numbers, using, e.g., two’s complementrepresentation [6]. However, all designs of DACs in this thesis operate by sum-ming positive analog weights, so from a DAC designer’s point of view it is moreconvenient to use positive weights also in the digital domain.
X n( ) nX n( )
X n( ) bN 1– n( ) bN 2– n( ) … b0 n( ), , ,[ ]=
X n( ) bk n( ) wk⋅k 0=
N 1–
∑=
bk n( ) X n( ) wkk
wk 2k= wk 1= k
bb X X
wk
The ideal DAC
13
2.2.2 Digital-to-analog conversion
The purpose of a DAC is to perform a mapping of the digital input to an analog.The analog signal can be represented by, e.g., an electrical current or voltage. Ifan analog signal, , that has a limited frequency bandwidth, , is uniformlysampled with a sample frequency to a discrete-time signal, , itcan be perfectly reconstructed by the function
, (2.4)
where for , , and is thereconstructed signal. The ideal DAC could be defined as a device performing themapping from the digital signal, , to the analog signal, , given by
, (2.5)
where is the gain of the DAC, is the update period, and .For practical reasons, e.g., the noncausal properties of the function, weinstead define the ideal DAC according to
, (2.6)
where is a unit square pulse with duration , i.e.,
. (2.7)
In other words, , is a piecewise constant signal with
for . (2.8)
When designing a DAC, the goal is to come as close as possible to the operationdescribed in (2.6) and (2.8). It is, however, not possible to achieve exactly theoperation of an ideal DAC, since given by (2.6) is discontinuous (unless
is constant). The sinc pulse and the unit square pulse are plotted together inFig. 2.4.
A t( ) f 0f s 2 f 0⋅> D n( )
A t( ) D n( ) sinc f s t nT–( )⋅( )⋅n ∞–=
∞
∑=
sinc x( ) sin π x⋅( ) π x⋅( )⁄= x ∞– ∞,[ ]∈ T 1 f s⁄= A t( )
X n( ) A t( )
A t( ) K X n( ) sinc f u t nT–( )⋅( )⋅n ∞–=
∞
∑⋅=
K T f u f s 1 T⁄= =sinc
A t( ) K X n( ) P t nT–( )⋅n ∞–=
∞
∑⋅=
P t( ) T
P t( )1 for 0 t T<≤0 otherwise
=
A t( )
A t( ) K X n( )⋅ K bi n( ) wi⋅i 0=
N 1–
∑⋅= = nT t≤ n 1+( )T<
A t( )X n( )
DACs in Telecommunication
14
In the applications considered here, there is no information in the DC level of thesignal. In the general case, we add a constant to the right hand sides of (2.6) and(2.8).
2.2.3 Nyquist rate DACs vs. oversampled DACs
Assume that we want to output a signal with bandwidth Hz. By the samplingtheorem, the minimum required update frequency is [7]
(2.9)
as touched upon in the previous section. A DAC using this update frequency isreferred to as a Nyquist rate DAC.
In an ideal data converter, the only errors are those caused by the quantizationprocess, referred to as quantization noise. It is sometimes argued that there is noquantization noise in a DAC, since the input signal is already quantized [8]. How-ever, since the input is already quantized it contains quantization noise. We cantherefore talk about quantization noise in the output signal from a DAC, even ifthe quantization is a process in the circuits preceding the DAC.
For an -bit DAC with relatively large and with a varying input signal, thequantization noise, , can often be adequately described as a white noise sig-nal with rectangular distribution between 0 and 1 (assuming that the size of thequantization step is unity). The total power of the quantization noise is then [7, 9]
Figure 2.4 The sinc pulse (dashed) and the unit square pulse (solid) plotted together.
−5 −4 −3 −2 −1 0 1 2 3 4 5
0
1
Normalized time, t/T
Am
plitu
de le
vel
sinc(t/T) and P(t/T) plotted together
f 0
f u 2 f 0⋅=
N Nq n( )
The ideal DAC
15
. (2.10)
This power is evenly distributed over frequencies in the interval (sincethe noise is treated as white). If we use an update frequency larger than therequired , some of the noise will appear outside of the signal band, at fre-quencies in the interval . This part of the noise can be filtered out,since the signal does not have any spectral content for these frequencies, and theoverall signal-to-noise-and-distortion ratio (SNDR) (see Sec. 2.3.2) is improved.
A DAC with is known as an oversampled DAC, and the oversamplingratio (OSR) is defined as
. (2.11)
Compared with a Nyquist rate DAC, the signal-to-noise ratio (SNR) due to quan-tization noise is increased with dB [8]. To further decrease thepower of the quantization noise within the signal band, delta-sigma modulationtechniques are often used. These techniques utilize feedback loops to spectrallyshape the quantization noise to frequencies outside of the signal band, and arebriefly outlined in Sec. 4.2.2.
Another reason for using oversampling is that using square pulses instead of sincpulses for reconstruction affects the spectral properties of the output signal. Let
denote the power spectrum of the signal reconstructed with sinc pulses,and let denote the corresponding spectrum for the signal reconstructedusing square pulses. Then, the following equality holds [7, 8]
, (2.12)
i.e., the signal is attenuated for frequencies close to . For the Nyquist fre-quency, , this attenuation is . For a Nyquistrate DAC this attenuation may need to be compensated for with so called anti-sinc filters, depending on the requirements of the application. For oversampledDACs there is no spectral content of the signal close to the Nyquist frequency, ifhigh enough OSR is used. Therefore, the attenuation becomes neglectable.
Moreover, the images of the signal appearing around multiples of the update fre-quency need to be filtered out with image rejection filters before the signal entersthe communication channel to minimize the interference with other types ofcommunication utilizing other frequency bands. In an oversampled DAC the
images are better separated from the signal, compared with Nyquist rate DACs,and the requirements on the transition band widths of the image rejection filtersare reduced.
2.3 DAC performance measures
Some performance measures are needed to describe the quality of a DAC. In thissection we define the performance measures that are commonly used for charac-terizing communication DACs [10, 11], used throughout this thesis.
2.3.1 Performance measures in the code domain
The static transfer characteristics, , of a nonideal 4-bit DAC is shown inFig. 2.5. We also plot the line , i.e., the transfer character-istics for the corresponding ideal DAC, for comparison. and are chosento yield a best-fit straight line (least mean square) with respect to the data pointsfor the nonideal DAC. If the DAC would be linear, all data points would be on thestraight line. In the following we define two common linearity measures in thecode domain.
Differential nonlinearity, DNL
The differential nonlinearity (DNL) for a code , , describes the devia-tion from an ideal step in the transition from to [9]. is definedas
Figure 2.5 Static transfer characteristics of a nonideal 4-bit DAC.
A X( )Y X( ) K X⋅ Y offset+=
K Y offset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0123456789
101112131415
Input code
Out
put l
evel
Static transfer characteristics for a nonideal DAC
X DNL X( )X 1– X DNL X( )
DAC performance measures
17
(2.13)
The DNL for the DAC with the transfer characteristics in Fig. 2.5 is plotted inFig. 2.6.
Integral nonlinearity, INL
The integral nonlinearity (INL) describes the deviation from the line [10],i.e.,
. (2.14)
Combining (2.13) and (2.14) yields that
. (2.15)
Hence, DNL is a redundant measure (if the INL is known). The INL for the DACwith the transfer characteristics in Fig. 2.5 is plotted in Fig. 2.7.
2.3.2 Measures in the frequency domain
For communication DACs we are often more interested in the frequency domainbehavior than in the corresponding code-domain behavior [10]. In Fig. 2.8 weshow a typical power spectral density (PSD) plot of an output signal for a DACwith a single-tone (sinusoidal) input signal. Nonlinearities in the DAC cause har-
monic distortion in the output signal. The second and third harmonics are indi-cated in Fig. 2.8. Hence, the different measures of distortion presented in thissection is also measures of the DAC linearity.
The signal impurities can be divided into noise and distortion. Noise is typicallysignal independent, due to, e.g., thermal activity in circuit elements, having asmooth spectral appearance. Distortion, on the other hand, is generally character-
Figure 2.7 INL of a nonideal 4-bit DAC.
Figure 2.8 PSD plot of the output signal from a nonideal DAC with a single-tone input sig-nal.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
−2
−1
0
1
2
Input code
INL
INL for a nonideal DAC
SFDR
PSD for distorted single−tone signal
Frequency
PS
D
fundamental
2:nd harmonic
3:rd harmonic
DAC performance measures
19
ized by clearly visible peaks in the output spectrum and is often signal dependent,e.g., due to circuit nonlinearities. Gray zones are present in the analysis, e.g.,quantization errors are clearly signal dependent, but are often treated as sourcesof noise. The total output power is
, (2.16)
where is the power of the wanted output signal, is the noise power,and is the total power due to distortion.
Signal-to-noise ratio, SNR
As a measure of how well the signal can be distinguished from the noise, we havethe signal-to-noise ratio (SNR)
. (2.17)
Signal-to-noise-and-distortion ratio, SNDR
The signal-to-noise-and-distortion ratio (SNDR, in some literature abbreviatedSINAD) is
. (2.18)
This is a more adequate measure of signal quality than SNR if a large amount ofdistortion is present. The SNDR due to quantization noise of the ideal -bit(Nyquist rate) DAC with a full-scale sinusoidal input signal can be expressed as[7, 8]
dB. (2.19)
Effective number of bits, ENOB
For a nonideal DAC we rearrange (2.19) to define the effective number of bits(ENOB) as
, (2.20)
which is only a different way of expressing the SNDR. It is a useful measure to,e.g., find a lower bound on the number of bits, , to achieve a given SNDR.
Pout Psignal Pnoise Pdist+ +=
Psignal PnoisePdist
SNRPsignal
Pnoise---------------=
SNDRPsignal
Pnoise Pdist+-------------------------------=
N
SNDR 6.02N 1.76+≈
ENOB SNDR 1.76–6.02
--------------------------------=
N
DACs in Telecommunication
20
Spurious-free dynamic range, SFDR
The spurious-free dynamic range (SFDR) is defined as
, (2.21)
where is the power of the largest spurious (unwanted) tone. SFDR is indi-cated in Fig. 2.8. It should be mentioned that this definition of SFDR, which isoften used for data converters, is different from the one most often used foramplifiers, in which case SFDR is defined as the SNR for the maximum outputpower without having any spurious tones [8].
Total harmonic distortion, THD
The second and third harmonic tone is indicated in Fig. 2.8. If the power of the:th harmonic tone is denoted , the total harmonic distortion (THD) is
, (2.22)
i.e., THD is the power of all harmonics, normalized with respect to the signalpower.
Multi-tone power ratio, MTPR
Nonlinear systems, as opposed to linear systems, cannot be completely describedby single-tone properties [12]. In multi-carrier applications, e.g., ADSL, themulti-tone properties of the transmitting system are more adequate for describingthe performance. One multi-tone linearity measure often used is the multi-tonepower ratio. A number of tones with equal amplitude and frequency spacing areapplied to the input. One tone is left out, and the multi-tone power ratio (MTPR)is defined as the ratio between the rms amplitude of a carrier and the peak spuri-ous tone in the region of the left out tone [10], as indicated in Fig. 2.9. MTPR is ameasure on how much the other tones affect the amplitude of a specific tone,compare, e.g., with the nonlinearly distorted constellation discussed in Sec. 2.1.1.
SFDRPsignal
Pls---------------=
Pls
n Pn
THD
Pn
n 2=
∞
∑Psignal----------------=
DAC performance measures
21
Figure 2.9 PSD plot of a multi-tone signal with one tone left out.
MTPR
PSD for distorted multi−tone signal
Frequency
PS
D
DACs in Telecommunication
22
23
3 Modeling of Current-Steering DACs
In this chapter we discuss modeling of current-steering DACs. Both static errors,such as component mismatch, and dynamic errors, e.g., due to parasitic capaci-tance are discussed. The study is focused on the dynamic errors.
Modeling of nonlinear behavior in analog circuits is often made using polyno-mial models, such as Taylor or Volterra series expansions [12, 13]. Some initialattempts of characterizing DACs using Volterra models were made in this work.These were, however, unsuccessful in capturing the nonlinear behavior of thecurrent-steering DAC, except for in very limited frequency bands. Hence, thepolynomial type models have been discarded in this work.
3.1 Classification of systems
Consider an arbitrary system (i.e., mapping from an input signal to an output sig-nal) with input and output . Some useful definitions for classificationof such a system are presented here.
• Suppose that we have two arbitrary input signals and , yieldingthe output signals and , respectively. Then the system is calledlinear if the input signal yields the output signal
, where and are arbitrary constants. Otherwise,the system is nonlinear.
X n( ) Y n( )
X1 n( ) X2 n( )Y 1 n( ) Y 2 n( )
X n( ) aX1 n( ) bX2 n( )+=Y n( ) aY 1 n( ) bY 2 n( )+= a b
Modeling of Current-Steering DACs
24
• Consider the special case for the signals above when ,where is an arbitrary integer. The system is time-invariant if
, otherwise the system is time-variant.
• The system is called causal if the value of the output signal, , at instant only is a function of the input signal for
(i.e., future values of have no influence on the output).
• The system is called static if the value of the output signal, , at instantonly is a function of the input signal for . Otherwise, the sys-
tem is called dynamic.
Some comments can be made regarding the application of the definitions toDACs. When implementing the DAC it is desired to come as close as possible (insome sense) to a linear, time-invariant (LTI) system. However, the linearity prop-erty is, as for most other physical systems, limited by the fact that the DAC has alimited input (and output) range determined by the number of bits in the inputsignal. Thus, the constants and in the definition of linearity cannot be arbi-trary, since overflow in the input signal causes a large amount of nonlinear distor-tion. Moreover, the time-invariance property does not hold because of aging ofthe chips and temperature variations. We do, however, regard the DAC as a time-invariant system over a limited range of time. In ADSL each DMT signal has aduration of less than 1 ms, and we consider the DAC to be a time-invariant sys-tem for this short period of time.
3.2 The ideal current-steering DAC
The ideal current-steering DAC is composed of a number of ideal currentsources, , and a number of ideal switches, , as shown inFigure 3.1. To each current source, , we associate a weight, , such that
, (3.1)
where is called the unit current. The DAC shown in Fig. 3.1 utilizes a differ-ential architecture. The switches are controlled by the digital input such that thecurrent from source is directed to the analog output terminal when the dig-ital input bit , otherwise the current is directed to terminal . The totalpositive output current is
. (3.2)
X2 n( ) X1 n k–( )=k
Y 2 n( ) Y 1 n k–( )=
Y n1( )n1 X n( ) n n1 n1 1– n1 2– …, , ,=
X n( )
Y n1( )n1 X n( ) n n1=
a b
I0 … IM 1–, , S0 … SM 1–, ,I i wi
I i wi Iunit⋅=
Iunit
I i A+bi 1= A–
I+ bi I i⋅i 0=
M 1–
∑ Iunit bi wi⋅i 0=
M 1–
∑⋅ Iunit X⋅= = =
The ideal current-steering DAC
25
Similarly for the negative output current
. (3.3)
If we let the weights, , be the same as for the digital bits, , and compareexpression (3.2) with expression (2.8) in Chapter 2, we find that the output cur-rent can be regarded as the output from an ideal DAC. Similarly, the outputcurrent can be regarded as the output from an ideal DAC with input
.
Differential architectures are often used to reject noise and distortion [8]. The dif-ferential output current, , is defined as
, (3.4)
where is the value of when all bits . From (3.4) we see that thedifferential output current can be regarded as the output from an ideal DAC. Wealso refer to the outputs in terms of voltages, i.e.,
, (3.5)
, (3.6)
and
Figure 3.1 The ideal current-steering DAC.
I0 Ij IN1
b0 bj bN1
RLRL
II+A+ A
I– Iunit bi wi⋅i 0=
M 1–
∑⋅ Iunit X⋅= =
wi bi
I+I–
X bN 1– … b0, ,[ ]=
Idiff
Idiff I+ I–– 2 Iunit bi wi⋅∑⋅ ⋅ Iunit wi
i 0=
M 1–
∑⋅–= = =
2 Iunit X⋅ ⋅ Iunit Xmax⋅–( )=
Xmax X bi 1=
V + RL I+⋅ RL Iunit X⋅ ⋅= =
V – RL I–⋅ RL Iunit X⋅ ⋅= =
Modeling of Current-Steering DACs
26
, (3.7)
where is the load resistance.
We have now shown that the desired operation of an ideal DAC can be achievedby directing the currents from ideal current sources using ideal switches con-trolled by the digital input. When implementing current-steering DACs in, e.g.,CMOS technology, building blocks like the current sources and switches are non-ideal. In the rest of this chapter, behavioral-level modeling is used to discuss theimpact of nonideal components on the performance characteristics of the current-steering DAC.
3.3 Modeling of static errors
Static errors are defined as errors that are only depending on the present inputcode. This definition is similar to the definition of a static system given inSec. 3.1. In this section we discuss two different sources of static errors; compo-nent mismatch and finite output resistance of current sources.
3.3.1 Component mismatch
Assuming a long channel device and neglecting channel length modulation, thedrain current in an NMOS transistor in the saturation region can be approximatedby
. (3.8)
The parameter is the charge carrier (electron) mobility which is dependent on,e.g., doping concentration and temperature [14]. is the oxide capacitance perunit area, and depends on, e.g., the oxide thickness. and are the width andthe length of the transistor channel, is the gate-source voltage, and is thethreshold voltage, which is dependent on, e.g., the bulk-source voltage of thetransistor. A closer description of MOS transistors is given in Sec. 5.1.
If these transistors are to be used as current sources in a current-steering DAC itis important that the transistors are well matched to obtain the correct bit weights(within tolerable margins). Hence, it is desirable to manufacture transistors withthe same value of the parameters , , , etc. However, when manufacturingchips, variations in these parameters over the chip area occur, something we referto as component mismatch.
V diff V + V –– RL Idiff⋅ 2 Iunit RL X⋅ ⋅ ⋅ Iunit RL Xmax⋅ ⋅–= = =
RL
ID
µ Cox⋅2
---------------- WL----- V gs V T–( )2⋅ ⋅=
µCox
W LV gs V T
µ Cox V T
Modeling of static errors
27
On a higher level of abstraction mismatch leads to deviations from the desiredoutput currents in the current sources implemented with MOS transistors. Thecurrent from current source can be expressed as
, (3.9)
where the first term, , is the desired current, and the second term, , isthe deviation due to mismatch. This is equivalent to the model shown in Fig. 3.2,where an error current source, , is connected in parallel with the desired cur-rent source, .
For good matching it is important to have equivalent geometrical boundary con-ditions for the devices to be matched [8]. For this purpose it is a common designstrategy to divide the components, e.g., transistors and capacitors, into unit ele-ments which are connected in parallel. Following this strategy, a current sourcewith weight is constructed connecting unit current sources in parallel. Welet be a set of unit current sources. To each unit current source, ,there is a corresponding matching error, . Further we let be a set of indi-ces such that the current
, (3.10)
i.e., the current source is a parallel connection of the unit current sources with indices belonging to the set . We can rewrite (3.10) yielding
. (3.11)
The last term in (3.11) is identified as the matching error of , i.e.,
. (3.12)
If we consider two MOS transistors, and , on the same die, biased withthe same voltages and having (nominally) the same geometry, and compare thecorresponding drain currents and it has been shown that [15]
Figure 3.2 Model of current source with matching error.
I i
I i wi Iunit⋅ ∆i+=
wi Iunit⋅ ∆i
∆iwi Iunit⋅
Ii wi Iunit Di
wk wkIunit j, Iunit j,
δ j J i wi
I i Iunit j,j J i∈∑=
I iIunit j, j J i
I i Iunit j,j J i∈∑ wi Iunit⋅ δ j
j J i∈∑+= =
I i
∆i δ jj J i∈∑=
M1 M2
I1 I2
Modeling of Current-Steering DACs
28
, (3.13)
where is the distance between the centers of the transistors, and and areprocess dependent constants. We see that for good matching properties (i.e.,small variance) we should use transistors with large area ( ) and keep themas close as possible (small ). Different yield estimation methods based on(3.13) have been proposed in the literature [16, 17]. The use of a current-steeringDAC for efficient estimation of the parameters in (3.13) was presented in [18].
Another useful guideline for good matching properties, which is not captured in(3.13), is to avoid covering the transistors with metal, since metal coverageincreases the variance [19].
Influence of graded element matching errors
In this section we analyze the influence of the second term in (3.13), which isoften referred to as graded matching errors. This analysis was originally pre-sented in [20].
On a larger scale, graded matching errors are caused by parameters with circulardistribution over the wafer [15], i.e., the value of a parameter is roughly deter-mined by the distance from the center of the wafer. As a first order approximationover a small area (e.g., a chip), we can make a Taylor expansion of the parameterwith respect to the geometrical coordinates, which is illustrated in Fig. 3.3.
The current from a current source can thus be approximately expressed as
, (3.14)
Figure 3.3 Illustration of a parameter (e.g., oxide thickness) with circular distribution overthe wafer. Over a small area (e.g., a chip) the parameter value can be approxi-mated with the first order Taylor expansion.
Var I1 I2–( )AI
2
W L⋅------------- SI
2 D2⋅+=
D AI SI
W L⋅D
Iunit j, Iunit kx x⋅ ky y⋅+ +=
Modeling of static errors
29
where and are constants and and are the geometrical coordinates of thecurrent source with respect to a cartesian coordinate system. The matching error
is given by
. (3.15)
When implementing current-steering DACs, the unit current sources are oftenplaced in an array, as indicated in Fig. 3.4(a), where each square represents a unitcurrent source. A straightforward assignment of unit current sources to the differ-ent current sources of a 6-bit binary weighted DAC is shown in Fig. 3.4(b),where the upper half of the array is dedicated to the most significant bit (MSB),the upper half of the remaining part of the array to MSB-1, etc., until the remain-ing bits can be placed in the last row of the array.
The way of assigning unit current sources indicated in Fig. 3.4(b) is known tohave poor properties in terms of suppressing graded matching errors. Differentlayout techniques for suppressing the influence of graded matching errors havebeen proposed in the literature [21, 22, 23]. However, we use this approach toshow how matching errors can affect the DAC performance. First of all, we gen-eralize the concept illustrated in Fig. 3.4(b) for an -bit binary weighted DACwith the least significant bits (LSBs) contained within the bottom row. Forcomparison, the DAC in Fig. 3.4(b) has and . The array will thenhave elements in the -direction and elements in the -direction.
Computing the values of the different yields
(a) (b)
Figure 3.4 (a) Array of unit current sources and (b) unit current source assignment for a 6-bit binary weighted DAC.
kx ky x y
δ j
δ j x y,( ) kx x⋅ ky y⋅+=
I i
x
y
5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4
3 3 3 3 3 3 3 3
2 2 2 2 1 1 0
x
y(b)
NM
N 6= M 3=2M x 2N M– y
∆i
Modeling of Current-Steering DACs
30
, (3.16)
where and are the coordinates of unit current source , and andare the average coordinates for the unit current sources assigned to bit . We nor-malize the coordinate axis such that the distance between adjacent unit currentsources are unity in both the - and the -direction, and we also normalize thecurrents so that . We have that
for , (3.17)
for , (3.18)
for , (3.19)
and
for . (3.20)
The parameter only affects the errors for the LSBs. These errors are typi-cally much less than the errors for the more significant bits (assuming that isnot very large compared with ) due to the factor in (3.16). With this as anargument we set to simplify the calculations. This results in
for (3.21)
and
for . (3.22)
We define the error signal, , as
∆i δ jj J i∈∑ kx x j⋅ ky y j⋅+
j J i∈∑= = =
wi kx
x j
wi-----
j J i∈∑⋅ ky
y j
wi-----
j J i∈∑⋅+
⋅ wi kx xi⋅ ky yi⋅+( )⋅==
x j y j Iunit j, xi yii
x yIunit 1=
xi 2M 1– 32--- 2i⋅+= i 0 … M 1–, ,=
xi 0= i M … N 1–, ,=
yi 2N M– 1–– 2 1–+= i 0 … M 1–, ,=
yi 2N M– 1––32--- 2i M–⋅+= i M … N 1–, ,=
kx Mkx
ky wikx 0=
∆i wi ky 2 1– 2N M– 1––( )⋅ ⋅= =
ky 2i 1– 2i N M– 1–+–( )⋅( )= i 0 … M 1–, ,=
∆i wi ky32--- 2i M–⋅ 2N M– 1––
⋅ ⋅= =
ky32--- 22 i⋅ M–⋅ 2i N M– 1–+–
⋅= i M … N 1–, ,=
e n( )
Modeling of static errors
31
, (3.23)
i.e., the actual output signal minus the wanted output signal. Clearly,
, (3.24)
where . The power of this error signal, , can be expressed as
. (3.25)
If we assume that the probability that and are equal, i.e.,
(3.26)
we obtain
, (3.27)
which yields
. (3.28)
The covariance terms in (3.25) are signal dependent, since
(3.29)
and can therefore not be expressed explicitly for an arbitrary signal. We shall inthe following assume that the covariance sum in (3.25) is zero (or small), whichis true if, e.g., the bits are mutually uncorrelated. With this assumption,becomes
. (3.30)
Combining (3.21), (3.22), (3.28), and (3.30) yields
e n( ) bi n( ) I i⋅i 0=
N 1–
∑ bi n( ) wi Iunit⋅ ⋅i 0=
N 1–
∑–=
e n( ) bi n( ) ∆i⋅i 0=
N 1–
∑ ei n( )i 0=
N 1–
∑= =
ei n( ) bi n( ) ∆i⋅= Pe
Pe Var e n( )( ) Var ei n( )( )i 0=
N 1–
∑ Cov ei n( ) e j n( ),( )i j≠∑+= =
bi n( ) 1= bi n( ) 0=
P bi n( ) 1=( ) P bi n( ) 0=( ) 12---= =
Var bi n( )( ) E bi2 n( )( ) E2 bi n( )( )– 1
2---
12---
2– 1
4---= = =
Var ei n( )( ) Var ∆i bi n( )⋅( ) ∆i2 Var bi n( )( )⋅
∆i2
4------= = =
Cov ei n( ) e j n( ),( ) ∆i ∆ j Cov bi b j,( )⋅ ⋅=
Pe
Pe Var ei n( )( )i 0=
N 1–
∑=
Modeling of Current-Steering DACs
32
, (3.31)
where is a number calculated according to
.(3.32)
If we assume that the term is dominating (which is true for rea-sonable values of and , e.g., and ), we can approximatewith
. (3.33)
For a full-scale sinusoid, with , the signal power is given by
(3.34)
and the power of the quantization noise is [7, 9]
. (3.35)
Assuming that the quantization noise is uncorrelated with yields the follow-ing expression for the SNDR
. (3.36)
For larger (3.36) can be approximated with
. (3.37)
In [20] there is an analysis of SFDR due to graded matching errors utilizing aFourier series expansion of an approximated error signal to estimate the power ofthe spurious tones. The resulting expression was given as
. (3.38)
To check the validity of (3.37) and (3.38) we have performed some simulations inMatlab. A 14-bit DAC architecture has been used in the simulation and hasbeen chosen to 7. A full-scale sinusoidal input was used, and matching errors
were added to the bit weights according to (3.21) and (3.22). Simulated signalspectra for and are plotted in Fig. 3.16(a) and (b), respec-tively. In Fig. 3.16(c) we show simulated and calculated (using (3.36)) values ofSNDR vs. . The corresponding plots for SFDR, with the calculated valuesgiven by (3.1), are shown in Fig. 3.5(d). In this example we conclude that simu-lated and calculated values agree well, e.g., the simulated and calculated SNDRhas a maximum deviation of less than 2.5 dB even if rough approximations aremade. In [20] there was an extended analysis taking into account the correlationbetween the input bits and , reducing the maximum deviationbetween the curves to approximately 0.1 dB.
(a) (b)
(c) (d)
Figure 3.5 Simulated signal spectra of 14-bit DAC with for (a) and (b). The plots in (c) and (d) show simulated (dashed) and calculated
(solid) values of SNDR and SFDR vs. .
ky 10 4–= ky 10 3–=
ky
bN 1– bN 2–
0 0.1 0.2 0.3 0.4 0.5−120
−100
−80
−60
−40
−20
0
Normalized frequency
PS
D [d
B]
Output signal spectrum, ky=10−5
0 0.1 0.2 0.3 0.4 0.5−120
−100
−80
−60
−40
−20
0
Normalized frequency
PS
D [d
B]
Output signal spectrum, ky=10−4
10−7
10−6
10−5
10−4
10−3
10−2
10
20
30
40
50
60
70
80
90
ky
SN
DR
[dB
]
SNDR vs. ky
simulatedcalculated
10−7
10−6
10−5
10−4
10−3
10−2
10
20
30
40
50
60
70
80
90
100
110
120
ky
SF
DR
[dB
]
SFDR vs. ky
simulatedcalculated
M 7= ky 10 4–=ky 10 3–=
ky
Modeling of Current-Steering DACs
34
Modeling of random matching errors
Special layout techniques are often used to reduce or eliminate the influence ofgraded element matching errors, e.g., distributed biasing discussed in Sec. 4.1.2.However, if this is done, random parameter variations, which can be modeled asspatial white noise [15] and correspond to the first term in (3.13) still remain.Unit current sources with random matching errors are often modeled as
, (3.39)
where is an observation of a stochastic variable with zero mean and Gaus-sian distribution [15, 24]
, (3.40)
where the different are mutually uncorrelated. This way of modeling match-ing errors will be used in Chapter 4 to analyze some methods for error compensa-tion.
3.3.2 Finite output resistance
The ideal current source has infinite output resistance, i.e., the output current isindependent on the voltage across the current source. When implementing cur-rent sources in, e.g., MOS or bipolar technologies, the output resistance is finite.We now examine what influence the finite output resistance will have on thetransfer characteristics of the DAC. The results presented here have previouslybeen presented by Wikner in [25], and are not original parts of this work. It isincluded here because it provides a good starting point for the modeling of finiteoutput impedance, including capacitive parts, in Sec. 3.4.
Assume that we have unit current sources with finite output resistance, . Forinput code there are unit current sources connected in parallel to the outputnode. The equivalent circuit model for the DAC is shown in Fig. 3.6.
Figure 3.6 Equivalent model of current-steering DAC with current sources having finiteoutput resistance.
Iunit j, Iunit δ j+=
δ j ∆ j
∆ j N 0 σ,( )∈
∆ j
RunitX X
IunitX
RL
Runit/X
Vout(X)
VDD
Modeling of dynamic errors
35
The output voltage of the circuit in Fig. 3.6 is
, (3.41)
which clearly is a nonlinear function of . Thus, the finite output resistance inthe current sources introduces nonlinear behavior, and we can conclude that isimportant to have high output resistance compared with the load resistance to gethigh linearity. Equation (3.41) can be used to find design criteria for the outputresistance of the current sources [26].
3.4 Modeling of dynamic errors
Modeling of different sources of dynamic errors is discussed in this section. Theerror focused on in this work is the error caused by the nonzero output capaci-tance of current sources. Nonlinear behavior due to parasitic capacitance is aknown phenomenon [27]. The work presented in this section contributes withtwo different behavioral-level models that have been developed by the author,one of which is closer to a circuit-level model.
3.4.1 State-space model of a current-steering DAC
The finite output resistance of the current sources was mentioned as a limitationof the DAC performance in Sec. 3.3.2. In this section we present a model of theDAC which also includes parasitic capacitance in the current sources and thewires. The system of differential equations describing the DAC during an updateperiod is expressed on a state-space form. A numerical computation program,e.g., Matlab, can then be used to calculate the final values of the different volt-ages in the circuit, i.e., the values of the voltages at the end of the update period.The model presented in this section was first introduced in [28].
Modeling of nonideal DAC components
The ideal current source shown in Fig. 3.7(a) has infinite output impedance. Asingle transistor and a single cascode version of a PMOS current source areshown in Fig. 3.7(b) and (c), respectively. The cascode transistor increases theoutput resistance (see Sec. 5.2.1), but the source still has finite output impedance,as indicated in the linearized model of a current source in Fig. 3.7(d).
Results from simulations of the output impedance of a single transistor currentsource and a single cascode current source [7] are shown in Fig. 3.8. The simula-tion used PMOS transistor parameters for a CMOS process.
V out X( ) Iunit
V DD
Runit-----------+
X
1RL
Runit----------- X⋅+
-----------------------------⋅ RL⋅=
X
0.35 µm
Modeling of Current-Steering DACs
36
for the source transistor and the corresponding ratiofor the cascode transistor is . The current is .We can see that the output resistance (i.e., output impedance at low frequencies)of the cascode current source is higher than for the single transistor currentsource. For higher frequencies the capacitive part of the output impedancebecomes dominating, and for the frequencies where the output impedance forboth types of current sources is essentially capacitive, they both have the sameoutput impedance. This is true provided that all transistors are equally wide,since the output capacitance is more or less the parallel connection of an overlapcapacitance and a junction capacitance, which are both depending on the transis-tor widths [14]. For the cascode current source it is the parasitic capacitance inthe cascode transistor that dominate. More information on the implementation ofcurrent sources is given in Chapter 5.
Use of differential signal paths is an efficient way of rejecting noise and distor-tion, e.g., substrate noise or channel charge injection, provided that the two pathsare symmetrically designed [8]. Therefore, differential current switches are com-monly used and they are implemented with two or more MOS transistors in par-allel, as shown in Fig. 3.9(a). In this work the switch is represented by the MOS
(a) (b)
(c) (d)
Figure 3.7 (a) Ideal current source, (b) single transistor PMOS implementation of a currentsource, (c) single cascode PMOS implementation of a current source, and (d)linearized model of the nonideal current source.
switch-on resistance, as shown in Fig. 3.9(b), assuming that the switch transistoroperates in the linear region. This is a simplification, because the voltage over theswitch is varying with the output voltage of the DAC, and for some configura-tions the switch transistor may even enter the saturated region. Thus, the linear-ized model of the switch is a coarse approximation. However, it is good enoughto illustrate the effect of finite output impedance in the current sources. There isalso parasitic capacitance in the switch, but it is lumped into the parasitics of thecurrent source and output wire.
Figure 3.8 Output impedance vs. frequency for (a) a single transistor current source, and(b) a single cascode current source.
(a) (b)
Figure 3.9 (a) Example of a differential PMOS switch and (b) linearized model of the dif-ferential switch.
102
103
104
105
106
107
108
106
107
108
109
1010
|Zout
(f)| for single transistor (solid) and single cascode (dashed)
Frequency [Hz]
Out
put i
mpe
danc
e [Ω
]
Iin
Iout+ Iout–
Q–Q+
Iin
Iout+ Iout–
Rswitch
Modeling of Current-Steering DACs
38
The output wires of the DAC should have zero impedance to reduce the internalvoltage drop. In reality, the wires contain resistive as well as capacitive andinductive parts [29]. For high accuracy, a transmission line model or an RC-lad-der network should be used as a model for the wire. However, we want to achieveshort simulation times, so a small number of circuit nodes is desired. Therefore,we trade accuracy for a lower degree of complexity in the model. As an approxi-mation we use a resistor and capacitor in parallel, i.e., a simple RC-ladder, asshown in Fig. 3.10. The impedance includes the internal wire impedance as wellas the off-chip load.
Circuit-level model of the DAC
The model of the complete current steering DAC is found by replacing the com-ponents of the ideal DAC in Fig. 3.1 with their nonideal counterparts presented inthe previous section. This yields the schematic in Fig. 3.11.
To simplify further analysis, we first examine the current-voltage relationship forthe model of the current source in Fig. 3.7(d). We have
(3.42)
where
. (3.43)
Figure 3.10 Model of the output wire load.
Iout t( ) IV DD V out t( )–( )
Rout------------------------------------- Cout t∂
∂V out t( )⋅–+= =
IV out t( )
Rout----------------– Cout t∂
∂V out t( )⋅–=
I IV DD
Rout----------+=
Modeling of dynamic errors
39
Hence, the linearized model of a unit current source is equivalent to the circuit inFig. 3.12, where the current is replaced with the slightly larger currentand the output impedance connected to ground instead of . This is the modelwe will use from now on to eliminate terms including from the calculations.
Assume that we during an update period have a value of the digital input, , suchthat of the current sources are connected to one of the analog outputs. For sim-ple notation we let these current sources, , have indices . Thecircuit schematic for this specific configuration shown in Fig. 3.13.
The following relations between voltages and currents hold for this circuit
Figure 3.11 Circuit schematic of the model of the nonideal differential current-steeringDAC.
Figure 3.12 Equivalent circuit of current source.
I0 R0 C0
Rs0
Ij Rj Cj
Rsj
IN1RN1
CN1
RSN1
VDD
Iunit Iunit
V DDV DD
Iunit
output impedance
XK
I j j 1 2 … K, , ,=
Modeling of Current-Steering DACs
40
for , (3.44)
for , (3.45)
, (3.46)
and
. (3.47)
Combining (3.44) and (3.45) yields
. (3.48)
In a similar way, combining (3.45), (3.46), and (3.47) yields
. (3.49)
Figure 3.13 Circuit schematic of one output during an update period for a certain value ofthe input .
I1
R1 C1Rs1
Iout1
V1
IK
RK CKRsK
IoutK
VK
I
R C
V
X
Ioutj t( ) I j
V j t( )
R j-----------– C j t∂
∂V i t( )⋅–= j 1 2 … K, , ,=
Ioutj t( )V j t( ) V t( )–
Rsj---------------------------= j 1 2 … K, , ,=
I t( ) V t( )R
---------=
I t( ) Ioutj t( )j 1=
K
∑ Ct∂
∂V t( )⋅–=
t∂∂
V i t( )1
C j------ I j V j t( ) 1
R j----- 1
Rsj-------+
⋅– V t( )1
Rsj-------⋅+⋅=
t∂∂
V t( )1C----
V j t( )
Rsj-----------
j 1=
K
∑ V t( ) 1R--- 1
Rsj-------
j 1=
K
∑+
⋅–⋅=
Modeling of dynamic errors
41
We let denote the update period of the DAC. We are interested in finding thevalues of the different nodal voltages at the end of the update period. For this pur-pose we define the voltage vector
. (3.50)
For simplicity we let the update period start at time . We further define thestate vector
, (3.51)
where contains the initial voltages, i.e., the voltages just before the switch-ing occurs. The state vector should not be confused with the input . Using(3.48)-(3.51) we can now express the system of differential equations for theDAC as
, (3.52)
where
(3.53)
and
T
V t( ) V 1 t( ) V 2 t( ) … V K t( ) V t( ), , , ,[ ]T=
t 0=
X t( ) V t( ) V 0–( )–=
V 0–( )X X
t∂∂ V t( )
t∂∂ X t( ) A X t( )⋅ B u t( )⋅+= =
A
1R1------ 1
Rs1--------+
1C1------ 0 … 0
1Rs1-------- 1
C1------
0 1R2------ 1
Rs2--------+
1C2------ … 0
1Rs2-------- 1
C2------
… … … … …
0 0 … 1RK------- 1
RsK--------+
1CK------- 1
RsK-------- 1
CK-------
1Rs1-------- 1
C---- 1
Rs2-------- 1
C---- … 1
RsK-------- 1
C---- 1
R--- 1
Rsj-------
j 1=
K
∑+ 1
C----–
=
Modeling of Current-Steering DACs
42
. (3.54)
is a unit step used to apply the initial conditions given in at time . Asimple manipulation of (3.51) yields
. (3.55)
Equations (3.52)-(3.55) form a state-space representation of a linear system withinput and output [30, 31]. Hence, the nodal voltages in the DAC circuitare given as the step response of a linear system on a state-space form. This kindof system can easily be simulated with, e.g., Matlab or another numerical compu-tation tool.
The following algorithm is used for simulation of the model.
1. For a given value of the input, , find the appropriate matrix representingone of the output terminals.
2. Use the final voltages from the last update period as initial values to calculatethe vector . (Reasonable initial voltages are assigned for the first updateperiod.)
3. Calculate/simulate the final value of , e.g., with a numerical computationtool like Matlab.
4. Repeat steps 1 through 3 for the other output terminal.
In this way we calculate the final values of all the nodal voltages in the circuit,which reenter as initial values for one or the other output terminal in the nextupdate period. The outputs from the DAC, and , are given as the out-put node voltage at the end of each update period, i.e., . If current is pre-ferred as output, each output voltage is divided by the corresponding loadresistance.
Simulations
In this section we present simulation results to illustrate the effect of the nonidealcomponents introduced in the model. We consider a 14-bit binary weightedarchitecture. The parameters used in the simulations are given in Table 3.1.
Fig. 3.14(a) and (b) show simulated PSD plots for single-ended and differentialoutputs, respectively. The input is a full-scale, single-tone signal with signal fre-quency and update frequency .
Fig. 3.15 show the simulated PSD plots when the signal frequency is reduced to, i.e., one tenth of the signal frequency used in Fig. 3.14. Com-
paring the two figures we find that the harmonic distortion is largely reduced
B A V 0–( )⋅I1
C1------
I2
C2------ …
IK
CK------- 0, , , ,
T
+=
u t( ) B t 0=
Y t( ) V t( ) X t( ) V 0–( )+= =
u t( ) Y t( )
X A
B
V t( )
V + n( ) V – n( )V nT( )
f sig 1.104 MHz= f u 10 MHz=
f 110.4 kHz=
Modeling of dynamic errors
43
when the signal frequency is lowered. For the differential case the SFDR (deter-mined by the third harmonic) is increased from 70 to 87 dB. We can also see thatthe even order harmonics that appear in the single-ended spectra (the (b) figures)are efficiently cancelled in the differential case.
In Fig. 3.16 we show how SFDR varies with signal frequency for a half-scale sin-gle-tone signal with update frequency . This behavior is typicalfor current-steering DACs [10, 32, 33], compare, e.g., with the measurementresults presented in Chapter 5.
Parameter Value
Unit current
Output resistance, unit current source
Output capacitance, unit current source
Switch resistance,
,
Load resistance
Load capacitance
Table 3.1 Model parameter values used in the simulations.
(a) (b)
Figure 3.14 Simulated (a) single-ended and (b) differential outputs for a full-scale single-tone input with 10 MHz update frequency and 1.104 MHz signal frequency.
1.22 µA
1 GΩ
5 fF
100 Ω j 0 … 7, ,=
100 27 j– Ω⋅ j 8 … 13, ,=
70 Ω
200 pF
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
PSD for single−ended output signal
Frequency [Hz]
PS
D [d
B/H
z]
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
PSD for differential output signal
Frequency [Hz]
PS
D [d
B/H
z]
f s 10 MHz=
Modeling of Current-Steering DACs
44
3.4.2 A low-complexity model
In this section we present a model with much lower computational complexitythan the state-space model in the previous section. One use of a model with lowcomputational complexity is that it can be implemented on-chip, to a relativelylow hardware cost, and used for error estimation in error compensation tech-niques. Examples on such techniques are presented in Chapter 4.
(a) (b)
Figure 3.15 Simulated (a) single-ended and (b) differential outputs for a full-scale single-tone input with 10 MHz update frequency and 110.4 kHz signal frequency.
(a) (b)
Figure 3.16 Simulated SFDR as a function of signal frequency for (a) single-ended outputand (b) differential output. The update frequency is 10 MHz, and the signal is afull-scale single-tone signal.
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
PSD for single−ended output signal
Frequency [Hz]
PS
D [d
B/H
z]
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
PSD for differential output signal
Frequency [Hz]
PS
D [d
B/H
z]
105
106
55
60
65
70
SFDR vs fsig
, single−ended output
Frequency [Hz]
SF
DR
[dB
]
105
106
70
75
80
85
90
SFDR vs fsig
, differential output
Frequency [Hz]
SF
DR
[dB
]
Modeling of dynamic errors
45
A simple DAC model
The nonlinear behavior in the models presented in Sec. 3.3.2 and Sec. 3.4.1, iscaused by a signal dependent parasitic network connected to the internal nodes ofthe DAC. Consider the simplified case when this parasitic network is reduced to asingle signal dependent capacitor connected to the output node, as illustrated inFig. 3.17.
This is a single pole system with the output voltage, , given by
, (3.56)
where is the output current for the input code , nominally , andis the signal dependent parasitic load. In discrete time we are interested in thevalue of the output at multiples of the update period , i.e.,
, (3.57)
where has been chosen as . From (3.57) it can be seen that isdepending on , which in turn is dependent on , etc. Thus, thenonlinearity is dynamic and has infinite memory. We can however define a staticparameter describing the error, namely the relative step error
(3.58)
where is the settled output value for input code , for the sim-ple model in Fig. 3.17. Combining (3.57) and (3.58) yields
Figure 3.17 DAC model with signal dependent capacitive load.
R CX
IX
V(t)
V t( )
V t( ) V t0( ) I X R⋅ V t0( )–( ) 1 e
t t0–
RCX------------–
–
⋅+=
I X X Iunit X⋅ CX
T
Y n( ) V nT( ) Y n 1–( ) I X R⋅ Y n 1–( )–( ) 1 eT
RCX-----------–
–
+= =
t0 n 1–( )T Y n( )Y n 1–( ) Y n 2–( )
erel X( ) 1 Y n( ) Y n 1–( )–Y X Y n 1–( )–
------------------------------------–=
Y X X Y X I X R⋅=
Modeling of Current-Steering DACs
46
(3.59)
for the simple model in Fig. 3.17. This expression can be interpreted as that theDAC has a signal dependent settling time constant .
Model structure
Based on the simple model in the previous section, we propose a low-complexitymodel to be used for estimation of the output in a current-steering DAC with non-zero output capacitance in the current sources, as discussed in Sec. 3.4.1. We startby normalizing the output such that
, (3.60)
i.e., we let the static gain of the DAC be unity. We rewrite (3.57)-(3.59) yielding
, (3.61)
which is the first approach to the low-complexity model. A block diagram of acircuit that calculates (3.61) is shown in Fig. 3.18. The relative step error is storedin a lookup table. If can be well approximated with a piece wise constantfunction, the lookup table can be addressed by a few MSBs of (instead of allbits), and the size of the lookup table can be reduced.
The state-space model presented in Sec. 3.4.1 is used as a reference to investigateif the model given by (3.61) is reasonable. The model parameters given inTable 3.1 on page 43 is used in a simulation, and the input is a white noise signalwith rectangular distribution where all input codes are equally probable. Thelength of the signal is samples. In Fig. 3.19(a) we plot observations of
(3.62)
Figure 3.18 Proposed model.
erel X( ) eT
RCX-----------–
=
τX RCX=
Y X X=
Y n( ) Y n 1–( ) Y X n( ) Y n 1–( )–[ ] 1 erel X n( )( )–[ ]⋅+= =
Y n 1–( ) X n( ) Y n 1–( )–[ ] 1 erel X n( )( )–[ ]⋅+=
erel X( )X
lookuptable
z1
X(n) erel(n) Y(n)
216
erel X n( )( ) 1 Y n( ) Y n 1–( )–Y X n( ) Y n 1–( )–-------------------------------------–=
Modeling of dynamic errors
47
as a function of . In (3.62) we use instead of in the denominator,because the finite output resistance yields a nonlinear static transfer function ofthe model, and by (3.58), is a measure of the deviation from this static trans-fer curve. However, for estimation of errors at frequencies, where the dynamicerrors dominate, it is sufficient to assume that the static transfer characteristic islinear. A large spread in can be observed in Fig. 3.19(a). This is because it isnot only the value of the capacitive load that determines the step error, but alsothe initial values of the voltages across the capacitances. These initial values areroughly determined by , so a natural modification of the model is toassume that is a function of and . In Fig. 3.19(b) we plot theobserved values of together with estimated values. The estimations havebeen made using 5 MSBs of and 3 MSBs of . The estimated valueshave been taken as the mean value of all observations having the same value ofthe 5 MSBs of and the 3 MSBs of . Each of the lines inFig. 3.19(b) represents a specific value of quantized to 3 bits. From theplot in Fig. 3.19(b) we conclude that it is reasonable that a better estimation of
is found if is used together with than if is used alone.
The modified approach is given by
. (3.63)
A block diagram of a circuit that calculates (3.63) is shown in Fig. 3.20. Againwe have set the static gain of the DAC to unity, replacing with in (3.63).The lookup table may be addressed by only a few MSBs of and tokeep the size of the lookup table small, as discussed above.
(a) (b)
Figure 3.19 The relative step error, , plotted as a function of the input code (a) with-out and (b) with the estimated values using the low-complexity model.
X n( ) Y X n( ) X n( )
erel
erel
X n 1–( )erel X n( ) X n 1–( )
erelX n( ) X n 1–( )
X n( ) X n 1–( )X n 1–( )
erel X n 1–( ) X n( ) X n( )
0 2000 4000 6000 8000 10000 12000 14000 16000−5
0
5
10x 10
−3 erel
vs X
Input code
Rel
ativ
e er
ror
0 2000 4000 6000 8000 10000 12000 14000 16000−5
0
5
10x 10
−3 erel
vs X
Input code
Rel
ativ
e er
ror
erel X
Y n( ) Y n 1–( ) Y X n( ) Y n 1–( )–[ ] 1 erel X n( ) X n 1–( ),( )–[ ]⋅+=
Y X XX n( ) X n 1–( )
Modeling of Current-Steering DACs
48
Simulation of the low-complexity model
Simulation plots from the model type in Fig. 3.20 are shown in Fig. 3.21. Theparameters in the lookup table have been extracted from the model presented inSec. 3.4.1 using the parameters given in Table 3.1 on page 43. 5 MSBs from
and 5 MSBs from have been used for estimation of . Thespectra in Fig. 3.21 correspond to the spectra in Fig. 3.14, and there is a goodagreement between the simulation results from the two different models. Animportant difference is that the simulation time is reduced to approximately atenth using the low-complexity model. Moreover, solving the state-space equa-tions is a complex task and is not suitable for simple on-chip estimation of errors,whereas the solutions in Fig. 3.18 and Fig. 3.20 require relatively little hardwareprovided that the lookup tables are reasonably small.
The agreement between simulation results from the state-space model and thelow-complexity model is further illustrated in Fig. 3.22. Simulated SFDR as afunction of the signal frequency for the differential output of the low-complexitymodel using a 10 MHz update frequency is shown Fig. 3.22(a). The correspond-ing plot for the state-space model is shown in Fig. 3.22(b), and a good agreementbetween the two plots can be observed.
3.5 Combined models
In previous sections of this chapter we have isolated a nonideal property of a cur-rent-steering DAC, and discussed the impact of that property on the performanceof the DAC. In reality, all these nonideal properties are present at the same time.To get more realistic simulation results, the models should be combined and sim-ulated together. Such combined modeling was used to simulate the behavior of acurrent-steering dynamic element matching (DEM) DAC [34, 35]. The resultsfrom this work is presented in Sec. 5.6.2. The comparisons between simulationsand measurements presented there provide a validation of the state-space modelin Sec. 3.4.1.
Figure 3.20 Block diagram for the modified approach.
lookuptable
z1
X(n)erel(n) Y(n)z1
X n( ) X n 1–( ) erel
Combined models
49
(a) (b)
Figure 3.21 (a) Single-ended and (b) differential outputs for a full-scale single-tone inputwith 10 MHz update frequency and 110.4 kHz signal frequency simulated withthe low-complexity model.
(a) (b)
Figure 3.22 Simulated SFDR as a function of signal frequency for differential output signalswith full-scale amplitude. The plot in (a) shows the results for the low-complex-ity model, whereas (b) shows the results for the state-space model for compari-son.
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
Single−ended PSD for low−complexity model
Frequency [Hz]
PS
D [d
B/H
z]
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
Differential PSD for low−complexity model
Frequency [Hz]
PS
D [d
B/H
z]
105
106
70
75
80
85
90
SFDR vs fsig
, differential output
Frequency [Hz]
SF
DR
[dB
]
105
106
70
75
80
85
90
SFDR vs fsig
, differential output
Frequency [Hz]
SF
DR
[dB
]
Modeling of Current-Steering DACs
50
51
4 Compensation andCorrection of Errors
It can be hard to meet a DAC design specification using a straightforward imple-mentation. In this chapter we present some ideas on how to compensate for theerrors, in order to improve the linearity of the circuits. So called predistortion is afamily of techniques widely used in telecommunication circuits, mostly RFpower amplifiers, to enhance the linearity and, thereby, improve the quality of thecommunication link. The idea is to use models of the nonlinearity and modify theinput signal in order to get the desired output signal. Other techniques, e.g.,dynamic element matching (DEM), rely on randomization in order to change thespectral properties of the nonlinearities from spurious tones to (white or shaped)noise.
The presentation of the different techniques given in this chapter has beendivided into two main groups, compensation and correction of static errors,which is presented in Sec. 4.1, and compensation and correction of dynamicerrors, which is presented in Sec. 4.2.
4.1 Compensation and correction of static errors
In this section we discuss compensation of static errors in DACs caused bymatching errors in the current sources. In Sec. 4.1.1 and Sec. 4.1.2 we discussmethods aiming for reduction of the matching errors between the different cur-rent sources using calibration and careful design styles. In the DEM methods pre-sented in Sec. 4.1.3, special randomization techniques make it possible to alterthe spectral properties of the errors in a favorable way.
Compensation and Correction of Errors
52
4.1.1 Calibration of the MSBs
One way of reducing the distortion caused by inadequate matching is to calibratethe current sources, in order to get output currents closer to the nominal currentsthan would be the case without calibration. A method for calibrating the mostsignificant current sources in a binary weighted DAC is proposed in this section.
Basic idea
The idea behind the proposed calibration method is to remove the DNL error inthe transition from to . This error isoften the dominating one in binary coded DACs due to the large amount ofswitches turning on and off. To achieve this, the MSB current, , is substi-tuted with a current
, (4.1)
with the intention of using the currents from the less significant bits and one addi-tional unit current source as reference for the calibration. The DNL and INL for a12-bit binary coded DAC with random matching errors having a standard devia-tion of 1% are shown in Fig. 4.1 and Fig. 4.2, respectively. Values without cali-bration are given in the (a) figures, whereas values with calibration are given inthe (b) figures. In Fig. 4.2(a) we can observe a problem with the binary weightedarchitecture in that its transfer characteristics is not always monotone. In thiscase,
. (4.2)
It is therefore common to use thermometer coded or segmented architecturesinstead, which is further discussed in Sec. 5.3.1.
PSD plots of full-scale single-tone signals without and with calibration are shownin Fig. 4.3(a) and (b), respectively. For this particular stochastic outcome, theSFDR is improved from 66 dB to 80 dB when calibration is applied. It can beconcluded that the proposed calibration method improves the static linearity ofthe binary weighted DAC for this particular case. The proposed method can eas-ily be extended to calibrating more bits than one [36], starting with the least sig-nificant of the bits to be calibrated, proceeding with the next bit until the mostsignificant bit has been calibrated.
X 0 1 1 … 1, , , ,[ ]= X 1 0 0 … 0, , , ,[ ]=
IN 1–
IN 1– Iunit I j
j 0=
N 2–
∑+=
IN 1– I j
j 0=
N 2–
∑<
Compensation and correction of static errors
53
(a) (b)
Figure 4.1 DNL for binary weighted DAC (a) without and (b) with calibration of the MSB.
(a) (b)
Figure 4.2 INL for binary weighted DAC (a) without and (b) with calibration of the MSB.
(a) (b)
Figure 4.3 PSD plot for full-scale single-tone signals (a) without and (b) with calibration ofthe MSBs.
0 500 1000 1500 2000 2500 3000 3500 4000−4
−3.5
−3
−2.5
−2
−1.5
−1
−0.5
0
0.5
1DNL curve, uncalibrated DAC
Input code
DN
L
0 500 1000 1500 2000 2500 3000 3500 4000−4
−3.5
−3
−2.5
−2
−1.5
−1
−0.5
0
0.5
1DNL curve, calibrated DAC
Input code
DN
L
0 500 1000 1500 2000 2500 3000 3500 4000−3
−2
−1
0
1
2
3INL curve, uncalibrated DAC
Input code
INL
0 500 1000 1500 2000 2500 3000 3500 4000−3
−2
−1
0
1
2
3INL curve, calibrated DAC
Input code
INL
0 0.1 0.2 0.3 0.4 0.5−120
−100
−80
−60
−40
−20
0
Output spectrum, uncalibrated DAC
Normalized frequency
PS
D [d
B]
0 0.1 0.2 0.3 0.4 0.5−120
−100
−80
−60
−40
−20
0
Output spectrum, uncalibrated DAC
Normalized frequency
PS
D [d
B]
Compensation and Correction of Errors
54
Proposed implementation
A proposed circuit for the calibration technique is shown in Fig. 4.4. The calibra-tion phase is shown in Fig. 4.4(a). A current mirror is utilized to construct the dif-ference , and a current memory is set to hold the current
. During the operation phase, shown in Fig. 4.4(b), the current memory isutilized to subtract the current from , yielding the total output cur-rent .
(a)
(b)
Figure 4.4 Proposed circuit solution for the calibration technique during (a) the calibrationphase and (b) the operation phase.
∆IN 1– IN 1– IN 1––=∆IN 1–
∆IN 1– IN 1–IN 1–
IN1 IN2 I0 Iunit
DIN1
current memorycurrentmirror
DIN1
IN1 IN2 I0
Compensation and correction of static errors
55
Qualitative comparison with other calibration techniques
In other calibration techniques [32], a capacitor is used to hold the proper gatepotential for the current source. Charge leakage in that capacitor causes adecrease in the output current over time, so periodical recalibration of the currentsources are required.
Charge leakage also causes the current in the current memory, used in the pro-posed technique, to decrease. However, if the current sources are carefullydesigned, so the matching errors are small, the current will also be small.Hence, even if charge leakage resets the current memory, yielding the total outputcurrent instead of , the performance of the DAC is not as severelydeteriorated as is the case when the complete output current is stored in a currentmemory. A similar idea is used in [37], where a static DC current source is set todeliver approximately 90% of the nominal current, and a current memory is usedfor fine tuning the remaining part.
4.1.2 Distributed biasing
The impact of graded element matching errors was discussed in Sec. 3.3.1. Onetechnique that can be used to reduce the effect of graded errors is distributed bias-ing [21, 38]. This design technique is used in the DAC presented in Sec. 5.7 toobtain good matching properties.
A multiple-output PMOS current mirror is shown in Fig. 4.5. If we neglect theinfluence of channel-length modulation (i.e., let the output transistors have infi-nite output resistance), we have that
(4.3)
provided that the output transistors are operating in the saturated region and thatthe transistors are perfectly matched. The transistors have the same length.denotes the width of the output transistors and is the width of the input tran-sistor. In the following we discuss how current mirrors can be utilized for biasingcurrent sources and how the matching properties are affected.
In Fig. 4.6(a) we show an example where the current-source array is made up ofthe output transistors of a single multiple-output current mirror. Graded parame-ter variations, discussed in Sec. 3.3.1, cause the output currents from the differentcurrent sources to vary over the array. The matching of output currents can beimproved by partitioning the array of current sources into smaller parts, lettingeach such part be an individual multiple-output current mirror, as indicated inFig. 4.6(b). This is because the bias voltage ( in Fig. 4.5) is set individually for
∆i
IN 1– IN 1–
Iout j,W out
W in----------- I in⋅=
W outW in
V b
Compensation and Correction of Errors
56
each current mirror. If the input transistors are located close to the output transis-tors, the bias voltage is set to give the proper output current for the values of tran-sistor parameters in the proximity of the input transistors, reducing the currentvariations over the array due to graded parameter mismatch, compared with theapproach in Fig. 4.6(a). The biasing strategy has no effect on the influence of ran-dom matching errors, so this problem remains.
4.1.3 Dynamic element matching
This section is an overview of dynamic element matching (DEM) techniques.The purpose is to provide a background to DEM, in order to simplify the under-standing of the description of the DEM DAC presented in Sec. 5.6, were mea-surement and simulation results can be found as well.
If the error in the output level, , is determined by the input code, , i.e.,, the same error will occur each time a certain input code, , is
applied. Hence, if the input signal is periodic (which is the case for, e.g., asinusoidal input signal), will also be periodic with the same fundamentalfrequency as the input signal. This results in harmonic distortion, unless the erroris a linear gain error, where is a constant. DEM techniquesutilize randomization to make sure that the input code do not cause the sameerror each time it is applied. Generally, one can say that ,where is a control signal. The control signal may, e.g., be random or a deter-ministic function of the input. In this way, the error signal is changed from yield-ing harmonic distortion to having more noise-like properties.
Some DEM algorithms transform distortion into white noise, whereas the noise-shaping DEM techniques moves a large amount of the noise out of the signalband. These two types of DEM are discussed in this section. There are also DEMtechniques that minimize the number of switching events [39, 40], and hence theglitches. These techniques will not be further discussed here. DEM is especially
Figure 4.5 Multiple output PMOS current mirror.
Iin Iout,1Iout,K
Vb
e Xe n( ) f X n( )( )= X
X n( )e n( )
e n( ) K X n( )⋅= KX
e n( ) f X n( ) r n( ),( )=r n( )
Compensation and correction of static errors
57
suitable in audio applications where the signal bandwidths are low (comparedwith, e.g., DSL applications) and a large amount of oversampling can beafforded.
Generalized DEM
A general DEM DAC is shown in Fig. 4.7. The input, , is converted into athermometer coded signal
. (4.4)
The bits of are scrambled yielding a third code
, (4.5)
such that
(a) (b)
Figure 4.6 Current-source arrays with (a) global and (b) distributed bias.
X3 n( ) uK n( ) uK 1– n( ) … u2 n( ) u1 n( ), , , ,[ ]=
Compensation and Correction of Errors
58
, (4.6)
and for each there is exactly one such that (4.6) holds. Which is mappedon what is determined for each update instant by the control signal .Each is an input to a one bit DAC with nominal gain and an associatedmatching error . The outputs from all one bit DACs are summed, yielding thetotal output
, (4.7)
where the first term in is the desired output, and the second term is the error dueto mismatch. Without scrambling, the error becomes
(4.8)
and harmonic distortion occurs because the resulting error is periodic. This is nottrue in DEM DACs, provided that the control signal is properly chosen. Thescrambling ensures that different errors occurs for the same input code at differ-ent update instants, a property which is used to transform harmonic distortioninto noise. The overall SNDR is improved if oversampling is used, because theout-of-band noise can be filtered out.
A straightforward implementation of the digital circuits required in DEM mayresult in high hardware complexity. There is a large amount of research on DEMcircuit techniques with reduced hardware complexity presented in the literature[41, 42]. Some of these techniques are overviewed in the following sections. Forcomparisons of different networks used for DEM realizations, see, e.g., [43, 44].
DEM utilizing switching trees
One approach to implement DEM uses a tree of switches according to Fig. 4.8.The input to the tree, denoted in Fig. 4.8, is binary coded, so the tree per-forms both the binary-to-thermometer encoding and the scrambling. Each switchlayer, , is controlled by a pseudo random control signal, . Aswitch has one -bit input and two ( )-bit outputs, which we denoteand , that are inputs to the switches in the following layer. If , thenthe bits of the ( )-bit output are given the values of the LSBs of
ui n( ) t j n( )=
j i t j n( )u j n( ) n r n( )
ui n( ) w∆i
Y n( ) w ∆i+( ) ui n( )⋅i 1=
K
∑ w ui n( )i 1=
K
∑⋅ ∆i ui n( )⋅i 1=
K
∑+= = =
w X1 n( )⋅ ∆i ui n( )⋅i 1=
K
∑+=
∆i ti n( )⋅i 1=
K
∑
r n( )
X n( )
i r i n( ) 0 1, ∈M M 1– out1
out2 r i 1=M 1– out1 M 1–
Compensation and correction of static errors
59
the input, whereas the value of the MSB of the input is assigned to all individualbits of . When the MSB of the input is instead mapped on the bits of
, and the LSBs of the input are mapped on . The number of out-put bits for each switch is linearly decreasing with decreasing layer index, andthe tree is terminated with the switching layer having 1-bit outputs. These 1-bitsignals constitute a scrambled, thermometer coded word that is used to control 1-bit DACs, whose outputs are summed yielding the total output for the DEMDAC.
An additional bit with the same weight as the LSB, and fixed value ‘0’, is addedto the binary weighted input to give the LSBs the same total weight as the MSB.This is required because there is an even number of output bits from the switch-ing tree, whereas a thermometer coded word has an odd number of bits. Thisresults in that at least one of the output bits from the tree will have the value ‘0’.
Partial randomization DEM
The tree approach described above is known as full randomization DEM(FRDEM). For DACs with a large number of input bits, the hardware complexityof the FRDEM switching tree becomes large, since the number of outputs fromthe tree grows exponentially with the number of input bits. An approach that hasbeen proposed to trade the hardware complexity for a lower degree of randomiza-tion is the partial randomization DEM (PRDEM) technique. In PRDEM, theswitching tree is terminated before 1-bit outputs are achieved, thus resulting in alower hardware complexity. The outputs from the switches in the last layer areused as inputs to DAC banks consisting of one 1-bit DAC and one multi-bit DAC(the 1-bit DAC in the DAC bank is a required because of the added LSB in the
Figure 4.7 Generalized block diagram of a DEM DAC.
bina
ry-t
o-th
erm
omet
er e
ncod
er
scra
mbl
er1-bit
DACs
X1(
n)
X2(
n)
X3(
n) combinedoutputr(
n)
out2 r i 0=out1 M 1– out2
Compensation and Correction of Errors
60
input to the tree). Design, modeling, and measurements of a current-steeringPRDEM DAC is discussed in Sec. 5.6. From the simulations and measurementspresented there we find that randomization in a few layers only is enough formaking the distortion due to mismatch neglectable compared with the dynamicerrors. Hence, terminating the switching tree after a few layers is acceptable.
Mismatch shaping DEM
Using random scrambling has the effect of transforming harmonic distortioncaused by mismatch into (approximate) white noise. Hence, the power of the dis-tortion is evenly distributed over the whole frequency range. To gain even morein SNDR it is desirable to shape the noise, so that a larger portion of the noiseappears outside of the signal band, where it can be filtered out. This is the goalwith so called mismatch shaping DEM [24, 45, 46]. In mismatch shaping DEM,the one bit signals are chosen according to [45]
, (4.9)
where is the number of 1-bit signals and is a signal with very little powerwithin the signal band. The total output is
. (4.10)
Figure 4.8 DEM circuit utilizing switching tree.
switch2
r1(n)
switchN+1
rN(n)switch
N
rN1(n)
switchN
rN1(n)
switch2
r1(n)
NX(n)
0 to 1
-bit
DA
Cs
layer 1
layer N1
layer N
ui n( )
ui n( )1K---- X1 n( )⋅ zi n( )+=
K zi n( )
Y n( )1K---- w ∆i+( ) X1 n( )⋅ ⋅
i 1=
K
∑ 1K---- w ∆i+( ) zi n( )⋅ ⋅
i 1=
K
∑+= =
X1 n( ) w 1 ∆i
i 1=
K
∑+
⋅ w ∆i+( ) zi⋅i 1=
K
∑+⋅=
Compensation and correction of dynamic errors
61
The first term in (4.10) is the desired output (with a slightly different gain com-pared with (4.7)). The second term is the error, , due to mismatch. Moreover
, (4.11)
yielding
. (4.12)
Combining (4.10) and (4.12) yields
. (4.13)
Since every has very little power within the signal band, so does . Theconstruction of the different is similar to delta-sigma modulation (which isoutlined in Sec. 4.2.2) and is nontrivial. Several circuit solutions have been pro-posed (see, e.g., [24, 45, 47, 48]), and there are also solutions where the different
are multi-bit words.
4.2 Compensation and correction of dynamic errors
Techniques on compensation and correction of dynamic errors are presented inthis section. For behavioral-level simulations of the different techniques we useMatlab in combination with the state-space model presented in Sec. 3.4.1. Anarchitecture that utilizes redundant coding of differential signals to increase theflexibility and hence give the possibility for improved linearity is presented inSec. 4.2.1. The techniques described in Sec. 4.2.2 and Sec. 4.2.3 are dependenton models to compute the expected error and the predistorted input, respectively.For this purpose we base our techniques on the low-complexity model describedin Sec. 3.4.2. Here we only consider improvement on the linearity of the single-ended signals. The models need modifications to reduce distortion in the differ-ential signals. The update frequency is 10 MHz In all simulations and measure-ments.
Methods that have been claimed to improve the dynamic behavior, are the use oftrack and hold circuits or deglitcher circuits connected to the DAC outputs[49, 50]. These techniques are not considered in this thesis.
e n( )
X1 n( ) ui n( )i 1=
K
∑ X1 n( ) zi n( )i 1=
K
∑+= =
zi n( )i 1=
K
∑ 0=
e n( ) ∆i zi n( )⋅i 1=
K
∑=
zi e n( )ui n( )
ui n( )
Compensation and Correction of Errors
62
4.2.1 Differential DACs with variable common mode
In this section we propose a redundant differential DAC architecture whichallows the common mode level to be varied. This can be used, e.g., to reduce theoverall load at the outputs or to apply a dithering signal [51, 52] to reduce thenonlinear behavior. The ideas presented in this section were introduced in[53, 54, 55].
Proposed redundant architecture
The proposed redundant DAC architecture is shown in Fig. 4.9. It combines twocurrent-steering DACs (DAC1 and DAC2), which may be single-ended or differ-ential. In the latter case we only use output , and connect to a constant DCvoltage, , which in practice is the same as having a single-ended current-steering DAC.
The input, , to DAC1 is
, (4.14)
where is the input to the whole system and is a control signal. Theinput, , to DAC2 is similarly given by
, (4.15)
Figure 4.9 Proposed redundant DAC architecture.
A+ A–V dump
DAC1
A+
A
DAC2
A+
A
r(n)X(n)
X1(n)
X2(n)
Vdump
RL RL
I2 I1
X1 n( )
X1 n( ) X n( ) r n( )+=
X n( ) r n( )X2 n( )
X2 n( ) Xmax X n( )– r n( )+=
Compensation and correction of dynamic errors
63
where is the maximum value of for the given code, i.e., with all individ-ual bits . If the input code is binary weighted, then corre-sponds to with all individual bits inverted, represented by the invertersymbol in Fig. 4.9. The control signal must not cause any of the signals and
to overflow, since this causes distortion. Thus, the DAC inputs need to fulfill
, (4.16)
yielding
. (4.17)
With ideal DACs (DAC1 and DAC2) we obtain the following expressions for theoutput currents
and
. (4.18)
For the combined differential output current, , we obtain
. (4.19)
Hence, ideally we have the same differential output current as for a single idealdifferential current-steering DAC, because the control signals cancel. Of course,in reality the control signal will affect the two outputs differently due to any non-linearity in the transfer functions of the DACs, and the cancellation will not beperfect.
We also consider the common-mode signal
. (4.20)
Hence, the control signal is added to the common-mode signal. One factor thatlimits the possibly useful control signals is, therefore, the common-mode rejec-tion of the following circuitry. Another factor is, as mentioned earlier, how thecontrol signal is distorted between the two DAC outputs.
Xmax Xbi 1= Xmax X n( )–
X n( )X1
X2
0 X i Xmax≤ ≤
r min X Xmax X–,( )–≥
I1 Iu wi bi n( )⋅i 0=
N 1–
∑ Iu r n( )⋅+=
I2 Iu wi bi n( )⋅i 0=
N 1–
∑ Iu r n( )⋅+=
Idiff I1 I2–=
Idiff I1 I2– 2Iu bi wi⋅i 0=
N 1–
∑ Iu wi
i 0=
N 1–
∑–= =
Icm
I1 I2+
2--------------- Iu wi
i 0=
N 1–
∑ Iu r n( )⋅+= =
Compensation and Correction of Errors
64
In an implementation, the two DACs have to be mutually well-matched, prefera-bly manufactured on the same die, sharing same master bias, etc. It is also impor-tant to avoid clock skew between the two DACs, and therefore it is desirable thatthey share the same clock net. Obvious penalties, compared with conventionalDACs, are increased area requirements and power consumption. A test chip thatcan be used for evaluation of the ideas discussed here is presented in Sec. 5.7. Atthis point, however, the DACs on this chip have only been measured one at atime, not combined.
Dithering of the common-mode level
A first method of utilizing the redundancy is to apply dithering of the common-mode level to reduce the nonlinear distortion caused by random matching errorsin the current sources. This technique is similar to DEM techniques presentedearlier, and is actually a technique for compensation of static errors. It appears inthis section because the other methods of utilizing the redundant architectureaims at reducing dynamic errors. For simulation purposes, we add a randommatching error with Gaussian distribution, standard deviation ofand expectation value 0 to each unit current source. The simulated DAC architec-ture utilizes segmentation where the 6 MSBs are encoded into thermometer code.The matching errors have not been altered between the runs, i.e., the same DACshave been used in all simulations.
The control signal was chosen to be quantized values of
, (4.21)
where is a scaling constant and is white noise with a rectangular distribu-tion
. (4.22)
The PSD plots of for and are shown in Fig. 4.10(a) and (b),respectively. The input is a single-tone signal with half-scale amplitude. It is seenthat the added dithering signal reduces the spurious tones to a large extent. InFig. 4.11 the SFDR is plotted vs. . We see that the SFDR increases withincreasing . The quantitative results are, obviously, specific for this particularoutcome of the stochastic matching errors.
DC level minimization
We propose a second method based on the proposed redundant architecture inFig. 4.9 that aims at reducing the parasitic load associated with an output termi-nal. Looking at the circuit models presented in Sec. 3.4 we see that each current
σ 0.02 Iu⋅=
r n( )
a ψ n( )⋅
a ψ n( )
ψ n( ) Re 0.5– 0.5,( )∈
Idiff a 0= a 213=
a2loga
Compensation and correction of dynamic errors
65
source connected to a terminal provides an additional load through its outputimpedance. For the best possible dynamic behavior (i.e., short settling times) it isdesired to minimize the load at the output terminal, i.e., minimize the number ofunit current sources connected to the terminal. If the input does not make use ofthe whole range, e.g., a half-scale single-tone signal, this can be achieved by let-ting be a (negative) constant. This is equivalent to reducing the DClevel of each single-ended output.
(a) (b)
Figure 4.10 PSD plots for simulated outputs from redundant DAC with matching errors (a)without dither signal and (b) with dither signal having amplitude .
Figure 4.11 SFDR as a function of .
0 1 2 3 4 5−120
−100
−80
−60
−40
−20
0
PSD plot of DAC output, a = 0
Frequency [MHz]
PS
D [d
B/H
z]
0 1 2 3 4 5−120
−100
−80
−60
−40
−20
0
PSD plot of DAC output, a = 8192
Frequency [MHz]
PS
D [d
B/H
z]
a 213=
4 6 8 10 12 1480
82
84
86
88
90
92
94
96
98
100
SFDR vs. log2(a)
log2(a)
SF
DR
[dB
]
log2 a( )
r n( ) r=
Compensation and Correction of Errors
66
Here we present some simulation results using the model presented in Sec. 3.4.1.The simulated DAC is 14-bit binary-weighted, and the model parameters are thesame as in Table 3.1 on page 43. The current sources are assumed to be perfectlymatched, but matching errors can also be added in the model, as discussed inSec. 3.5. PSD plots of the simulated DAC outputs using half-scale sinusoidalinputs are shown in Fig. 4.12. The PSD for a single differential DAC is shown inFig. 4.12(a). PSDs for the proposed redundant architecture, with the dump termi-nal connected to a DC voltage source of 0.5 V, are shown in Fig. 4.12(b) and (c).The PSD for is shown in Fig. 4.12(b) and the PSD for (yieldingthe lowest possible DC level without overflow) is shown in Fig. 4.12(c). A Com-parison of Fig. 4.12(a) and (b) indicates that switching a current source betweenan output node and a silent node has favorable effects on the distortion, comparedwith switching between two output nodes, since the distortion is 5 dB lower inFig. 4.12(b). This also agrees with some single-ended measurements performed.The spurious tones are reduced even more, resulting in an improvement in theSFDR by approximately 7 dB when the DC level is reduced, as is the case inFig. 4.12(c). Further measurements have to be performed before any conclusionscan be made regarding the application to real DAC circuits.
Common-mode level reduction with boundary conditions
Using the approach with a constant is only applicable to a limited class ofsignals, i.e., the ones that do not utilize the possible input range. Moreover, it isrequired that the maximum and minimum value of all future samples of the inputare known. Even if the signal has finitely many samples, the number of samplesis often so large that this is not possible to obtain to a reasonable hardware cost oracceptable delay. Instead we modify the approach and choose as the small-est integer fulfilling the boundary conditions
(4.23)
and
. (4.24)
Boundary condition (4.23) ensures that overflow is avoided, and is chosensuch that the common mode variations can be sufficiently rejected in the follow-ing circuitry. The previous approach with a constant corresponds to
. The boundary conditions should hold for all , so we need to keeptrack of some future samples of , otherwise we risk choosing too small tofulfil both (4.23) and (4.24) for some future sample. However, since we do notneed to keep track of all future samples, which is the case when using a constant
, this approach is more suitable for implementation.
r 0= r 212–=
r n( )
r n( )
r n( ) min X n( ) Xmax X n( )–,( )–≥ rmin n( )=
r n( ) r n 1–( )– ∆rmax≤
∆rmax
r∆rmax 0= n
X r n( )
r
Compensation and correction of dynamic errors
67
In Fig. 4.13(a) and (b) we show simulated 3-tone PSD plots for a single DAC andfor the proposed redundant DAC with chosen as above, respectively. Thesimulation model is a 14-bit binary weighted version of the one presented inSec. 3.4.1. Parameter values are given in Table 3.1 on page 43, and .The peak-to-peak value for this particular input is approximately 10600. Thelargest distortion peak is reduced from –72 to –82 dB.
4.2.2 Modulation of expected errors
Delta-sigma modulation is a technique used in data conversion to achieve high-resolution with quantizers having few quantization levels. This is performedusing the quantization error in a feedback loop, spectrally moving a large amountof the quantization noise power to a frequency range above the signal band. How-
(a)
(b) (c)
Figure 4.12 PSD plots of simulated DAC outputs from (a) a conventional DAC, and the pro-posed redundant DAC with (b) and (c) . The input is a half-scale sinusoid with signal frequency 2.208 MHz and update frequency 10 MHz.
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
PSD for output from conventional DAC
Frequency [Hz]
PS
D [d
B/H
z]
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
PSD for output signal, r=0
Frequency [Hz]
PS
D [d
B/H
z]
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
PSD for output signal, r=−4096
Frequency [Hz]
PS
D [d
B/H
z]
r 0= r 212–=
r n( )
∆rmax 20=
Compensation and Correction of Errors
68
ever, an ideal quantizer is a poor model of a real data converter. Reference levelswill not be evenly spaced due to, e.g., component mismatch. Other dynamic andstatic errors also occur, as was discussed in Chapter 3.
In this section we propose a linearization technique based on delta-sigma modu-lation, primarily intended for DACs, which also spectrally shapes nonlinearitiesarising from other sources than the quantization process. The application, how-ever, is not limited to DACs, but can be applied to any kind of oversampled sys-tem. The technique presented here was first proposed in [56].
Delta-sigma modulator basics
The aim for a delta-sigma modulator is to spectrally shape the quantization noise,so that it is moved out of the signal band. This technique implies that oversamp-ling has to be used. A general delta-sigma modulator is shown in Fig. 4.14(a).The feedback filter is assumed to be a linear filter. The quantizer is often modeledwith an error, , added to the quantizer input, as shown in Fig. 4.14(b).
In the frequency domain, the output can be written as
(a) (b)
Figure 4.13 PSD for 3-tone signal (a) without and (b) with common-mode level reduction.
(a) (b)
Figure 4.14 (a) General delta-sigma modulator and (b) delta-sigma modulator with quanti-zer modeled as an added error signal.
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
PSD for simulated output signal, r=0
Frequency [Hz]
PS
D [d
B/H
z]
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
PSD for simulated output signal, ∆rmax
=10
Frequency [Hz]
PS
D [d
B/H
z]
e n( )
Qfeedback
filter
X(n) Y(n)
feedbackfilter
X(n) Y(n)e(n)
Compensation and correction of dynamic errors
69
(4.25)
where is the signal transfer function, is the noise transfer func-tion, and , , and are the z-transforms of , , and ,respectively.
The modulator structure we use in the following is shown in Fig. 4.15. It isreferred to as an error feedback modulator [8, 57], since the quantization error isused as an input to the filter .
It is easily derived from Fig. 4.15 that
(4.26)
and
. (4.27)
We let be an FIR transfer function, making an FIR filter. We cannow specify , and is implicitly given by (4.27). An orderis chosen by placing poles in the origin and zeros strategically on the unitcircle. This structure is sensitive to coefficient errors [8], and may be difficult toimplement. It is, however, an easy way to design an example for simulations inMatlab, where we can have virtually infinite precision in the coefficients.
Simulation results for a 5th order modulator of this type, using , with asingle-tone input is shown in Fig. 4.16. The input and output spectra are shown inFig. 4.16(a) and (b), respectively. The input has 14 bits of resolution, and a 6-bitquantizer is used. The zeros of the noise transfer function are located on the unitcircle at , , and . The spectrum for theinput signal quantized to 6 bits without the feedback is plotted in Fig. 4.16(c) forcomparison. As for all types of delta-sigma modulators, stability is an importantissue. The stability of delta-sigma modulators with FIR noise transfer functions isdiscussed in [58].
Figure 4.15 Error feedback modulator.
Y z( ) X z( ) STF z( )⋅ E z( ) NTF z( )⋅+=
STF z( ) NTF z( )Y z( ) X z( ) E z( ) Y n( ) X n( ) e n( )
H z( )
Q
H(z)
X(n) Y(n)
e(n)
STF z( ) 1=
NTF z( ) 1 H z( )–=
NTF z( ) H z( )NTF z( ) H z( ) Lth NTF
L L
OSR 4=
z 1= z e j π OSR⁄( )±= z e j π 2 OSR⋅( )⁄( )±=
Compensation and Correction of Errors
70
Spectral shaping of nonlinearities
As mentioned earlier, an ideal quantizer is a poor model of a real DAC. In thissection we propose a technique for compensating nonidealities due to physicalimperfections utilizing the basic ideas of delta-sigma modulation. The modulatorspectrally shapes the quantization noise through feedback of the quantizationerror. We want to do the same thing with distortion arising from nonlinearities inthe DAC. Therefore, the quantizer in Fig. 4.15 is substituted with a quantizer cas-caded with an accurate model of the DAC, yielding the block diagram shown inFig. 4.17. We refer to this circuit as the distortion shaper. The output from thequantizer, , is passed on as the input to the real DAC.
This structure can be modeled similarly as the delta-sigma modulator was inFig. 4.14(b), replacing the quantizer and the DAC model with an addition of anerror signal. However, the error signal, , might be considerably larger thanthe quantization error, which is bounded within one LSB of the quantizer. There-
(a)
(b) (c)
Figure 4.16 Spectra for (a) 14-bit single-tone signal, (b) delta-sigma modulated signal using5th order modulator with a 6-bit quantizer, and (c) 6-bit single-tone signal.
0 0.1 0.2 0.3 0.4 0.5−120
−100
−80
−60
−40
−20
0
14−bit input signal to modulator
Normalized frequency
PS
D [d
B]
0 0.1 0.2 0.3 0.4 0.5−120
−100
−80
−60
−40
−20
0
6−bit output signal from modulator
Normalized frequency
PS
D [d
B]
0 0.1 0.2 0.3 0.4 0.5−120
−100
−80
−60
−40
−20
0
6−bit single−tone signal
Normalized frequency
PS
D [d
B]
Y n( )
e n( )
Compensation and correction of dynamic errors
71
fore, a feedback configuration which is guaranteed to be stable according to somecriterion in the delta-sigma modulator case, need not necessarily be stable in thiscase. The stability issue has to be carefully considered for each special case, e.g.,through extensive simulation of the system.
For an implementation of the distortion shaper it is important to have an accuratemodel of the DAC. The best model is of course the DAC itself, meaning that weaccurately measure the error for each update instant, i.e., a fast and accurate ADCis required in the feedback loop. This is not easily achieved, so a better solutionwould be to use an adaptive model of the DAC, which is updated, e.g., during atraining period.
Simulations
A suitable candidate for the model in the feedback loop to compensate for errorsdue to finite output impedance is the low-complexity model presented inSec. 3.4.2. Here some simulation results for linearization of the DAC model inSec. 3.4.1 are presented. The simulation parameters are the same as in Table 3.1on page 43, except that the output resistance in the unit current sources has beenincreased a factor 10 to reduce the static nonlinearity, which is not included in thelow-complexity model. The parameters for the low-complexity model are thesame as those used in the simulations in Sec. 3.4.2. The filter is the same asin the delta-sigma simulation in Fig. 4.16. The method is illustrated in by thesimulation plot in Fig. 4.18 where the dominating second harmonic is suppressedwith 20 dB, to the cost of increased high frequency distortion. There is one spuri-ous tone within the signal band that increases, so the SFDR improvement is only11 dB.
Figure 4.17 Block diagram of the proposed distortion shaping device.
Q
H(z)
X(n)
Y(n) (to DAC)
e(n)
DACmodel
H z( )
Compensation and Correction of Errors
72
Measurements
Measured PSD plots for single-ended outputs from the DAC presented inSec. 5.5 are shown in Fig. 4.19. Fig. 4.19(a) shows the spectrum using an uncom-pensated input, whereas the input used in Fig. 4.19(b) has been processed withthe distortion shaping technique presented in this section. The model used forestimation of the error is a simple version of the low-complexity model presentedin Sec. 3.4.2, namely
. (4.28)
Referring to the block diagram of the model shown in Fig. 3.18, the lookup tableonly contains two values, and 0, and is addressed by the MSB of the input tothe DAC. The resulting SFDR improvement is approximately 12 dB, which givesa strong indication that the model structure presented in Sec. 3.4.2 is suitable forits purpose, i.e., to estimate dynamic errors in order to compensate for them.
4.2.3 Predistortion of dynamic errors
The method described in Sec. 4.2.2 reduces the distortion within the signal bandto the cost of increased out-of-band distortion, which requires filtering to removethe out-of-band distortion. The technique is particularly suited to use in a delta-sigma DAC, where filters are required in any case to remove the shaped quantiza-tion noise. For other cases it is better to compute an input that yields an output asclose as possible to the desired output, removing the distortion rather than spec-trally shaping it. By doing so, we also increase the possible signal bandwidth fora given update frequency, compared with if the distortion is shaped. Filters arestill required to remove images of the signal, but the filter requirements are not ashard as if the filters also have to remove the shaped distortion. This technique is
(a) (b)
Figure 4.18 PSD plots for simulated outputs (a) without and (b) with distortion shaping.
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
Output signal wihtout distortion shaped
Frequency [Hz]
PS
D [d
B/H
z]
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
Output signal with distortion shaped
Frequency [Hz]
PS
D [d
B/H
z]
erel X n( )( ) a bN 1– n( )⋅=
a
Compensation and correction of dynamic errors
73
known as predistortion [12]. Methods based on predistortion are often proposedfor improving the linearity in power amplifiers for radio frequency (RF) applica-tions [59, 60, 61]. Very little work has been done in the field of predistortion forDACs. In [62] a method was reported utilizing a black-box model of the DAC.No consideration was, however, taken to the computational complexity of thepredistortion block.
In this section we present a predistortion method for DACs aimed at reducing thenonlinear behavior caused by parasitic capacitance, as discussed in Sec. 3.4. Themethod utilizes the low-complexity model presented in Sec. 3.4.2 to calculate thepredistorted input to the DAC. The method first appeared in [63].
Predistortion block
The purpose of the predistortion block is to, for a given input , find a modi-fied input, , such that . To accomplish this we use the low-com-plexity DAC model presented in Sec. 3.4.2. In accordance with Sec. 3.4.2 we use
(4.29)
as an estimate of the output from the current-steering DAC and normalize theoutput such that the static gain of the DAC is unity. To find the appropriate pre-distorted signal we replace with in (4.29), yielding
.
(4.30)
Further, we set and assume that , i.e., that thepredistortion for the previous sample was successful. This yields
(a) (b)
Figure 4.19 PSD plots for measured outputs from a DAC (a) with and (b) without the distor-tion shaped.
X n( )X p n( ) Y n( ) X n( )≈
Y n( ) Y n 1–( ) X n( ) Y n 1–( )–[ ] 1 erel X n( ) X n 1–( ),( )–[ ]⋅+=
X X p
Y n( ) Y n 1–( ) X p n( ) Y n 1–( )–[ ] 1 erel X p n( ) X p n 1–( ),( )–[ ]⋅+=
Y n( ) X n( )= Y n 1–( ) X n 1–( )=
Compensation and Correction of Errors
74
.
(4.31)
Solving for yields
. (4.32)
In Sec. 3.4.2 only a few MSBs of are used to estimate . Thus, if we assumethat the correction introduced by the predistortion is small, i.e., issmall, it is reasonable to approximate with
. We can then make a nonrecursive definition of
, (4.33)
where
. (4.34)
Similarly to the error estimation presented in Sec. 3.4.2, can be stored in alookup table. Further, the lookup table may be addressed with only a few MSBsof and to keep the size of the lookup table small. We propose apredistorter circuit according to Fig. 4.20.
Simulation results
In this section we present results from simulations where the predistortion tech-nique is used to linearize the state-space model of the current-steering DAC pre-sented in Sec. 3.4.1. The simulation parameters are given in Table 3.1 on page43, and the parameters for the predistortion block are the same as in the simula-tions in Sec. 3.4.2.
Figure 4.20 Proposed predistorter circuit.
X n( ) X n 1–( ) X p n( ) X n 1–( )–[ ] 1 erel X p n( ) X p n 1–( ),( )–[ ]⋅+=
X p n( )
X p n( ) X n 1–( ) X n( ) X n 1–( )–1 erel X p n( ) X p n 1–( ),( )–------------------------------------------------------------+=
X erelX p n( ) X n( )–
erel X p n( ) X p n 1–( ),( )erel X n( ) X n 1–( ),( ) X p n( )
X p n( ) X n 1–( ) X n( ) X n 1–( )–1 erel X n( ) X n 1–( ),( )–-------------------------------------------------------+= =
X n 1–( ) prel X n( ) X n 1–( ),( ) X n( ) X n 1–( )–( )⋅+=
prel X n( ) X n 1–( ),( ) 11 erel X n( ) X n 1–( ),( )–-------------------------------------------------------=
prel
X n( ) X n 1–( )
lookuptableX(n)
prel(n) Xp(n)z1
Compensation and correction of dynamic errors
75
The PSD plots for outputs without and with predistorted inputs are shown inFig. 4.21(a) and (b), respectively. The input is a half-scale sinusoid with signalfrequency 1.104 MHz and the update frequency is 10 MHz. Full-scale inputscannot be used since the predistorted inputs are likely to overflow in that case. InFig. 4.22 we have increased the signal frequency to 2.208 MHz. For both fre-quencies it can be concluded that the predistortion reduces the second harmonicto a large extent and suppresses the other harmonics below the noise floor. SFDRis plotted as a function of signal frequency in Fig. 4.23. For this example theSFDR at low frequencies is preserved over the whole frequency range when thepredistortion technique is used.
(a) (b)
Figure 4.21 PSD plots for outputs (a) without and (b) with predistortion. The input is a half-scale sinusoid with signal frequency 1.104 MHz, and the update frequency is10 MHz.
(a) (b)
Figure 4.22 PSD plots for outputs (a) without and (b) with predistortion. The input is a half-scale sinusoid with signal frequency 2.208 MHz, and the update frequency is10 MHz.
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
PSD for nonpredistorted input signal
Frequency [Hz]
PS
D [d
B/H
z]
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
PSD for predistorted input signal
Frequency [Hz]
PS
D [d
B/H
z]
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
PSD for nonpredistorted input signal
Frequency [Hz]
PS
D [d
B/H
z]
0 1 2 3 4 5
x 106
−120
−100
−80
−60
−40
−20
0
PSD for predistorted input signal
Frequency [Hz]
PS
D [d
B/H
z]
Compensation and Correction of Errors
76
4.2.4 Implementation issues
Methods for compensating dynamic errors utilizing models of the errors werepresented in Sec. 4.2.2 and Sec. 4.2.3. The hardware complexity for an imple-mentation of the compensation blocks used in the simulations is low, a fewadders and multipliers, and a small lookup table. A problem that needs to besolved, however, is the estimation of model parameters. In simulations this is nota problem, since both the input and the output are accessible (without approxima-tion), and model parameters can be estimated with high precision. To do the samething for an actual circuit, a fast and accurate ADC is required to measure theerror in a wide-band DAC aiming for high resolution. In [62] this problem wasapproached by using a state-of-the-art commercial ADC operating at a limitedpart of the signal band. This solution failed to compensate for any distortion thatappeared outside of this band.
Figure 4.23 Simulated SFDR as a function of signal frequency with and without predistor-tion.
105
106
50
55
60
65
70
75
80
85
90
Simulated SFDR vs. fsig
fsig
[Hz]
SF
DR
[dB
]
without predistortionwith predistortion
77
5 Current-Steering DACImplementations
The most common type of DAC for high-speed applications, e.g., broadbandcommunication, is the current-steering. The implementation of three different 14-bit current-steering DACs in standard digital CMOS processes is discussed in thischapter, together with the measurement results.
5.1 CMOS processes
Complementary metal oxide semiconductor (CMOS) processes are very popularfor implementing integrated circuits, mainly due to low cost, but also becausethey provide good possibilities for designing digital low-power circuits. Thewords “metal oxide semiconductor” refers to the physical structure of the transis-tors, whereas the word “complementary” means that the designer have access toboth NMOS and PMOS transistors. All DACs presented in this chapter have beenimplemented in standard digital CMOS processes. In this section we give anoverview of the CMOS transistor.
5.1.1 Large signal models
The large signal behavior of the CMOS transistor in different operation regions isbriefly discussed in this section. Well known equations for the current-voltagerelationships, assuming long channel devices, are also presented.
Current-Steering DAC Implementations
78
NMOS transistors
A commonly used symbol for an NMOS transistor is shown in Fig. 5.1(a). Thelabels G, S, D, and B denote the gate, source, drain, and bulk terminal, respec-tively. We have also indicated the gate-source voltage, , the drain-sourcevoltage, , and the bulk-source voltage, . The drain current, is alsoindicated in the figure. In most processes, the bulk terminals of all NMOS tran-sistors are connected to ground, and the simplified symbol in Fig. 5.1(b), withoutthe bulk terminal explicitly shown, can be used instead.
Equations (5.1), (5.2), and (5.3) model the relationships between the drain cur-rent and the different voltages for a long channel NMOS transistor in the cut-off,linear, and saturated region, respectively.
, (5.1)
,
, (5.2)
and
,
. (5.3)
(a) (b)
Figure 5.1 (a) Symbol for an NMOS transistor, and (b) simplified symbol for an NMOStransistor with the bulk terminal connected to ground.
V GSV DS V BS ID
D
S
G B
VBS
VDS
VGS
ID
V GS V T n,< ⇒ID 0=
V GS V T n,≥ V DS V GS V T n,–< V eff= ⇒
ID µ0 n, CoxWL----- V eff V DS
V DS2
2----------–
=
V GS V T n,≥ V DS V GS V T n,–≥ V eff= ⇒
ID
µ0 n, Cox
2-------------------W
L-----V eff
2 1 λ V DS V eff–( )+( )=
CMOS processes
79
is the threshold voltage, is the electron mobility, is the gate oxidecapacitance per unit area, and and is the width and the length of the transis-tor, respectively. is a parameter known as the output impedance constant,which is roughly proportional to [8]. A phenomenon known as the bodyeffect makes the threshold voltage dependent on the bulk-source voltage accord-ing to
, (5.4)
where is the threshold voltage at zero . The built-in Fermi potential and the body effect constant are process dependent parameters [8].
PMOS transistors
Symbols for PMOS transistors are shown in Fig. 5.2. In Fig. 5.2(a) the four ter-minal symbol is shown, and the corresponding simplified symbol where it isimplied that the bulk terminal is connected to the power supply voltage ( ) isshown in Fig. 5.2(b).
Equations (5.5), (5.6), and (5.7) model a long channel PMOS transistor in thecut-off region, linear region, and saturated region, respectively
, (5.5)
,
, (5.6)
and
(a) (b)
Figure 5.2 (a) PMOS transistor symbol and (b) simplified PMOS transistor symbol.
V T n, µ0 n, CoxW L
λ1 L⁄
V T n, V T n 0, , γ 2ΦF V BS– 2ΦF–( )+=
V T n 0, , V BSΦF γ
V DD
S
D
G B
VSBVSD
VSG
ID
V SG V T p,< ⇒ID 0=
V SG V T p,≥ V SD V SG V T p,–< V eff= ⇒
ID µ0 p, CoxWL----- V eff V SD
V SD2
2----------–
=
Current-Steering DAC Implementations
80
,
. (5.7)
The threshold voltage for PMOS transistors is negative. Due to the body effectwe get
. (5.8)
Notes on large signal models
The large signal equations presented above are only suitable for long channeldevices. Circuit simulators utilize more elaborate models, including many higherorder effects, to get more accurate results. Higher order effects become more andmore important as device dimensions become smaller and smaller.
5.1.2 Small signal models
As can be seen from the equations in Sec. 5.1.1, MOS transistors are nonlineardevices. In order to find the effect of small variations in currents and voltages weuse linearized models, so called small signal models.
In Fig. 5.3(a) below we show a so called -parameter model of an NMOS tran-sistor. The parameters in the saturated region are given by
, (5.9)
, (5.10)
and
. (5.11)
The corresponding small signal equivalent model for PMOS transistors is shownin Fig. 5.3(b). The parameters are given by
, (5.12)
V SG V T p,≥ V SD V SG V T p,–≥ V eff= ⇒
ID
µ0 p, Cox
2-------------------W
L-----V eff
2 1 λ V SD V eff–( )+( )=
V T p, V T p 0, , γ 2ΦF V SB– 2ΦF–( )–=
g
gm V GS∂∂ID 2µ0 n, Cox
WL-----ID≈=
gds V DS∂∂ID λID≈=
gmbs V BS∂∂ID γ gm
2 2ΦF V BS–------------------------------------≈=
gm V SG∂∂ID 2µ0 p, Cox
WL-----ID≈=
Analog DAC building blocks
81
, (5.13)
and
. (5.14)
5.2 Analog DAC building blocks
Different aspects of the design of analog building blocks are discussed in thissection. An overview of implementation a current source is given in Sec. 5.2.1,and implementation of switches is discussed in Sec. 5.2.2.
5.2.1 CMOS current sources
Current sources are essential building blocks in current-steering DACs, and in theprevious section we have established transistor models that are adequate to dis-cuss the implementation of current sources in CMOS technology. We know fromChapter 3 that the output impedance of the current source, and the matchingbetween the current sources, are critical parameters for the linearity of the DACs.
Single transistor current source
A single transistor PMOS current source is shown in Fig. 5.4(a). The bias voltageis set by a bias circuit, as discussed in Sec. 4.1.2. The ideal current source hasinfinite output impedance, i.e., the output current is independent on the voltageacross the current source. This is desired in current steering DACs since we wantthe output current (from each current source) to be independent on the outputvoltage. In reality the output resistance of the current source is
(a) (b)
Figure 5.3 Small signal equivalent model of (a) an NMOS transistor and (b) a PMOS tran-sistor.
gmvgs gmbsvbs gds
G D
S
vgs vds
id
gmvsg gmsbvsb gds
G D
S
vsg vds
id
gds V SD∂∂ID λID≈=
gmsb V SB∂∂ID γ gm
2 2ΦF V SB–------------------------------------≈=
Current-Steering DAC Implementations
82
, (5.15)
due to the channel length modulation. Moreover, parasitic capacitance in thedevices, indicated in Fig. 5.4(a), contributes to a capacitive part of the outputimpedance. The total output impedance is
, (5.16)
where the output capacitance and is the for the tran-sistor.
Cascode current source
If the output resistance is not large enough to meet the required linearity, we canuse a cascode current source as shown in Fig. 5.4(b). The output resistance forthis current source is approximately
, (5.17)
where and are small signal parameters for the cascode transistorand is the for the source transistor. The output resistance isincreased, since . The cascode transistor reduces the voltagevariations over the parasitic capacitance , compared with the single transis-
(a) (b)
Figure 5.4 PMOS current sources (a) without and (b) with cascode transistor.
tor case. Hence, the influence of on the bandwidth of the current source isreduced. There are, however, also parasitic capacitance in the output node of thecascode transistor. The output impedance is approximately
, (5.18)
where in this case . For higher frequencies where the capacitive partdominates, then for both type of current sources. isroughly a parallel connection between the gate-drain and the drain-bulk capaci-tance for the transistor connected to the output node. The value of the parasiticcapacitance is mainly determined by the width of the transistor. If the width is ofthe same order in both the cascoded and the single transistor case, yielding
, we have not gained very much in the range of frequencies wherethe capacitive part is dominating. A part of the output capacitance is also contrib-uted to by the metal wires connected to the current sources. This part of thecapacitance is unaffected by the choice of current source. In the next section weshow that the cascoding effect can also be achieved with the switch. The conclu-sions are that for higher frequencies we do not gain very much by introducingcascode transistors but we loose in possible output swing since we need to keepall transistors in saturation (the output resistance is severely deteriorated if thetransistors enter the linear region). Therefore, the cascode transistors have beenomitted in the later DAC implementations.
5.2.2 CMOS switches
The switches are also critical building blocks in current-steering DACs. In thissection we will assume that the current sources are of PMOS type. In the case ofNMOS current sources the discussion is similar. Differential PMOS and NMOSswitches are shown in Fig. 5.5(a) and (b), respectively.
(a) (b)
Figure 5.5 CMOS implementations of (a) a differential PMOS switch and (b) a differentialNMOS switch.
It is important that the signals controlling the switches are such that the two tran-sistors in the switch are not simultaneously completely turned off, in which casecharge will be assembled at the output node of the current source and give rise tolarge transients once one of the transistors is turned back on.
Assume that the PMOS type differential switch is used. In steady-state, when oneof the transistors is conducting and the other turned off, the conducting switchtransistor acts as a cascode transistor (compare with Fig. 5.4(b)). In order to haveshort switching times and low channel charge injection from the switches it isdesired to use transistors with small area in the switches. A large isrequired to get a good cascoding effect. Since is proportional to ,there is a trade-off between switch area and cascoding effect. Moreover, when theoutput voltage exceeds the absolute value of the threshold voltage, the switchtransistor enters the linear region of operation and the ratio is deterio-rated. Even if the cascoding effect of the switch is limited, it is better to usePMOS switches than NMOS switches. Similarly, NMOS switches are preferredwhen NMOS current sources are used.
5.3 Digital DAC building blocks
Some digital building blocks are required when implementing DACs. In this sec-tion we discuss the implementation of binary-to-thermometer encoders andswitch signal generators, i.e., the circuits used to generate proper signals to con-trol the switches. The latter is an interface circuit between the digital and the ana-log circuits, and is placed in the group of digital circuits since all circuitsimplemented during this work are designed with classical digital circuit tech-niques. All digital gates have been implemented using the complementary staticCMOS logic style [64, 65, 66].
5.3.1 Binary-to-thermometer encoding
Thermometer coded and segmented DAC architectures are discussed in this sec-tion, and it is motivated why they are preferred to binary coded DACs. We alsopresent the binary-to-thermometer encoder architecture that has been used in theDAC implementations presented in the following.
Thermometer coded and segmented structures in general
First consider a binary weighted architecture, i.e., where the weights .In a transition between, e.g., the codes and
, we may during a short moment have some erroneouscode, e.g., controlling the switches due to different rise and falltimes of the digital circuits. This will cause a so called glitch in the transient
gm gds⁄gm gds⁄ W
gm gds⁄
wi 2i 1–=X 0 1 1 … 1 1, , , , ,[ ]=
X 1 0 0 … 0 0, , , , ,[ ]=1 1 1 … 1 1, , , , ,[ ]
Digital DAC building blocks
85
response of the DAC, as shown in Fig. 5.6. This can occur because in the transi-tion there are individual bits making transitions from to , at the same time asthere are other bits making transitions from to .
Next consider a thermometer coded architecture. The corresponding thermome-ter codes for 2-bit, 3-bit, and 4-bit binary codes are given in Fig. 5.7(a), (b), and(c), respectively. The weight for each bit is , and the superscriptindicates the corresponding number of bits in the binary code. The thermometercode is monotone, i.e., in each transition between codes there only exist transi-tions from to or from to in the individual bits, not both. Therefore,glitches as in Fig. 5.6 cannot occur, indicating an advantage for the thermometercode compared with the binary code. Moreover, even if matching errors willcause the weights to deviate from 1, a thermometer coded DAC is guaranteed tobe monotone, i.e., the output if and only if . This isbecause
(5.19)
and all . As discussed in Sec. 4.1.1, a binary coded converter is not neces-sarily monotone.
Figure 5.6 Large glitch due to poor internal timing in a 4-bit binary weighted DAC. Thedesired transition is from 7 to 8.
0 11 0
n
123456789
101112131415
update instant
outp
ut le
vel
Glitch in 4−bit binary weighted DAC
tik wi 1= k
1 0 0 1
Y X1( ) Y X2( )> X1 X2>
Y X1( ) wi
i 1=
X1
∑ wi
i 1=
X2
∑ wi
i X2 1+=
X1
∑+ Y X2( ) wi
i X2 1+=
X1
∑+= = =
wi 0>
Current-Steering DAC Implementations
86
Other types of codes that falls somewhere between the binary code and the ther-mometer code have also been proposed, e.g., linear and polynomial codes[67, 68], but these are not covered in this thesis. One code, that also falls betweenthe binary and the thermometer code, and is commonly used in DAC design is thesegmented code. An -bit binary code corresponds to a -bit thermome-ter code. Hence, the hardware complexity in the encoding circuitry increasesexponentially with , and becomes excessively large for large . An often used
(a) (b)
(c)
Figure 5.7 Truth tables for (a) 2-3 encoder and (b) 3-7 encoder, and (c) 4-15 encoder.
b1
b0
t32 t
22 t
12
0 0 0 0 00 1 0 0 11 0 0 1 11 1 1 1 1
b2
b1
b0
t73 t
63 t
53 t
43 t
33 t
23 t
13
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 1
0 1 1 0 0 0 0 1 1 1
1 0 0 0 0 0 1 1 1 1
1 0 1 0 0 1 1 1 1 1
1 1 0 0 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
b3
b2
b1
b0
t154 t
144 t
134 t
124 t
114 t
104 t
94 t
84 t
74 t
64 t
54 t
44 t
34 t
24 t
14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
1 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
1 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
N 2N 1–( )
N N
Digital DAC building blocks
87
compromise is to use thermometer code for a few of the MSBs, say of theMSBs, and let the remaining LSBs be binary weighted. This is referred toas a segmented code. Assume a binary weighted input code
, (5.20)
which is encoded into segmented code
, (5.21)
where
, (5.22)
and is thermometer encoded from .This is illustrated in Fig. 5.8(a), where a block diagram of a segmented DAC isshown. The corresponding weights for the segmented codes, , are
. (5.23)
There are also multi-segmented architectures, as indicated in Fig. 5.8(b), wheremore segments of the binary coded input are converted into thermometer code.One example is the doubly segmented DAC presented in Sec. 5.7.
Implementation of binary-to-thermometer encoders
Analyzing the truth tables in Fig. 5.7 we will come up with a regular circuit solu-tion utilizing a tree structure of NAND gates, NOR gates, and inverters, previ-ously reported by Wikner in [69]. This type of encoder has been used in allimplementations described in this chapter. A similar (or possibly identical) solu-tion has been faintly outlined by others [70].
First we consider the 2-3 encoder. It is easily verified from the truth table inFig. 5.7(a) that
,
, and
. (5.24)
KN K–
Xb bN 1– bN 2– … b0, , ,[ ]=
Xs s2K N K– 2–+ … sN K– sN K– 1– … s0, , , , ,[ ]=
sN K– 1– … s0, ,[ ] bN K– 1– … b0, ,[ ]=
s2K N K– 2–+ … sN K–, ,[ ] bN 1– … bN K–, ,[ ]
ws i,
ws i,2i for i 0 N K– 1–,[ ]∈
2N K– for i 2K N K– 2–+ N 1–,[ ]∈
=
t12 b1 b0,( ) b1 b0+=
t22
b1 b0,( ) b1=
t32 b1 b0,( ) b1 b0⋅=
Current-Steering DAC Implementations
88
(a)
(b)
Figure 5.8 (a) Segmented and (b) multi-segmented current-steering DAC architecture.
bina
ry-t
o-th
erm
omet
eren
code
rde
lay
bina
ry c
ode
MSBs
LSBs
latches,switches,
andcurrent sources
dela
yen
code
rs
latches,switches,
andcurrent sources
Digital DAC building blocks
89
In Fig. 5.7(b) it is indicated that the truth table of the 2-3 encoder, with inputsand , appears twice in the truth table for the 3-7 encoder. The logic expressiondescribing the 3-7 encoder is
,
, and
, (5.25)
where .
In Fig. 5.7(c) it is indicated that the logic expressions for a 4-bit encoder can beobtained in a similar fashion if a 3-bit encoder is available. For the general -bitencoder we have
,
, and
, (5.26)
where . Rewriting (5.26) yields
,
, and
. (5.27)
Since differential signals are used to control the switches, it is unimportantwhether the outputs from the encoder are the thermometer coded bits or theirinverses, since both types are required. Therefore, if we allow that the outputsfrom even order encoders (i.e., the encoders for which is an even integer) arethe inverted thermometer coded bits, any -bit encoder can be implemented witha tree of NAND gates, NOR gates and inverters. A 2-bit encoder, a general evenorder encoder, and a general odd order encoder are shown in Fig. 5.9(a), (b) and(c), respectively.
The binary-to-thermometer encoder can be physically implemented in variousways. One way is to describe the block in a hardware description language, e.g.,VHDL or Verilog [71], and utilize a synthesis flow on this description to auto-matically generate the circuit. In the implementations presented in this chapterwe have used the full-custom approach.
b0b1
t j3 b2 b1 b0, ,( ) b2 t j
2 b1 b0,( )+ b2 t j2 b1 b0,( )⋅= =
t43 b2 b1 b0, ,( ) b2 b2= =
t j 4+ b2 b1 b0, ,( ) b2 t j2 b1 b0,( )⋅ b2 t j
2 b1 b0,( )+= =
j 1 2 3, , ∈
N
t jN bN 1– … b0, ,( ) bN 1– t j
N 1– bN 2– … b0, ,( )⋅=
t2N 1– bN 1– … b0, ,( ) bN 1–=
t j 2N 1–+N bN 1– … b0, ,( ) bN 1– t j
N 1– bN 2– … b0, ,( )+=
j 1 … 2N 1– 1–, , ∈
t jN bN 1– … b0, ,( ) bN 1– t j
N 1– bN 2– … b0, ,( )+=
t2N 1– bN 1– … b0, ,( ) bN 1–=
t j 2N 1–+N bN 1– … b0, ,( ) bN 1– t j
N 1– bN 2– … b0, ,( )⋅=
NN
Current-Steering DAC Implementations
90
5.3.2 Switch signal generators
In the following we assume that the switches are PMOS switches, as inSec. 5.2.2. To avoid that both transistors are simultaneously turned off, theswitching signals and should not simultaneously be high [72], but ratherhave nonoverlapping waveforms similar to those in Fig. 5.10. Two different cir-cuits for creating nonoverlapping switching signals are presented in this section.Both have been used in the implementations presented in the following. ForNMOS switches it is instead required that the switching signals are overlapping.These signals can be generated in a similar way as nonoverlapping signals.
The first circuit, which uses digital logic gates, is shown in Fig. 5.11. It isassumed that the inputs are synchronized with flip-flops or similar. In steadystate, and . When there is a transition in the inputs, an outputcannot go high until the other output has reached a low level.
(a)
(b) (c)
Figure 5.9 (a) 2-bit encoder, (b) even order N-bit encoder, and (c) odd order N-bit encoder.The boxes in (b) and (c) represents (N-1)-bit encoders.
b0
b1
t12
t22
t32
b0
bN−2
bN−1
t1N−1
t2
N−1−1
N−1
t1N
t2
N−1−1
N
t2
N−1N
t2
N−1+1
N
t2
N−1
N
b0
bN−2
bN−1
t1N−1
t2
N−1−1
N−1
t1N
t2
N−1−1
N
t2
N−1N
t2
N−1+1
N
t2
N−1
N
Q+ Q–
Q+ D= Q– D=
DAC design strategies and measurement setup
91
The second solution utilizes clocked differential cascode voltage switch (DCVS)[73] latches, and is shown in Fig. 5.12. It is required that the inputs only changetheir values while the clock signal, , is high, i.e., when the clocked transistorsare turned off. This can be ensured by adding a latch at the input which is trans-parent only during the high clock phase. By proper sizing of the transistors, thecrossover point between and can be chosen to avoid having both switchtransistors simultaneously shut off [21].
5.4 DAC design strategies and measurement setup
Some overall design strategies are shared between the current-steering DACimplementations presented in this chapter. To avoid repeating these design strate-gies for each DAC separately, we have compiled them in this section. We alsopresent the measurement setup that has been used.
Figure 5.10 Nonoverlapping switch signals for controlling differential PMOS switches.
Figure 5.11 Implementation of switch signal generator utilizing cross coupled NOR gates.
n n+1 n+2
0
1
Nonoverlapping switch signals
Update instant
Logi
c le
vel
D
D
Q+
Q−
Φ
Q+ Q–
Current-Steering DAC Implementations
92
5.4.1 Overall layout structure
An overview of a DAC floor plan is shown in Fig. 5.13. Starting from the left wehave the digital inputs entering the digital encoder consisting of binary-to-ther-mometer encoders and delay elements. Once the decoding is performed, the sig-nals are applied to the switch signal generators (denoted latches in Fig. 5.13),whose outputs are used to control the switches. The current sources are placed inthe block in the right part of Fig. 5.13, and the output current wires are placedbetween the array and the switches.
Figure 5.12 Clocked DCVS latch implementation of a switch signal generator.
Figure 5.13 Layout strategy used in the DAC implementations.
D D
F F
Q Q+
current source array
latc
hes
& s
wit
ches
enco
ding
& d
elay
output currentsdigital input
DAC design strategies and measurement setup
93
In other design strategies, using so called row-column decoding for thermometerencoding, the switches and some digital logic are placed within the arrays [7].This may cause interference between digital and analog parts, leading to a noisyoutput signal. With the layout strategy used in the implementations presented inthis chapter, the analog and digital parts are separated. Guard rings are usedaround digital as well as analog parts to reduce the substrate noise in the analogparts due to switching in the digital parts. Separate supply voltages are used fordigital and analog circuitry, to reduce the amount of simultaneous switchingnoise [74] in the analog signals.
5.4.2 Clocking strategy
Uncertainties in the timing of the switching signals, known as jitter, cause distor-tion and noise in the DAC output. It is therefore important that the DAC isupdated at well-defined instants in time. In order to achieve that, it is requiredthat the clock net driving the switch signal generators is carefully designed. Aschematic of a clock net with a tree structure that has been used in the implemen-tations is shown in Fig. 5.14. Special care has been given to equalizing thelengths of the wires connected to the output of the inverting buffers in each levelof the tree in the layout. This is in order to have the same capacitive load in eachbranch to avoid skew of the clock signal between the branches.
5.4.3 Measurement setup
The DAC measurements presented in the following sections have been performedusing a measurement system outlined in Fig. 5.15(a). The measurement system iscontrolled by a personal computer (PC) running Matlab. Input data to the DAC is
Figure 5.14 Tree clock network for driving the switch signal generators.
Current-Steering DAC Implementations
94
delivered from a measurement board with a low voltage differential signalling(LVDS) interface to the DAC. This measurement board is also capable of collect-ing digital data for, e.g., ADC measurements. This feature is not used during theDAC measurements, and is therefore omitted in Fig. 5.15. The peripheral instru-ments, such as power supply, clock generator, oscilloscope, and spectrum ana-lyzer, are connected to the PC via a general purpose interface bus (GPIB). Theinstruments are controlled by a GPIB controller, which in turn is controlled fromMatlab. Measurement data can be collected from the measurement instrumentsover the GPIB, and further analyzed in Matlab.
A printed circuit board (PCB) for DAC measurement is outlined in Fig. 5.15(b).The output currents from the DAC is directed into off-chip resistors. An RF-transformer is used to convert the differential signal to a single-ended signal thatcan be handled by the different measurement instruments. In order to measure theindividual single-ended outputs, the transformer must be removed.
5.5 A 14-bit DAC in 0.35 µm CMOS
In this section we present the first DAC chip manufactured during this work. Abrief overview of the chip is given in Sec. 5.5.1. Measurement results are pre-sented in Sec. 5.5.2.
5.5.1 Chip description
A photo of the chip is shown in Fig. 5.16. The chip was fabricated in a 0.35 µmCMOS process with three metal layers. The total chip area is 7.3 mm2, whereasthe core area is 2 mm2. The DAC is segmented, where the 5 MSBs are encodedinto thermometer code and the remaining 9 LSBs are binary weighted. The cur-rent sources are of PMOS type utilizing a single cascode transistor, and theswitches are of NMOS type. As was mentioned in Sec. 5.2.2, it would have beena better choice to use PMOS switches. This mistake was corrected in the laterimplementations. The strategy used for placement of unit current sources in thearray was aimed at reducing the influence of linearly graded parameter varia-tions. The switch signal generators are of the type shown in Fig. 5.11. A thoroughdescription of the design is given in [75].
5.5.2 Measurement results
Output spectra from differential full-scale single-tone measurements are shownin Fig. 5.17. For the (a) and (b) figures the update frequency is 5 MHz, and thesignal frequencies are approximately 0.6 MHz and 1.6 MHz, respectively. Theupdate frequency in the (c) and (d) figures is 20 MHz, and the signal frequencies
A 14-bit DAC in 0.35 µm CMOS
95
are approximately 2.5 MHz and 6.5 MHz, respectively. A common property forall spectra in Fig. 5.17 is that the dominating spurious tone is the third harmonic,and we observe that the SFDR decreases with increasing signal frequency.
(a)
(b)
Figure 5.15 Setup for DAC measurements. The block diagram in (a) shows the PC con-trolled measurement system, and a PCB used for DAC measurement is outlinedin (b).
PC GPIBcontroller
powersupply
clockgenerator
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oscilloscope
spectrumanalyzer
measurementboard
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loadresistors
RFtransformer
single-endedoutputs
digital input
combinedoutput
analog supplydigital supply
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Output spectra for half-scale single-tone measurements are shown Fig. 5.18below. The signal and update frequency for each sub figure is the same as in thecorresponding sub figure in Fig. 5.17. Once again we find that the dominatingspurious tone is the third harmonic, and that the SFDR decreases with increasingsignal frequency.
The measurements were carried out for several signal frequencies, and the SFDRwas extracted from the spectra. SFDR is plotted as a function of signal frequencyin Fig. 5.19. Fig. 5.19(a) shows SFDR for the full-scale inputs, whereasFig. 5.19(b) shows SFDR for the half scale inputs.
These measurement results correspond well with the simulation results presentedin Sec. 3.4. This indicates that the models of nonlinear behavior due to parasiticcapacitance that was presented provide good descriptions of the behavior of cur-
Figure 5.16 Chip photo of the 14-bit current-steering DAC implemented in a 0.35 µmCMOS process.
A 14-bit PRDEM DAC in 0.35 µm CMOS
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rent-steering DACs at higher frequencies. In the later implementations, presentedin Sec. 5.6 and Sec. 5.7, the dynamic properties were improved (compared withthis implementation) by reducing the amount of parasitic capacitance.
5.6 A 14-bit PRDEM DAC in 0.35 µm CMOS
DEM techniques that use randomization to reduce the harmonic distortion causedby component mismatch were presented in Sec. 4.1.3. In the PRDEM techniquethe degree of randomization is lower than in fully randomized DEM techniques,e.g., FRDEM, but the hardware cost is considerably lower. The design, simula-tion and measurement of a 14-bit PRDEM DAC is discussed in this section.
(a) (b)
(c) (d)
Figure 5.17 Single-tone full-scale measurements on 14-bit DAC in 0.35 µm CMOS. For (a)and (b) the update frequency is 5 MHz, and the signal frequencies are approxi-mately 0.63 MHz and 1.64 MHz, respectively. For (c) and (d) the update fre-quency is 20 MHz, and the signal frequencies are approximately 2.55 MHz and6.55 MHz, respectively.
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Comparisons between measurements and simulations using models of mismatchand dynamic errors discussed in Chapter 3 are presented, showing a good agree-ment between simulations and measurements.
5.6.1 Implementation
The PRDEM chip is constructed with four layers of switching. The control sig-nals for the switches are generated off-chip to allow flexibility. The switchingtree is terminated with DAC banks consisting of one 1-bit DAC and one 10-bitDAC, as was discussed in Sec. 4.1.3. The current sources and the currentswitches are both of PMOS type, and no cascodes have been used in the current
(a) (b)
(c) (d)
Figure 5.18 Single-tone, half-scale measurements on a 14-bit DAC in 0.35 µm CMOS. For(a) and (b) the update frequency is 5 MHz, and the signal frequencies areapproximately 0.63 MHz and 1.64 MHz, respectively. For (c) and (d) the updatefrequency is 20 MHz, and the signal frequencies are approximately 2.55 MHzand 6.55 MHz, respectively.
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A 14-bit PRDEM DAC in 0.35 µm CMOS
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sources. A description of the design strategy used is given in [76]. A chip photoof the PRDEM DAC is shown in Fig. 5.16. The core area of the chip is approxi-mately 6.3 mm2.
(a) (b)
Figure 5.19 SFDR vs. signal frequency for (a) full-scale signals and (b) half-scale signals.The upper curve in both figures correspond to the update frequency 5 MHz,whereas the lower curves correspond to the update frequency 20 MHz.
Figure 5.20 Chip photo of current-steering PRDEM DAC.
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5.6.2 Simulations and comparison with measurements
Comparisons between measurements and simulations of the PRDEM DAC arepresented in [34] and [35]. This section is a summary of these papers.
Simulation setup and results
In the simulations a Gaussian distributed error current with a standard deviationof approximately 10% has been added to each unit current source. This is a ratherlarge value but it includes all static errors in the DAC, e.g., mismatch betweencurrent sources, mismatch in biasing, gain errors between the DAC banks etc.The input is a full scale sinusoid with frequency and update fre-quency of . The single-ended output, terminated over 50 Ω, isexamined. The parameters used for the state-space model are given inTable 5.1.The output without randomization is shown in Fig. 5.21(a). The SFDR(60.2 dB) is limited by the third harmonic. When introducing switching in thefirst layer (Fig. 5.21(b)) the SFDR is increased to 67.7 dB, an improvement of7.5 dB corresponding to approximately one effective bit, to the cost of a some-what higher noise floor. The SFDR is now limited by the second harmonic. Whenintroducing switching in all four layers (Fig. 5.21(c)) we can see some smallerdifferences compared with Fig. 5.21(b) but the SFDR remains the same, hencewe do not gain any SFDR performance by having more than one switching layer.This can be explained by observing the second harmonic in Fig. 5.21(a), (b) and(c). The second harmonic is almost unaffected by the randomization, because itarises from dynamic errors in the DAC and as soon as the third harmonic, arisingfrom mismatch, is suppressed below the second harmonic we do not gain inSFDR performance by using DEM [69].
DAC model parameter Value
Unit current (nominal) 1.22 µA
Output resistance (unit current source) 1 GΩ
Output capacitance (unit current source) 10 fF
Switch resistance 200 Ω
Load resistance 50 Ω
Load capacitance 100 pF
Table 5.1 DAC model parameters used in the simulations.
f sig 1.25 MHz≈f u 10 MHz=
A 14-bit PRDEM DAC in 0.35 µm CMOS
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Measurement results
To verify the simulated results, the implemented DAC is measured with the sameupdate frequency, . In Fig. 5.22(a) and Fig. 5.22(b) we comparethe gain in performance between using no randomization and using one switch-ing layer. We find that the SFDR is increased from 60.7 to 67.7 dB, an improve-ment of 7.5 dB which could be predicted from the simulation results. Whenswitching all four layers (Fig. 5.22(c)) we do not gain much in SFDR perfor-mance compared with the results in Fig. 5.22(b).
Comparison of SFDR performance
To see how well the model works for different update frequencies, the simulatedresults were compared with measurement results from the real PRDEM DAC.The update frequency is swept while the ratio between signal frequency andupdate frequency, , is held constant. The simulated and measured
(a)
(b) (c)
Figure 5.21 Simulated spectra using 10MHz update frequency, (a) without randomization,with (b) one switching layer and (c) four layer switching.
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SFDR without randomization are compared in Fig. 5.23(a). The same compari-son with randomization is shown in Fig. 5.23(b). We find from Fig. 5.23(a) andFig. 5.23(b) that the simulated and measured results behaves similarly, which is agood validation of the models used in the simulations.
5.7 A dual 14-bit DAC in 0.25 µm CMOS
Design and measurement results of a 14-bit dual DAC implemented in a 0.25 µmCMOS process is presented in this section. The term dual indicates that twoDACs are implemented on the same chip. The chip can, e.g., be used for evalua-tion of the techniques presented in Sec. 4.2.1, or to realize a single switchinglayer PRDEM DAC.
(a)
(b) (c)
Figure 5.22 Measured spectra, 10MHz update frequency, (a) without randomization, with(b) one switching layer and (c) four layer switching.
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5.7.1 Architecture and implementation
The DAC has a doubly segmented architecture where both the seven LSBs andthe seven MSBs are converted into thermometer code controlling the currentswitches. A single PMOS transistor current source and PMOS current switchesare used. The circuit in Fig. 5.12 is used for generation of the switching signals.Distributed biasing (see Sec. 4.1.2) is used to achieve good matching properties.The current source arrays are divided into eight sub arrays having individuallocal bias circuits. The bias currents for the local bias circuits are generated witha global bias circuit consisting of a multiple output cascoded NMOS current mir-ror, which is shared between the two DACs to obtain good mutual matching. Aplot of the DAC chip is shown in Fig. 5.24.
Current source arrays and the binary-to-thermometer encoder described inSec. 5.3.1 are examples of regular circuit structures. The regularity has been uti-lized in this implementation for automated design. Some sub cells, like a currentsource, a switch and logic gates, have been designed by hand, whereas practicallyall other parts of the design have been based on scripts. This has greatly reducedthe time required for the design. Similar approaches are used by others [77].There is a trend of increased use of design automation for analog and mixed sig-nal circuits [78], which will likely continue in the future.
5.7.2 Measurement results
One reason for implementing two converters on the same chip is, as mentioned,to have a test chip for the techniques presented in Sec. 4.2.1. At this point, how-ever, the DACs have only been measured one at a time, mainly due to the lack ofproper test equipment. SFDR for full-scale signals is plotted as a function of sig-
(a) (b)
Figure 5.23 Simulated and measured SFDR performance for different update frequencieswith (a) no randomization, and (b) switching in all layers.
1 5 10 30
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nal frequency in Fig. 5.25. For the cases when the update frequency is 5 and10 MHz, SFDR is higher than 73 dB for a range of signal frequencies up to3 MHz. This can be regarded as a good result, even if an SFDR of at least 86 dBis required for 14 effective bits. The linearity is deteriorated when the update fre-quency is increased to 25 MHz. This phenomenon is not yet explained, andrequires more study.
A more adequate measure for DMT applications is the MTPR, which is definedin Sec. 2.3.2. For this purpose we use an ADSL-like input, which is quantizedvalues of
, (5.28)
Figure 5.24 Chip plot of the dual current-steering DAC.
X n( ) XDC K a j 2πnj ∆ f⋅
f u------------- φ j+
sin⋅j 1=
255
∑⋅+=
Summary of implemented DACs
105
where for and otherwise. The frequency spacingand the update frequency . The phases are
random and the scaling factor and the dc level are chosen such that thewhole input range of the DAC ( ) is used. The measured signal spec-trum is shown in Fig. 5.26. The MTPR, limited by the noise floor, is approxi-mately 71 dB. This is a good result, even compared with commercial DACs forDSL applications, e.g., AD9764 [33] from Analog Devices, Inc.
5.8 Summary of implemented DACs
The DAC implementations presented in this chapter are summarized in Table 5.2.The DAC with the highest performance is clearly the dual DAC presented inSec. 5.7. The modeling of nonideal behavior presented in Chapter 3 has providedan insight in what parameters are most important and allowed an improvementfrom one circuit implementation to the next.
Figure 5.25 Measured SFDR as a function of signal frequency.
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6 ConclusionsThe thesis covered selected topics in the areas modeling, error correction tech-niques and implementation of CMOS DACs. The main focus was on the linearityproperties of current-steering DACs for telecommunication applications.
The application of DACs in DSL environments was outlined. The requirementson high linearity in the DAC was illustrated by examining the influence of non-linear distortion on QAM constellations. The ideal DAC was presented, as wellas some performance measures commonly used for characterizing communica-tion DACs.
Different sources of nonlinear behavior in current-steering DACs were discussed.The static errors dominate the low-frequency behavior, whereas the high-fre-quency behavior is dominated by dynamic errors. Mismatch between circuit ele-ments is one of the main sources of static nonlinear behavior. An analysis of theinfluence of linearly graded matching errors on the performance of current-steer-ing DACs with a certain layout strategy was made. This layout strategy is knownto have poor properties when it comes to suppressing matching errors, but wasuseful in the example. The source of nonlinear behavior that was focused on inthis work was the parasitic capacitance in the transistors and the wires. The phe-nomenon was first modeled with a state-space model in Matlab. Results fromsimulations using this model were presented to illustrate the effect of the noni-deal components included in the model. A model with relatively low computa-tional complexity was developed. This model is suitable for on-chipimplementation for use in error correction/compensation techniques.
Various methods for improving the linearity of DACs were discussed. Some ofthe methods, like DEM and the differential DAC architecture, rely on redundantcoding to improve the linearity. In DEM the distortion caused by mismatch is, insome sense, transformed into noise. To gain in the overall SNDR, oversampling
Conclusions
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and filtering of out-of-band noise are required. Other methods, like distributedbiasing and a proposed calibration technique, aim at reducing the mismatchbetween the output currents from the current sources. Two ideas utilizing modelsof the dynamic nonlinearity caused by nonzero output capacitance in the currentsources were proposed. Both ideas aimed for enhanced linearity at higher signalfrequencies. The first method utilized a feedback loop similar to delta-sigmamodulation, and was denoted distortion shaping. The second method was a typeof predistortion. The simulations showed promising results, and an initial mea-surement of the distortion shaping method indicates that the models used aregood enough to be practically useful. More measurements, and possibly modelmodifications, are, however, required to draw any further conclusions.
Three different implementations of current-steering DACs in CMOS were pre-sented. The required building blocks were discussed separately, and overalldesign considerations were presented. The first two DACs were fabricated in a0.35 µm CMOS process. One of these DACs utilizes the PRDEM technique forenhanced static linearity. The third converter was fabricated in a 0.25 µm CMOSprocess. Distributed biasing of current sources was used in this implementationto reduce the matching errors between the current sources. Knowledge from thebehavioral level modeling was utilized to improve the performance from one cir-cuit implementation to the next. Measurement results show close resemblancewith the simulation results using the behavioral level models presented in thisthesis. The simulations and measurements on the PRDEM DAC are especiallyinteresting, since they illustrate the limited efficiency of DEM when dynamicerrors dominate, besides validating the behavioral level modeling.
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References[1] T. Starr, J.M. Cioffi, and P.J. Silverman, Understanding Digital
Subscriber Line Technology, Prentice Hall PTR, Upper Saddle River, NJ,USA, 1999, ISBN 0-13-780545-4.
[2] W.Y. Chen, DSL Simulation Techniques and Standards Development forDigital Subscriber Line Systems, Macmillan Technical Publishing,Indianapolis, IN, USA, 1998, ISBN 1-57870-017-5.
[3] D.J. Rauschmayer, ADSL/VDSL Principles, Macmillan TechnicalPublishing, Indianapolis, IN, USA, 1999, ISBN 1-57870-015-9.
[4] S. Haykin, Communication Systems, 4th Ed., John Wiley & Sons, NewYork, NY, USA, 2001, ISBN 0-471-17869-1.
[6] L. Wanhammar, DSP Integrated Circuits, Academic Press, San Diego, CA,USA, 1999, ISBN 0-12-734530-2.
[7] M. Gustavsson, J.J. Wikner, and N. Tan, CMOS Dataconverters forCommunications, Kluwer Academic Publishers, Boston, MA, USA, 2000,ISBN 0-7923-7780-X.
[8] D.A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley& Sons, New York, NY, USA, 1997, ISBN 0-471-14448-7.
[9] R.J. van de Plassche, Integrated Analog-to-Digital and Digital-to-AnalogConverters, Kluwer Academic Publishers, Boston, MA, USA, 1994,ISBN 0-7923-9436-4.
110
[10] P. Hendricks, “Specifying communication DACs,” IEEE Spectr., vol. 34,no. 7, pp. 58-69, Jul. 1997.
[11] Defining and Testing Dynamic Parameters in High-Speed ADCs, Part 1,Maxim Integrated Products, Inc. [Online]. Available: http://dbserv.maxim-ic.com/tarticle/view_article.cfm?article_id=111.
[12] M. Schetzen, The Volterra and Wiener Theories of Nonlinear Systems,Krieger Publishing Company, Malabar, FL, USA, 1989, ISBN 0-89464-356-8.
[13] P. Wambaq and W. Sansen, Distortion Analysis of Analog IntegratedCircuits, Kluwer Academic Publishers, Boston, MA, USA, 1998, ISBN 0-7923-8186-6.
[14] B.G. Streetman, Solid State Electronic Devices, Prentice-Hall, EnglewoodCliffs, NJ, USA, 1995, ISBN 0-13-436379-5.
[15] M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, “Matchingproperties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5,pp. 1433-1439, Oct. 1989.
[16] A. Van den Bosch, M. Steyaert, and W. Sansen, “An accurate statisticalyield model for CMOS current-steering D/A converters,” Proc IEEEInternational Symposium on Circuits and Systems (ISCAS’00), vol. 4,pp. 105-108, Geneva, Switzerland, May 28-30, 2000.
[17] M.J.M. Pelgrom, H.P. Tuinhout, and M. Vertregt, “Transistor matching inanalog CMOS applications,” Proc. 1998 International Electron DevicesMeeting, pp. 915-918, 1996.
[18] A. Van den Bosch, M. Steyaert, and W. Sansen, “The extraction oftransistor mismatch parameters: the CMOS current-steering D/A converteras a test structure,” Proc IEEE International Symposium on Circuits andSystems (ISCAS’00), vol. 2, pp. 745-748, Geneva, Switzerland, May 28-30,2000.
[19] H. Tuinhout, M. Pelgrom, R. Penning de Vries, and M. Vertregt, “Effectsof metal coverage on MOSFET matching,” Proc. 1996 InternationalElectron Devices Meeting, pp. 735-738, 1996.
[20] K.O. Andersson and J.J. Wikner, “Modeling of the influence of gradedelement matching errors in CMOS current-steering DACs,” Proc.NORCHIP Conference, pp. 399-404, Oslo, Norway, Nov. 8-9, 1999.
111
[21] G.A.M. Van der Plas, J. Vandenbussche, W. Sansen, M.S.J. Steyaert, andG. Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,”IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1708-1718, Dec. 1999.
[23] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, “A 10-b70-MS/s CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 26,no. 4, pp. 637-642, Apr. 1991.
[24] I. Galton, “Spectral shaping of circuit errors in digital-to-analogconverters,” IEEE Trans. Circuits Syst. II, vol. 44, no. 10, pp. 808-817,Oct. 1997.
[25] J.J. Wikner and N. Tan, “Modeling of CMOS digital-to-analog convertersfor telecommunication,” IEEE Trans. Circuits Syst. II, vol. 46, no. 5,pp. 489-499, May 1999.
[26] J.J. Wikner, CMOS Digital-to-Analog Converters for TelecommunicationApplications, Linköping studies in science and technology, Thesis No. 715,ISBN 91-7219-277-1, Linköping, Aug., 1998.
[27] A. Van den Bosch, M. Steyaert, and W. Sansen, “SFDR-bandwidthlimitations for high speed high resolution current steering CMOS D/Aconverters,” Proc. IEEE International Conference on Electronics, Circuits,and Systems (ICECS’99), pp. 1193-1196, 1999.
[28] K.O. Andersson and J.J. Wikner, “Characterization of a CMOS current-steering DAC using state-space models,” Proc. 43rd Midwest Symposiumon Circuits and Systems (MWSCAS’00), pp. 668-671, Lansing, MI, USA,Aug. 8-11, 2000.
[29] H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI,Addison-Wesley, USA, 1990, ISBN 0-201-06008-6.
[30] L. Ljung, System Identification, Theory for the User, Prentice-Hall, UpperSadle River, NJ, USA, 1999, ISBN 0-13-656695-2.
[31] Control Systems Toolbox for use with Matlab - Reference Version 5,Mathworks Inc., 2001, [Online]. Available: http://www.mathworks.com/access/helpdesk/help/toolbox/control/control.shtml.
[32] A. Bugeja and B.S. Song, “A self-trimming 14-b 100-MS/s CMOS DAC,”IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1841-1852, Dec. 1999.
112
[33] AD9764, Datasheet, Analog Devices, Norwood, MA, USA, 1999.
[34] N.U. Andersson, K.O. Andersson, J.J. Wikner, and M. Vesterbacka,“Models and implementation of a dynamic element matching DAC,” toappear in Kluwer International Journal of Analog Integrated Circuits andSignal Processing, Special Issue: Selected Papers from the NORCHIP2001 Conference.
[35] N.U. Andersson, K.O. Andersson, J.J. Wikner, and M. Vesterbacka,“Models and implementation of a dynamic element matching DAC,” Proc.NORCHIP Conference, pp. 155-160, Kista, Sweden, Nov. 12-13, 2001.
[37] D.W.J. Groeneveld and H.J. Schouwenaars, “A dual 3.4V bitstreamcontinuous calibration CMOS D/A converter with 110 dB dynamic range,”Proc. 2nd IEE International Conference on Advanced A/D and D/AConversion Techniques and their Applications, pp. 42-47, 1994.
[38] C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,”IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948-58, Dec. 1998.
[39] M.K. Rudberg, M. Vesterbacka, N. Andersson, J.J. Wikner, “GlitchMinimization and Dynamic Element Matching in D/A Converters”, Proc.IEEE International Conference on Electronics, Circuits, and Systems(ICECS’01), Beirut, Lebanon, Dec. 17-20, 2000.
[40] M. Vesterbacka, M.K. Rudberg, J.J. Wikner, and N.U. Andersson,“Dynamic Element Matching in D/A Converters with RestrictedScrambling,” Proc. IEEE International Conference on Electronics,Circuits, and Systems (ICECS’01), Beirut, Lebanon, Dec. 17-20, 2000.
[41] J.W. Bruce and P. Stubberud, “A comparison of hardware efficientdynamic element matching networks for digital to analog converters,”Proc. 43rd Midwest Symposium on Circuits and Systems (MWSCAS’00),pp. 672-675, Lansing, MI, USA, Aug. 8-11, 2000.
[42] H.T. Jensen and I. Galton, “An analysis of the partial randomizationdynamic element matching technique,” IEEE Trans. Circuits Syst. II,vol. 45, no. 12, pp. 1538-1549, Dec. 1998.
[43] P. Stubberud and J.W. Bruce, “An analysis of dynamic element matchingflash digital-to-analog converters,” IEEE Trans Circuits Syst. II, vol. 48,no. 2, Feb. 2001.
113
[44] N.U. Andersson and J.J. Wikner, “A comparison of dynamic elementmatching in DACs,” Proc. NORCHIP Conference, pp. 385-390, Oslo,Norway, Nov. 8-9, 1999.
[45] J. Steensgaard, “High-resolution mismatch-shaping digital-to-analogconverters,” Proc. IEEE International Symposium on Circuits and Systems(ISCAS’01), vol. 1, pp. 516-519, Sydney, Australia, May 6-9, 2001.
[46] U.K. Moon, G.C. Temes, and J. Steensgaard, “Digital techniques forimproving the accuracy of data converters,” IEEE Commun. Mag., vol. 37,no. 10, pp. 136-143, Oct. 1999.
[47] J. Steensgaard, U.-K. Moon, and G.C. Temes, “Mismatch-shaping serialdigital-to-analog converter,” Proc IEEE International Symposium onCircuits and Systems (ISCAS’99), vol. 2, pp. 5-8, Orlando, FL, USA, Jun.1999.
[48] R.E. Radke, A. Eshraghi, and T.S. Fiez, “A 14-bit current-mode ∆Σ DACbased upon rotated data weighted averaging,” IEEE J. Solid-State Circuits,vol. 35, no. 8, pp. 1074-1084, Aug. 2000.
[49] A. Bugeja and B.S. Song, “A 14-b 100-MS/s CMOS DAC designed forspectral performance,” IEEE J. Solid-State Circuits, vol. 35, no. 12,pp. 1841-1852, Dec. 2000.
[50] M. Waltari, J. Pirkkalaniemi, M. Kosunen, L. Sumanen, and K. Halonen,“A 14-bit, 40 MS/s DAC with current mode deglitcher,” Proc. NORCHIPConference, pp. 242-247, Kista, Sweden, Nov. 12-13, 2001.
[51] R.M. Gray and T.G. Stockham Jr., “Dithered quantizers,” IEEE Trans.Inform. Theory, vol. 39, no. 3, pp. 805-812, May 1993.
[52] B. Brannon, Overcoming Converter Nonlinearities with Dither,Application Note AN-410, Analog Devices, Norwood, MA, USA.
[53] K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner, “Adifferential DAC architecture with variable common-mode level,” Proc.IEEE International Symposium on Circuits and Systems (ISCAS’02),vol. 1, pp. 113-116,Scottsdale, AZ, USA, May 26-29, 2002.
[54] K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner,“Combining DACs for improved performance,” Proc. 4th IEEInternational Conference on Advanced A/D and D/A ConversionTechniques and their Applications, Prague, Czech Republic, June 26-28,2002.
114
[55] K.O. Andersson, “Current Steering DAC,” pending Swedish patent, 2001.
[56] K.O. Andersson, N.U. Andersson, and J.J. Wikner, “Spectral shaping ofDAC nonlinearity errors through modulation of expected errors,” Proc.IEEE International Symposium on Circuits and Systems (ISCAS’01),vol. 3, pp. 417-420, Sydney, Australia, May 6-9, 2001.
[57] D. Anastassiou, “Error diffusion coding for A/D conversion,” IEEE Trans.Circuits Syst., vol. 36, no. 9, pp. 1175-1186, Sep. 1989.
[58] R. Schreier and Y. Yang, “Stability tests for single-bit sigma-deltamodulators with second-order FIR noise transfer functions,” Proc. IEEEInternational Symposium on Circuits and Systems (ISCAS’92), vol. 3,pp. 1316-1319, 1992.
[59] K. Morris and P. Kennington, “Power amplifier linearisation usingpredistortion techniques,” IEE Colloquium on RF and MicrowaveComponents for Communication Systems, Digest no. 1997/126, pp. 6/1-6/6, 1997.
[60] S. Andreoli, H.G. McGLure, P. Banelli, and S. Cacopardi “Digitallinearizer for RF amplifiers,” IEEE Trans. Broadcast., vol. 43, no. 1,pp. 12-19, Mar. 1997.
[61] H.W. Kang, Y.S. CHo, and D.H. Youn, “On compensating nonlineardistortions of an OFDM system using an efficient adaptive predistorter,”IEEE Trans. Commun., vol. 47, no. 4, pp. 522-526, Apr. 1999.
[62] K.J. Riley, D.M. Hummels, F.H. Irons, and A. Rundell, “Dynamiccompensation of digital to analog converters,” Proc. 16th IEEEInstrumentation and Measurement Technology Conference (IMTC’99),vol. 2, pp. 1310-1315, 1999.
[63] K.O. Andersson and J.J. Wikner, “Digital-to-analog converter having errorcorrection,” pending Swedish patent, 2002.
[64] J.M. Rabaey, Digital Integrated Circuits - a Design Perspective, Prentice-Hall, Upper Saddle River, NJ, USA, 1996, ISBN 0-13-394271-6.
[65] N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design aSystems Perspective, Addison-Wesley, USA, 1993, ISBN 0-201-53376-6.
[66] S.M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits Analysisand Design, McGraw-Hill, USA, 1996, ISBN 0-07-038046-5.
115
[67] J.J. Wikner and M. Vesterbacka, “D/A conversion with linear-codedweights,” Proc. 2000 IEEE Southwest Symposium on Mixed-Signal Design(SSMSD’00), pp. 61-66, San Diego, CA, USA, Feb. 28-29, 2000.
[68] M. Vesterbacka, K.O. Andersson, N.U. Andersson, and J.J. Wikner,“Using different weights in DACs,” Proc. 4th IEE InternationalConference on Advanced A/D and D/A Conversion Techniques and theirApplications, Prague, Czech Republic, June 26-28, 2002.
[69] J.J. Wikner, Studies on CMOS Digital-to-Analog Converters, Linköpingstudies in science and technology, dissertation no. 667, ISBN 91-7219-910-5, Linköping, Sweden, Apr. 2000.
[70] A. Van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, “A 10-bit1-GSample/s current-steering CMOS D/A converter,” IEEE J. Solid-StateCircuits, vol. 6, no. 3, pp. 315-324, Mar. 2001.
[71] K. Skahill, VHDL for Programmable Logic, Addison-Wesley, USA, 1996,ISBN 0-201-89573-0.
[72] J. Bastos, A.M. Marques, M.S.J. Steyaert, W. Sansen, “A 12-bit intrinsicaccuracy high-speed CMOS DAC,” IEEE J. Solid-State Circuits, vol. 33,no. 12, pp. 1959-1969, Dec. 1998.
[73] K. Bernstein, et. al., High Speed CMOS Design Styles, Kluwer AcademicPublishers, Kluwer Academic Publishers, Boston, MA, USA, 1999,ISBN 0-7923-8220-X.
[74] X. Aragones, J.L. Gonzalez, and A. Rubio, Analysis and Solutions forSwitching Noise Coupling in Mixed-Signal ICs, Kluwer AcademicPublishers, Boston, MA, USA, 1999, ISBN 0-7923-8504-7.
[75] O. Andersson, Mismatch Modeling and Design of CMOS Current-SteeringDigital-to-Analog Converters, M.Sc. thesis, Linköping, Nov., 1999.
[76] N.U. Andersson and J.J. Wikner, “A Strategy of Implementing DynamicElement Matching in Current-Steering DACs,” Proc. 2000 IEEESouthwest Symposium on Mixed-Signal Design (SSMSD’00), pp. 51-56,San Diego, CA, USA, Feb. 28-29, 2000.
[77] J. Vandenbussche, G. Van der Plas, W. Daems, A. Van den Bosch,G. Gielen, M. Steyaert, and W. Sansen, “Systematic design of high-accuracy current-steering D/A converter macrocells for integrated VLSIsystems,” IEEE Trans. Circuits Syst II, vol. 48, no. 3, pp. 300-309, Mar.2001.
116
[78] G.E.G. Gielen, “New methods and tool for analog IP use in mixed-signalintegrated systems,” Proc. NORCHIP Conference, pp. 5-9, Kista, Sweden,Nov. 12-13, 2001.
Systematic Design of a 14-bit 150-MS/s CMOS Current-Steering D/A Converter
G. Van der Plas, J. Vandenbussche, W. Daems, A. Van den Bosch, G. Gielen*, M. Steyaert, W. Sansen
Department of Electrical Engineering, Katholieke Universiteit Leuven, ESAT-MICAS Kardinaal Mercierlaan 94, 3001 Heverlee, Belgium
* research associate of the National Fund of Scientific Research (Belgium)
Abstract
This paper presents a D/A converter with a 14-bit in-trinsic linearity in 0.5µm CMOS technology, which has been designed using a systematic design methodology for current-steering D/A converters. A flexible architec-ture is proposed for which the design parameters are calculated using a performance-driven top-down design methodology. The layout of the regular structures typi-cal for D/A converters is automatically generated. Measurement results are reported. Due to the system-atic design methodology, the design was realized in less than one month total accumulated person effort.
I Introduction In this paper the design methodology and the design of a complete current-steering D/A converter implemented in a standard 0.5µm CMOS technology, is presented. This is the first publicly reported CMOS D/A converter with 14-bit intrinsic linearity, achieved without trimming or tuning [1]. The D/A converter has been de-signed according to a systematic design methodology which al-lows to generate new designs for given specifications, or to easily port designs to new processes. The design methodology covers the complete design flow and is supported by both commercial and in-house developed academic software tools to speed up the task significantly. Design times of less than one month total ac-cumulated person effort are obtained. The inputs are the specifica-tions of the D/A converter and the technology and the result is a verified layout.
This paper is organized as follows. In section II the architecture of the D/A converter and its design parameters are described. Sec-tion III explains the proposed systematic design methodology. The sizing synthesis is explained to its full extent in section IV. Section V describes the layout generation process. Section VI presents the experimental results and measurements of the im-plemented design. Conclusions are given in section VII.
II Current-steering D/A Converter Architecture For high-speed, high-accuracy D/A converters, a segmented cur-rent-steering topology is usually chosen as it is intrinsically faster and more linear than competing architectures [2]. The principle of this type of D/A converter is depicted in Fig. 1: the l least signifi-cant bits are binary implemented, the m most significant bits steer a unary current source array.
VDD
t1
IMSB
t0
IMSB
t2
IMSB
t3
IMSB
t5
IMSB
t4
IMSB
t6
IMSB
t7
IMSB
t8
IMSB
t251
IMSB
t253
IMSB
t252
IMSB
t254
IMSB
b1
2ILSB
b0
ILSB
b2
4ILSB
THERMOMETER
DECODER
b6
b7
b8
b9
t0
t1
t2
t3
t251
t252
t253
t254binary weighted
current cells
unary current cells
b10
b11
b12
b13
... ...
t4
t5t6
t7
b4
16ILSB
b3
8ILSB
b5
32ILSB
Fig. 1: Simplified block diagram of a 14-bit segmented current-steering
D/A converter. The l (=6) least significant bits steer the binary weighted current sources directly. The m (=8) most significant bits are fed into the thermometer decoder, which steers the unary current source array
Specification Unit Value
Static Number of bits (n) - 14 INL LSB 0.5 DNL LSB 0.5 Parametric Yield % 99.9
Dynamic Sample frequency MHz 100 SFDR@500kHz dB 80 Settling time ns 10
Environmental Output range (Vswing) V 0.5 RLoad Ω 25 Digital levels - CMOS Power Supply V 2.7 Technology - 0.5µ 1P3M
Optimization Power Consumption mW Minimize (300) Area mm2 Minimize (10)
Table 1: General specification list for a current-steering D/A converter with typical values.
Permission to make digital/hardcopy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC 2000, Los Angeles, California (c) 2000 ACM 1 -58113-188-7/00/0006..$5.00
The general specification list for a current-steering D/A converter is given in Table 1. The specifications can be divided into four categories: static, dynamic, environmental and optimization specifications. In the case of a D/A converter the static parameters include static accuracy (i.e. number of bits), integral non-linearity (INL), differential non-linearity (DNL) and yield. The dynamic parameters include sample frequency, spurious free dy-namic range (SFDR) and settling time. The environmental pa-rameters include the power supply, the digital levels, the output load and the input/output range. The power consumption and area need to be minimized for the specified technology. This specifica-tion list serves as input for the design process as will be explained in the following sections.
In the next paragraphs the proposed D/A converter architecture and its design parameters will be presented in detail.
Thermometer decoder Latency equaliser
b0b1b4b5b6b7b8b9b10b11
Full Decoder
Swatch Array
Current Source Array
Iout
Clock driver
1...255 1...6
255 6
b12b13 ...
Iout
Binary latch & switches
Binarycurrent src
array
un bin
M1
VSScur_src
M2a2b
VDDcur_src
Iout
Iout
Unary current source array
Unary latches & switches
Fig. 2: The block diagram and floorplan of the proposed architecture.
The simplified block diagram of Fig. 1 has been implemented by the proposed segmented architecture shown in Fig. 2. The current generated by the current sources (M1) are switched to one of the two differential output nodes of switch transistors M2a and M2b. These are driven by a latch. The full decoder comprises the ther-mometer decoder, which generates the steering signals for the unary latches, and a latency equalizer block. This latency equal-izer block ensures correct timing for the steering signals of the binary latches. One of the important architectural design parame-ters is how many bits are implemented with binary weighted cur-rent sources and how many with unary weighted current sources.
The floorplan of the presented architecture is also shown in Fig. 2. The switches and latches are implemented as one unit cell, and placed in an array, referred to as the “swatch” array. The current source transistors are also placed in an array, the current source array. The three large modules (full decoder, swatch array and current source array) are connected by signal busses. A clock driver completes the D/A converter.
(a) (b) (c) Fig. 3: Three different switching schemes:
(a) unary current source implemented as 1 unit (b) unary current source implemented as 4 units in parallel (c) unary current source implemented as 16 units in parallel
The last important architectural design parameter of a current-steering D/A converter is the switching scheme. The switching scheme has two components. A unary current source can be split in one or more units, as shown in Fig. 3. By splitting the unary current source the spatial errors are averaged out, which is neces-sary for high-accuracy applications [3,4]. The second parameter of the switching scheme is the switching sequence. In [5] it is shown that the remaining spatial errors are not accumulating when the current sources are switched on in an optimal order when the input code increases. The here proposed architecture differs from previously used architectures in that the switching is fully flexible and can be programmed when generating the layout to optimally compensate for systematic errors which would otherwise deterio-rate the targeted linearity.
The designable parameters of the presented D/A converter are summarized in Table 2. They have been classified in architecture level parameters and circuit level parameters
Design parameters of the converter
Architecture level l (number of LSBs) m (number of MSBs) Number of units (1/4/16 units) for unary current
Table 2: The designable parameters of the presented D/A converter.
III Systematic Design Methodology The performance-driven top-down design methodology has been accepted as the de facto standard for systematically designing analog building blocks in academia [6,7]. In [8] the design of current-steering D/A converters has been automated following this methodology for a specific architecture which is however only feasible for 8 or 10-bit D/A converters.
SizingArchitectural level
Verification
Verification
SizingDevice level
Floorplanning
VerificationVerification
LayoutModule & Device level
Layout Assembly & Verification
Synthesis
Standard cellPlace & route
Verification
Analog Digital
Fig. 4: Presented systematic design flow for a current-steering D/A con-
verter
The design flow, shown in Fig. 4, presents the design methodol-ogy that we applied to the design of a high-accuracy D/A con-verter. It is a mixed-signal design. The analog design flow is grouped on the left, the corresponding digital flow is grouped on the right. The analog flow starts with a sizing at two levels: the architectural-level and the device level. The digital logic synthesis completes the sizing of the mixed-signal design. These topics will be explained in detail in section IV. The design steps are verified using classical approaches: numerical verification with a simula-tor, at the behavioral, device respectively gate level. The floor-planning is done jointly for analog and digital blocks, after which the analog layout is generated, and standard cell place & route is used to create the digital layout. Both layouts are separately veri-fied. The blocks are assembled at the chip-level and again a chip-level verification is done with industry standard tools.
The remainder of the paper focuses on the sizing synthesis and layout generation steps in the systematic design flow. Measure-ment results of a fabricated design will be presented afterwards.
IV Sizing Synthesis
A. Architectural-level synthesis
The architectural-level parameters are determined during architec-tural-level sizing synthesis. These have to be optimized such that the two important performance criteria, as listed in Table 1 (static and dynamic performance) are met while minimizing chip area and power consumption.
Static performance
The static behavior of a D/A converter is specified in terms of INL and DNL. A distinction has to be made between random errors and systematic errors. The random errors are determined solely by mismatch. The systematic errors are caused by process, temperature and electrical gradients. In optimally designed D/A converters the INL and DNL are determined by random errors (i.e. mismatch) only which are related to the device sizes. A small safety margin (10 % of INL) is reserved to allow for systematic contributions. The systematic errors are dependent on the layout and are minimized, among others, by optimizing the switching scheme. This also generates constraints for the layout process (as explained in section V).
Any gradient on chip (be it caused by process, thermal or electri-cal effects) creates a systematic deviation over the current sources in the large current source array. In order to compensate this, every current source can be split in a parallel connection of smaller transistors spread over the array (see Fig. 3). In this way the average currents for all current sources are closer to each other. This splitting of the unary current source is required for 12 or 14-bit intrinsic linearity and beyond [3,4]. At least a value of 4 for number of units (Table 2) is required for 12-bit linearity and a value 16 units for 14-bit in the used technology.
But even with this splitting there are remaining current differ-ences. The switching sequence is therefore optimized to reduce the accumulation of remaining systematic errors. A branch and bound search algorithm has been used to determine the switching order of the allocated current sources so that the errors do not accumulate but are “randomized” (i.e. compensate each other as much as possible). The result is shown in Fig. 5. On the left a traditionally used manually derived switching sequence has been simulated. With the same spatial error profiles but an optimal (smallest INL) computer generated switching scheme the remain-ing systematic errors don’t accumulate anymore, resulting in an
INL of 0.2 LSB instead of 2.1 LSB. The search algorithm has been implemented in a C program.
Fig. 5: Prediction of the INL obtained with two different switching se-
quences. On the left a manually derived (sub-optimal) switching sequence, on the right the optimized switching sequence (random walk). The same error profile (extracted from a test chip) has been applied.
Dynamic performance
The dynamic behavior of a D/A converter is usually specified in terms of spurious free dynamic range (SFDR). This specification is mainly determined by (1) the number of bits implemented unary/binary [9] and (2) the way the current sources are synchro-nized when switched on/off. This implies that the decision on the number of bits l to be implemented binary and the number of bits m to be implemented unary determines the SFDR: more segmen-tation (higher m) results in a better SFDR performance [9]. The synchronization of the switching signals is achieved by using a clocked latch to derive the steering signals for the switches.
Fig. 6: Estimated area of the D/A converter in function of number of unary
bits (m).
The highest possible SFDR is obtained when a full unary imple-mentation is chosen [9]. This would however result in a large area increase. The total chip area is estimated by:
area area area
area l m area l m
total est cur src swatch
decoder routing
_ _
( , ) ( , )
= +
+ + (1)
The area of the current source array is fixed (see below) as is the area of the swatch array by the required linearity constraints. However, the area of the decoder increases (2m), as does the size of the routing busses connecting the three modules, if the number of unary bits is increased. Fig. 6 shows that in current technolo-gies an optimal number of unary implemented bits is 8, otherwise the area becomes unacceptable. This choice will ultimately limit the dynamic performance of the D/A converter.
In this way all architectural-level parameters of the converter have been determined (see Table 3) for the specifications of Table 1.
B. Circuit level synthesis
The circuit level synthesis determines the circuit level design pa-rameters, these are the sizing and biasing of the current source, and the sizing of the latch and switches. Again the two perform-ance constraints (static and dynamic) are taken into account.
Static Performance
The active area of the unit current source array is calculated from mismatch constraints.
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.510
20
30
40
50
60
70
80
90
100
Yie
ld [%
]
σ(I)/I [%] Fig. 7: Yield as a function of unit current cell variance for a 14-bit D/A
converter (INL < 0.5LSB).
The acceptable random current error can be calculated from yield simulations. The tolerable relative standard deviation of current matching (σ(I)/I) can thus be calculated [10]. Fig. 7 depicts the yield simulation for a 14-bit D/A converter: to achieve a targeted yield of 99% (INL < 0.5LSB), the relative standard deviation of current matching for the unit current cell (1 LSB) has to be smaller than 0.1%. The plot shown in Fig. 7 has been calculated using a Matlab program.
From the required full swing (Vswing), the number of bits (n) and the load resistance (Rload) the current of one LSB (ILSB) is calcu-lated:
IV
RLSB
swing
Loadn
=2
(2)
An estimate can then be calculated for the active area of the cur-rent source transistor according to the used mismatch model [11] and the derived current matching:
W LI
I
AA
V VVT
GS T
∗ = +−
1
2
42
2
22
2σ β( ) ( ) (3)
where σ(I)/I is the derived unit current source standard deviation and Aβ , AVT are technology constants [11]. For minimal area the Vgs-Vt is maximized.
The lower bound for the area is given by:
( )W LI
I
Aest∗ ≈1
2 2
2
2
σ β( ) (4)
The total current source array area is then estimated to be at least:
routingest
nsrccur fLWarea )(2_ ∗≈ (5)
where frouting is the routing overhead factor. The static perform-ance places a strict constraint on the minimal area of the current source array.
The upper limit for the biasing voltage is determined by the output swing (switching transistors M2 need to be in saturation region) and the power supply. From equation (2) and (3), W1 and L1 can be calculated for a choice of Vgs-Vt.
These calculations resulting in the sizing of the current source transistors (M1) have been automated in a Matlab script. For a 14-bit converter this gives a W/L=1.1µm/104.5µm in a standard 0.5µm CMOS technology.
Dynamic performance
In order not to deteriorate the dynamic performance, the following factors are taken into account in the circuit level synthesis [12]: (1) synchronize the control signals of the switching transistors, (2) reduce voltage fluctuations in the drains of the current sources, (3) carefully switch the current source transistor on/off. The synchro-nization of the control signals is achieved by adding a latch im-mediately in front of the switching transistors M2. The voltage fluctuation at the drain changes the current from the current source because of the finite output impedance of the current source transistor M1. The problem can be solved by using a large channel length for the current source transistor, and tuning the crossing point of the switching control signals such that both switches are never switched off simultaneously [4].
Using a simulator (Hspice) in an optimization loop, the latch and the switches have been sized, taking the crossing point and speed as constraints in the optimization process.
C. Decoder Synthesis
Since the architectural design parameters (l, m) and the latch tran-sistor sizes are known, the thermometer decoder can then be syn-thesized. The remaining l LSBs are delayed by the equalizer block. The digital decoder has been synthesized using logic syn-thesis from a VHDL description.
D. Clock Driver Synthesis
The clock driver generates the clocking signals for the decoder and swatch array. Both these blocks have been sized and thus the load is known. An invertor chain has been designed to drive this load.
Design parameters of the architecture
Architecture level 6 (number of LSBs) 8 (number of MSBs) 16, Quad Quadrant [1] (number of units) Random Walk [1] (INL optimized
Table 3: The sized values of the designable parameters of the proposed D/A converter architecture.
E. Sizing Result
In Table 3 the final sizing results are summarized for the specifi-cations of Table 1.
V Layout Generation Current-steering D/A converters are a typical example of layout-driven analog design. The sized schematic alone does not consti-tute an operational converter. An important part of the perform-ance is determined by the handling of layout-induced parasitics and error components (i.e. systematic errors). All classical coun-termeasures for digital to analog coupling (guard rings, shielding, separate supplies, …), and matching guidelines (equal orientation, dummies, …) have been applied and will not be further discussed.
A. Floorplanning
The floorplan proposed in Fig. 2 is now refined. The relative placement of the modules (full decoder, swatch array, current source array) was already fixed and the actual sizes (area) of the modules are readily available. However the aspect ratio is still to be determined. First of all the global aspect ratio influences the aspect ratio of the modules. In general a square or near square chip layout is preferred. Secondly, at the chip-level the connec-tions between the modules are extremely important: a fixed pitch for the three modules must be chosen to route the busses between the different modules to avoid wiring area loss. Furthermore, the choice of the chip-level pitch also ensures that the modules will have the same width, resulting in an elegant chip assembly as can be seen in Fig. 9.
B. Circuit and Module Layout Generation
The current source cell array, swatch cell array and full decoder are generated next.
Current Source Layout Generation
The sizes of the unit current source have been determined. From this the sizes of all other weighted current sources and the unary current source are derived. To have optimal matching properties the current source must be built up from identical basic units. This basic unit is manually laid out. Also the floorplan of the current source array is determined (number of units, switching sequence).
contactarea
YX-Y
Fig. 8: Symbolic view of cells and routing channels: vertical (Y) routing
across cells, horizontal (X) routing in between cells. Vertical wires connect to the contact areas in the cell, horizontal wires connect to the vertical wires.
The placement of the basic units is thus determined. The current source array is then generated automatically with the Mondriaan tool [13]. The Mondriaan tool is targeted to the automated layout generation of highly regular array-type analog modules. Fig. 8 shows a symbolic view of the layout structures that Mondriaan generates. The basic cell of the array is tiled, optionally flipped horizontally or vertically. The connectivity inside the array and to the outside world is realized through abutment (for power distri-bution, biasing, clock distribution, …) and by X/Y bus routing. The Y bus routing connects wires to the contact areas defined inside the basic cell’s boundary, the X routing connects the Y
wires. The connection pattern has to be entered in a C-like format, and the tool automatically generates the actual physical layout.
The current source unit is the basic cell in our case. It is placed in a regular array and the parallel units are connected with the de-scribed bus routing. In total over 4000 units are placed and con-nected with more than 1000 wires. Doing this task manually is impossible. The CPU time of Mondriaan on a standard SUN Ul-tra I-166 workstation is less than 2 minutes (including the transfer to a commercial EDA framework). The result is a layout and a pin list, which serves as input to the swatch array layout generation.
Swatch Array Layout Generation
One swatch cell has been manually laid out. The placement and routing of the swatch array is then done automatically with the Mondriaan tool [13]. Inputs to the tool are the pin list of the cur-rent source array, the netlist and the swatch cell layout. From this the placement of the cells is derived and the routing created. The output is the layout and a pin list of the bus for the steering signals coming from the decoder.
Decoder Standard Cell Place and Route
The layout of the digital decoder is generated using a standard cell place and route tool, i.e. the tools from Avant!. The pin list ob-tained from the swatch array layout is input to the floorplan for the layout generation.
C. Layout Assembly
The modules are placed stacked on top of each other. The bus generators of the Mondriaan tool [13] are used to generate the actual connections between the three modules (full decoder, swatch and current source array). Trees are used to collect the output signals and distribute the clocking signal from the clock driver to the swatch array to have equal delay.
Fig. 9: Layout of the 14-bit segmented current-steering D/A converter.
The bonding pads are placed and manually connected to all the external pins of the D/A converter.
With this approach the 14-bit D/A converter has been laid out. This layout is shown on the microphotograph in Fig. 9. DRC and LVS checking was done to verify the generated layout. Parasitics were extracted and the sizing was verified using Hspice.
Fig. 10: Measurement setup of the 14-bit D/A converter.
VI Experimental Results A 14-bit D/A converter was implemented in 0.5µm CMOS tech-nology and measured [1]. The measurement setup is shown in Fig. 10. The update rate of this converter is 150MSamples/s. The chip has an INL of 0.3LSB and a DNL of 0.2LSB (see Fig. 11). Its settling time is 0.9ns. It has an SFDR of 84dB @ 500kHz full scale input signal, the measured spectrum is shown in Fig. 12. In Fig. 13 the spectrum at the output is shown for a 5MHz full-scale input signal. An SFDR of 61dB is obtained. The power consump-tion of the design is 300mW. The measurement results for this design are summarized in Table 4.
Specification Obtained value
Number of bits 14 INL [LSB] 0.3 DNL [LSB] 0.2 Settling time (10-90%) [ns] 0.9 Sample frequency [Mhz] 150 Output range [V] 0.5 Rload [Ω] 25 Digital levels CMOS Power supply [V] 2.7 Power consumption [mW] 300 Area [mm2] 3.2 x 4.1 Technology 1P3M 0.5µ SFDR @ 500kHz [dB] 84
Table 4: Measured performance of the designed D/A converter.
Fig. 11: INL and DNL measurement results.
VII Conclusions A 14-bit 150-Ms/s CMOS D/A converter has been designed using a systematic design methodology, which implements the well established performance-driven top-down design methodology. Both commercially available and newly developed software tools support the methodology. The total design effort was reduced to less than one person-month accumulated effort. The correctness of the approach has been proven by the fabrication and measure-ment of the 14-bit D/A converter.
Fig. 12: Output spectrum measurement. The applied signal frequency is
approximately 500 kHz at full scale.
Fig. 13: Output spectrum measurement. The applied signal frequency is
approximately 5 MHz at full scale.
References [1] J. Vandenbussche, et al., “A 14-bit, 150 MSamples/s Update Rate, Q2
Random Walk CMOS DAC”, Proc. IEEE 1999 ISSCC, pp. 146-147, February 1999.
[2] B. Razavi, “Principles of Data Conversion System Design", IEEE Press, ISBN 0-7803-1093-4, pp. 62-63, 1995.
[3] J. Bastos, A. M. Marques, M. S. J. Steyaert and W. Sansen, “A 12-bit Intrinisic Accuracy High-Speed CMOS DAC, IEEE JSSC, vol SC-33, no. 12, pp. 1959-1969, December 1998.
[4] A. Van den Bosch, et al., “A 12 bit 200 MHz Low Glitch CMOS D/A Converter”, Proc. IEEE 1998 CICC, pp. 249-252, May 1998.
[5] T. Miki et. Al., “An 80 Mhz 8 bit CMOS D/A Converter”, IEEE JSSC, Vol. SC-21, no. 6, pp. 983-988, Dec. 1986.
[6] Carley R., Gielen G., Rutenbar C., Sansen W., “Synthesis tools for mixed-signal ICs: progress on front-end and back-end strategies”, Proc. DAC, pp.298-303 (1996).
[7] Chang H., “A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits”, Phd dissertation Electronics Research Laboratory, College of Engineering, UCB, CA 94720.
[8] R. Neff, “Automatic Synthesis of CMOS Digital/Analog Converters”, PhD. Dissertation Electronics Research Laboratory, College of Engi-neering, Berkeley University, 1995 (available on the WWW).
[9] C-H. Lin and K. Bult, “A 10b 500 MSamples/s CMOS DAC in 0.6mm2”, IEEE JSSC, vol SC-33, no. 12, pp. 1948-1958, December 1998.
[10] J. Bastos, M. Steyaert, and W. Sansen, “A High Yield 12-bit 250-MS/s CMOS D/A Converter”, Proc. IEEE 1996 CICC, pp. 431-434, May 1996.
[11] M.J.M. Pelgrom, et. Al., “Matching Properties of MOS Transistors”, IEEE JSSC, Vol. SC-24, pp. 1433-1439, Oct. 1989.
[12] T. Wu et. al., “A Low Glitch 10-bit 75-Mhz CMOS video D/A Con-verter”, IEEE JSSC, Vol. 30, no. 1, pp. 68-72, Jan. 1995.
[13] G. Van der Plas, et al., “Mondriaan : a Tool for Automated Layout Synthesis of Array-type Analog Blocks”, Proc. IEEE 1998 CICC, pp. 485-488, May 1998.
268 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007
The Analysis and Improvement of a Current-SteeringDAC’s Dynamic SFDR—II: The Output-Dependent
Delay DifferencesTao Chen, Student Member, IEEE, and Georges Gielen, Fellow, IEEE
Abstract—For a current-steering digital-to-analog converter(DAC) without an extra output stage, the variation of the outputvoltage will result in the variation of the output delay. Theseoutput-dependent delay differences will deteriorate the spu-rious-free dynamic range (SFDR) of a high-speed high-accuracyDAC, especially when glitches exist. In this paper, a convenientmathematical model is presented to analyze during design the im-pact of this kind of delay differences on the SFDR. The results areverified by comparison to the results of more detailed simulations.Also the impact of glitches on this effect is demonstrated. Possiblesolutions to reduce this impact are discussed and summarized.
Index Terms—Current-steering digital-to-analog converters(DACs), glitch, output-dependent delay difference (ODDD),output variation, spurious-free dynamic range (SFDR).
I. INTRODUCTION
HIGH-SPEED high-accuracy digital-to-analog converters(DACs) are demanded by many communication and
signal processing applications. The spurious-free dynamicrange (SFDR) is one of the most important properties for theseDACs. Very high linearity is required in order to achieve sat-isfying SFDR. For this purpose, the nonlinearities which mayimpact the SFDR have to be analyzed and kept under controlby the designers.
The current-steering DAC architecture is almost exclusivelyused for high-speed high-accuracy DACs [1]. Two kinds of non-linearities have been distinguished for this kind of DACs [2].One is the limited output impedance of the current sources,which has been well analyzed and solved by taking the dif-ferential output [3]. The other kind is the delay-related nonlin-earities. According to the different causes of the delay differ-ences, the cell-dependent delay differences (CDDDs) and theoutput-dependent delay differences (ODDDs) are distinguishedin our previous paper [2]. A mathematical method is presentedin [2] to analyze the impact of the CDDDs on the SFDR of a cur-rent-steering DAC. Formulas with clear physical meaning werederived, and were verified by comparing them to simulation re-sults and published measurement results [4]. In this paper, themethod proposed in [2] is further extended to the case of theODDD. As in [2], formulas with clear physical meaning will beobtained and verified by simulations, and then solutions to im-prove the SFDR will be discussed based on these formulas.
Manuscript received March 20, 2006; revised August 4, 2006. This paper wasrecommended by Associate Editor T. N. Tarim.
The authors are with ESAT-MICAS, Katholieke Universiteit Leuven, Heverll3001, Belgium (e-mail: [email protected]).
Digital Object Identifier 10.1109/TCSI.2006.887598
Fig. 1. Schematic of a current-source cell.
The variation of the output voltage of the DAC will result inthe variation of the moment when the switches steering the cur-rent from the current sources to either of the two outputs changetheir status. We call this variation the ODDD in this paper. Thephysical reason of the ODDDs is as follows. Fig. 1 shows thebasic schematic of a current-source cell used in current-steeringDACs. Normally the switch transistors work in saturation re-gion (when on) or cutoff region (when off). The voltage of theinternal node X depends on the drain voltage of the on transistor.Thus, the variation of the output voltage will cause a small vari-ation of , which will result in a change of the next switchingtime.
For example, assume that in the current sampling period,is high and is low, so the left transistor is on.
Different values of will result in different values of .When the next sampling period comes, is getting lowerto turn off the left switch. The switch will not be turned offuntil reaches the value of , where isthe threshold voltage of the switch transistors. On the otherside, the right switch will not be turned on until reaches
. Thus, the delay of the next sampling period willdepend on the value of hence . This dependencewill cause harmonic distortion on the output of the DAC andtherefore deteriorate the SFDR.
CHEN AND GIELEN: ANALYSIS AND IMPROVEMENT OF CURRENT-STEERING DAC’S DYNAMIC SFDR—II 269
where is the transconductance and output resistanceof the switch transistor respectively, and is the outputimpedance of the cascoded current source (see Fig. 1). Thevalue of is normally in the order of 10 or lower for verydeep-submicrometer technologies. Assume for example thevariation of the output voltage is 0.5 V, and is 10,then the variation of will be up to 0.05 V. If the risingspeed of the control signal is 1.25 V/ns, the 0.05 Vvariation of will result in a delay difference of up to40 ps. This is already a very large value for a 14-bit DAC withsampling frequency higher than 100 MHz. The impact on thedynamic properties will be investigated in detail in this paper.
In Section II, a mathematical analysis is presented to analyzethe impact of the ODDDs on the SFDR of both the single-endedand differential outputs of a full-unary DAC. Then the behav-ioral-level simulations (with and without glitches) are discussedin Section III. Both the results of calculations and simulationsare compared in this section. In Section IV, the design require-ments imposed by this nonlinearity are given, and possible solu-tions are summarized, some of which have already been appliedin publications from different authors. Finally, Section V drawsconclusions.
II. MATHEMATICAL ANALYSIS
In the following analysis, we assume an ideal full-unary cur-rent-steering DAC, whose only nonlinearity is the ODDDs.1 Wecompare this to other effects in the conclusions.
Consider one of the current sources . Assume it is switchedon in the sampling cycle with delay . Then its outputcurrent is
(2)
where is the sampling period, is the time constant at theoutput node determined by the DAC’s load. The amplitude isset to be one. This is a simplified expression, the internal polesof the current cell have been omitted, but it’s sufficient to getmeaningful results.
The distortion of this current source due to the delay is thus
(3)
1For a full-binary or segmented DAC, the dynamic property should beworse than a full-unary DAC due to the extra nonlinearity caused by thebinary-weighted current sources.
where Taylor series expansion has been applied. Higher orderterms are omitted, since it should always be true for a gooddesign that . This condition also means that, if a termin (3) with low order contributes to harmonic distortion at somefrequency, the impact of the higher order terms in (3) on thatharmonic distortion will be very small and negligible.
A. SFDR of the DAC’s Single-Ended Output
As will be seen later, the first term of (3) will result in thesecond-order distortion, the second term in (3), which onlyslightly impacts the amplitude of the second-order distortion,can be omitted
(4)Assume the DAC’s input is a sinusoidal signal
(5)
where is the DAC’s number of bits. For convenience, the am-plitude is set so that the amplitude of every unit current sourceis 1. This will not impact the results since the SFDR is a ratio.
For a high-resolution DAC, ignoring the quantization errors,the ideal output current (which is an integer due to the assump-tion of (5)) of the DAC in the period from to
can be expressed as
(6)
(7)
Correspondingly, for the complementary output the current is
(8)
(9)
During this period the full-unary DAC’s total second-orderdistortion in the single-ended output currents is contained in theequation below
(10)
where (4) has been used and
whenelse
(11)
is a square function.
270 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007
Fig. 2. Output-dependent switching delays. (a) Different on/off delays,(b) D = 2 a.
Fig. 2(a) shows the waveform of the control signals andduring the transition. The moment when the switches change
their status depends on their common-source voltage, i.e., inFig. 1. The value of is determined by the voltage of the outputend whose switch is on. In the case of Fig. 2(a), is determinedby since is high before the transition and therefore thecorresponding switch is on. and are the minimumand maximum values of , corresponding to the minimum andmaximum values of respectively. If we select the momentwhen the off switch is turned on at the maximum (that is
) to be time 0 as a reference, then, according to (1), when, this delay can be expressed as where is a
proportionality factor. For the other switch, which is turning off,the delay is between and , where is the delaydifference between the two transitions (on to off and off to on).
can be adjusted (by the designer) by changing the crossingpoint of the two control signals and . If is adjusted tothe value , there will be no delay difference between thetwo transitions. This is used by some designs [5], [4] to avoid thesituation that both the switches are on or both are off, thus thecurrent of the current sources can be kept stable. For simplicity,we adopt this condition in our analysis as shown in (12) andFig. 2(b), meaning that by design the switches are on/off at thesame moment and the current is constant. The impact of onthe SFDR will be investigated by simulations in Section III-A.
The results [shown in Fig. 4(d), later] show that only slightlyimpacts the SFDR of a DAC without glitches.2
(12)
For the transition from the period to the period, the output of the DAC is expressed in (6)–(7). There
are two possibilities as follows.a) When is changing from low to high, and
is changing from high to low, the value of dependson (note that the (6)–(7) describe the current), the de-lays of the two switches can be expressed as
(13)
(14)
b) When , the value of depends on , thedelays of the two switches can be expressed as
(15)
(16)
For the case (a), applying (13) into (10) gives
(17)
For the case (b), applying (15) into (10) gives
(18)
With the condition of (12), (18) can be simplified into (17).The second term in (17) only slightly impacts the amplitude atthe signal frequency and can be omitted. Thus, the distortion canbe expressed as
(19)
2In an actual current-source cell, the different delays between the on-to-offand off-to-on transitions (D 6= d ) will result in the variation of the totalcurrent, which will result in glitches and deteriorate the dynamic properties ofthe DAC.
CHEN AND GIELEN: ANALYSIS AND IMPROVEMENT OF CURRENT-STEERING DAC’S DYNAMIC SFDR—II 271
where
(20)
The second term in the bracket of (19) only affects the dc leveland can be omitted. So
(21)
The total distortion can be obtained by summing the distor-tions in all the sampling periods
(22)
where is the convolution operator.Applying the Fourier transform
(23)
(24)
(25)
where is the clock frequency.The Fourier transform of (22) is given by
(26)
This is a sequence of Dirac functions at the frequencies. What we are interested in is the component at the frequency. Its amplitude is
(27)
where is the absolute value of the maximum delaydifference.
The signal amplitude at the frequency for the single-endedoutput is calculated in [6]
(28)
Combining (27) and (28), the SFDR can be obtained
(29)
where is the signal’s radial frequency, is the time constantof the output node, and is the maximum ODDDs. Interest-ingly, (29) shows that the SFDR due to ODDD has nothing todo with the clock frequency.
It is normally true for a current-steering DAC that. Under this condition, (29) can be simplified into
(30)
Approximately, the SFDR will decrease with increasing signalfrequency or increasing maximum delay difference ata slope of about dB/dec.
B. SFDR of the DAC’s Differential Output
The distortion generated by the i’th current source in then’th sampling cycle is expressed in (3). For the complementaryoutput, the delays may be different (see (13)–(16)), and thecorresponding distortion is
(31)
The impact on the differential-output SFDR of the two terms in(3) and (31) will be analyzed separately, assuming the conditionof (12).
1) Impact of the First Terms: We will firstly analyze the firstterms of (3) and (31). They are shown below
(32)
(33)
where the subscription “ ” is used to clarify that this distortioncomes from the first terms of (3) and (31).
272 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007
With the output current expressed in (6)–(9), the total distor-tion generated by (32) and (33) during this sampling cycle is
(34)
(35)
where is defined in (11).The total distortion in the th sampling cycle of the differen-
tial output is then
(36)
For the case (a) defined in (13) and (14)
(37)
where the condition of (12) has been applied, and is de-fined in (20).
With (6)–(9), (37) can be simplified into
(38)
For the case (b) defined in (15) and (16), similar calculationsgive the same result as (38). So this equation describes the dis-tortion (during the n’th sampling cycle) caused by the first termsof (3) and (31) in the DAC’s differential output.
Adding up the distortions in all the sampling cycles, the totaldistortion caused by the first terms can be obtained as
(39)
Applying the Fourier transform to (39) gives
(40)
It is clearly shown in (40) that no harmonic can be gener-ated from the first terms of (3) and (31). That means that wehave to take the higher order harmonics (the second terms) intoconsideration.
2) Impact of the Second Terms: The second terms of (3) and(31) are
(41)
(42)
where the subscription “ ” is used to clarify that this distortioncomes from the second terms of (3) and (31).
The current output of the DAC is expressed in (6)–(9). Duringthe n’th sampling cycle the DAC’s distortion generated by (41)and (42) in both the two output currents is
(43)
(44)
where (41), (42) and (11) have been used.Similar to the previous analysis, there are also two cases here:
(a) ; (b) .
CHEN AND GIELEN: ANALYSIS AND IMPROVEMENT OF CURRENT-STEERING DAC’S DYNAMIC SFDR—II 273
For the case (a), applying (43), (44), and (13)–(16), the third-order distortion of the differential output is
(45)
where has been defined in (20).With further calculations, (45) can be transformed into
(46)
For the case (b), with similar calculations, the third-order dis-tortion is
(47)
Applying (12) into (46) and (47), the same result is obtained
(48)
Similar analysis as in Section II-B1) shows that the secondterm in the braces of (48) does not generate any harmonic dis-tortion. Only the first term needs to be considered
(49)
Again, the second term in the bracket of (49) is at the signalfrequency and can be omitted. So
(50)
From (50), the distortion for all cycles can be obtained
(51)
where is the convolution operator.Applying the Fourier transform
(52)
With the results of (23), (25), and (52), the Fourier transformof (51) can be obtained
(53)
This is a sequence of Dirac functions at the frequencies. What we are interested in is the component at the frequency. Its amplitude is
(54)
where is the absolute value of the maximum delaydifference.
For the differential output, the signal amplitude at the fre-quency is twice the amplitude for the single-ended outputcase [see (28)]
(55)
With (54) and (55), the SFDR can be obtained
(56)
274 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007
where is the signal’s radial frequency, is the time constantof the output node, and is the maximum ODDDs. Equation(56) shows that the SFDR has nothing to do with the samplingfrequency.
When the condition holds, (56) can be simpli-fied into
(57)
To first order, the SFDR decreases with increasing signal fre-quency at a slope of about dB/dec. The SFDR also de-creases with increasing at a slope of about dB/dec. Itwill increase with increasing time constant at a rate of about
dB/dec.The results of (29) and (56) are shown in Fig. 4 later on.
III. SIMULATION RESULTS
A. Simple Single-Pole-Model Simulations
We will now compare the above calculation results with be-havioral simulation results.
If we only take the dominant pole in the output node intoconsideration, the output of the DAC can be simplified into asimple single-pole model
(58)
where and are the code levels between whichthe converter switches. is the delay of the transition. For the
th sampling cycle, is or respectivelyfor the two outputs, where is the sampling period, and
are defined in (13)–(16) which can be verified by SPICEsimulations. Thus, the ODDDs are included in the simulations.The output waveform can be obtained by applying (58) to eachsampling cycle. Then the output is sampled to apply the FFT.
The spectra of the output signals are shown in Fig. 3. It canclearly be seen from this figure that the second-order distor-tion dominates for the case of the single-ended output, and the(small) third-order distortion dominates for the case of the dif-ferential output. This fits well with the calculation results inSection II. Although the SFDR can be greatly improved by thedifferential output, it may still be deteriorated by the ODDDs.
Fig. 4 compares the calculation results and the simulation re-sults of the impact of the ODDDs on the SFDR for both thesingle-ended output and the differential output as a function ofthe parameters involved. A sampling frequency of 153 MHzis used in our simulations. All the simulations are done underthe condition of (12), which means that thereis no delay difference between the turning on and turning offtransitions.
Fig. 4(a) is the SFDR- curves with fixed and ;Fig. 4(b) is the SFDR- curves with fixed and ; andFig. 4(c) shows the SFDR- curves with fixed and . Forall the three variables and in (29) and (56), we seethat the calculation results fit pretty well with the simulationresults. Fig. 4(d) is the SFDR- curve with fixed
Fig. 3. Spectra for a DAC with ODDDs: f = 21:5 MHz, d = 20 ps,D = 20 ps, = 0:25 ns. (a) Spectrum of the single-ended output: second-order harmonic distortion dominates. (b) Spectrum of the differential output:third-order harmonic distortion dominates.
and . The result shows that the SFDR changes only slightlywith the variation of , which also fits the calculation results.
The results in Fig. 4 show that for the single-ended output,ODDD can deteriorate the SFDR seriously. For the differentialoutput, the SFDR is also deteriorated by ODDD, although thisdeterioration is rather small for a 14-bit DAC with signal fre-quency lower than 75 MHz and maximum delay difference lessthan 40 ps. However, our calculations and simulations above arebased on the simplified first-order model. No glitches are in-cluded. Our further simulations in Section III-B will show thatODDD make the dynamic property of DACs more sensitive toglitches.
B. Simulations of a Model Including Glitches
In [7] the glitches of a full-binary DAC were analyzed andshown to have a serious impact on the SFDR. For full-unaryDACs the amplitude of the glitches is proportional to the varia-tion of the output current. As a result, glitches become a kindof linear distortion and will not impact the SFDR. However,glitches can impact the way that the ODDDs impact the dis-tortion, even for a full-unary DAC. It is therefore necessary toanalyze the dynamic properties of DACs with both ODDD andglitches. We will do the analysis by simulations in this section.
CHEN AND GIELEN: ANALYSIS AND IMPROVEMENT OF CURRENT-STEERING DAC’S DYNAMIC SFDR—II 275
Fig. 4. Single-pole-model simulations: the deterioration of the SFDR caused by ODDDs as a function of the different parameters. (a) SFDR versus signal fre-quency: d = 40 ps, D = d ; = 0:25 ns. (b) SFDR versus maximum delay difference: f = 21:5MHz, D = d ; = 0:25 ns, (c) SFDR versusoutput time constant: f = 21:5MHz, d = 40 ps, D = d . (d) SFDR versus on-to-off and off-to-on delay difference: f = 21:5MHz, d = 40 ps, = 0:25 ns.
A behavioral model of DACs was presented in [8], wherethe glitches are included as an exponentially damped sine and ashifted hyperbolic tangent
(59)
in which is the output current, and is the amplitudeand period of the glitch, respectively. and are thecode levels between which the converter switches. is the delayof the transition.
Our simulations are based on this model. In our simulations,is set as described in Section III-A to include the ODDDs.
For full-unary DACs can be set to be proportional to thevariation of the codes, i.e., to . We define theproportionality factor pAgl as below
pAgl (60)
So the glitches themselves are a kind of linear distortion andwill not impact the SFDR. However, the glitch will change
the way that ODDD impact the SFDR since the DAC’s outputduring transition is changed by the glitches. In the model of(59), the glitch period describes the time needed for the DACto transit from one output value to another; it can be extractedfrom the results of SPICE simulations.
In our simulations the time-domain output of each transitionis obtained by (59), after which it is sampled to do the FFT. Thesampling points are carefully selected so that one of the samplesis located in the middle of the transition. This is to achieve thehighest accuracy, since the value in the middle of the transitionis very sensitive to the delay of the transition.
Repeating this process for each cycle, we can get the wholetime-domain output of the DAC. A Hanning window is used be-fore the FFT analysis to reduce the time length needed whilemaintaining enough accuracy. From the power spectrum ob-tained, the SFDR at that signal frequency can be obtained.
The impact of the glitches is shown in Fig. 5. Fig. 5(a) showsthe impact of the glitches on the SFDR of a full-unary DACwithout ODDDs . As we expect, the glitches donot impact the SFDR for both the single-ended and differentialoutput.
In Fig. 5(b), the curve with star markers is the case of thesingle-ended output. The glitch has little impact on its SFDR
276 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007
Fig. 5. The SFDR versus normalized glitch amplitude on a full-unary DAC:f = 21:5MHz,D = d ; T = 0:35 ns. (a) Without ODDD: d = 0
(both curves coincide). (b) With ODDDs: d = 40 ps.
since the ODDD itself has already deteriorated the SFDRgreatly (see Fig. 4). The curve with circle markers shows theimpact of the glitches on the SFDR of the differential output ofDACs with ODDD. The SFDR reduces quickly with increasingamplitude (energy) of the glitches, hence illustrating the impactof glitches.
The SFDR- and SFDR- curves with different values ofpAgl are shown in Fig. 6. In these simulations was chosento be 0.41 ns so that the simulated SFDR when pAgl (thatmeans no glitches exist in the output) is the same as the SFDRcalculated when ns. In this way the simulation re-sults in this section can be easily compared with the resultsin Sections II and III-A, where the analysis was based on thefirst-order model. The latter calculation results are also drawnin Fig. 6 for comparison reasons.
Fig. 6(a) shows the SFDR- curves with different pAglvalues. The SFDR decreases with increasing signal frequencyat a slope of about dB/dec, which is the same as the resultsof the mathematical model based on the first-order model.For the differential output, the SFDR is seriously reducedwhen the amplitude of the glitches increases. The SFDR-curves with different pAgl values are shown in Fig. 6(b). Forthe single-ended output, the SFDR decreases with increasingmaximum delay differences at a slope of about dB/dec,
Fig. 6. Impact of the glitches on a full-unary DAC with ODDDs:T = 0:41 ns, D = d ; = 0:25 ns (for calculations). (a) SFDRversus signal frequency: d = 40 ps. (b) SFDR versus maximum delaydifference: f = 75 MHz.
while for the differential output this slope is about dB/dec.These slopes are consistent with our mathematical results ((30)and (57)), although the mathematical calculations are based onthe simplified first-order model.
Two conclusions can be drawn from these results as follows.• Even for DACs with glitches, the impact of ODDD on
SFDR still obeys similar rules as predicted by our math-ematical model ((29) and (56)), i.e., the slope of the falloffremains the same (but the magnitude is different).
• The glitches can deteriorate the impact of ODDD on theSFDR seriously, especially in the case of the differentialoutput.
All these simulations in Figs. 5 and 6 are for full-unary DACs.For segmented DACs with binary LSBs, the glitches themselvesbecome a kind of nonlinear distortion and the SFDR can beexpected to be even worse.
IV. APPLICATION OF THE RESULTS
In order to get some quantitative idea about the maximumpermitted , we will present some calculations with actualvalues. For example, assume we want to design a 14-bit DACwith signal frequency up to 75 MHz and SFDR higher than
dB. Assume the time constant at theoutput node is ns, then with (56) the maximum
CHEN AND GIELEN: ANALYSIS AND IMPROVEMENT OF CURRENT-STEERING DAC’S DYNAMIC SFDR—II 277
Fig. 7. Transition of the control signal.
permitted is 30 ps. This is normally achievable in designsusing today’s CMOS technologies. However, if the glitches arebeing taken into consideration, this requirement may becomecritical. By curve-fitting the behavioral model (59) to theSPICE-simulation results, we can get the values of andpAgl for the behavioral model of the designed circuit. Assumethe parameters that we obtain are ns and pAgl ,then from Fig. 6(b) we can obtain that the maximum permitted
is only 8 ps. Special design and layout measures must betaken to ensure such small ODDDs.
Fig. 7 shows the waveform of the control signal . isthe peak-to-peak value of the control signal, is the transi-tion time of the control signal. is the peak-to-peak valueof the internal node’s voltage (see Fig. 1). According to (1)
(61)
where is the peak-to-peak value of the output voltage.The maximum ODDD therefore is
(62)
This points us to some solutions to improve the SFDR lim-ited by ODDD. In (62) the factor is the switchingspeed, so the first solution is to accelerate the switching speed.The intrinsic idea of this method is to reduce in (62). Thissolution is for instance used in [9] by applying a David-Goliathlatch.
The second possible solution is using a return-to-zero (RZ)output stage as presented in [10]. With the RZ output stage,the glitches are greatly reduced. Furthermore, folding currentsources with gain-boosting are applied in this output stage toreduce the variation of the output voltages at the drain nodesof the switch transistors. So in (62) is reduced. This RZoutput stage improves the dynamic property greatly, as shownin [10] and [11]. The price is a lot of extra power consumptionby the folded current sources and a significant reduction of thesignal power due to the RZ operation.
The term in (62) is the gain of the switch transistors.So another method to reduce the impact of ODDD is to increasethe gain of the switch transistors. Using cascoded switches as in[5] helps but it will consume extra voltage and is seldom used intoday’s designs.3 Optimizing the size of the switch transistorsto increase is a better choice. For current-steering DACs,the switches are driven by latches. Normally the slew rate of thelatches determines the transition time . As a first-order ap-proximation, the latch can be simplified to a current source withdrive current . If the gate capacitance of the switch transistoris , then the transition time can be expressed as
(63)
Since the switch transistors may work in both the cutoff re-gion and the saturation region, their gate capacitance is highlynonlinear. With a rough approximation, we assume that the ca-pacitance is constant, and can be expressed as
(64)
where and are coefficients, and are the width andlength of the switch transistor, respectively.
Expressing the small-signal parameters and with tech-nological parameters[12]
(65)
where (the Early voltage per unit-channel length) andare technological parameters [12]. is the drain current of theswitch transistor and it is determined by the design specifica-tions (output swing and load resistor) and is thus unadjustable.
Applying (63) –(65) into (62) gives
(66)
According to (66), we can reduce the maximum ODDDs byreducing the sizes of the switch transistor and increasing its gateoverdrive voltage (to reduce the value of ). For today’s de-signs, the latter is difficult to achieve since the available voltageis very limited. But the smallest sizes should be used for theswitches (to reduce ).
Equation (56) also shows that increasing the output time con-stant (by increasing the load capacitance) can also reduce theharmonic distortion caused by the ODDDs. But this reduces theoverall bandwidth.
Finally, enough attention should be paid to the control ofthe glitch energy, even for DACs with their most MSBs imple-mented in a unary way. This has been done in many publisheddesigns. In [5] and [4], delay-controllable latches are used to re-duce the glitches. The crossover adjustment circuit presented in
3In [5] the cascoded switches are actually used for reducing the glitches in-stead of increasing the gain of the switches.
278 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007
Fig. 8. Impact of technology scaling on DACs’ SFDR deterioration caused byCDDD and ODDD.
[13] does the same thing automatically. The current-switchingcell used in [13] further reduces the glitches by compensatingthe clock feedthrough. Low-swing buffers are used in [14] toreduce the glitches.
V. CONCLUSION
In this paper, an important nonlinear distortion due to theODDDs in high-speed, high-accuracy DACs has been analyzedand simulated. Formulas for the SFDR due to this effect havebeen derived and verified with simulations for full-unary DACswithout glitches. Both the calculations and the simulations fitvery well. Our simulations also show that even for DACs in-cluding glitches, the ODDD will impact the SFDR in a similarway as described in our mathematical models. The formulas de-scribe the impact on the SFDR of the output-dependent delayvariations due to the limited gain of the switch transistors, andcan be turned into a condition that has to be satisfied during thedesign of high-speed, high-accuracy DACs. Some possible so-lutions to reduce this impact have been summarized.
A mathematical method to analyse SFDR based on signalanalysis has been developed in [2] and in this paper. The stepsfor the analysis are as follows.
1) Calculate the distortion in one sampling cycle.2) With Taylor expansion, simplify the expressions for the
distortion in one sampling cycle.3) Sum the distortion in all the sampling cycles and get the
full distortion.4) Apply Fourier analysis to the distortion and obtain the am-
plitude of the harmonic distortions.5) Calculate the amplitude at the signal frequency.6) Calculate the SFDR.Two kinds of delay-related nonlinearities, due to ODDDs and
due to CDDDs, for current-steering DACs have been discussedwith simple but accurate mathematical models and simulationsin this paper and in our previous paper [2]. The results show
that both these nonlinearities may seriously deteriorate thedynamic SFDR of high-speed high-accuracy current-steeringDACs, even for differential outputs.
Depending on the design, either of these two delay-relatednonlinearities can be dominating. Generally, when the min-imum width of the technology shrinks, the CDDDs reduce dueto the shrinking of the layout area, while the ODDDs increasedue to the decrease of of the switch transistors [see(62)]. The arrows in Fig. 8 show the direction of ODDD’s andCDDD’s change with the shrinking of technology.4 Therefore,even though today the CDDD effect on the SFDR might stilldominate above the ODDD effect, this might change in futuretechnologies.
This paper, together with [2] has paved the way for the designof DACs with higher and higher dynamic accuracy and speed.
REFERENCES
[1] Y. Cong and R. Geiger, “A 1.5-V 14-bit 100-MS/s self-calibratedDAC,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2051–2060,Dec. 2003.
[2] T. Chen and G. G. E. Gielen, “The analysis and improvement of a cur-rent-steering DACs dynamic SFDR—I: The cell-dependent delay dif-ferences,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 1, pp.3–15, Jan. 2006.
[3] S. Luschas and H. S. Lee, “Output impedance requirements for DACs,”in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS’03), May 2003, pp.I-861–I-864.
[4] G. Van der Plas, J. Vandenbussche, W. Sansen, M. Steyaert, and G.Gielen, “A 14-bit intrinsic accuracy Q random walk CMOS DAC,”IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1708–1718, Dec. 1999.
[5] J. Bastos, A. Marques, M. Steyaert, and W. Sansen, “A 12-bit intrinsicaccuracy high-speed CMOS DAC,” IEEE J. Solid-State Circuits, vol.33, no. 12, pp. 1959–1969, 1998.
[6] T. Chen and G. Gielen, “Analysis of the dynamic SFDR property ofhigh-accuracy current-steering D/A converters,” in Proc. IEEE Int.Symp. Circuits Syst. (ISCAS’03), May 2003, pp. I-973–I-976.
[7] J. Bastos, “Characterization of MOS transistor mismatch for analogdesign,” Ph.D. dissertation, ESAT-MICAS, Katholieke Univ. Leuven,Leuven, Belgium, 1998.
[8] J. Vandenbussche, G. Van Der Plas, G. Gielen, and W. Sansen, “Be-havioral model of reusable D/A converters,” IEEE Trans. Circuits Syst.II, Analog Digit. Signal Process., vol. 46, no. 10, pp. 1323–1326, Oct.1999.
[9] J. Deveugele and M. Steyaert, “A 10 b 250 MS/s binary-weighted cur-rent-steering DAC,” in Dig. Tech. Papers IEEE Inst. Solid-State Cir-cuits Conf. (ISSCC’04), Feb. 2004, pp. 362–363.
[10] A. R. Bugeja and B. Song, “A self-trimming 14-b 100-MS/s CMOSDAC,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1841–1852,2000.
[11] Q. Huang, P. A. Francese, C. Martelli, and J. Nielsen, “A 200 MS/s 14 b97 mW DAC in 0.18/spl mu/m CMOS,” in Dig. Tech. Papers IEEE Inst.Solid-State Circuits Conf. (ISSCC’04), Feb. 2004, no. 2, pp. 364–532.
[12] K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuitsand Systems. New York: McGraw-Hill , 1994.
[13] B. Schafferer and R. Adams, “A 3 V CMOS 400 mW 14 b 1.4 GS/sDAC for multi-carrier applications,” in Dig. Tech. Papers IEEE Inst.Solid-State Circuits Conf. (ISSCC’04), Feb. 2004, no. 2, pp. 360–532.
[14] K. Doris, J. Briaire, D. Leenaerts, M. Vertregt, and A. van Roermund,“A 12 b 500 MS/s DAC with>70 dB SFDR up to 120 MHz in 0.18-m CMOS,” in Dig. Tech. Papers IEEE Inst. Solid-State Circuits Conf.(ISSCC’05), 2005, vol. 1, pp. 116–588.
4The data come from designs with 0.5- and 0.13-m technologies, respec-tively. The actual values heavily depend on the design (circuits and layout).
CHEN AND GIELEN: ANALYSIS AND IMPROVEMENT OF CURRENT-STEERING DAC’S DYNAMIC SFDR—II 279
Tao Chen (S’02–M’07) was born in Zhangping City,Fujian Province, China, in 1974. He received theB.Sc. degree in electronic engineering from ZhejiangUniversity, Hangzhou, China, the M.Sc. degree inelectronic engineering from Tsinghua University,Beijing, China, and the Ph.D. degree in electronicengineering from Katholieke University Leuven,Belgium, in 1996, 1999, and 2006, respectively.
From 1999 to 2000, he was an ASIC Engineer atHuawei High-Tech Incorporated, Beijing, and then aChip Design Engineer at Capella Microsystem Inco-
poration, Beijing. Currently, he is with Mindspeed Technologies, Inc, NewportBeach, CA. His research interests are in the area of analog/mixed-signal inte-grated circuits design and computer-aided design tools.
Georges G. E. Gielen (S’87–M’92–SM’99–F’02)received the M.Sc. and Ph.D. degrees in electrical en-gineering from the Katholieke Universiteit Leuven,Leuven, Belgium, in 1986 and 1990, respectively.
In 1990, he was appointed as a Postdoctoral Re-search Assistant and Visiting Lecturer in the Depart-ment of Electrical Engineering and Computer Sci-ence, University of California, Berkeley. From 1991to 1993, he was a Postdoctoral Research Assistantof the Belgian National Fund of Scientific Research,ESAT Laboratory, Katholieke Universiteit Leuven. In
1993, he was appointed as a tenure Research Associate of the Belgian NationalFund of Scientific Research and also an Assistant Professor at the KatholiekeUniversiteit Leuven. In 1995, he was promoted to Associate Professor at thesame university, where he is now a full-time Professor. His research interestsare in the design of analog and mixed-signal integrated circuits, and especiallyin analog and mixed-signal computer-aided design tools and design automation(modeling, simulation and symbolic analysis, analog synthesis, analog layoutgeneration, analog and mixed-signal testing). He is coordinator or partner ofseveral (industrial) research projects in this area. He has authored or coauthoredone book and more than 250 papers in edited books, international journals, andconference proceedings.
Dr. Gielen served as the 2005 President of the IEEE Circuits and Systems(CAS) Society. He was an Associate Editor of the IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, andlater of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: ANALOG AND
DIGITAL SIGNAL PROCESSING. He is also a member of the Program Commit-tees of international conferences (ICCAD, DATE, ISCAS). He received the BestPaper Award of the Wiley International Journal on Circuit Theory and Appli-cations in 1995. He was the 1997 Laureate of the Belgian National Academy ofSciences, Literature and Arts. He received the 2000 Alcatel Award of the Na-tional Fund of Scientific Research for innovations in telecom research, and the2004 Best Paper Award at the DATE conference.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006 3
The Analysis and Improvement of a Current-SteeringDACs Dynamic SFDR—I: The Cell-Dependent
Delay DifferencesTao Chen, Student Member, IEEE, and Georges G. E. Gielen, Fellow, IEEE
Abstract—For a high-accuracy current-steering digital-to-analog converters (DACs), the delay differences between the cur-rent sources is one of the major reasons that cause bad dynamicperformance. In this paper, a mathematical model describing theimpact of the delay differences on the DACs SFDR property is pre-sented. The results are verified by comparison to behavioral-levelsimulations and to actual measurement data from publishedpapers. Based on this analysis, the delay differences cancellation(DDC) technique to reduce the impact of the delay differences onthe SFDR property is proposed and verified by simulation results.
Index Terms—Current-steering digital-to-analog converters(DACs), delay differences cancellation (DDC), delay differ-ence, delay distribution, spurious-free dynamic range (SFDR),switch-and-latch cell, switching sequence.
I. INTRODUCTION
FOR TODAY’S digital-to-analog converters (DACs), higherand higher accuracy and speed are required. Such DACs
are typically implemented as current-steering DACs. For a DACwith an accuracy higher than 12 bits, its spurious-free dynamicrange (SFDR) property has become one of the major limitingfactors for its performance [1]–[5]. There are quite a lot of non-ideal factors which will impact the DACs SFDR property. Somework has been done to explore the physical reasons of the dete-rioration of the SFDR. In [6] and [7], the impact of the currentsources’ limited output impedance for current-steering DACs isanalyzed. As a conclusion, this limited output impedance willdeteriorate the SFDR for high-accuracy high-speed DACs, es-pecially when the single-ended output is used [7]. This conclu-sion can be verified by the model provided in [8].
The delay-related nonlinearities are another kind of main con-tributors to the bad dynamic property. Our previous paper [9]proposes a method for analyzing this kind of nonlinearities. Theresults of the analysis show that the delay-related nonlinearitiescan indeed limit the dynamic performance of a high-accuracyhigh-speed DAC if one does not apply any special techniques tosolve this problem.
Based on their different causes, two kinds of delay differencesin a high-accuracy current-steering DAC can be distinguished.One is the cell-dependent delay differences, and the other is theoutput-dependent delay differences.
Manuscript received December 14, 2004; revised April 18, 2005. This paperwas recommended by Associate Editor J. Silva-Martinez.
The authors are with ESAT-MICAS, Katholieke Universiteit Leuven, Hev-erlee 3001, Belgium (e-mail: [email protected])
Digital Object Identifier 10.1109/TCSI.2005.854409
Fig. 1. Schematic of a current cell and the floorplan of the layout.
When the accuracy of a current-steering DAC increases, thenumber of current cells1 increases, and it will be more and moredifficult to let all these current sources have the same delay fromthe clock pad or to the output pad under the condition of keepinga reasonable layout aspect ratio. Fig. 1 shows the floorplan of theDAC and the schematic of a current cell. All the switch-and-latch cells are connected to the same output pad and the sameclock pad. The delays from the clock pad to the switch-and-latchcells, or the delays from the switch-and-latch cells to the outputpad, are determined by the length of the connection wire, asshown in the two circles in Fig. 1, and has nothing to do withthe output value. We call this kind of delays the cell-dependentdelays. Due to the different positions of the switch-and-latchcells (not the current-source cells) on the layout, the delays aredifferent from cell to cell. For a DAC with a number of bitshigher than 14, the delay differences may be as high as dozens ofpicoseconds in today’s mainstream CMOS technologies. This isthe physical reason for the cell-dependent delay differences.
Besides the cell-dependent delays, another kind of the delaydifferences is the output-dependent delay differences, whosedelay values will depend on the output value, instead of thephysical position of the current cells. The basic schematic ofa current source used in the current-steering DACs is shown inFig. 2(a). (Note that the current source or the switch transistorcould also be cascoded.) Normally the switch transistors workin saturation region (when on) or cutoff region (when off). Thevoltage of the internal node X will change when changing thedrain voltage of the on transistor because of the limited output
1From now on, the phrase “current cell” means the whole unit cell of theDAC, i.e., the current source together with the switches and latches. The phrase“current-source cell” only means the current source transistor, and “switch-and-latch cell” means the switches and latches. See Fig. 1.
4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006
Fig. 2. Voltage variation of the internal node. (a) Schematics. (b) Small-signalequivalent circuit.
impedance of the switch transistor. Thus, the variation of theoutput voltage will cause a small variation of , which willresult in a change of the next switching time. Fig. 2(b) showsthe small-signal equivalent circuit. The transistor which is off isomitted. When the output impedance of the (cascoded) currentsource is very large, with KCL the equation below can beobtained
(1)
where and are the transconductance and the outputimpedance of the switch transistor respectively. This is thephysical reason of the output-dependent delay differences.
As the first part (part I) of our study, this paper will onlyfocus on the analysis and improvement of the cell-dependentdelay differences. However, our calculations show that the samemethod can also be applied to the analysis of the output-depen-dent delay differences to get meaningful results. The analysisand improvement of the output-dependent delay differences willbe proposed in the part II of this paper.
This paper is organized as follows. In Section II, the methodused in [9] is explained in full detail to analyze the impact ofthe delay differences in the clock net on the SFDR of the DAC.Formulas with clear physical meaning are derived, and are com-pared to the measurement results from a published paper [1].Next, this method is extended in Section III to analyze the delaydifferences in the output net. The impact of the return-to-zero
(RZ) output stage on the cell-dependent delay differences willthen be analyzed in Section IV. The intrinsic advantage of theRZ stage in reducing the impact of the delay differences on theSFDR can be observed from the results of the analysis. In Sec-tion V behavioral-level simulations are presented and the resultsare compared to the results of the mathematical model. Sec-tion VI proposes the delay-difference-cancellation (DDC) tech-nique to overcome the cell-dependent delay differences. Oursimulations show that the cell-dependent delay differences willnot impact the SFDR any more with this technique. The DDCtechnique paves the way to the design of current-steering DACswith high dynamic accuracy ( bits). Finally, Section VIIsummarizes the paper and draws conclusions.
II. DELAY DIFFERENCES ON THE CLOCK NET AND ITS
MATHEMATICAL ANALYSIS
For the cell-dependent delays, the delay values are deter-mined by the position of the current cell on the layout, whilethe delays in both the two differential output ends are the same.This means that taking the differential output will not reducethe nonlinearity caused by this kind of delay differences, andthe second-order harmonic distortion is the dominant distortionwhich will determine the SFDR deterioration. In this section,the second-order distortion of a DACs single-ended output willfirst be calculated. Then we will calculate the amplitude ofthe signal frequency. From these results, the expression of theSFDR can be obtained.
A. Second-Order Distortion Caused by the Delay Differenceson the Clock Net
For a current-steering DAC without RZ output stage,2 theoutput of the current sources are added directly to the outputcurrent of the DAC; the delay differences among these currentsources will reflect on the output current directly.
Consider one of the current sources with clock delay .Assume it is switched on in the th sampling cycle. Then itsoutput current is
(2)
where is the sampling period, is the time constant decidedby the DACs load. The amplitude is set to be one. This is asimplified expression, the internal poles of the current cell havebeen omitted. But this is sufficient to get meaningful results.
The distortion of this current source is thus
(3)
Assume the DACs input is a sinusoidal signal
(4)
where is the DACs number of bits. The amplitude is set sothat the amplitude of every unit current source is 1.
2Current-steering DACs with RZ output stage will be analyzed later in Sec-tion IV.
CHEN AND GIELEN: CURRENT-STEERING DACs DYNAMIC SFDR I 5
Fig. 3. DACs output signal without RZ output stage.
For a high-resolution DAC, ignoring the discrete nature of theoutput signal, the ideal output of the DAC in the period from
to can be expressed as
(5)
(6)
During this period the DACs total distortion is
(7)
where (3) has been used, and
whenelse
(8)
is a square function.In order to simplify the calculations, only linearly-distributed
delays are considered for now. That is
(9)
where is a constant. Two assumptions are contained in thisapproximation. First, the delay values are integer times of .(We will refer to this condition as linearly distributed delayvalues or simply LDDV assumption later.) Second, the current
cells are switched on in the same order as their delay increases(referred to as linear switching sequence or LSS assumption).The LDDV assumption does not exist in a real DAC, but as willbe seen in Section V, it has little impact on the result, so it isjustifiable to adopt this assumption to simplify the derivation.What will impact the SFDR is actually the distribution ofthe delay values rather than the values themselves. The delaydistribution is determined by the switching sequence of theswitch-and-latch cells3 when the input code step by step changesfrom the minimum value to the maximum value. Here, the LSSassumption is one of the possible cases in a real DAC and itleads to an interpretable analytic result. For the cell-dependentdelays, when the positions of the switch-and-latch cells in theswitch-and-latch block are decided, the delay values for thecorresponding current cells are fixed, but the designer can stilldecide the delay distribution freely by arranging the actualswitching sequence of the switch-and-latch cells. We will seelater from the simulation results in Section VI that the LSScase is one of the worst delay distributions.4 However, throughthe analysis of this worst case, we will obtain the optimizeddelay distribution and the corresponding optimized switchingsequence of the switch-and-latch cells.
3Note that the switching sequence of the switch-and-latch cells can bedifferent from the switching sequence of the current source cells.
4Actually, what we simulated and optimized in Sections V and VI isthe distribution of the delays in the output net. But we will see later thatthe delay differences in both the clock net and the output net impact theSFDR in a similar way [see (23) and (46)].
6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006
Using (9) into (7), with a little calculation we can get the resultfor the DACs total distortion in the th time window
(10)
Define the function as
(11)
As will be seen later, determines the amplitudes of thedistortion components at different frequencies. Then (10) canbe simplified to
(12)
With (5) and (6), we can get
(13)
Thus the DACs overall distortion is
(14)
where “ ” is the convolution operator.Since the distortion is very small compared to the signal am-
plitude for high-resolution converters, the distortion at the signalfrequency can be neglected. Thus, only the second-order distor-tion must be considered5:
(15)
Applying the Fourier transform
(16)
(17)
(18)
5Results later on confirm that the second-order distortion is the dominatingcontribution if the signal frequency is not too high.
For the high-accuracy DACs of nowadays, it normally holds that
(19)
It meas that, the output settles well at the end of each samplingcycle.
Thus, (18) can be simplified into
(20)
With (16), (17), and (20), the Fourier transform of canbe obtained
(21)
This is a sequence of Dirac functions at the frequencies. What we are interested in is the component at frequency, its amplitude is
(22)
Using (20), we get
(23)
where is the maximum delay difference of the cur-rent cells. We see from this result that the second-order distor-tion is proportional to both the maximum delay differenceand the sampling frequency , and that there is a peak whenthe signal frequency is near . is the time constant ofthe output node. We see from (23) that a bigger results in asmaller second-order distortion.
B. Signal Amplitude and the SFDR of a DAC Without RZOutput Stage
In order to get the SFDR, the signal amplitude at has tobe calculated. For a DAC without RZ output stage, its outputsignal is shown in Fig. 3, where is the sampling cycle, and
are the DACs output values at time and ,respectively, as defined in (5) and (6). is the DACs outputsignal. It can easily be decomposed into two parts: (theright bottom curve) and (the left bottom curve) , that is
(24)
Then we can get by calculating and , respec-tively.
Define the function as
(25)
CHEN AND GIELEN: CURRENT-STEERING DACs DYNAMIC SFDR I 7
where the square function is defined in (8). Thencan be expressed as (ignoring the discrete nature of the outputsignal)
(26)
Under the condition of (19), we get the Fourier transform ofas
(27)
With (16), and (27), s Fourier transform is obtained
(28)
Now we calculate the Fourier transform of . It can beexpressed as
(29)
Applying the Fourier transform
(30)With the above equations, together with (16), we get the Fouriertransform of as
(31)
From (24), (28), and (31), the Fourier transform of canbe obtained
(32)
The amplitude of the component at the signal frequencyis
(33)
Observing (27) and (30), the relation holds
(34)
Using this equation into (33) gives
(35)
With some calculations, (35) can be simplified into
(36)
Thus, we have obtained the amplitude of the signal frequency.Combining (23) and (36), the SFDR of a current-steering
DAC without RZ output stage due to cell-dependent delay dif-ferences caused by the clock net of the latches can be obtainedas (assuming that the second-order distortion is dominant)
(37)
where is the maximum delay difference of thecurrent cells. We see from this expression that the SFDR willincrease with decreasing delay differences ( ) of the currentcells. This is consistent with our intuition. The most interestingthing about this result is the dependency of the SFDR on thesignal frequency and the sampling frequency. Fig. 4(a) showsthe SFDR- curve, where the signal frequencyhas been normalized to the sampling frequency .When the signal frequency increases from zero up to , theSFDR will first decrease and then increase. When ,the SFDR reaches its lowest value. This result will be verifiedwith more detailed simulation results later in Section V.
The SFDR- curve is shown in Fig. 4(b), where the sam-pling frequency has been normalized to the signal frequency
. We conclude from this figure that, when the signal fre-quency is a constant, we can improve the SFDR by decreasingthe sampling frequency. This is reasonable because, when thesampling frequency increases, the distortion in every samplingcycle appears with a higher frequency, thus deteriorating theDACs SFDR property. When the sampling frequency becomeseven higher, the amplitude of the distortion in every samplingcycle is reduced, the total distortion will not increase much,thus, the SFDR will approach a constant value, as shown in thefigure.
When the signal frequency is so low that , (37) canbe simplified into
(38)
This result shows that the SFDR will decrease with increasingsignal frequency at a rate of about dB when the signalfrequency is low. This is consistent with [1]’s measurement (see
8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006
Fig. 4. Equation (37): the dependence of the SFDR on the signal frequencyand the sampling frequency due to the delay differences on the clock net for aNRZ DAC. (a) SFDR-f curve. (b) SFDR-f curve.
[1, Fig. 16]). Another conclusion which can be drawn from (38)is that, when the signal frequency is low enough, the DACsSFDR property will have nothing to do with the sampling fre-quency. In [1, Fig. 18], we can see that the DACs SFDR propertyis nearly constant provided that the sampling frequency is lowerthan 150 MHz. (If the sampling frequency becomes higher, theDAC will not be able to achieve 14 bits accuracy, thus the SFDRwill decrease.) This result also verifies our analytic result.
With (38) we can estimate the maximum signal frequency aDAC can achieve under a given maximum delay difference. Foran N-bit DAC, the SFDR it should achieve is at least
dB [10]. So the relation below should be satisfied
(39)For example, for a 14-bit DAC, when ps (extractedfrom the layout of a real DAC [1]), the maximum frequency itcan achieve is only 1.39 MHz, even when all other nonlinearitiesare omitted. Of course, this result is based on the simplificationof (9). However, our simulations in Section V with the actual
delay values extracted from the layout obtain a result very closeto this number. The reason will be analyzed in that section. Ob-viously, the cell-dependent delay difference may indeed deteri-orate the DACs SFDR property seriously.
III. DELAY DIFFERENCES ON THE OUTPUT NET AND ITS
MATHEMATICAL ANALYSIS
Now consider the second source of possible delay differencesin a current-steering DAC, i.e., when the delays from the outputof the switches to the DACs output pad are different (see Fig. 1).This difference can be described as a different time constant in(2). The distortion of the th current source in the th samplingcycle is
(40)
where is the variation of the time constant , and is muchless than itself, say, . With this condition, (40) can besimplified into
(41)
Since
we have
So, (41) can be further simplified into
(42)
As in Section II-A, the total distortion in the th samplingcycle is
(43)
where and are defined in (5) and (6), and the functionis defined in (8).
Again, we assume the variation of the time constant, , to belinearly distributed
(44)
where is a constant. The LDDV and LSS assumptions are in-cluded in this equation just as in (9). Their impact on the results
CHEN AND GIELEN: CURRENT-STEERING DACs DYNAMIC SFDR I 9
Fig. 5. Equation (46): the dependence of the SFDR on the signal frequencyand the sampling frequency due to the delay differences on the output net for aNRZ DAC. (a) SFDR-f curve. (b) SFDR-f curve.
is also similar to the case of the delay differences in the clocknet, which has been discussed when we introduce (9).
With similar calculations as in Section II-A, we can get theamplitude of the second-order distortion as
(45)
Combining (36) and (45), the SFDR of a DAC without outputstage due to output time constant differences is obtained as
(46)where is the maximum time constant variation. This re-sult is shown in Fig. 5. It is very similar to (37)’s result (seeFig. 4), i.e., the impact of the output time constant variation onthe SFDR is similar to that of the clock delay difference. Thatmeans that the output time constant variation will impact theSFDR in the same way as the clock delay difference does. Thus,
Fig. 6. RZ DACs output signal. (a) The simplified output signal f (t). (b)The actual output signal f (t).
when designing the layout of the switch-and-latch block, it ispossible to let both delay differences cancel each other and thusreduce the whole delay variation.
IV. IMPACT OF RZ OUTPUT STAGE ON DELAY DIFFERENCES
In [2] and [3], an RZ output stage was used to enhance theSFDR property by setting the output to a fixed value (ac ground)at the start of any transition. With this architecture, the outputsignal is divided into two phases in every clock cycle: the trackphase and the attenuate phase. The output tracks the DAC outputonly during the track phase, and it is attenuated to a very lowfixed value during the attenuate phase [2]. When the signal fre-quency increases, the SFDR property of such a DAC will de-crease with a much slower rate compared to DACs without RZoutput stage. In this section, a simplified ideal RZ output stagewith attenuation time assumed to approach zero as shown inFig. 6(a) will be analyzed as a worst-case situation to a real RZDAC. The impact of the cell-dependent delay differences on theSFDR of such a DAC will be obtained. Since the delay differ-ences on the clock net and the output net impact the SFDR in asimilar way, only the delay differences on the clock net are an-alyzed in this section.
Fig. 6(a) shows the simplified output signal of an RZ DAC. Inthis figure, the curve is the output of the RZ DAC. For com-parison, a normal (without RZ output stage) DACs output signal
is also shown. Both the signal amplitude at frequency
10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006
and the amplitude of the second-order distortion have to be re-calculated in order to get the SFDR. The curve in Fig. 6(b)shows the output of an actual RZ DAC with nonzero attenuationtime. We will discuss the impact of the attenuation time on theSFDR later.
Using the function defined in (25), we can expressas
(47)With calculations similar to Section II-B, the amplitude of the
component at frequency can be obtained as
(48)
where
(49)
The second-order distortion of such a DAC has to be recalcu-lated too. Instead of (7), the total distortion of the th cycle isnow
(50)
where is defined in (11).With calculations similar to Section II-A, we can get the am-
plitude of the second-order distortion as
(51)
As we now have the signal amplitude [(48)] and the amplitudeof the second-order distortion [(51)], the DACs SFDR can beobtained as
(52)
where is the maximum delay difference. Again,the SFDR property of such a DAC will increase with decreasingdelay differences of the current cells. But the frequencydependence is different from that of a DAC without RZ outputstage. The SFDR- curve is shown in Fig. 7(a). We see thatthe SFDR will decrease with increasing signal frequency witha small slope. This is consistent with the measurement resultsin [2], [3], and [5]. Fig. 7(b) shows the SFDR- curve re-sulting from (52). We see from this figure that the SFDR alsodecreases with increasing sampling frequency, but the reductionhappens slower than in the case without the RZ output stage [seeFig. 4(b)].
For the RZ output stages with nonzero attenuation time [seethe curve in Fig. 6(b)], if ignoring the settling error at the
Fig. 7. Equation (52): the dependence of the SFDR on the signal frequencyand the sampling frequency due to the delay differences on the clock net for aRZ DAC. (a) SFDR-f curve. (b) SFDR-f curve.
end of the last track phase, the DACs output during the attenu-ation phase will not be impacted by the delay differences. Thenonlinear distortion only exist in the track phase. According to(3), the nonlinear distortion decreases exponentially when re-ducing the time of the track phase. Meanwhile, the signal energyreduces linearly when reducing the time of the track phase. Asa result, for an actual RZ output stage whose attenuation time islarger than zero, if the only nonlinearity that is taken into consid-eration is the cell-dependent delay differences, the SFDR shouldeven be better than what we have obtained in (52).
When the signal frequency is so low that , (52) canbe further simplified into
(53)
This result shows that when the signal frequency is low, the RZDACs SFDR property will depend on the sampling frequency,instead of the signal frequency. This property is different from
CHEN AND GIELEN: CURRENT-STEERING DACs DYNAMIC SFDR I 11
Fig. 8. Layout of the switch-and-latch block from [1].
that of a DAC without output stage [see (38)], the SFDR ofwhich depends on the signal frequency instead of the samplingfrequency.
V. SIMULATION VERIFICATION OF MATHEMATICAL MODEL
According to the previous analysis, the delay differences onboth the clock net and the output net will impact the SFDR in asimilar way. Therefore, in our simulations we only consider thedelay differences on the output net.
Fig. 8 shows the layout of the switch-and-latch block as ex-tracted from a real DAC [1], which is used as illustrative ex-ample here. The clock net is not shown for simplification. Wewill simulate the behavior of every current cell, and then get thebehavior of the whole DAC by adding up the current of all thecurrent cells. In this figure, unit 183 is taken as an example. Theresistances and the capacitors are the extracted parasitic resis-tances and capacitors of the actual wires on the layout. For theswitch-and-latch cells in different positions, these parametershave different values, and will result in the delay differences onthe output net.
The corresponding extracted circuits are shown in Fig. 9. Asshown in Fig. 8, , are the parasitic parameters of the mainwire on the left side of unit 183. and are on the right side.
, are the parasitic parameters of all the branch wires onthe left side of the branch wire where unit 183 is located, and
, are those on the right side. The parasitic parameters onthe branch wire where unit 183 is located are divided into twoparts. , are on the bottom side, and , are on the topside. Replacing unit 183 with a current source, we obtain theequivalent circuit of Fig. 9. In order to simplify the simulation,the , subcircuit and the , subcircuit are placed inthe middle of the , subcircuit and the , subcircuitrespectively. and are the load of the DAC. The point Ais where the switch-and-latch cell is connected to the output net.The current source describes the switching behavior of thecurrent source. Ignoring the internal poles, can be thoughtas an ideal step function when the current cell is switched on.The values of the resistances and the capacitances can be ex-tracted from the layout. With this circuit model, we can calcu-late the output current caused by every current cell. When theclock transition happens, the output current of the DAC can be
Fig. 9. Extracted circuit for calculating the delays.
Fig. 10. Flowchart of the SFDR simulation method.
obtained by adding up the output currents of all the current cellswhich are turned on. Applying the same calculations to eachsampling cycle, the total output signal can be obtained. Thenthe FFT analysis is applied to obtain the SFDR. The flowchartof the simulation method is shown in Fig. 10.
Fig. 11 shows the results of the simulations. For compar-ison, the calculation results of (46) are also shown as the thickcurve without markers. The curve with the circle markers showsthe simulation results. We see that both curves agree with eachother well when the signal frequency is not so high. But whenthe signal frequency is higher than 72 MHz in the example ofFig. 11, the results of the calculation and simulation are be-coming different: the simulated SFDR curve even flattens off.This is because at those frequencies the higher-order distortiondominates and makes the SFDR lower than the case when onlythe second-order distortion is considered, while in our mathe-matical model only the second-order distortion is taken into con-sideration. If we only consider the second-order distortion in thesimulation, we will get the curve with triangle markers. It fits thecalculation results much better at higher frequencies, and it alsomatches the total SFDR curve at lower frequencies, indicatingthat at lower frequencies indeed the second-order componentdominates.
Our mathematical model is based on the very simplified as-sumptions [see (9) and (44)] and these assumptions do not exist
12 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006
Fig. 11. Comparison of SFDR calculation and simulation results for a DACwithout output stage [1].
in real DACs. The reason why the simulation results fit the cal-culation result is that, in the chip [1] we used, the current cellsare switched on nearly in the same order as their delays decrease[Fig. 13(a)], i.e., it approximately fits the LSS assumption de-fined in Section II-A. In such a case, the peak of the nonlineardistortion caused by the different delays appears twice in onesinusoidal cycle, and results in big second-order distortion, thusdeteriorating the SFDR.
We will show in Section VI by simulations that the delay dis-tribution (physically the switching sequence of the switch-and-latch cells) greatly affects the DACs SFDR property assumingthat the delay difference values are fixed. Since it is hard fora high-accuracy DAC to reduce the delay differences of all thecurrent cells through proper design and layout, finding a bestdelay distribution becomes a promising way to solve the SFDRproblem.
VI. DDC TECHNIQUE
As aforementioned, we can reduce the delay differences bymaking the delay differences on the clock net and those on theoutput net cancel with each other, as shown in Fig. 12(a). Butthe length differences in the clock net and in the output net willnot result in exactly the same delay differences, therefore thismethod cannot solve the problem completely. Another possiblesolution is to use a tree-like connection for both the clock netand the output net as shown in Fig. 12(b). This method willinevitably increase the area and slow down the sampling fre-quency, and for high-accuracy DACs, the tree-like buses willmake it difficult to get a reasonable aspect ratio.
The methods mentioned above work by reducing the valuesof the delay differences. In this section, we will present anothermethod which will not change the delay difference values of thecurrent cells. Instead, we will reduce the impact of the cell-de-pendent delay differences on the SFDR directly by properlychoosing the switching sequence of the switch-and-latch cells.In this way, what is changed is the delay distribution instead ofthe values of the delay differences. It is to some degree similar
Fig. 12. Reduction of the cell-dependent delay differences. (a) Delaycancellation between the clock net and the output net. (b) Tree-like clock netand output net.
to what has been done to the current source cells in order toachieve good INL static property in [1] and [11]. Fig. 1 showsthe floorplan of a typical high-accuracy current-steering DAC.The connections between the thermodecoder block and theswitch-and-latch block (connections 1 in the figure), togetherwith the connections between the switch-and-latch block andthe current source block (connections 2), provide enoughfreedom to the designers for realizing in the same chip boththe optimum switching sequence in the current-source blockfor good static INL performance and the optimum switchingsequence in the switch-and-latch block for good dynamicSFDR performance.
If we only take the distortion caused by the delay differencesinto consideration, two conclusions are justifiable based on theabove analysis and simulations. First, to first-order approxima-tion, the total distortion is the sum of all the distortions in everysampling cycle; in each cycle, the distortion is the sum of thedistortions of every current cell that is switched on; and the dis-tortion of a current cell in a sampling cycle is linearly propor-tional to the delay difference value of the current cell [see (3)and (42)]. Second, the second-order distortion dominates whenthe signal frequency is not too high. Correspondingly, there aretwo solutions to improve the SFDR property: to reduce the am-plitude of the distortion in each sampling cycle, or to reduce theenergy of the second-order distortion. Thus, we get two rules(we call them “the DDC rules”) for arranging the switching se-quence of the switch-and-latch cells
1) The amplitude of the distortion in every sampling cycleshould be reduced to as low as possible. That means thatthe current cells with big delay values should neighborthe current cells with small delay values in the switchingsequence.
CHEN AND GIELEN: CURRENT-STEERING DACs DYNAMIC SFDR I 13
TABLE IPOSITIONS OF SWITCH-AND-LATCH CELLS IN BLOCK
2) The distortion should appear with high frequency. Thatmeans that the current cells with big delay variationsshould be distributed as uniformly as possible. Thus, theenergy of the lower-order distortion can be reduced.
Below we will illustrate these rules by an example.The layout of the switch-and-latch block extracted from a real
DAC [1] is shown in Fig. 8. The clock network in this chip is atree-like net, the delay differences are very small compared tothose caused by the output net, so it is not shown for reasonsof simplification. The positions of the switch-and-latch cellsin the matrix decide the actual delay values and are shown inTable I, where the numbers designate the switching sequence ofthe cells as used in [1]. (We will refer to it as “cell number” inthis paper.) When the DAC is working, the unary current cellswill turn on according to the order of the “cell number.” Theposition of a number in the table designates its position in theswitch-and-latch block. The number “0” means that the positionis vacant. The delay values of each current cell can be calculatedby the model presented in Section V. The normalized delay dis-tribution is shown in Fig. 13(a). Obviously, they don not satisfythe assumptions of (9) and (44).
We see from Fig. 13(a) that in this chip the current cellswith smaller cell numbers have greater delays. As a result, fora full-scale sinusoidal input signal, the distortion will have twopeaks in every signal cycle, i.e., , the DAC will have a very bigsecond-order distortion, and such a second-order distortion willdetermine the DACs SFDR property when the signal frequencyis not too high (see Fig. 11). This conclusion is consistent withthe previous analysis.
We can change the switching sequence by rearranging the po-sitions of the switch-and-latch cells. Table II shows one possiblerearrangement. The cells with consecutive cell numbers are put
Fig. 13. Normalized delay distributions of the switch-and-latch cells from [1].(a) Original distribution. (b) After the sequence rearrangement.
in the opposite place vertically to satisfy DDC rule 1. Accordingto DDC rule 2, the cell numbers are uniformly distributed in thewhole table. The corresponding delay distribution is shown inFig. 13(b). The current cells with big delay deviation have beenuniformly distributed among all the cell numbers, and every bigdelay cell is always neighbored by two cells with small delayvalues. So the DDC rules are satisfied by this arrangement.
Performing behavioral-level simulations as before on the“new” DAC, the SFDR results obtained are shown in Fig. 14,where the curve with circle markers is the case with the opti-mized switching sequence while still having the same delayvalues from the original layout [1]; the curve with right-pointingtriangle markers shows the ideal case when there is no delaydifference; the curve with upward-pointing triangle markersis the original case [1] before optimization; and the curveswith asterisk markers are cases when uniformly distributedrandom switching sequences are applied. We see from theseresults that the rearrangement of the delay values can improvethe DACs SFDR property significantly to a level that is very
14 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006
TABLE IIOPTIMIZED POSITIONS OF SWITCH-AND-LATCH CELLS IN BLOCK
near to the ideal case without delay differences. Even theSFDR at high signal frequencies where the dominant harmonicdistortion is higher than the second order is improved. Thisis because at these high signal frequencies the dominant har-monic distortion, though higher than the second order, is stilla relatively low-order distortion (for example, the third-order),which is also reduced by the DDC technique together with thesecond-order distortion6.
Under the condition of satisfying the DDC rules, i.e., a delaydistribution similar to what is shown in Fig. 13(b), there maybe lots of switching sequences of the switch-and-cell cells. Oursimulations show that SFDR values very close to the ideal casewith no delay differences can be obtained for all these switchingsequences that satisfy the DDC rules. These results mean thatwith a DDC switching sequence the delay differences will havevery little impact on the DACs SFDR property.
VII. CONCLUSION
Driven by signal processing and telecommunication applica-tions, DACs with higher and higher accuracy and speed are re-quired. As the accuracy and speed increase, some high-orderdistortions become important and impose additional constraintsupon the designers. The impact of the current sources’ limitedoutput impedance on the SFDR has been well analyzed and canbe solved for state-of-the-art DACs by using a differential output[6], [7]. Since most of the DACs nowadays are using differentialoutput to achieve large output swing, no extra solution is needed
6Actually the switching sequence (of the switch-and-latch cells) which canreduce the second-order distortion normally can also reduce the distortions thatare slightly higher than the second-order. This can be observed from the resultsof the uniformly distributed random switching sequences in Fig. 14.
Fig. 14. Result of optimizing the switching sequence for a real design case(f = 150 MHz).
to overcome the impact of the limited output impedance. How-ever, even for DACs with differential output, our studies showthat the delay-related nonlinearities still deteriorate the SFDRseriously.
The impact of the cell-dependent delay differences on theSFDR of thermometercode-based current-steering DACs hasbeen analyzed in this paper. Formulas with clear physicalmeaning have been derived and verified by both behav-ioral-level simulations and results described in publishedpapers. The results are also justifiable for a segmented archi-tecture, because in this architecture the thermometric part hasa much more significant weight compared to the binary partand its delay differences will be the main contribution to theSFDR deterioration. According to our results, delay differencesdeteriorate the DACs SFDR property already at very low signalfrequencies, and are thus one of the main reasons that maycause a bad SFDR property.
With the method proposed, the intrinsic advantage of the Re-turn-to-Zero output stage in improving the SFDR property of aDAC has been analyzed and explained.
The DDC technique has been presented to reduce the impactof the cell-dependent delay differences on the SFDR. This tech-nique makes use of the freedom in choosing the switching se-quence of the switch-and-latch cells, and can improve the SFDRgreatly with very low penalty on the layout area and complexity.The simulation results show that with the DDC technique, theDACs SFDR performance is very close to that of an ideal DACwhich has no delay differences.
ACKNOWLEDGMENT
The authors would like to thank Dr. G. Van der Plas for hisvaluable discussions and suggestions.
REFERENCES
[1] G. Van der Plas, J. Vandenbussche, M. Steyaert, W. Sansen, and G.Gielen, “A 14-bit intrinsic accuracy Q random walk CMOS DAC,”IEEE J. Solid-State Circuits, vol. 34, pp. 1708–1718, Dec. 1999.
CHEN AND GIELEN: CURRENT-STEERING DACs DYNAMIC SFDR I 15
[2] A. R. Bugeja and B. Song, “A self-trimming 14-b 100-MS/s CMOSDAC,” IEEE J. Solid-State Circuits, vol. 35, pp. 1841–1852, 2000.
[3] J. Hyde, T. Humes, C. Diorio, M. Thomas, and M. Figueroa, “A 300-ms/s 14-bit digital-to analog converter in logic CMOS,” IEEE J. Solid-State Circuits, vol. 38, pp. 734–740, 2003.
[4] A. Van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, “A 12 b500 msample/s current-steering CMOS D/A converter,” in Proc. IEEE2001 ISSCC, vol. XLIV, Feb. 2001, pp. 366–367.
[5] Y. Cong and R. Geiger, “A 1.5 v 14 b 100 MS/s self-calibrated DAC,”in Proc. IEEE 2003 ISSCC, vol. 1, Feb. 2003, pp. 128–482.
[6] A. Van den Bosch, M. Steyaert, and W. Sansen, “SFDR-bandwidth lim-itations for high speed high resolution current steering CMOS D/A con-verters,” in Proc. IEEE 1999 ISCAS, 1999, pp. 1193–1196.
[7] S. Luschas and H. S. Lee, “Output impedance requirements for DAC’s,”in Proc. IEEE 2003 ISCAS, May 2003, pp. I–861–I–864.
[8] T. Chen and G. Gielen, “Modeling of the impact of the current sourceoutput impedance on the SFDR of current-steering CMOS DA con-verters,” in Proc. IEEE 2004 ISCAS, May 2004.
[9] , “Analysis of the dynamic SFDR property of high-accuracy cur-rent-steering D/A converters,” in Proc. IEEE 2003 ISCAS, May 2003,pp. I–973–I–976.
[10] S. Haykin, An Introduction to Analog and Digital Communica-tions. New York: Wiley, 1989.
[11] Y. Cong and R. Geiger, “Switching sequence optimization for gradienterror compensation in thermometer-decoded DAC arrays,” IEEE Trans.Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 7, pp.585–595, Jul. 2000.
Tao Chen (S’02) was born in Zhangping City, FujianProvince, P.R. China, in 1974. He received the B.S.degree in electronic engineering in 1996 from Zhe-jiang University, and in 1999, he received the M.S.degree, also in electronic engineering, from TsinghuaUniversity, China.
From 1999 to 2000, he was an ASIC engineer atHuawei High-Tech Incoporation, Beijing, and then achip design engineer with Capella Microsystem In-coporation, Beijing. Currently, he is a research as-sistant with the MICAS Laboratories, K.U. Leuven,
Belgium. He is working toward the Ph.D. degree on the design of analog/mixed-signal integrated circuits.
Georges G. E. Gielen (S’87–M’92–SM’99–F’02)received the M.Sc. and Ph.D. degrees in electrical en-gineering from the Katholieke Universiteit Leuven,Leuven, Belgium, in 1986 and 1990, respectively.
From 1986 to 1990, he was appointed as a Re-search Assistant by the Belgian National Fund ofScientific Research. In 1990, he was appointed aPostdoctoral Research Assistant and Visiting Lec-turer with the Department of Electrical Engineeringand Computer Science, University of California,Berkeley. From 1991 to 1993, he was a Postdoctoral
Research Assistant with the Belgian National Fund of Scientific Research,ESAT Laboratory, Katholieke Universiteit Leuven. In 1993, he was appointedas a tenure Research Associate of the Belgian National Fund of ScientificResearch and also an Assistant Professor at the Katholieke Universiteit Leuven.In 1995, he was promoted to Associate Professor at the same university, wherehe is now a full-time Professor. His research interests are in the design of analogand mixed-signal integrated circuits, and especially in analog and mixed-signalCAD tools and design automation (modeling, simulation and symbolic analysis,analog synthesis, analog layout generation, analog and mixed-signal testing).He is coordinator or partner of several (industrial) research projects in this area.He has authored or coauthored one book and more than 250 papers in editedbooks, international journals, and conference proceedings.
Dr. Gielen was the 2004 President-Elect of the IEEE Circuits and Systems(CAS) Society. He has been an Associate Editor of the IEEE TRANSACTIONS
ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS,and recently also of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS––II:ANALOG AND DIGITAL SIGNAL PROCESSING. He is also a member of the Pro-gram Committees of international conferences (ICCAD, DATE, ISCAS). Hereceived the Best Paper Award of the Wiley International Journal on CircuitTheory and Applications in 1995. He was the 1997 Laureate of the Belgian Na-tional Academy of Sciences, Literature, and Arts, and is a member of the Edi-torial Board of the Kluwer International Journal on Analog Integrated Circuitsand Signal Processing.
