Conventional Design FlowFunct. Spec

Logic Synth.

Gate-level Net.

RTL

Layout

Floorplanning

Place & Route

Front-end

Back-end

Behav. Simul.

Gate-Lev. Sim.

Stat. Wire Model

Parasitic Extrac.

Behavioural Simulation : Synthesis begins with a high-level

specification of the problem. behavior is generally decoupled

from e.g. clock-level timing. The high-level synthesis tools

handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations,

The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control.

Verification at different levels of abstraction

BehavioralHDL

System Simulators

HDL Simulators

Code Coverage

Gate-level Simulators

Static Timing Analysis

Layout vs Schematic (LVS)

RTL

Gate-level

PhysicalDomain

Verification

Verification Techniques

Simulation (functionalfunctional and timingtiming) Behavioral RTL Gate-level (pre-layout and post-layout) Switch-level Transistor-level

Formal Verification (functionalfunctional) Static Timing Analysis (timingtiming)

Goal:Goal: Ensure the design meets its functional and timing requirements at each of these levels of abstraction

Classification of Simulators

Logic Simulators

Emulator-based Schematic-basedHDL-based

Event-driven Cycle-based Gate System

Formal Verification

Can be used to verify a design against a reference design as it progresses through the different levels of abstraction.

Verifies functionality without test vectors

(Some) EDA Tools and Vendors

Behavioral synthesisBehavioral compiler Synopsys

Logic SynthesisDesign Compiler SynopsysBuildGates Ambit Design SystemsGalileo (FPGA) Examplar (Mentor Graphics)FPGAExpress (FPGA) SynopsysSynplify (FPGA) Synplicity

(Some) EDA Tools and Vendors

Logic SimulationScirocco (VHDL) SynopsysVerilog-XL (Verilog) Cadence Design SystemsLeapfrog (VHDL) Cadence Design SystemsVCS (Verilog) Chronologic (Synopsys)

Cycle-based simulationSpeedSim (VHDL) QuickturnPureSpeed (Verilog) Viewlogic (Synopsys)Cobra Cadence Design SystemsCyclone Synopsys

(Some) EDA Tools and VendorsFormal VerificationFormality SynopsysFormalCheck Cadence Design SystemsDesignVerifyer Chrysalis

Static Timing AnalysisPrimeTime Synopsys (gate-level)PathMill Synopsys (transistor-level)Pearl Cadence Design Systems

FPGA Design Flow Verilog RTL Coding

Functional/Gate simulation

& Verification

Logic Synthesis

Physical Layout

Device Configuration

ucf

sdc

Verilog testbench

Verilog model

Verilog

Netlist

bit

par

ngc

Xilinx ISEXilinx Impact

Pyhsical Design & Implementation

Xilinx ISE - XSTSynplify Pro

Synthesis

Modelsim SELeda

Verification

Text EditorEmacs, Nedit, Vi

Verilog Design

ToolsDesign Stage

SDC: is a format used to specify the design intent, including the timing, power and area constraints for a design. SDC is tcl based.

Using Synopsys Tool like DC, ICC or PrimeTime you can generate the SDC.

Ucf:The UCF file is an ASCII file specifying constraints on the logical design.

JTAGTest normally shows only pin numbers and their names. Unlike other boundary scan tools, you can load so-called UCF file and give each pin net name. This will make debugging much easier and faster as you don't have to look into schematics for net names.

The NGC file is a netlist that contains both logical design data and constraints This file replaces both EDIF(*1) and NCF(*2) files.

*1: EDIF = Electronic Data Interchange Format. An industry standard file format for specifying a design netlist.

*2: NCF = Netlist Constraints File. This constraints file is commonly used to define constraints for schematic editors and third-party tools.

BIT was one of the original file formats for the PC. It refers to a program that is in Binary format. Meaning it is a program that has been converted to a machine format so the computer can unserstand and run it. Very similar to exe files.

Digital Design Flow Verilog Coding

Functional/Gate Simulation/Verification

Logic Synthesis

Clock Tree InsertionFinal Layout

Final Design CheckDRC/LVS

Test-Insertion

Static Timing Analysis

Floorplanning/Place & Route

scr

test.scr

_pre.sdf

_post.sdf

techfile.leftechfile.gcf*.lef*.tlf*.def

ctgen.con

gds2

Synopsys - StarRXTCadence - Pearl

Timing Extraction

Cadence - Assura, DraculaMentor Callibre

DRC/ANT Checking

Synopsys - TetraMaxMentor - Fastscan

Test Insertion

Synopsys - PrimetimeStatic Timing Anal. Cadence - Sensemble/

SOC EncounterSynopsys - Apolllo

Place & Route

Cadence - CTgenClock Tree Insertion

Cadence - Assura, DraculaMentor Callibre

LVS

Synposys - Design Compiler

Synthesis

Mentor - Modelsim SESynopsys - Leda

Verification

Text EditorEmacs, Nedit, Vi

Verilog DesignToolsDesign

StageVerilog

RTLVerilog test

bench

Verilog Netlist

Timing Extraction

Analogue Design Flow Schematic Entry

Simulation

Layout

Physical Verification / Extraction

Post-Layout Simulation

AssuraCalibre

Pyhsical Verification/Extraction SpectrePost-Layout Simulation

VirtuossoLayout

SpectreSimulation

ComposerSchematic Entry

ToolsDesign Stage

techfile.leftechfile.gcf*.lef*.tlf*.def

gds2

Mixed Signal Design Flow

Verilog Coding

Functional/Gate Simulation/Verification

Logic Synthesis

Clock Tree InsertionFinal Layout

Final Design CheckDRC/LVS

Test-Insertion

Static Timing Analysis

Floorplanning/Place & Route

scr

test.scr

_pre.sdf

_pst.sdf

techfile.leftechfile.gcf*.lef*.tlf*.def

ctgen.con

gds2

Verilog RTL

Verilog testbench

Verilog

Netlist

Timing Extraction

Schematic Entry

Simulation

Layout

Physical Verification / Extraction

Post-Layout Simulation

Co-simulationEnvironement

Cadence - SpectreVerilogCadence -UltraSimDigital Flow Analog Flow

BehaviouralModelling

techfile.leftechfile.gcf*.lef*.tlf*.def

gds2

Latch-Up and its Prevention

Latch is the generation of a low-impedance path in CMOS chips between the power supply and the ground rails due to interaction of parasitic pnp and npn bipolar transistors. These BJTs for a silicon-controlled rectifier with positive feedback and virtually short circuit the power and the ground rail.This causes excessive current flows and potential permanent damage to the devices. Analysis of the a CMOS Inverter CMOS depicting the parasitics.

Latch-Up Continued

The equivalent circuit shown has Q1 being a vertical double emmitter pnp transistor whose base is formed by the n-well with a high base to collector current gain (1).Q2 is a lateral double emitter npn transistor whose base is formed by the p-type substrate.Rwell represents the parasitic resistance in the n-well structure whose value ranges from 1K to 20k.The substrate resistance Rsub depends on the substrate structure.

Assume the Rwell and Rsub are significantly large so that they cause open circuit connections, this results in low current gains and the currents would be reverse leakage currents for both the npn and pnp transistors.If some external disturbance occurs, causing the collector current of one of the parasitic transistors to increase, the resulting feedback loop causes the current perturbation to be multiplied by 1.2

Latch-up Continued

This event triggers the silicon-controlled rectifier and each transistor drives the other with positive feedback eventually creating and sustaining a low impedance path between power and the ground rails resulting in latch-up.For this condition if 1 *1 is greater than or equal to 1 both transistors will continue to conduct saturation currents even after the triggering perturbation is no longer available.

Some causes for latch-up are:Slewing of VDD during start-up causing enough displacement currents due to well junction capacitance in the substrate and well.Large currents in the parasitic silicon-controlled rectifier in CMOS chips can occur when the input or output signal swings either far beyond the VDD level or far below VSS level, injecting a triggering current. Impedance mismatches in transmission lines can cause such disturbances in high speed circuits.Electrostatic Discharge stress can cause latch-up by injecting minority carriers from the clamping device in the protection circuit into either the substrate or the well.Sudden transient in power or ground buses may cause latch-up.

Prevention from latch-up:

1)Reduce the gain product b1 x b1. (1.a)move n-well and n+ source/drain farther apart

increases width of the base of Q2 and reduces gain beta2 > also reduces circuit density.

(1.b)buried n+ layer in well reduces gain of Q1.2)Reduce the well and substrate resistances, producing lower

voltage drops. 2.a)higher substrate doping level reduces Rsub2.b)reduce Rwell by making low resistance contact to GND.2.c)guard rings around p- and/or n-well, with frequent

contacts to the rings, reduces the parasitic resistances.

Clock Tree Synthesis:

The basics of CTS is to develop the interconnect that connects the system clock into all the cells in the chip that uses the clock.

For CTS, your major concerns are,Minimizing the clock skew.

Optimizing clock buffers to meet skew specifications and

Minimize clock-tree power dissipation

Clock Tree Synthesis:

Effect of CTS: Lots of clock buffers are added Congestion may increase Non-clock tree cells may have

been moved to non-ideal locations Can introduce new timing

violations

Clock Tree Synthesis:-

Frequently asked questions : What is Body effect ? What are standard Cell's? What are Design Rule Check (DRC) and

Layout Vs Schematic (LVS) ? What is Antenna effect ? What is Clock Gating ? What is Netlist ? What is Clock distribution network ? What are steps involved in Semiconductor

device fabrication ? What is Substrate coupling ?

Important sites/blogs for preparation:

http://www.asic.co.in/Index_files/asic_interview_questions.htm

http://www.edaboard.comhttp://www.vlsiinterviewquestions.org/www.allinterview.com Www.asicguru.com/interview_que/

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