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Presentation Outline
� What is Phase Locked Loop (PLL)
� Basic PLL System
� Problem of Lock Acquisition
� Phase/Frequency Detector (PFD)
� Charge Pump PLL
� Application of PLL
What is Phase Locked Loop (PLL)
� PLL is an Electronic Module (Circuit) that
locks the phase of the output to the input.
Phase Locked
Loop
Vi(t) Vo(t)
Locked Vs. Unlocked Phase
� Example of locked phase
� Example of unlocked phase
Vi(t)
Vo(t)
Vo(t)
Vi(t)
Phase Error
( ∆φ)
Basic PLL System
� PLL is a feedback system that detects the phase error ∆φand then adjusts the phase of the output.
� The Phase Detector (PD), detects ∆φ between the output and the input through feedback system
� Voltage Control Oscillator (VCO) adjusts the phase difference
Phase Locked
Loop
Vi(t) Vo(t)
Phase
DetectorVCO Vo
VI
∆φ
Implementation of PD
Phase Detector is an XOR gate
Phase
DetectorVCO Vo
VI
∆φV1
Vo
∆φ
1
0
I o
I o
V V
V Vϕ
≠∆ =
=
Vo(t)
Vi(t)
Phase Error
( ∆φ)
What is VCO ?
� VCO is a circuit module that oscillates at a controlled frequency ω.
� The Oscillating Frequency is controlled using
Voltage VControl.– That is why the module is called
� Voltage Control Oscillator
� Vcontrol must be in the steady state for the VCO to operate properly
VCOVControl ω
ω
ω0
VControl
o VCO ControlK Vω ω= +
Simple PLL
� Structure– Phase Detector ( XOR ) that detects the phase error ∆φ
– Low Pass Filter ( to smooth ∆φ )
– Voltage Control Oscillator (VCO)
� Basic Idea – If VI and Vout are out of phase (unlocked), then the PD module
detects the error and the LPF smoothes the error signal. The control signal slows down or speeds up the VCO module; hence, the phase is corrected (locked)
VCOVoutPhase
Detector
VI
∆φ
Vout
LPF VControl
∆φ
Locked Condition
– Locked Condition
– This implies that
VCOVoutPhase
Detector
VI
∆φ
Vout
LPF VControl
∆φ
( ) 0in out
d
dtϕ ϕ− =
in outω ω=
Example: In the UNLOCKED State
VI and Vout has ∆φ at the same
frequency ω1
� The phase detector must
produce VI
� Hence, VCO is dynamically
changing and PD is creating
VControl to adjust for the phase
difference.
� The PLL is in the Locked state
Vo(t)
Vi(t)
Phase Error
( ∆φ)
VControl
ω1
ω0
ω
VControlV1
VControl
V1
φ0
In the UNLOCKED State
� For Simplicity and by using Fourier Series
� Let
� Due to ∆φ, PD creates Vcontrol
� VCO will change
� The output voltage becomes
( )1cos
I AV V tω= ( )1
cosout B o
V V tω ϕ= +
1out VCO ControlK Vω ω= +
( )1cos ( )
out B oV V t tω ϕ ϕ= + − ∆
Dynamics of Simple PLL
� PLL is a feedback system– PD is a gain amplifier– LPF be first order filter ( as an example)– VCO is a unit step module
� The transfer function of the feedback system is given as:
φin φoutKPD
PDVCO
VCOK
s
1
1LPF
s
ω+
LPF
2
2 2( ) ( ) ( )
2
out out n
in in n n
H s s ss s
ω ω
ω ςω ω
Φ= = =
Φ + + 2( ) PD VCO LPF
LPF PD VCO LPF
K KH s
s s K K
ω
ω ω=
+ +
Transient Response to PLL
� The unit step response to second order system – Overdamped– Critically damped– Underdamped
� Problems with this PLL– Settling time Vs. ripple of Vcontor
– Stability of the system– Lacks performance in ICs
φin φoutKPD
PDVCO
VCOK
s
1
1LPF
s
ω+
LPF
2
2 2( ) ( ) ( )
2
out out n
in in n n
H s s ss s
ω ω
ω ςω ω
Φ= = =
Φ + +
t
ωi
ωout
t
Problem of Lock Acquisition
� When PLL is turned on, the output frequency is far from the input frequency
� It is possible that the PLL would never lock� Modern PLL uses FREQUENCY DEDECTOR (FD) in
addition to the PD.
VCO
LPF2
LPF1PD
FD
Vout
ωout
ωin
Vin
Phase/Frequency Detector (PFD)
� One Module that detects both frequency and phase differences
� This module senses the transition in A or BA B QA QB
Initially 0 0 0 0
A leads B 0 ���� 1 0 ���� 0 0 ���� 1 0 ���� 0
XX 0 ���� 1 1 ���� 0 0 ���� 0
A B QA QB
Initially 0 0 0 0
B leads A 0 ���� 0 0 ���� 1 0 ���� 0 0 ���� 1
0���� 1 XX 0 ���� 0 0 ���� 0
� If A leads B, QA changes its state and QB remains unchanged� If B leads A, QB changes its state and QA remains unchanged
PFDA
B
QA
QB
A
B
QB
QA
A
B
QB
QA
Hardware Implementation of PFD
� Uses two Edge Triggering modules using D-FF
� If A leads to “1” QA = “1”– When B becomes “1”, QB = “1”
momentarily
– The AND gate RESETs Both to Qs “0”
� If B leads to “1” QB = “1”– When A becomes “1”, QA = “1”
momentarily
– The AND gate RESETs Both to Qs “0”
VDD
A
QB
QAD
CK
Q
D
CK
Q
VDD
B
Hardware Implementation of PFD
VDD
A
QB
QAD
CK
Q
D
CK
Q
VDD
B
RES
A
B
QB
QA
RES
A
B
QB
QA
RES
The Vout is the average of (QA – QB)
is used to detect the phase and the
frequency difference
The Basic Block diagram
� Structure
– PFD– LPF
– Differential Amplifier
– VCO
– Negative Feedback
� Disadvantage:Sensitive to noise and offset voltages, ripple Vcontrol, ..
� Use Charge Pump PLL
D
CK
Q
D
CK
Q
VDD
VDD
Vin
φin
ωin
QB
QA
Vout
φout
ωout
VCO
Charge Pump PLL
� Structure
– PFD– Two switches
controlled by QA and QB
– Capacitor
– VCO
– Negative Feedback– It charges or
discharges the capacitor indefinitely
D
CK
Q
D
CK
Q
VDD
VDD
Vin
φin
ωin
QB
QA
Vout
φout
ωout
VCO
VDD
C
C
C C
d VI C
d t
d V I
d t C
=
=
Charge Pump PLL
� The capacitor is replaced with a LPF (Cp and Rp) to improve the phase margin for stability
� The transfer function of the system is approximated as follows:
� Rp slows down the system
D
CK
Q
D
CK
Q
VDD
VDD
Vin
φin
ωin
QB
QA
Vout
φout
ωout
VCO
VDD
CP
RP
( )
2
12
( )
2 2
P VCO
P P
P
P P VCO
VCO P VCO
P
I KR C s
CH s
I I Ks K R s K
C
π
π π
+
=
+ +
Application of PLL
� Frequency Multiplications – The feedback loop has frequency division – Frequency division is implemented using a counter
Clock Skew ReductionBuffers are used to distributethe clockEmbed the buffer within the loop
VCOVoutPFD
VI
∆φLPF VControl
∆φ
Counter
(Frequency
Division)
Application of PLL
� Clock Skew Reduction– Buffers are used to distribute the clock
– Embed the buffer within the loop
� Jitter Reduction
VCOVoutPFD
VI
∆φ
Vout
LPF VControl
∆φ
Buffer
