DigSys3ASM

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Prof. Dr. J. Reichardt

Prof. Dr. B. Schwarz

Digital Systems

B. Schwarz 3-1

university of applied sciences hamburg

DEPARTEMENT OF ELECTRICAL ENGINEERING

AND COMPUTER SCIENCE

3 Designing Digital Systems with Algorithmic State MachineCharts

An ASM chart is a method of describing the sequential operations of a digital systemwhich has to implement an algorithm. An algorithm is a well defined sequence of

steps that produces a desired sequence of actions and/or calculation results in re-

sponse to a given sequence of control and data inputs.

ASM charts are similar in appearance to flowcharts used in the early days of com-puter programming. Unlike the traditional flowchart the ASM chart includes timing

information because it implicitly specifies that the FSM steps from one state to an-

other only after each active clock edge.

ASM charts are constructed of three elements.


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AND COMPUTER SCIENCE3.1 Graphical ASM Chart-Notations

State box: A rectangle describes one state of the synchronous sequential digital system. Itis similar to a circle representing a state of a state diagram. The main difference is that it

only has one output transition (exit path). The state block symbol contains a listing of allunconditional actions and (Moore) outputs associated with that state. The outputs are up-

dated concurrently when the state is entered after an active clock edge.

Asserted signals are written as: Z which means Z = 1

Input

condition0 1

Entry path

Exit falsepath

Exit truepath

Entry path

Conditional(Mealy) output

list

Exit path

Unconditional(Moore) output

list

State entry path

State name State code

Exit path


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Digital Systems

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AND COMPUTER SCIENCERegistered mathematical operations: COUNT COUNT + 1 ; MULT A * B

The activated state will assert the enable signal which causes the counter to incre-

ment and the multiplier to operate a multiplicand and a factor.

Registered signal assignments: INT_REG INPUT_1REG A(2:0) @ C(4:0) concatenation.

Condition symbol: A diamond shape contains the input condition on which depends thebranching from a given state. It has one entry point and two exit path. Condition symbols

can be concatenated.

X means that the input signal X has to be tested.X1 X2 indicates that X1 = X2 = 1 has to be true.

Conditional output box: An oval or rectangular with rounded edges represents an action,i.e. signal assignment or calculation, that is taken if an input condition is fulfilled. Condi-

tional output boxes are only used to depict Mealy-type outputs. The entry path to the

symbol is always from a decision symbol, but its exit path can be either to a state box or to

another decision symbol.


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Digital Systems

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AND COMPUTER SCIENCEASM Chart Representation of a Simple Moore-Type FSM

X=0

B

Z=0

A

Z=0

X=1

X=0

X=1X=0

X=1

C

Z=1

Reset

Transformation of a state

diagram


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Digital Systems

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0 1

10

0 1

ResetAssociated ASM chart for a Moore-Type FSM

Output signals Z = 0 are not depicted in order to

support transparency!


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Digital Systems

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AND COMPUTER SCIENCEASM Chart Representation of a simple Mealy-Type FSM

X=0 / Z=0

X=1 / Z=0

X=0 / Z=0

A

Reset

B X=1 / Z=1

It has to be checked which state is of Moore-type or Mealy-Type before transformation

can be performed.

State diagram


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AND COMPUTER SCIENCEAssociated ASM Chart


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Digital Systems

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AND COMPUTER SCIENCE3.2 FSM as a Server's Polling Circuit

A polling circuit for a client-server system with 3 clients has to determine which clientis to be serviced by a server of many clients.

A client i requests service by asserting its service-request flagRi to the client. In eachclock cycle the polling circuit polls its inputs Ri to determine whether service is being

requested and to identify the requesting client having the highest priority.

In general the client having the highest priority is to be serviced. As long as a clientrequests for service it will be granted by the polling circuit independently of other cli-

ent requests.

After a request flag Ri is deasserted the polling circuit will enter the polling state atleast for one clock cycle. No other client's concurrently asserted request will change

this FSM behaviour.


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Each client has a polling priority level: client0 > client1 > client2. The request Ri withthe highest priority is granted by the polling circuit with the corresponding grant bit

Gi. Only one bit Gi a time can be asserted.

The FSM states are called: IDLE, GNT0, GNT1,GNT2. In IDLE state no Gi is as-serted.

Start with a block diagram and decide which FSM type will be appropriate.


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Digital Systems

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AND COMPUTER SCIENCEState Diagram for the Polling Circuit

100

x10

Reset

GNT0GNT1

000

Idle

GNT2

State

G2 G1 G0

R2, R1, R0

xx1


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Digital Systems

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AND COMPUTER SCIENCEState Diagram with Transition Conditions

R0

Reset

R2R1R0

R2

R1 R2 R3

R1 R0R0 R1

IDLE

GNT0GNT1GNT2

G2 G1G0

R2 R1 R0


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GNT0

Idle

GNT1

GNT2

0

0

0

0

0

0

1

1

1

1

1

1

ASM Chart for the

Polling Circuit


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Digital Systems

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AND COMPUTER SCIENCEVHDL Code for the Polling Circuit

-- Polling circuit: client arbiterentity ar bi t er isport( CLK, RESET : in bi t ;

R: in bi t _vect or ( 2 downto 0) ; -- device requestsG: out bi t _vect or ( 2 downto 0)) ; -- device grants

endARBI TER;architecture BEHAVI OUR of ARBI TER istype STATE_TYPE is ( I DLE, GNT0, GNT1, GNT2) ; --

signal STATE, NEXT_STATE: STATE_TYPE;begin

REG: process( CLK, RESET)begin

if RESET = ' 1' then

STATE


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COMB_LOGI C: process( STATE, R)begin

G ' 0' ) ; -- default output signalscase STATE is

when I DLE =>if R( 0) =' 1' then NEXT_STATE


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AND COMPUTER SCIENCEwhen GNT2 =>

G( 2)


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AND COMPUTER SCIENCESimulation Result for the Polling Circuit


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CPLD Implementation of the Polling Circuit (Xilinx XC95108 PC84)

State encoding default for CPLDs: binary and sequential 2 D-flip-flops"STATE" := "R" * /"STATE".LFBK

+ "R" * "STATE".LFBK * "STATE".LFBK+ "R" * /"R" * /"STATE".LFBK * /"STATE".LFBK"STATE".CLKF = CLK"STATE".RSTF = RESET"STATE".PRLD = GND"STATE" := "R" * "STATE".LFBK * "STATE".LFBK+ "R" * /"R" * /"STATE".LFBK+ "R" * "STATE".LFBK * /"STATE".LFBK+ "R" * /"R" * /"STATE".LFBK * /"STATE".LFBK"STATE".CLKF = CLK"STATE".RSTF = RESET

"STATE".PRLD = GND Output forming logic:"G" = "STATE" * "STATE""G" = /"STATE" * "STATE""G" = /"STATE".LFBK * "STATE".LFBK

Association of state

bits and output sig-nals to function

blocks:

STATE: FB1/17

STATE: FB1/18

G0: FB1/2G1: FB3/2

G2: FB2/2

"Signal".LFBK

describes a generated

signal which is feed

back to the same func-

tion block.


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AND COMPUTER SCIENCEFPGA Implementation Xilinx XC4013XL PQ160


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AND COMPUTER SCIENCEConfigurable Logic Block (CLB)


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AND COMPUTER SCIENCE3.3 Shift and Add Multiplier; Data and Control Path

A binary multiplier has to be designed that will compute the 16 bit product of two 8bit unsigned binary numbers.

The multiplication algorithm is developed by first examining the "pencil and paper"algorithm. Consider the product of (1101)2 and (1011)2: Multiplier bits are examined sequentially from right to left. If the multiplier bit is 1,the partial product is the multiplicand, and if the multiplier bit is 0, the partial prod-

uct is simply 0000. Each new partial product is shifted one bit position to the left be-

fore adding it to the total.

Decimal:

13 Multiplicand

*11 Multiplier

13

13143 Product

Binary:1101 Multiplicand A

*1011 Multiplier B

1101

11010000110110001111 Product P


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Pseudo code to describe the binary multiplication: The binary multiplication is based on a

shift left register which has to be filled

with the multiplicand A and successive

adding of partial products.

The for loop will be realized with a shift right of B for each shift left of A. The multiplication procedure will be started by a signal S after two new operands A

and B have been loaded to registers with the signals LA and LB.

The shift and add procedure is finished if the B shift register is filled up with zeros.This will be indicated with the signal DONE.

P=0;

for i=0 to n-1 doif Bi=1 then

P = P+A;

end if;

Shift left A;

end for;


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AND COMPUTER SCIENCEASM Chart for the

Multiplier

Description of the

Operation!

0 1

0

00

1

1

1

S1

S2 S3


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AND COMPUTER SCIENCEDesign of the Multiplier Circuit

Device interfacing:

-- NxN serial Multiplier

library i eee;use i eee. st d_l ogi c_1164. al l ;use i eee. st d_l ogi c_unsi gned. al l ; -- unsigned number representation

entity MULTI PLI ER isgeneric( N: i nt eger : =8; NN: i nt eger : =16) ; -- input width, output width

port( CLK, RESET : in bi t ;LA, LB, S: in bi t ; -- load and start signalA, B: in st d_l ogi c_vect or ( N- 1 downto 0) ; -- N-bit operandsP: out st d_l ogi c_vect or ( NN- 1 downto 0) ; -- result with double widthDONE: out bi t ) ; -- status signal

endMULTI PLI ER;


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AND COMPUTER SCIENCEPartitioning of Digital Circuits

At the beginning a digital systems design flow the digital circuit will be partitioned into thecontrol logic and the data path section. It is appropriate to separate both parts because to

each part different design strategies and optimisation methods can be applied.

State Register

Next Stateand Output

Forming Logic

Data Path

ALU Steering - Memory

Control Signals

Data

Input

Control

Input

Status

Control Unit

Data

Output

Control

Output


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AND COMPUTER SCIENCE Partitioning a Systems belongs to Architectural SynthesisArchitectural synthesis means constructing a macroscopic structure of a digital

hardware. The process starts with behavioural models that are described by mathe-

matical equations and ASM charts.

The first outcome of architectural synthesis is the structural view of the hardware asa combination of two components: Data path section and the control logic section.

The data path section is an interconnection of resources which implement arithmeticand logic functions such as adders, multipliers, comparators, registers and steering

logic (multiplexers and busses) as well.

The control logic section consists of all logic required to generate control signals forALU functions. It receives status signals from the data path and sends back control

signals to the data path. Synchronous finite state machines usually build up the con-

trol unit.


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The second outcome of architectural synthesis is the placing of data path operations intime and place. That means determining the time interval for their execution and their

binding to resources. The interconnections of the data path to the sequence of control

unit operations have also to be determined.

The final result will be a so called register transfer level (RTL) description of compo-nents which consist of register models interconnected by combinational logic elements.

Typical HDL syntax elements which are used for this description style will be logic ex-

pressions (and, or) and behavioural decisions with if-then-else and case-when expres-sions.


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1

+

n

2n

n

n

2n 2n

2n

2n

SRG left SRG right

Register

A_INT P_INTB_INT

0 A B

P

CLK

0

LA LB

EA EB

PSEL B0Z

EP

SUM

MX_P Data path for the

multiplier


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AND COMPUTER SCIENCEThe components of the multipliers data path serve following functions:

Ashift left register that holds the multiplicand A has a width of2n bit. The upper n bitswill be initialised with '0's and a '0' is shifted in from the right (LSB) end (comp. the

paper and pencil example). A synchronous load of the shift left register is controlled bythe LA signal. Shifting will be enabled by the EA signal.

A 2n bit register holds the product P (result register). Partial products are stored undercontrol of a clock enable input EP

In combination with an 2n bitadderthe result register builds an partial product accu-mulator.

The result register P has to be initialised with zero in order to start with a second ad-dend equal to zero. This is realised with amultiplexer in the registers input path. A se-

lect signalPSEL performs the channel switching.


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AND COMPUTER SCIENCE The multiplier B is stored in a n bitshift right register. Synchronous load is controlled

by LB and shifting is enabled with EB. The LSB B0 is a status signal.

The product will be computed by adding the multiplicand to the current total in registerP when the tested multiplier bit B0 is 1. Instead of adding a partial product zero ( 2n'0's) to the total P when the multiplier bit '0' the addition step will simply be omitted.

The end of multiplication is indicated by B = '0' i.e. with NOR gate output Z.


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AND COMPUTER SCIENCEVHDL Model for the Data Path

architecture BHAVI OUR of MULTI PLI ER istype STATE_TYPE is ( S1, S2, S3) ; -- enumeration state typesignal STATE, NEXT_STATE: STATE_TYPE; --

signal P_I NT, SUM, MX_P: st d_l ogi c_vect or ( NN- 1 downto 0) ; -- data path signalssignal PSEL, Z, EA, EB, EP: bi t ; -- control- and status signalssignal ZEROS: st d_l ogi c_vect or ( N- 1 downto 0) ;signal B_I NT: st d_l ogi c_vect or ( N- 1 downto 0) ; -- multiplier shift right registersignal A_I NT: st d_l ogi c_vect or ( NN- 1 downto 0) ; -- multiplicand shift left reg.

begin-- ======================== data path ==========================

ZEROS ' 0' ) ;SHL_REG: process( CLK) -- shift left register

beginif CLK=' 1' andCLK' event then

if EA =' 1' thenif LA = ' 1' then -- synchronousload

A_I NT


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Digital Systems B. Schwarz 3-31



AND COMPUTER SCIENCESHR_REG: process( CLK) -- shift right register


if EB =' 1' thenif LB = ' 1' then -- synchronous load

B_I NT


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AND COMPUTER SCIENCEP_REG: process( CLK) -- result register


if EP=' 1' thenP_ I NT


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S1

S2 S3

000

0

0

111

1

1

RESET

1

Control unit

of the multiplier

i i f li d i h b


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AND COMPUTER SCIENCEComments on the Controller FSM

State S1: Initialisation of P with zeros: PSEL='0' (default) and EP='1'.Both shift register will be loaded if input signals LA and LB indicate a new multiplicand A

and a new multiplier B and start bit S is '0': Enable with EA and EB. A transition tostate S2 takes place if the start bit S is asserted.

State S2: Shifting in both input registers is enabled by asserted signals EA and EB. Anadder result SUM is connected to the output register with select bit PSEL equals '1'. No

adder result will be registered if the LSB B0 is '0'. A transition to state S3 is prepared by

Z='1' if all bits in input register B are zero.

State S3: Output status signal DONE is asserted. A return to the idle state S1 is con-trolled by start bit S='0'.

-- ========== control unit architecture continued ======================FSM_REG: process( CLK, RESET) -- state register

begin

if RESET = ' 1' thenSTATE


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COMB_LOGI C: process( STATE, S, Z, LA, LB, B_I NT( 0) )begin

EA


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AND COMPUTER SCIENCEif Z=' 0' then

NEXT_STATE


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AND COMPUTER SCIENCEVHDL Simulation Results of the Shift and Add Multiplier (0x64*0x19 = 0x9C4)

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