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Prof. Dr. J. Reichardt

Prof. Dr. B. Schwarz

Digital Systems 7-1 B.Schwarz

university of applied sciences hamburg

DEPARTEMENT OF ELECTRICAL ENGINEERING

AND COMPUTER SCIENCE

7 Synchronous FSM Design: Timing Considerations All introduced digital circuits

and systems have been describedat the "Register Transfer Level"(RTL): Signals are stored in reg-isters and combinational logicblocks are located between the

registers. All flip-flops of a synchronous system are clocked with one common triggering waveform

CLK.

External asynchronous reset and preset signals should be synchronised in order to avoidcoincidence with the clock signals transitions.

All other flip-flop resets or presets are controlled synchronously (i. e. by a FSM control-ler).

Digital systems designed by these criteria will work stable without oscillating effects and

won't be influenced seriously by any hazards:

comb. logic

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AND COMPUTER SCIENCE Manufacturers will guarantee flip-flop without hazards in output transitions. All glitches which are caused by race glitches during state transitions and static hazards

in output logic can be assumed to have a duration less than the clock period.

Up to this chapter the main concern and emphasis was concentrated on functional designand analysis issues: so called "front end" of digital system development.

Several timing considerations and problem areas were purposely avoided:1.The designer has to insure that no shift in the triggering clock edge of one flip-flop rela-

tive to another will exist (clock skew) which can cause erroneous transitions.2. All setup tSU and hold time tH requirements (sampling intervall tSU + tH) have to be

meet especially under clock skew influence.

3.External asynchronous input signals have to be synchronised with input flip-flops inorder to prevent metastableflip-flop states within the digital system. Metastable statesof synchronisers have to be prevented either.

Several of these activities belong to the "back end" design after having performed theRTL development.

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7.1 Timing Considerations in Synchronous Systems with a Data and Control PathA digital system can bepartitioned into the control

logic section and the datapath section: processormodule

The control logic sectionconsists of all the FSM

logic required to gene-rate control signals forthe data path section. Itreceives status signalsfrom the data path sec-tion.

The data path sectionconsists of all the logicused to store and trans-form data.

Control Signals

Control Signals

Control Signals

FSM

Controller

Data PathInput

DataProcessing

Data Path

Output

Data Input

Data OutputStatus Signals

Commands

Clock

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AND COMPUTER SCIENCETimingexample of a coupled control and data path

1.Shortly after the first positive clock edge the FSM controller has a transition to new validstate. The data path status signal registers concurrently deliver new values with a D flip-flop delay. (at 360 ns)

2.FSM Moore outputs are updated after a delay by the output forming logic. These controlsignals will influence the data path behaviour with the next clock edge. (at 380 ns)

3.The calculation results of the data path are updated at 400 ns.4.The next state forming logic of the FSM controller delivers new values at 430 ns. It is more

convenient to assume that in most cases data path logic will cause larger delays.

All signal updates have to be prepared before the sampling interval of the D flip-flopsbegins!

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AND COMPUTER SCIENCETiming example with sampling interval

Flip-flop output delay is always much larger than the hold time and therefore signalfeedback in sequential systems is possible.

positive slack

cl k

state

st at us si gnal s

cont r ol si gnal s

dat a output

next st at e

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7.2 Clock Distribution7.2.1 Clock SkewIn synchronous VLSI designs clock signals are fed to several thousands flip-flops, registersand synchronous RAMs bytes and the wire length of clock signals may exceed several me-ters. To achieve high system performance the clock frequency is often maximised. This com-

bination of large clock load and high clock frequency is the cause of large clock delays be-tween flip-flops relative to each other: Clock Skew.

Clock skew has to be less than the sum of all other data signal delays!

CLK CLK_D

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AND COMPUTER SCIENCETiming problem because of large clock skew

The second flip-flop has anerroneous output response q2= '1' because clock skew 20

ns is larger than 10 ns datadelay: The "new" data sam-ple will be clocked into theflip-flop by the "old" clock.

Data path delays will dependon each special applicationtherefore dedicated clock dis-tribution networks are pro-vided by FPGA and ASIChardware.

With "balanced clock tree"networks clock skew will beminimised and worst casevalues are guaranteed by manufactures.

TSkew correct

erroneous!

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AND COMPUTER SCIENCEBalanced clock tree

In the clock tree approach it is extremely important that the clock branches are equallyloaded: clock interfacing has to be symmetrically and low resistive, dedicated globalclock buffers (BUFG) are strong current drivers in order to ensure steep clock edges.

FPGAs designs are supported by an automatic clock tree synthesis with multiple clockdistribution networks.

In ASIC small clock drivers are placed at thebranches over the logic blocks, so they are rightthere where they are needed.

wrong correct

On chip

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7.2.2 Gated ClocksParticularly in low-power CMOS circuits some logic blocks may often be inactive for a certain periodsof time. Such a chip with different clock domains is controlled by a gated clock. In case of that no clockenable inputs are available the main clock is used as in-put to some function:

CLK_EN2: Problem: Hazards in the enable inputwill generate erroneous positive clock edges duringCLK = '0' .

CLK_EN1: A transparent D latch avoids this mal-function but it ha s to be initialised.

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7.2.3 Multiple Clock DomainsComplex VLSI designs are build up with certainlogic cores which may have different clock wave-

forms. Therefore multiple clocks have to be gen-erated by a main clock without relative delay(phase shift) in order to support syn-chronous behaviour.

Reduced clock frequencies can berealised with simple clock dividers.

As complex ICs require many dif-ferent clock domains multiple fre-quencies are generated on chip withphase-locked-loops (PLLs). ThePLL output frequency equals

f = fin n mi (n, mi > 1)[H.V.]

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7.2.4 Clock Phase SynchronisationBecause of differences in the clock arrival times at the flip-flops of different cores these de-lays must be compensated to allow proper communication between different cores.

The first method is adaptive skew control. The clock skew in each core is made equal tothe worst case clock skew by using a chain of inverters. The worst case has to be esti-mated by separate core timing simulations.

The PLL property oflocking phases of differentsignals can be used forcompensation of clockskew.

The clock phase at node Bwill be locked to the inputreference signal which isthe chips main clock[H.V.]. [H.V.] H. Veendrick: Deep-Submicron CMOS ICs. From Basics toASICs. Kluwer academic publishers, 2nd edition 2000

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7.3 Asynchronous InputsAn asynchronous input is one that can change logic levels at any time, particularly during the samplinginterval (decision window) established by the sampling signal clock (CLK):

Requests of external devices like keyboard inputs and interrupts. Communication and interfacing of synchronous systems which are under operation with different

clock frequencies.

All external inputs to D flip-flops, registers,counters and FSMs have to be synchronised to

the clock waveform by a special synchroniser cir-cuit. The input to the digital device's flip-flopmust meet the setup and hold time requirementsotherwise proper transitions cannot be guaran-teed and even the metastable state can be en-tered.

The metastable state lies somewhere between aset and a reset condition at midsupply. The timethe flip-flop spends in the metastable state tr iscalled the resolution time. It cannot be predictedwhich logic level will emerge following exit from the metastable state.

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7.3.1 Synchroniser for Long Pulses The preceding synchroniser is itself

subject to effects of metastabilitycaused by sampling itervall viola-

tion. The idea depicted here is that in the

event of synchroniser 1 should gometastable it would exit from me-tastable state long before synchro-niser 2 is triggered. This greatly re-

duces the probability that synchro-niser 2 will become metastable andcause malfunction of the connectedFSM.

The input e will be delayed by thesynchroniser up to two clock cycles.

Once a metastable event is triggeredthe probability of the output recov-ering to high or low level increasesexponentially with increased re-solved time tr.

setup-time

violation

Synchroniser flip-flops

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7.3.2 Synchroniser for Short PulsesThe narrow asynchronous pulse E

is first stretched by the pulsetriggered D flip-flop, then syn-chronised by the synchroniser.

The stretcher is reset asynchro-nously by the fed back synchro-niser output.

Without influence of the inputpulse duration the stretcher - syn-chroniser circuit always generatesan output pulse Q1 which willhave a high phase of one clock cy-cle.

Output Q1 may become metasta-ble and therefore another flip-flopshould be connected to Q1.

Stretcher Synchroniser

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7.3.3 Metastability and Mean Time Between Failure of Flip-FlopsThe expected time until the output of a single flip-flop with asynchronous data has a metastable eventthat lasts longer than tr is characterised by the following mean time between failures (MTBF) equation:

f : clock frequency of the flip-flop

a: asynchronous data frequencyT0: flip-flop constant representing the

time window during which changingdata invoke a failure

: flip-flop constant related to the set-tling time of a metastable event.Example: An interrupt input signal to a

microprocessor which operates with a clock frequency of f = 10 MHz will be synchronised with a 74LS74

type flip-flop. The asynchronous interrupts will appear with a data rate of a = 10

5

1/s . For an exit frommetastable state there will be aresolution timeof about:

tr = 1/f - tSU = 80 ns.

Failures will arise with MTBF(tr = 80 ns) = 3.6 1011s, so that wrong transitions my be expected within100 years.

MTBF trtr

T0 f a( )

exp( / )=

Family /ns T0/s tr/ns tSU/ns74LS74

74HCxx

XC95108-20

1.5

1.82

0.17

4.010-1

1.510-69.610-18

77.71

71.55

2.3

20

25

10

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7.3.4 Switch Debouncing CircuitThe use of push-button switches is a common problem in digital systems. The asynchronous input

signal often produce a phenomenon called switch bounce that derives from the mechanical structureof the witch and the nature ofthe contact surfaces: Multipleopen/close transitions occur.

Serious problem can result in aFSM if a high frequency clockcatches the bounce signals and

introduces false data. A RS latch with input pull up

resistors will latch the firstchange of signal value. Oscillat-ing inputs are suppressed be-

cause the state with a retainedoutput is forced.

Only bounce-free switches areallowed for clock inputs.

bouncing switch : contact noise

moved contact

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AND COMPUTER SCIENCE7.4 10 Recommendations for Digital System Design

(following J .F. Wakerly, Digital Design Principles; Prentice Hall 1990)

1. All state-machine outputs shall always be registered.

2. Use clock edge triggered registers never latches.

3. Inputs to FSMs including resets shall be synchronous.

4. Minimise skew of clock signals.

5. Beware of fast paths, because of delayed clock signal waveform.6. Cross clock domains with the greatest caution and synchronise the interfacing signals.7. Have no dead states in state-machines.8. Have no logic with unbroken-asynchronous feedback, in order to avoid the malfunction reports

from myriad of test engineers.

9. All decode logic must be crafted carefully - avoid asynchronicity.

10. Trust not thy simulator - it may be cheating with correct looking results.

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