Date post: | 02-Jun-2018 |
Category: |
Documents |
Upload: | omgcharlie12 |
View: | 214 times |
Download: | 0 times |
of 23
8/11/2019 Dl5 Arithmetic
1/23
8/11/2019 Dl5 Arithmetic
2/23
8/11/2019 Dl5 Arithmetic
3/23
ENGI 3861 Digital Logic
Arithmetic Devices - 3
- to add 2 SM values,xandy, to producez=x+y, a digital circuitwould need to execute the following logical procedure:
- to subtract, simply change sign ofy, soz=x+ ("y)
It turns out that this is more complex than necessary if we chooseanother representation for negative numbers.
8/11/2019 Dl5 Arithmetic
4/23
ENGI 3861 Digital Logic
Arithmetic Devices - 4
Twos Complement
Consider n-bit positive binary integerBof value < 2n"1:
"B represented as 2n"B
but 2n"B = (2
n"1 "B) + 1
= (111112"B) + 1= (complement each bit ofB) + 1 (*)
- leftmost bit indicates sign (0 $+ve, 1 $"ve), but is not asign bit as in signed magnitude
Two's complement representation:
+ve integer from 0 to +2n-1
"1
$same as unsigned binary representation with leftmost
bit set to 0
"ve integer from "2n-1to "1
$take 2s complement of +ve representation as per (*)
(a) What is the 10-bit 2s complement representation of +27?
(b) Find the 8-bit 2s complement representation of "106.
8/11/2019 Dl5 Arithmetic
5/23
ENGI 3861 Digital Logic
Arithmetic Devices - 5
(c) Consider the 6-bit 2s complement representation of a number:
1101002
What is the signed decimal value of the number?(This is a "ve number. To determine the magnitude, take 2s
complement.)
(d) Perform the 2s complement operation on the 8-bit 2scomplement representation of +0.
(e) Consider 2s complement representation: 100000002
Take the 2s complement of the number and determine thesigned decimal value of the number above.
8/11/2019 Dl5 Arithmetic
6/23
ENGI 3861 Digital Logic
Arithmetic Devices - 6
- to convert to decimal could use
D =
where bn-1bn-2b1b0is 2s complement representation.
e.g., 100101002 =
Note range of integers that can be represented by n-bit 2scomplement representation is:
"2n"1%D%+2
n"1"1
Convince yourself for n= 4!
One's Complement
Consider n-bit positive binary numberBof value < 2n"1:
"B represented as 2n"1 "B = (111112"B)
= complement each bit ofB
e.g., Take one's complement of
011010102 (+106) $ ("106)
000000002 (0) $ (0)
- positive numbers same as 2s complement and signed magnitude
- zero is either 00000 or 11111
- negation is easier than 2s complement but adder design is morecomplex.
8/11/2019 Dl5 Arithmetic
7/23
ENGI 3861 Digital Logic
Arithmetic Devices - 7
Twos Complement Addition and Subtraction
Consider n= 3
Signed Decimal 2s Complement"4 100
"3 101
"2 110
"1 111
0 000+ 1 001+ 2 010
+ 3 011
- counting up from "4 is equivalent to adding 1 in each step and
ignoring carry past MSB
- hence, addition in 2s complement
$add normally and toss out carry beyond MSB
e.g., 0 0 1 1 0 1 1 1 55+ 0 1 0 0 0 0 1 1 + 67
1 0 1 0 1 1 1 1 "81
+ 0 1 1 0 1 0 0 1 + 105
8/11/2019 Dl5 Arithmetic
8/23
ENGI 3861 Digital Logic
Arithmetic Devices - 8
- overflows can occur if two numbers of same sign are added
e.g.,
$if sign bit changes &overflow
- subtraction: z = x !y
subtrahendminuend
$negate subtrahend y(i.e., take 2s complement) and add to
minuendx
e.g.,
8/11/2019 Dl5 Arithmetic
9/23
ENGI 3861 Digital Logic
Arithmetic Devices - 9
- only one addition required ifyis complemented bit-by-bit andthen +1 used as carry-in
$2s complement is very efficient for addition/subtraction
Ones Complement Addition and Subtraction
- add normally and if there is a carry out of sign, then add +1(i.e., end-around carry)
e.g.,
- subtraction: complement subtrahend and add
(b) Binary Codes
- numbers, characters, and other data can be represented in n-bitcodewords or symbols
Binary Coded Decimal (BCD)
- represent each decimal digit by 4 bits
0 $0000, 1 $0001, , 8 $1000, 9 $1001
so 7310$01110011
- addition: if binary addition exceeds 9 (1001), add 6 (0110)
8/11/2019 Dl5 Arithmetic
10/23
8/11/2019 Dl5 Arithmetic
11/23
ENGI 3861 Digital Logic
Arithmetic Devices - 11
- parity is used to detect errors when data transmitted throughcommunications channel or retrieved from memory
e.g., Assume a system is using even parity and the word 11011101
which includes 1 parity bit (the leftmost bit) and 7 data bits(the rightmost 7 bits) is transmitted through a noisy
communications channel as follows:
$receiver is expecting a byte with an even parity and yet
the # ones in the received byte is odd &an error must
have occurred in at least one bit
What if errors occur in two bits? An even number of bits? An oddnumber of bits?
8/11/2019 Dl5 Arithmetic
12/23
ENGI 3861 Digital Logic
Arithmetic Devices - 12
ASCII (American Standard Code for Information Interchange)
- 7 bit code to represent numbers, letters, punctuation, etc..
$128 symbols in total
e.g., Character ASCII Codeword (hex)09 3039
AT 4154ai 6169} 7D$ 24+ 2B
etc.
- very common way to represent and store text
- often add parity bit as 8thbit
$can be used to look for errors in data recovered from
memory or transmitted through communication channel
- 8-bit ASCII codeword + parity #1 byte
$convenient data word
$most computer systems and digital systems with memory
have memory organized in bytes or multiples of bytes
(e.g., 32-bit words common in computers)
8/11/2019 Dl5 Arithmetic
13/23
ENGI 3861 Digital Logic
Arithmetic Devices - 13
(c) Adders, Subtractors, and ALUs
Adders
How do we add 2 unsigned binary numbers using digitalhardware?
recall process: 1 0 1 1 &each column requires 2 inputs1 1 0 1 plus carry in to produce
sum bit and carry out
Half Adder: (does not accept carry in)
XY S C
00
0110
11
8/11/2019 Dl5 Arithmetic
14/23
8/11/2019 Dl5 Arithmetic
15/23
ENGI 3861 Digital Logic
Arithmetic Devices - 15
Ripple Adder X3X2X1X0+ Y3Y2Y1Y0
- iterative circuit $simple but slow since carry needs to propagatethrough all FAs
- could make faster by using 2 level combinational logic butS3= f(X0, , X3, Y0, , Y3, C0)
&many gates, especially as adder size increases
Carry Lookahead Adder
concept:
8/11/2019 Dl5 Arithmetic
16/23
ENGI 3861 Digital Logic
Arithmetic Devices - 16
- we say that when stage iproduces a carry out (Ci+1= 1)independent of Ci, the carry is generated by:
Gi= Xi'Yi (not dependent on Ci)
- when stage iproduces a carry out (Ci+1= 1) because Ci= 1, wesay that the carry is propagated when:
Pi= Xi+ Yi (since if Xi= 1 or Yi= 1 producesCi+1= 1 if Ci= 1)
- so C1=
C2=
C3=
C4=
- each equation for Cihas 3 levels of delay: 1 for P/G and 2 forequations
- MSI adders such as 74x283 can use 4-bit CLA adder and thenlarger adders can use MSI adder as building block in iterative
(i.e., ripple) adder &group ripple adders
$see Figures 6.87 and 6.89
- generally faster but more and larger gates than ripple adder
8/11/2019 Dl5 Arithmetic
17/23
8/11/2019 Dl5 Arithmetic
18/23
ENGI 3861 Digital Logic
Arithmetic Devices - 18
- compare D / BOUT(to S / COUTfrom full adder
D = S =
BOUT(= COUT=
- equations similar with
CIN$BIN(, Y $Y(, and S $D, COUT$BOUT(
- so can build ripple subtractor using full subtractor similarly toripple adder using full adder
- alternatively, can use full adder to replace full subtractor
e.g., 4-bit ripple subtractor
- of course, to do subtraction, X "Y, using signed number
representation such as twos complement, simply need toconvert Y to 2s complement representation and add
8/11/2019 Dl5 Arithmetic
19/23
ENGI 3861 Digital Logic
Arithmetic Devices - 19
Arithmetic Logic Unit (ALU)
- MSI device to execute word-wise arithmetic or logical operations
e.g., 74x181 4-bit ALU$See Table 6.70 and Figure 6.90 in text.
(d) Parity Circuits
- recall 2-input XOR, F = X )Y
gate truth table
XY F
00 0
01 1
10 1
11 0
SOP circuit NANDs-only circuit
(Can you show?)
8/11/2019 Dl5 Arithmetic
20/23
ENGI 3861 Digital Logic
Arithmetic Devices - 20
- 3-input XOR, F = X )Y )Z
gate truth table
XYZ F000
001
010
011
100
101
110
111
F = 1 when XYZ have odd number of ones
&F #odd parity and F(#even parity
- 8-bit parity check
8/11/2019 Dl5 Arithmetic
21/23
ENGI 3861 Digital Logic
Arithmetic Devices - 21
(e) Comparators
Equality Comparator$compares 2 binary words for equality
- one approach:parallel comparator
- another approach: iterative comparator
IC will be slow since signals need to ripple through cascaded CMPcomponents
8/11/2019 Dl5 Arithmetic
22/23
ENGI 3861 Digital Logic
Arithmetic Devices - 22
Magnitude Comparator (An Iterative Design)
- determines if X > Y, when X and Y are 2 n-bit unsigned binary
numbers $building block is 1-bit magnitude comparator
8/11/2019 Dl5 Arithmetic
23/23
ENGI 3861 Digital Logic
$4-bit iterative magnitude comparator
- parallel 4-bit magnitude comparator design is achievable
$faster, but larger