281
MLR Institute of Technology Laxma Reddy Avenue, Dundigal, Quthbullapur (M), Hyderabad 500 043
Phone Nos: 08418 204066 / 204088, Fax : 08418 204088
Digital Logic Design
UNIT-I
1
A digital system is a system that manipulates discrete elements of information represented internally in binary form.
Digital computers general purposes many scientific, industrial and commercial applications
Digital systems telephone switching exchanges digital camera electronic calculators, PDA's digital TV
Digital Systems and Binary Numbers
2
Signal
An information variable represented by physical quantity For digital systems, the variable takes on discrete values
Two level, or binary values are the most prevalent values
Binary values are represented abstractly by: digits 0 and 1 words (symbols) False (F) and True (T) words (symbols) Low (L) and High (H) and words On and Off.
Binary values are represented by values or ranges of values of physical quantities
3
Binary Numbers
Decimal number
5 4 3 2 1 0 1 2 35 4 3 2 1 0 1 2 310 10 10 10 10 10 10 10 10a a a a a a a a a
a5a4a3a2a1.a1a2a3 Decimal point
3 2 1 07,329 7 10 3 10 2 10 9 10 Example:
jaBase or radix
Power
General form of base-r system 1 2 1 1 2
1 2 1 0 1 2n n m
n n ma r a r a r a r a a r a r a r
Coefficient: aj = 0 to r 1
Binary Numbers
Example: Base-2 number 2 10
4 3 2 1 0 1 2
(11010.11) (26.75)1 2 1 2 0 2 1 2 0 2 1 2 1 2
Example: Base-5 number
53 2 1 0 1
10
(4021.2)4 5 0 5 2 5 1 5 2 5 (511.5)
Example: Base-8 number 8
3 2 1 0 110
(127.4)1 8 2 8 1 8 7 8 4 8 (87.5)
Example: Base-16 number 3 2 1 0
16 10(B65F) 11 16 6 16 5 16 15 16 (46,687)
Binary Numbers Example: Base-2 number
2 10(110101) 32 16 4 1 (53) Special Powers of 2
210 (1024) is Kilo, denoted "K" 220 (1,048,576) is Mega, denoted "M" 230 (1,073, 741,824)is Giga, denoted "G"
Powers of two
Table 1.1
Arithmetic operation
Arithmetic operations with numbers in base r follow the same rules as decimal numbers.
Binary Arithmetic
Addition Augend: 101101 Addend: +100111
Sum: 1010100
Subtraction Minuend: 101101 Subtrahend: 100111
Difference: 000110
Multiplicand 1011 Multiplier 101 Partial Products 1011 0000 - 1011 - - Product 110111
Multiplication
Octal Numbering System (Base 8)
Eight allowable digits: 0, 1, 2, 3, 4, 5, 6, 7 Weighting factor of 8
9
Octal Conversions
Binary to octal Group binary positions in groups of three Write the octal equivalent
Octal to binary Reverse the process
Octal to decimal Multiply by weighting factors
Decimal to octal Successive division
10
Hexadecimal Numbering System (Base 16)
16 allowable digits. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F
Each hex digit represents a 4-bit group See Table 1-3
Two hex digits are used to represent 8 bits 8 bits are called a byte 4 bits are called a nibble
11
Hexadecimal Numbering System
12
Hexadecimal Conversions
Binary-to-hexadecimal conversion Group the binary in groups of four Write the equivalent hex digit
Hexadecimal-to-binary conversion Reverse the process
Hexadecimal-to-decimal conversion Multiply by weighting factors
Decimal-to-hexadecimal conversion Successive division
13
Octal and Hexadecimal Numbers Conversion from binary to octal can be done by positioning the binary
number into groups of three digits each, starting from the binary point and proceeding to the left and to the right.
Conversion from binary to hexadecimal is similar, except that the binary number is divided into groups of four digits:
(10 110 001 101 011 111 100 000 110) 2 = (26153.7406)8
2 6 1 5 3 7 4 0 6
Conversion from octal or hexadecimal to binary is done by reversing the preceding procedure.
14
Number systems and codes
Representation of numbers Decimal - Octal - Hexadecimal number systems Representation of negative numbers Complement of a number Binary arithmetic Binary codes for decimal numbers Error detecting and correcting codes
15
Representation of numbers
A number in base-r has coefficients multiplied by powers of r and is of the form
Range of aj is from 0 to r-1 r is also called radix of the number system If r = 2, binary number system If r = 8, octal number system If r = 16, hexadecimal number system
m
m
n
n
n
n rarararararara
......... 2211001111
Number base conversions
To convert a number in base r to decimal is done by expanding the number in a power series and adding all the terms
If the number includes a radix point, it is necessary to separate the number k into an integer part and a fraction part.
Decimal number is converted to number in base r by dividing the number and all successive quotients by r and accumulating the remainders.
17
Number base conversions
Example 1: Convert decimal 153 to octal
Example 2: Convert (0.6875)10 to binary
18
Complement of a number
Used for Simplifying subtraction Logical manipulation Two types Radix complement Diminished radix complement
19
Complement of a number
Diminished Radix complement Given a number N in base r having n digits, its diminished
radix complement is
Radix complement Given a number N in base r having n digits, its diminished
radix complement
Nrn )1(
1))1(( Nrn
Representation of negative numbers
Eg: Represent -9 using 8 bits in both Sign magnitude form and sign complement form
21
Sign magnitude form
The number consists of magnitude bits and a sign bit Used in ordinary arithmetic It is simple
Drawbacks: Hardware limitations Two representations of zero
22
Signed complement form
A negative number is represented by its complement positive numbers always start with 0 in the leftmost position. The complement will always start with a 1, indicating a
negative number.
23
Binary arithmetic
Addition Subtraction Multiplication
Addition Similar to normal decimal addition Rules of addition: 1 + 1 = 0 CY = 1 1 + 0 = 0 + 1 = 1
24
Binary subtraction
The subtraction of two n-digit unsigned numbers M - N in base r can be done as follows:
1. Add the minuend M to the r's complement of the subtrahend N. Mathematically, M + (rn - N) = M - N + rn
2. If M >= N. the sum will produce an end carry rn which can be discarded. what is left is the result M - N.
3. If M < N. the sum does not produce an end carry and is equal to rn - (N - M) which is r's complement of (N - M).
4. To obtain the answer, take the r's complement of the sum and place a negative sign in front.
25
Binary subtraction
Eg: Perform the subtraction a) X Y and b) Y X if X = 1010100 and Y = 1000011 using twos complement form.
There is no end carry so the answer is (twos complement of 1101111)
26
Binary multiplication
Just like normal decimal multiplication Eg: Find (1 0 1)2 (1 1 0)2
27
Floating Point Numbers
In the decimal system, a decimal point (radix point) separates the whole numbers from the fractional part
Examples: 37.25 ( whole=37, fraction = 25) 123.567 10.12345678
28
Floating Point Numbers
For example, 37.25 can be analyzed as:
101 100 10-1 10-2
Tens Units Tenths Hundredths 3 7 2 5
37.25 = 3 x 10 + 7 x 1 + 2 x 1/10 + 5 x 1/100
29
Given the following binary representation:
37.2510 = 100101.012
7.62510 = 111.1012
0.312510 = 0.01012
How we can represent the whole and fraction part of the binary rep. in 4 bytes?
30
Solution is Normalization
Every binary number, except the one corresponding to the number zero, can be normalized by choosing the exponent so that the radix point falls to the right of the leftmost 1 bit.
37.2510 = 100101.012 = 1.0010101 x 25
7.62510 = 111.1012 = 1.11101 x 22
0.312510 = 0.01012 = 1.01 x 2-2
31
So what Happened ?
After normalizing, the numbers now have different mantissas and exponents.
37.2510 = 100101.012 = 1.0010101 x 25
7.62510 = 111.1012 = 1.11101 x 22
0.312510 = 0.01012 = 1.01 x 2-2
32
IEEE Floating Point Representation
Floating point numbers can be represented by binary codes by dividing them into three parts:
the sign, the exponent, and the mantissa.
1 2 9 10 32
33
IEEE Floating Point Representation
The first, or leftmost, field of our floating point representation will be the sign bit: 0 for a positive number, 1 for a negative number.
34
IEEE Floating Point Representation
The second field of the floating point number will be the exponent.
Since we must be able to represent both positive and negative exponents, we will use a convention which uses a value known as a bias of 127 to determine the representation of the exponent. An exponent of 5 is therefore stored as 127 + 5 or 132; an exponent of -5 is stored as 127 + (-5) OR 122.
The biased exponent, the value actually stored, will range from 0 through 255. This is the range of values that can be represented by 8-bit, unsigned binary numbers.
35
Binary codes for decimal numbers
A binary number of n digits gives 2n distinct combinations which can be used to represent distinct group of quantities
Different binary codes available are weighted codes, un-weighted codes, self- complementing codes, reflecting codes
Weighted codes: Each bit position is assigned a weighing factor and each digit is evaluated by adding the weights of all the ones in the coded combination
Eg: BCD code, 2-4-2-1 code, (8, 4,-2,-1) code, etc
36
Binary codes for decimal numbers
Un-weighted codes: Weight is not assigned to the bit positions Eg: Excess-3 code
Self complementing code: 9s complement of the decimal number is obtained by changing 1s to 0s and viceversa.
Eg: 2-4-2-1 code, Excess-3 code
37
BCD CODE
Decimal numbers 0 9 can be represented using 4 bits. There are 6 unused combinations in this coding scheme.
38
Different binary codes for decimal numbers
39
Gray Code
Reflection code Advantage of Gray code
over the straight binary number sequence is that only one bit in the code group changes in going from one number to the next.
40
ASCII Character code
The American Standard Code for Information Interchange ASCII was suggested in 1968
Represents alphanumeric character set. Uses 7 bits to represent 128 characters There are special symbols which can be represented by this
code The coding is given in next slide
41
42
Error detection and correction
Error detection and correction code An error-correcting code generates multiple parity check bits that
are stored with the data word in memory. Each check bit is a parity over a group of bits in the data word
When the word is read back from memory, the associated parity bits are also read back and compared with a new set of check bits generated from the data that have been read lf the check bits are correct, no error has occurred.
If the check bits do not match the stored parity, they generate a unique pattern, called a syndrome, that can be used to identify the bit that is in error.
A single error occurs when a bit changes in value from 1 to 0 or from 0 to 1 during the write or read operation.
If the specific bit in the error is misidentified, then the error can be corrected by complementing the erroneous bit.
43
Parity
Simplest form of error detection is achieved by using parity bits.
A parity bit is an extra bit included with a message to make the total number of 1's either even or odd.
Eg:
44
Hamming code
k parity bits are added to an n-bit data word forming a new word of n + k bits.
The bit positions are numbered in sequence from 1 to n + k.
The relation between the number of message bits and parity bits is
Those positions numbered as a power of 2 are reserved for the parity bits
The remaining bits are the data bits
45
Hamming code
Construction of hamming code for 11000100
Calculating parity bits
46
Hamming code Message bit sequence
Calculation of check bits
Message sequences with no error, error in bit 1 and error in bit 5
Calculation of check bits for the above message sequences
47
Binary Logic
Definition of Binary Logic Binary logic consists of binary variables and a set of logical operations. The variables are designated by letters of the alphabet, such as A, B, C, x, y, z, etc, with
each variable having two and only two distinct possible values: 1 and 0, Three basic logical operations: AND, OR, and NOT.
48
Logic Operators
AND
NAND (Not AND) x y NAND 0 0 1 0 1 1 1 0 1 1 1 0
x y AND 0 0 0 0 1 0 1 0 0 1 1 1
xy x y
xy x y
49
Logic Operators OR
NOR (Not OR)
x y OR 0 0 0 0 1 1 1 0 1 1 1 1
x y NOR 0 0 1 0 1 0 1 0 0 1 1 0
xy x + y
xy x + y
50
Logic Operators
XOR (Exclusive-OR)
XNOR (Exclusive-NOR) (Equivalence)
x y XOR 0 0 0 0 1 1 1 0 1 1 1 0
x y XNOR 0 0 1 0 1 0 1 0 0 1 1 1
xy
x yx y
x y + x y
xy x y x y + x y
51
Logic Operators
NOT (Inverter)
Buffer
x NOT
0 1
1 0
x Buffer 0 0
1 1
x x
x x
52
Basic Definitions
Binary Operators AND
z = x y = x y z=1 if x=1 AND y=1 OR
z = x + y z=1 if x=1 OR y=1 NOT
z = x = x z=1 if x=0 Boolean Algebra
Binary Variables: only 0 and 1 values Algebraic Manipulation
53
Boolean Algebra Postulates
Commutative Law x y = y x x + y = y + x
Identity Element x 1 = x x + 0 = x
Complement x x = 0 x + x = 1
54
Boolean Algebra Theorems
Duality The dual of a Boolean algebraic expression is
obtained by interchanging the AND and the OR operators and replacing the 1s by 0s and the 0s by 1s.
x ( y + z ) = ( x y ) + ( x z ) x + ( y z ) = ( x + y ) ( x + z )
Theorem 1 x x = x x + x = x
Theorem 2 x 0 = 0 x + 1 = 1
Applied to a valid
equation produces a
valid equation
55
Boolean Algebra Theorems
Theorem 3: Involution ( ) = x ( x ) = x
Theorem 4: Associative & Distributive ( x y z = x y z ) ( x + y ) + z = x + ( y + z ) x y + z ) = ( x y ) + ( x z ) x + ( y z ) = ( x + y x + z )
Theorem 5: DeMorgan ( x y ) = + ( x + y ) = ( x y ) = x + y ( x + y ) = x y
Theorem 6: Absorption x x + y ) = x x + ( x y ) = x
56
Operator Precedence
Parentheses ( . . . ) ( . . .)
NOT x + y
AND x + x y
OR
])([ xwzyx
])([)()()()(
xwzyx
xwzy
xwz
xw
xw
57
DeMorgans Theorem
)]([ edcba )]([ edcba ))(( edcba ))(( edcba
))(( edcba )( edcba
58
Boolean Functions
Boolean Expression Example: F = x + y z
Truth Table All possible combinations of input variables
Logic Circuit
x y z F
0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1
x
yz
F
59
Algebraic Manipulation
Literal: A single variable within a term that may be complemented or not.
Use Boolean Algebra to simplify Boolean functions to produce simpler circuits
Example: Simplify to a minimum number of literals F = x + x y ( 3 Literals) = x + ( x y ) = ( x + x ) ( x + y ) = ( 1 ) ( x + y ) = x + y ( 2 Literals)
Distributive law (+ over )
60
Complement of a Function
DeMorgans Theorm
Duality & Literal Complement
CBAF CBAF
CBAF
CBAF CBAF CBAF
61
Canonical Forms
Minterm Product (AND function) Contains all variables Evaluates to 1 for a
specific combination Example A = 0 A B C B = 0 (0) (0) (0) C = 0
1 1 1 = 1
A B C Minterm 0 0 0 0 m0 1 0 0 1 m1 2 0 1 0 m2 3 0 1 1 m3 4 1 0 0 m4 5 1 0 1 m5 6 1 1 0 m6 7 1 1 1 m7
CBACBACBACBACBACBACBACBA
62
Canonical Forms Maxterm
Sum (OR function) Contains all variables Evaluates to 0 for a
specific combination Example A = 1 A B C
B = 1 (1) + (1) + (1)
C = 1
0 + 0 + 0 = 0
A B C Maxterm 0 0 0 0 M0 1 0 0 1 M1 2 0 1 0 M2 3 0 1 1 M3 4 1 0 0 M4 5 1 0 1 M5 6 1 1 0 M6 7 1 1 1 M7
CBA CBA CBA CBA CBA CBA CBA CBA
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Canonical Forms
Truth Table to Boolean Function A B C F 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1
CBAF CBA CBA ABC
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Canonical Forms
Sum of Minterms
Product of Maxterms
A B C F 0 0 0 0 0 1 0 0 1 1 2 0 1 0 0 3 0 1 1 0 4 1 0 0 1 5 1 0 1 1 6 1 1 0 0 7 1 1 1 1
ABCCBACBACBAF 7541 mmmmF
)7,5,4,1(F
CABBCACBACBAF CABBCACBACBAF CABBCACBACBAF
))()()(( CBACBACBACBAF 6320 MMMMF
(0,2,3,6)F
F 1 0 1 1 0 0 1 0
65
Standard Forms
Sum of Products (SOP)
ABCCBACBACBAF
ACBBAC
)(
CBAACB
)(
BA
BA
CCBA
)1(
)(
)()()( BBACCCBAAACBF ACBACBF
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Standard Forms
Product of Sums (POS)
)( AACB )( BBCA
)( CCBA
)()()( AACBCCBABBCAF CBBACAF
CABBCACBACBAF
))()(( CBBACAF 67
UNIT II
Gate-Level Minimization and
combinational circuits
68
69
Gate-Level Minimization
The Boolean functions also can be simplified by map method as Karnaugh map or K-map.
The map is made up of squares, with each square representing one minterm of the function.
This produces a circuit diagram with a minimum number of gates and the minimum number of inputs to
the gate.
It is sometimes possible to find two or more expressions that satisfy the minimization criteria.
70
Two-Variable map
Two-variable has four minterms, and consists of four squares.
m1 + m2 + m3 = xy + xy + xy = x + y
71
Three-Variable map
Note that the minterms are not arranged in a binary sequence, but similar to the Gray code.
For simplifying Boolean functions, we must recognize the basic property possessed by adjacent squares.
m5+m7= xyz + xyz = xz(y + y) = xz y
cancel
72
Simplification of the number of adjacent
squares
A larger number of adjacent squares are combined, we obtain a product term with fewer literals.
1 square = 1 minterm = three literals.
2 adjacent squares = 1 term = two literals.
4 adjacent squares = 1 term = one literal.
8 adjacent squares encompass the entire map and produce a
function that is always equal to 1.
It is obviously to know the number of adjacent squares is combined in a power of two such as 1,2,4, and 8.
73
Example
Ex. 3-3 F, , z = , , , ,
F = z + xy
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Four-variable map
1 square = 1 minterm = 4 literals
2 adjacent squares = 1 term = 3 literals
4 adjacent squares = 1 term = 2 literals
8 adjacent squares = 1 term = 1 literal
16 adjacent squares = 1
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Example
Ex. 3-6 F = ABC + BCD + ABCD + ABC = BD BC + ACD +
76
Essential prime implicants
If a minterm in a square is covered by only one prime
implicant, that the prime
implicant is said to be
essential.
77
Prime implicant
A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map.
This shows all possible ways that the three minterms(m3,m9,m11) can be covered with prime implicants.
F = BD+BD+CD+AD = BD+BD+CD+AB = BD+BD+BC+AD = BD+BD+BC+AB
78
Five-variable map
Fig.3-12, the left-hand four-variable map represents the 16 squares where A=0, and the other four-variable map represents the squares where A=1.
In addition, each square in the A=0 map is adjacent to the corresponding square in the A=1 map.
79
Five-variable map
It is possible to show that any 2k adjacent squares, for k=(0,1,2,,n) in an n-variable map, will represent an area that gives a ter of k literals(n>k). When n=k, it is identity function.
80
example
Ex. 3-7 F(A, B, C, D, E) = (0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31)
Because of both parts of the map have the common term (ABDE+ABDE) so the sum of products is
F = ABE + BDE + ACE
common
81
Product of sums simplification
If we mark the empty squares by 0s rather than 1s and combine them into valid adjacent squares, we obtain
the complement of the function, F. Use the DeMorgans theorem, we can get the product of sums.
Ex.3-8 Simplify the Boolean function in
(a) sum of products
(b) product of sums
FA, B, C, D = , , , , , ,
82
Example
(a) SOPs
F=
(b) POSs
F= By DeMorgans thm F=
BD + BC + ACD
AB + CD + BD
(A+B) .(C+D) .(B+D)
83
Gate implementation
84
Exchange minterm and maxterm
Consider the truth table that defines the function F
in Table 3-2.
Sum of minterms
F, , z = , , , Product of maxterms
F, , z = , , , In the other words, the s
of the function represent
the minterms, and the s represent the maxterms.
85
Dont care conditions Ex.3-9 iplif the F , , , z= , , , , ith dont-are oditios d, , , z = , , In part (a) with minterms 0 and 2 F = z + In part (b) with minterm 5 F = z + z
86
NAND and NOR implementation
NAND gate is a universal gate because any digital system can be implemented with it.
NAND gate can be used to express the basic gates, NOT, AND, and OR.
87
Two graphic symbols for NAND gate
In part (b), we can place a bubble (NOT) in each input and apply the DeMorgans theorem, then get a Boolean function in NAND type.
88
Two-level implementation
F = AB + CD Double
complementation, so
can be removed
=
OR
gate,Fig.3-18
89
Multilevel NAND circuits
To convert a multilevel AND-OR diagram into an all-NAND diagram using mixed notation is as follows:
1. Convert all AND gates to NAND gates with AND-invert graphic
symbols.
2. Convert all OR gates to NAND gates with invert-OR graphic
symbols.
3. Check all the bubbles in the diagram. For every bubble that is
not compensated by another small circle along the same line,
insert an inverter or complement the input literal.
90
Multilevel NAND circuits
,
,
91
NOR implementation
The NOR operation is the dual of the NAND operation, all procedures and rules for NOR logic are the dual of NAND logic.
NOR gate is also a universal gate.
92
Two graphic symbols for NOR gate
In part (b), we can place a bubble (NOT) in each input and apply the DeMorgans theorem, then get a Boolean function in NOR type.
93
Implementing F with NOR gates
F = (AB + AB)(C + D) To compensate for the bubbles in four inputs, it is
necessary to complement the corresponding input
literals.
94
Other two-level implementations
Some NAND or NOR gates allow the possibility of a
wire connection between
the outputs of two gates to
provide a wired logic.
Open-collector TTL NAND gates, when tied together,
perform the wired-AND
logic (Fig.3-28).
The wired-AND gate is not a physical gate.
Wired-And
95
Nondegenerate forms
We consider four types of gates: AND, OR, NAND, and NOR. These will have 16 combinations of two-level forms.
Eight of these combinations are said to be degenerate forms, because they degenerate to a single operation.
The other eight nondegenerate forms produce an SOPs or POSs as follows:
AND-OR 3-4 OR-AND 3-4 NAND-NAND 3-6 NOR-NOR 3-6 NOR-OR NAND-AND
OR-NAND AND-NOR
96
AND-OR-INVERT implementation
The two forms NAND-AND and AND-NOR are equivalent forms and can be treated together.
F = (AB + CD + E)
Shift back
97
OR-AND-INVERT implementation
The OR-NAND form resembles the OR-AND form, except for the inversion done by the bubble in the NAND gate.
F = [(A + B)(C + D)E]
Shift back
98
Example
Ex.3-11 Implement the function of Fig.3-31(a) with the four two-level forms listed in Table 3-3.
The complement of the function by combining the 0s: F = xy + xy + z The normal output for this function
F = (xy + xy + z) Which is in the AND-OR-INVERT form.
99
Example
The AND-NOR and NAND-AND implementations are shown as follows.
100
Example
The OR-AND-INVERT forms require a simplified expression of the complement of the function in POSs.
Combine the 1s in the map F = xyz + xyz Complement of the function
F = (x + y + z)(x + y + z)
101
Example
The normal output F
F = (x + y + z)(x + y + z)] We can implement the function in the OR-NAND and NOR-OR forms
as follows.
102
Exclusive-OR function
The XOR symbol denote as , the Boolean operation: x = +
The X-NOR symbol denote as , the Boolean operation: x y = (x = +
The identities of the XOR operation: x 0 = x x = x x = 0 x = x = y = (x Commutative and associative: A B = B A (A B) C = A (B C) = A B C
103
Exclusive-OR implementations
Fig.3-32(b), the first NAND gate performs the operation (xy) = (x + y). (x + y)x + (x + y)y = xy + xy = x y
104
Odd function
Boolean expression of three-variable of the XOR: A B C = (AB + AB)C + (AB + AB)C
= ABC + ABC + ABC + ABC =, , , Odd function defined as the logical sum of the 2n/2 minterms whose
binary numerical values have an odd number of 1s.
105
Odd and Even functions
The 3-input odd function is implemented by means of 2-input exclusive-OR gates.
UNIT III
Combinational Circuits
106
Combinational Circuits
Designing Combinational Circuits
In general we have to do following steps:
1. Problem description
2. Input/output of the circuit
3. Define truth table
4. Simplification for each output
5. Draw the circuit
Binary adder
Binary adder that produces the arithmetic sum of binary numbers can be constructed
with full adders connected in cascade, with
the output carry from each full adder
connected to the input carry of the next full
adder in the chain
Note that the input carry C0 in the least significant position must be 0.
Binary Adder
Binary Adder
For example to add A= 1011 and B= 0011 subscript i: 3 2 1 0
Input carry: 0 1 1 0 Ci
Augend: 1 0 1 1 Ai
Addend: 0 0 1 1 Bi
--------------------------------
Sum: 1 1 1 0 Si
Output carry: 0 0 1 1 Ci+1
Binary Subtractor
The subtrcation A B can be done by taking the s opleet of B ad addig it to A because A- B = A + (-B)
It eas if e use the ieters to ake s complement of B (connecting each Bi to an inverter) and then add 1 to the least significant bit (by setting carry C0 to 1) of binary adder, then we can make a binary subtractor.
it s opleet utrator
= 1
Adder/Subtractor
The addition and subtraction can be combined into one circuit with one common binary
adder (see next slide).
The mode M controls the operation. When M=0 the circuit is an adder when M=1 the
circuit is subtractor. It can be don by using
exclusive-OR for each Bi and M. Note that 1 = ad x = x
Checking Overflow
Note that in the previous slide if the numbers considered to be signed V detects overflow. V=0 means no overflow and V=1 means the result is wrong because of overflow
Overflow can be happened when adding two numbers of the same sign (both negative or positive) and result can not be shown with the available bits. It can be detected by observing the carry into sign bit and carry out of sign bit position. If these two carries are not equal an overflow occurred. That is why these two carries are applied to exclusive-OR gate to generate V.
Magnitude Comparator
It is a combinational circuit that compares to numbers and determines their relative magnitude
The output of comparator is usually 3 binary variables indicating: A>B
A=B
A
Comparators For a 2-bit comparator we have four inputs A1A0 and B1B0 and three
output E ( is 1 if two numbers are equal) G (is 1 when A > B) and L (is 1
when A < B) If we use truth table and KMAP the result is
E= AABB + AABB + AABB + AABB or E=(( A0 B0) + ( A1 B)) (see next slide) G = AB + ABB + AAB L= AB + AAB + ABB
Comparator
A0
A1
B0
B1
E
G
L
Magnitude Comparator
Here we use simpler method to find E (called X) and G (called Y) and L (called Z)
A=B if all Ai= Bi Ai Bi Xi
------------
0 0 1
0 1 0
1 0 0
1 1 0
It eas X = AB + AB ad X= AB + AB If X0=1 and X1=1 then A0=B0 and A1=B1
Thus, if A=B then X0X1 = 1 it means
X= AB + ABAB + AB sie = + X= ( A0 B A B = ( A0 B0) + ( A1 B It means for X we can NOR the result of two exclusive-OR gates
Magnitude Comparator
A>B means A1 B1 Y1 ------------
0 0 0
0 1 0
1 0 1
1 1 0
if A1=B1 (X1=1) then A0 should be 1 and B0 should be 0
A0 B0 Y0
------------
0 0 1
0 1 0
1 0 0
1 1 0
For A> B: A1 > B1 or A1 =B1 and A0 > B0
It eas Y= AB + XAB should e for A>B
Magnitude Comparator
For B>A B1 > A1 or
A1=B1 and B0> A0
z= AB + XAB The procedure for binary numbers with more than 2 bits can
also be found in the similar way. For example next slide shows the 4-bit magnitude comparator, in which
(A= B) = x3x2x1x0
A> B = AB + AB + AB+ AB A< B = AB + AB + AB+ AB
Decoder
Is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines For
example if the number of input is n=3 the number of output
lines can be m=23 . It is also known as 1 of 8 because one
output line is selected out of 8 available lines:
3 to 8
decoder
enable
Decoder with Enable Line
Decoders usually have an enable line, If enable=0 , decoder is off. It means all output
lines are zero
If enable=1, decoder is on and depending on input, the corresponding output line is 1, all
other lines are 0
See the truth table in next slide
Truth table for decoder
E a2 a1 a0 D7 D6 D5 D4 D3 D2 D1 D0
-----------------------------------------------------------
0 x x x 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1
. .. 1
1
1 1 1 1 1 0 0 0 0 0 0 0
Major application of Decoder
Decoder is use to implement any combinational cicuits ( fn ) For eaple the truth tale for full adder is s ,,z = ,,, ad C,,z= ,,,. The ipleetatio ith deoder is:
Encoder Encoder is a digital circuit that performs the inverse
operation of a decoder
Generates a unique binary code from several input lines.
Generally encoders produce2-bit, 3-bit or 4-bit code. n bit encoder has 2n input lines
2 bit encoder
2-bit encoder
If one of the four input lines is active encoder produces the binary code corresponding to
that line
If more than one of the input lines will be activated or all the output is undefined. We
a osider dot are for these situatios but in general we can solve this problem by
using priority encoder.
2-bit Priority Encoder
A priority encoder is an encoder circuit that includes priority function.
It means if two or more inputs are equal to 1 at the same time, the input having higher subscript number, considered as a higher priority. For example if D3 is 1 regardless of the value of the other input lines the result of output is 3 which is 11.
If all inputs are 0, there is no valid input. For detecting this situation we considered a third output named V. V is equal to 0 when all input are 0 and is one for rest of the situations of TT.
2-bit Priority Encoder
By using TT and K-map we get following boolean functions for 4-input (or 2-bit)
priority encoder:
X = D2 + D3 Y = D + DD V= D0 + D1 + D2 + D3 See next two slides for K-maps and the logic
circuit of 2-bit priority encoder
Multiplexer
It is a combinational circuit that selects binary information from one of the input lines and directs it
to a single output line
Usually there are 2n input lines and n selection lines whose bit combinations determine which input line
is selected
For example for 2-to-1 multiplexer if selection S is zero then I0 has the path to output and if S is one I1
has the path to output (see the next slide)
Uses of Multiplexers
Used in data communications for several computers to communicate over 1 line
Used in radio to select one channel from many Used to route data within a computer Used for function generation
2-to-1 multiplexer
Boolean function Implementation
Another method for implementing boolean function is using multiplexer
For doing that assume boolean function has n variables. We have to use multiplexer with n-1 selection lines and
1- first n-1 variables of function is used for data input
2- the remaining single variable ( named z )is used for data iput. Eah data iput a e z, z, or . From truth table we have to find the relation of F and z to be able to design input lines. For example : f,,z = ,,,
F A,B,C,D = ,,,,,,,
147
Demultiplexers
A demultiplexer has
N control inputs 1 data input 2N outputs
A demultiplexer routes (or connects) the data input to the
selected output.
The value of the control inputs determines the output that is selected.
A demultiplexer performs the opposite function of a
multiplexer.
148
Demultiplexers
A B W X Y Z 0 0 I 0 0 0 0 1 0 I 0 0 1 0 0 0 I 0 1 1 0 0 0 I
W = A'.B'.I X = A.B'.I Y = A'.B.I Z = A.B.I
Out0
In
S1 S0
I
W X Y Z
A B
Out1
Out2
Out3
UNIT IV
Synchronous & Asynchronous
Sequential Circuits
149
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Sequential Circuits
Most digital systems like digital watches, digital phones, digital computers, digital traffic light
controllers and so on require memory elements
Memory elements are digital circuits that can store and retrieve data in the form of 1's and 0's.
The output of the systems with memory depends not only on present inputs but also on what has
happened in the past
SR latch is an example of memory circuits that can store one bit of information
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SR Latch
When SR latch is storing a 1 then its Q is 1 and when storing 0 its Q is 0
R Q
Q
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SR Latch
1. If SR=10 then Q=1 and the latch is storing a 1, We call this setting the Latch.
2. If SR =10 and we change to SR=00 then the latch will remain set with Q= 1. In other words it "remembers" to stay set
3. If SR=01 then Q=0 and the latch is storing a 0. We call this resetting or Clearing the latch
4. If SR =01 and we change to SR=00 then the latch will remain set with Q= 0.
We call the value of Q at any given time the state of the latch
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SR Latch
The circuit (in next slide) with NOR gates is able to do this because of the feedback from the output back to
the input
Note that both Q and Q' are "brought back" and connected to the inputs of the NOR gates
If both S (set) and R (reset) are 1 an undefined state with both output equal to 0 occurs ( it means the SET
and RESET commands are issuing at the same time).
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SR Latch
The SR latch with two cross-coupled NAND gate is shown in next slide.
By setting S to 0 the output Q will be 1 that putting the latch in the set state
If S goes to 1 the circuit remains in set state By setting R to 0 the circuit goes to reset state and
stay there even after both input returns to 1
The undefined state is when both input are 0 Because NAND latch requires 0 signal to change its
state it is also alled -R lath
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Synchronous vs. Asynchronous
The behavior of a synchronous sequential circuit depends upon the any input signal at any instant of time and order of input change. This synchronization is achieved by clock generators that provides clock pulses (see the next slide). The storage elements used in clocked sequential circuits are called flip-flops.
In asynchronous sequential circuits the storage elements are time delay devices (i.e., storage is because of their propagation delay). They implemented by feedback that may cause instability in Asynchronous circuits.
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CPS213 160
D latch is designed to eliminate the indeterminate state in SR latch
by making sure that inputs S and R are never equal to 1 at the same time
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JKFF
The JK flip-flop is an SRFF with some additional gating logic on the inputs in which the SR=11 udeteried oditio doest eist
J is used for the set and K is used for reset J K Q
-------------------
0 0 Q
0 1 0
1 0 1
Q
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TFF
By connecting K and J we can make TFF Qt T Qt + 1
----------------------
0 0 0
0 1 1 Qt
Qt 1 1 0
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CPS213 164
Edge-Triggered vs. Level sensitive
ET FF: Transition (output change) can happen only during clock pulse transition
Clock pulse transition can be positive clock transition or negative clock transition
Level Sensitive FF: as long as the pulse level is up or down output can change
Level sensitive clock is less favorite because depending on the duration of pulse, output may
change a number of times
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Master-Slave FF (Edge-Trigger FF)
Is a combination of 2 FFS. The first FF is master and responds to positive level of clock
The 2nd FF is slave and responds to negative level of clock
Therefore, the final output changes only during 1 to 0 transition of clock. It means during the
duration of clock pulses changes in input do
not have effect on output.
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Analysis of Clocked Sequential Circuits
The behaviour of circuit can be described by state equation
For example for the circuit (next slide) the state equations are as the follows:
A(t+1) = A(t)x(t) + B(t)x(t)
Bt+= At. t = Bt + At.t
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State Table
The time sequence of inputs, outputs and flip-flop states can be enumerated in a state table or transition table
In the state table the present state that shows the state of flip flops comes first. So n flip flops need n present states. The inputs, next state and output come after.
The combination of present state and inputs makes state table. Output and next state can be derived from the state equations
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State Table
There are two types of for state tables:
Mealy Model: In this model sequential circuit or state table the outputs depends on inputs as well as states
Moor Model: Where output depends on state. For example 2-D version of state table for previous circuit. Where there are only 4 different states and for each state the next states and outputs should be found based on the given inputs.
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State Diagram
Is the graphically representation of state table. Each state should be circled so for example if we have n
flip flops we have 2n states or n circles
Each circle should be labeled by a binary number. By using the state table the arrows can be drawn which
show changes from each state to another state.
At the top of each arrow input/output is shown Also at the top of each arrow only input(s) can be
shown. See next slide
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Analysis with D Flip Flop
Next slide is analysis of a D flip flop with one dimensional state table and a state diagram
based on Moor Model
Note that two dimensional table state is little bit difficult when there are more inputs and
will not discussed here
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Analysis with JKFF
1. Determine input equations in terms of
present state and input varaiables
2. List binary values of each equation
3. Use the corresponding flip-flop
characteristics table to determine the next
state value in the state table
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Analysis with T Flip-Flops
180
Introduction: Counters Counters are circuits that cycle through a specified
number of states.
Two types of counters: synchronous (parallel) counters asynchronous (ripple) counters
Ripple counters allow some flip-flop outputs to be used as a source of clock for other flip-flops.
Synchronous counters apply the same clock to all flip-flops.
181
Asynchronous (Ripple) Counters
Asynchronous counters: the flip-flops do not change states at exactly the same time as they do not have a common clock pulse.
Also known as ripple counters, as the input clock pulse ripples through the outer cumulative delay is a drawback.
n flip-flops a MOD (modulus) 2n counter. (Note: A MOD-x counter cycles through x states.)
Output of the last flip-flop (MSB) divides the input clock frequency by the MOD number of the counter, hence a counter is also a frequency divider.
182
Asynchronous (Ripple) Counters Example: 2-bit ripple binary counter. Output of one flip-flop is connected to the clock
input of the next more-significant flip-flop.
K
J
K
J
HIGH
Q0 Q1
Q0
FF1 FF0
CLK C C
Timing diagram
00 01 10 11 00 ...
4 3 2 1 CLK
Q0
Q0
Q1
1 1
1 1
0
0 0
0 0
0
183
Asynchronous (Ripple) Counters Example: 3-bit ripple binary counter.
K
J
K
J Q0 Q1
Q0
FF1 FF0
C C
K
J
Q1 C
FF2
Q2
CLK
HIGH
4 3 2 1 CLK
Q0
Q1
1 1
1 1
0
0 0
0 0
0
8 7 6 5
1 1 0 0
1 1 0 0
Q2 0 0 0 0 1 1 1 1 0
Recycles back to 0
184
Asynchronous (Ripple) Counters Propagation delays in an asynchronous (ripple-
clocked) binary counter.
If the accumulated delay is greater than the clock pulse, some counter states may be misrepresented!
4 3 2 1 CLK
Q0
Q1
Q2
tPLH
(CLK to Q0)
tPHL
(CLK to Q0)
tPLH
(Q0 to Q1)
tPHL
(CLK to Q0)
tPHL
(Q0 to Q1)
tPLH
(Q1 to Q2)
185
Asynchronous (Ripple) Counters Example: 4-bit ripple binary counter (negative-
edge triggered).
K
J
K
J Q1 Q0
FF1 FF0
C C
K
J
C
FF2
Q2
CLK
HIGH
K
J
C
FF3
Q3
CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q0
Q1
Q2
Q3
186
Asyn. Counters with MOD no. < 2n
States may be skipped resulting in a truncated sequence.
Technique: force counter to recycle before going through all of the states in the binary sequence.
Example: Given the following circuit, determine the counting sequence (and hence the modulus no.)
K
J Q
Q
CLK
CLR K
J Q
Q
CLK
CLR K
J Q
Q
CLK
CLR
C B A
B
C
All J, K
inputs are
1 (HIGH).
187
Asyn. Counters with MOD no. < 2n
Exercise: How to construct an asynchronous MOD-5 counter? MOD-7 counter? MOD-12 counter?
Question: The following is a MOD-? counter?
K
J Q
Q CLR
C B A
C D E F
All J = K = 1.
K
J Q
Q CLR
K
J Q
Q CLR
K
J Q
Q CLR
K
J Q
Q CLR
K
J Q
Q CLR
D E F
188
Asyn. Counters with MOD no. < 2n
Decade counters (or BCD counters) are counters with 10 states (modulus-10) in their sequence. They are commonly used in daily life (e.g.: utility meters, odometers, etc.).
Design an asynchronous decade counter.
D
CLK
HIGH
K
J
C
CLR
Q
K
J
C
CLR
Q C
K
J
C
CLR
Q B
K
J
C
CLR
Q A
(A.C)'
189
Asyn. Counters with MOD no. < 2n
Ashroous deade/BCD outer otd.
D
C
1 2
B
NAND output
3 4 5 6 7 8 9 10 Clock
11
A
D
CLK
HIGH
K
J
C
CLR
Q
K
J
C
CLR
Q C
K
J
C
CLR
Q B
K
J
C
CLR
Q A (A.C)'
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
190
Asynchronous Down Counters So far we are dealing with up counters. Down
counters, on the other hand, count downward from a maximum value to zero, and repeat.
Example: A 3-bit binary (MOD-23) down counter.
K
J
K
J Q1 Q0
C C
K
J
C
Q2
CLK
1
Q
Q'
Q
Q'
Q
Q'
Q
Q'
3-bit binary
up counter
3-bit binary
down counter
1
K
J
K
J Q1 Q0
C C
K
J
C
Q2
CLK
Q
Q'
Q
Q'
Q
Q'
Q
Q'
191
Asynchronous Down Counters Example: A 3-bit binary (MOD-8) down counter.
4 3 2 1 CLK
Q0
Q1
1 1
1 0
0
0 1
0 0
0
8 7 6 5
1 1 0 0
1 0 1 0
Q2 1 1 0 1 1 0 0 0 0
001
000 111
010
011
100
110
101
1
K
J
K
J Q1 Q0
C C
K
J
C
Q2
CLK
Q
Q'
Q
Q'
Q
Q'
Q
Q'
192
Cascading Asynchronous Counters Larger asynchronous (ripple) counter can be
constructed by cascading smaller ripple counters.
Connect last-stage output of one counter to the clock input of next counter so as to achieve higher-modulus operation.
Example: A modulus-32 ripple counter constructed from a modulus-4 counter and a modulus-8 counter.
K
J
K
J
Q1 Q0
C C CLK
Q
Q'
Q
Q'
Q
Q' K
J
K
J
Q3 Q2
C C
K
J
C
Q4
Q
Q'
Q
Q'
Q
Q'
Q
Q'
Modulus-4 counter Modulus-8 counter
193
Cascading Asynchronous Counters Example: A 6-bit binary counter (counts from
0 to 63) constructed from two 3-bit counters.
3-bit
binary counter
3-bit
binary counter Count
pulse
A0 A1 A2 A3 A4 A5
A5 A4 A3 A2 A1 A00 0 0 0 0 00 0 0 0 0 10 0 0 : : :0 0 0 1 1 10 0 1 0 0 00 0 1 0 0 1: : : : : :
194
Cascading Asynchronous Counters If counter is a not a binary counter, requires
additional output.
Example: A modulus-100 counter using two decade counters.
CLK
Decade
counter Q3 Q2 Q1 Q0
C
CTEN TC
1 Decade
counter Q3 Q2 Q1 Q0
C
CTEN TC
freq
freq/10 freq/10
0
TC = 1 when counter recycles to 0000
195
Synchronous (Parallel) Counters Synchronous (parallel) counters: the flip-flops are
clocked at the same time by a common clock pulse.
We can design these counters using the sequential logic design process (covered in Lecture #12).
Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs).
Present Next Flip-flopstate state inputs
A1 A0 A1+ A0+ TA1 TA00 0 0 1 0 10 1 1 0 1 11 0 1 1 0 11 1 0 0 1 1
01 00
10 11
196
Synchronous (Parallel) Counters Example: 2-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J,K inputs).
Present Next Flip-flopstate state inputs
A1 A0 A1+ A0+ TA1 TA00 0 0 1 0 10 1 1 0 1 11 0 1 1 0 11 1 0 0 1 1
TA1 = A0
TA0 = 1
1
K
J
K
J A1 A0
C C
CLK
Q
Q'
Q
Q'
Q
Q'
Synchronous (Parallel) Counters 197
Synchronous (Parallel) Counters Example: 3-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J, K inputs).
Present Next Flip-flopstate state inputs
A2 A1 A0 A2+ A1+ A0+ TA2 TA1 TA00 0 0 0 0 1 0 0 10 0 1 0 1 0 0 1 10 1 0 0 1 1 0 0 10 1 1 1 0 0 1 1 11 0 0 1 0 1 0 0 11 0 1 1 1 0 0 1 11 1 0 1 1 1 0 0 11 1 1 0 0 0 1 1 1
TA2 = A1.A0
A2
A1
A0
1
1
TA1 = A0 TA0 = 1
A2
A1
A0
1
1 1
1
A2
A1
A0
1 1 1
1 1 1 1
1
Synchronous (Parallel) Counters 198
Synchronous (Parallel) Counters Example: 3-it shroous iar outer otd.
TA2 = A1.A0 TA1 = A0 TA0 = 1
1
A2
CP
A1 A0
K
Q
J K
Q
J K
Q
J
Synchronous (Parallel) Counters 199
Synchronous (Parallel) Counters Note that in a binary counter, the nth bit (shown
underlined) is always complemented whenever
0 1 or 1 0
Hence, Xn is complemented whenever Xn-1Xn-2 ... X1X0 = . As a result, if T flip-flops are used, then
TXn = Xn-1 . Xn-2 . ... . X1 . X0
Synchronous (Parallel) Counters 200
Synchronous (Parallel) Counters Example: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1
1
K
J
K
J A1 A0
C C
CLK
Q
Q'
Q
Q'
Q
Q' K
J A2
C
Q
Q' K
J A3
C
Q
Q'
A1.A0 A2.A1.A0
Synchronous (Parallel) Counters 201
Synchronous (Parallel) Counters Example: Synchronous decade/BCD counter.
Clock pulse Q3 Q2 Q1 Q0Initially 0 0 0 0
1 0 0 0 12 0 0 1 03 0 0 1 14 0 1 0 05 0 1 0 16 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 1
10 (recycle) 0 0 0 0
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0 T3 = Q2.Q1.Q0 + Q3.Q0
Synchronous (Parallel) Counters 202
Synchronous (Parallel) Counters Example: Synchronous decade/BCD counter otd.
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0
1 Q1
Q0
CLK
T
C
Q
Q'
Q
Q'
Q2 Q3 T
C
Q
Q'
Q
Q'
T
C
Q
Q'
Q
Q'
T
C
Q
Q'
Q
Q'
Up/Down Synchronous Counters 203
Up/Down Synchronous Counters Up/down synchronous counter: a
bidirectional counter that is capable of counting either up or down.
An input (control) line Up/Down (or simply Up) specifies the direction of counting.
Up/Down = 1 Count upward Up/Down = 0 Count downward
Up/Down Synchronous Counters 204
Up/Down Synchronous Counters Example: A 3-bit up/down synchronous
binary counter. Clock pulse Up Q2 Q1 Q0 Down
0 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 07 1 1 1
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )
Up counter
TQ0 = 1
TQ1 = Q0
TQ2 = Q0.Q1
Down counter
TQ0 = 1
TQ1 = Q0 TQ2 = Q0.Q1
Up/Down Synchronous Counters 205
Up/Down Synchronous Counters Example: A 3-bit up/down synchronous iar outer otd.
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )
1
Q1 Q0
CLK
T
C
Q
Q'
Q
Q'
T
C
Q
Q'
Q
Q'
T
C
Q
Q'
Q
Q'
Up
Q2
Introduction: Registers 206
Introduction: Registers An n-bit register has a group of n flip-flops and
some logic gates and is capable of storing n bits of information.
The flip-flops store the information while the gates control when and how new information is transferred into the register.
Some functions of register: retrieve data from register store/load new data into register (serial or parallel) shift the data within register (left or right)
Simple Registers 207
Simple Registers No external gates. Example: A 4-bit register. A new 4-bit data is
loaded every clock cycle.
A3
CP
A1 A0
D
Q
D
Q Q
D
A2
D
Q
I3 I1 I0 I2
Registers With Parallel Load 208
Registers With Parallel Load Instead of loading the register at every clock pulse,
we may want to control when to load.
Loading a register: transfer new information into the register. Requires a load control input.
Parallel loading: all bits are loaded simultaneously.
Registers With Parallel Load 209
Registers With Parallel Load
A0
CLK
D Q
Load
I0
A1 D Q
A2 D Q
A3 D Q
CLEAR
I1
I2
I3
Load'.A0 + Load. I0
Shift Registers 210
Shift Registers Another function of a register, besides storage, is to
provide for data movements.
Each stage (flip-flop) in a shift register represents one bit of storage, and the shifting capability of a register permits the movement of data from stage to stage within the register, or into or out of the register upon application of clock pulses.
Shift Registers 211
Shift Registers Basic data movement in shift registers (four
bits are used for illustration).
Data in Data out
(a) Serial in/shift right/serial out
Data in Data out
(b) Serial in/shift left/serial out
Data in
Data out
(c) Parallel in/serial out
Data out
Data in
(d) Serial in/parallel out Data out
Data in
(e) Parallel in /
parallel out
(f) Rotate right (g) Rotate left
Serial In/Serial Out Shift Registers 212
Serial In/Serial Out Shift Registers Accepts data serially one bit at a time and
also produces output serially.
Q0
CLK
D
C
Q Q1 Q2 Q3 Serial data
input
Serial data
output D
C
Q D
C
Q D
C
Q
Serial In/Serial Out Shift Registers 213
Serial In/Serial Out Shift Registers Application: Serial transfer of data from one
register to another.
Shift register A Shift register B SI SI SO SO
Clock
Shift control
CP
Wordtime
T1 T2 T3 T4 CP
Clock
Shift
control
Serial In/Serial Out Shift Registers 214
Serial In/Serial Out Shift Registers Serial-transfer example.
Timing Pulse Shift register A Shift register B Serial output of BInitial value 1 0 1 1 0 0 1 0 0
After T1 1 1 0 1 1 0 0 1 1After T2 1 1 1 0 1 1 0 0 0After T3 0 1 1 1 0 1 1 0 0After T4 1 0 1 1 1 0 1 1 1
Serial In/Parallel Out Shift Registers 215
Serial In/Parallel Out Shift Registers Accepts data serially. Outputs of all stages are available simultaneously.
Q0
CLK
D
C
Q
Q1
D
C
Q
Q2
D
C
Q
Q3
D
C
Q Data input
D
C CLK
Data input
Q0 Q1 Q2 Q3
SRG 4
Logic symbol
Parallel In/Serial Out Shift Registers 216
Parallel In/Serial Out Shift Registers Bits are entered simultaneously, but output is serial.
D0
CLK
D
C
Q
D1
D
C
Q
D2
D
C
Q
D3
D
C
Q
Data input
Q0 Q1 Q2 Q3
Serial
data
out
SHIFT/LOAD
SHIFT.Q0 + SHIFT'.D1
Parallel In/Serial Out Shift Registers 217
Parallel In/Serial Out Shift Registers Bits are entered simultaneously, but output is serial.
Logic symbol
C CLK
SHIFT/LOAD
D0 D1 D2 D3
SRG 4 Serial data out
Data in
Parallel In/Parallel Out Shift Registers 218
Parallel In/Parallel Out Shift Registers
Simultaneous input and output of all data bits.
Q0
CLK
D
C
Q
Q1
D
C
Q
Q2
D
C
Q
Q3
D
C
Q
Parallel data inputs
D0 D1 D2 D3
Parallel data outputs
Bidirectional Shift Registers 219
Bidirectional Shift Registers Data can be shifted either left or right, using a
control line RIGHT/LEFT (or simply RIGHT) to indicate the direction.
CLK
D
C
Q D
C
Q D
C
Q D
C
Q
Q0
Q1 Q2 Q3
RIGHT/LEFT
Serial
data in
RIGHT.Q0 +
RIGHT'.Q2
220
Bidirectional Shift Registers 4-bit bidirectional shift register with parallel load.
CLK
I4 I3 I2 I1
Serial input
for shift-
right
D
Q
D
Q
D
Q
D
Q Clear
4x1
MUX
s1
s0 3 2 1 0
4x1
MUX
3 2 1 0
4x1
MUX
3 2 1 0
4x1
MUX
3 2 1 0
A4 A3 A2 A1
Serial input
for shift-
left
Parallel inputs
Parallel outputs
221
Bidirectional Shift Registers 4-bit bidirectional shift register with parallel load.
Mode Controls1 s0 Register Operation0 0 No change0 1 Shift right1 0 Shift left1 1 Parallel load
Asynchronous Sequential circuits
no clock pulse difficult to design delay elements: the propagation delay must attain a stable state before the input is
changed to a new value
DO NOT use asynchronous sequential circuits unless it is absolutely necessary
e.g., in you exam
222
223
Fig. 9.1
Block diagram of an
asynchronous
sequential circuit
224
Analysis Procedure
The procedure Determine all feedback loops Assign Yi's (excitation variables), yi's (the
secondary variables)
Derive the Boolean functions of all Yi's Plot each Y function in a map Construct the state table Circle the stable states
225
Examples
the excitation variables: Y1 and Y2 Y1 = xy1+ x'y2 Y2 = xy1' + x'y2
Fig. Example of an
asynchronous
sequential circuit
226
Maps and transition table
the y variables for the rows the external variable for the columns
Circle the stable states Y = y
Fig. Maps and
transition table for
the circuit of Fig.
227
The difference synchronous design: state transition happens only
when the triggering edge of the clock
asynchronous design: the internal state can change immediately after a change in the input
The total state the internal state + the input value y: the present state Y: the next state
228
The state transition table
229
A flow table a state transition table with its internal state being
symbolized with letters
Fig. (a) is called a primitive flow table because it has only one stable state in each row
Fig. Example of
flow tables
230
state assignment derive the logic diagram
Fig. Derivation of a circuit
specified by the flow table
of Fig. (b)
231
Race conditions when two or more binary state variables change
value
00 11 00 10 11 or 00 01 11
a noncritical race if they reach the same final state otherwise, a critical state
232
Reduction of State and Flow Table
Equivalent states for each input, two states give exactly the same
output and go to the same next states or to
equivalent next states
233
(a,b) are equivalent if (c,d) are equivalent (a,b) imply (c,d) (c,d) imply (a,b) both pairs are equivalent
234
Implication Table the checking of each pair of states for possible
equivalence
235
the equivalent states (a,b), (d,e), (d,g), (e,g)
the reduced states (a,b), (c), (d,e,g), (f)
the state table
236
Merging of the flow table consider the don't-care conditions combinations of inputs or input sequences may never
occur
two incompletely specified states that can be combined are said to be compatible
for each possible input they have the same output whenever specified and their next states are compatible whenever they are specified
determine all compatible pairs find the maximal compatibles find a minimal closed covering
237
Compatible pairs (a,b) (a,c) (a,d) (b,e) (b,f) (c,d) (e,f)
Fig. 9.23
Flow and implication
tables
238
Race-Free State Assignment
To avoid critical races only one variable changes at any given time
Three-row flow-table example flow-table and transition diagram example
Fig. Three-row flow-table example
239
an extra row is added no stable state in row d
Fig. Flow-table with an extra row
UNIT V
MEMORY
240
241
Memory Devices
Introduction Memory unit a collection of cells capable of storing a large quantity of binary
information and
to hih iar iforatio is trasferred for storage fro hih iforatio is aailale he eeded for
processing
together with associated circuits needed to transfer information in and out of the device
write operation: storing new information into memory read operation: transferring the stored information out of the memory
242
Memory Devices Two major types
RAM (Random-access memory): Read + Write
accept new information for storage to be available later for use
ROM (Read-only memory): perform only read operation
243
Random-Access Memory
A memory unit stores binary information in groups of bits 1 byte = 8 bits 16-bit word = 2 bytes, 32-bit word = 4 bytes
Interface n data input and output lines k address selection lines control lines specifying the direction of transfer
244
Random-Aess Meor Addressing each word is assigned to an address k-bit address: 0 to 2k 1 word size: K(kilo)=210, M(mega)=220, G(giga)=230 A decoder accepts an address and opens the paths needed to select
the word specified
245
1K words of 16 bits
Capacity: 1K * 16 bits = 2K bytes = 2,048 Bytes
Addressing data: 16-bit data and 10-bit address
246
Write and Read Operations
Steps of Write operation Apply the binary address to the address lines Apply the data bits to the data input lines Activate the write input
Steps of Read operation Apply the binary address to the address lines Activate the read input
247
Write ad Read Operatios Two ways of control inputs: separate read and write inputs memory enable (chip select) + Read/write (operation select)
widely used in commercial or multi-chip memory components
Random-Access Memory (RAM)
Key features RAM is packaged as a chip Basic storage unit is a cell (one bit per cell) Multiple RAM chips form a memory
Static RAM (SRAM) Each cell stores bit with a six-transistor circuit Retains value indefinitely, as long as it is kept powered Relatively insensitive to disturbances such as electrical noise Faster and more expensive than DRAM
Dynamic RAM (DRAM) Each cell stores bit with a capacitor and transistor Value must be refreshed every 10-100 ms Sensitive to disturbances Slower and cheaper than SRAM
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Timing Waveforms of Memory
Memory operation control: usually controlled by external devices such as CPU
CPU provides memory control signals to synchronize its internal clocked operations with memory operations
CPU also provides the address for the memory
Memory operation times access time: time to select a word and read it cycle time: time to complete a write operation both must be within a time equal to a fixed number of CPU
clock cycles
Non-Volatile RAM (NVRAM)
Key Feature: Keeps data when power lost Several types Most important is NAND flash Ongoing R&D
NAND flash Reading similar to DRAM (though somewhat slower) Writing packed with restrictions:
Cat hage eistig data Must erase in large blocks (e.g., 64K) Block dies after about 100K erases
Writing slower than reading (mostly due to erase cost) Chips often packaged with Flash Translation Layer (FTL)
preads out rites ear leelig Makes chip appear like disk drive
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Types of Memories
Random vs. sequential Random-Access Memory: each word is accessible separately equal access time
Sequential-Access Memory: information stored is not immediately accessible but only at certain intervals of time
magnetic disk or tape
access time is variable
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Tpes of Meories Static vs. dynamic SRAM: consists essentially of internal latches and remains valid as long as power is applied to the unit
advantage: shorter read and write cycles DRAM: in the form of electric charges on capacitors which are provided inside the chip by MOS transistors
drawback: tend to discharge with time and must be periodically recharged by refreshing, cycling through the words every few ms
advantage: reduced power consumption and larger storage capacity
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Tpes of Meories
Volatile vs. non-volatile volatile: stored information is lost when power is turned off
Non-volatile: remains even after power is turned off
magnetic disk, flash memory
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Read-Only Memory
ROM: permanent binary information is stored pattern is specified by the designer stays even when power is turned off and on again Pins k address inputs and n data outputs no data inputs since it doses not have a write operation one or more enable inputs
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32x8 ROM
A 2kxn ROM has an internal k x2k decoder and n OR gates 32 words of 8 bits each 32*8=256 programmable internal connections 5 inputs decoded into 32 distinct outputs by 5x32 decoder Each of 8 OR gates have 32 inputs
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ROM programmable
intersection:
crosspoint switch
To oditios close: two lines are connected
open: two lines are disconnected
Ipleeted fuse normally connects the two points
opeed or lo by applying a
high-voltage pulse
A7(I4,I3,I2,I1,I0)
=,,,,
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Types of ROM
4 methods to program ROM paths
mask programming ROM customized and filled out the truth table by customer and
masked by manufacturers during last fabrication process.
costly; economical only if large quantities
PROM: Programmable ROM PROM units contain all the fuses intact initially Fuses are blown by application of a high-voltage pulse to the
device through a special pin by special instruments called PROM programmers
Written/programmed once; irreversible
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Tpes of ROM EPROM: erasable PROM floating gates served as programmed connections When placed under ultraviolet light, short wave radiation
discharges the gates and makes the EPROM returns to its initial state
reprogrammable after erasure
EEPROM: electrically-erasable PROM erasable with an electrical signal instead of ultraviolet light longer time is needed to write flash ROM: limited times of write operations
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Memory Decoding
RAM of m words and n bits: m*n binary storage cells SRAM cell: stores one bit in its internal latch SR latch with associated gates, 4-6 transistors
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Example: capacity of 16 bits in 4 words of 4
bits each
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Example: capacity of 16 bits in 4 words of 4
its eah deoder: selet oe of the ords enabled with the Memory enable signal
Meor ith k words of n bits: k address lines go into a kx2k
decoder
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Address Multiplexing
DRAM: large capacity requires large address decoding Simpler cell structure DRAM: a MOS transistor and a capacitor per cell SRAM: 6 transistors Higher density: 4 times the density of DRAM larger capacity Lower cost per bit: 3-4 times less than SRAM Lower power requirement Preferred technology for large memories 64K(=216) bits and 256M(=228) bits may need 16 and 28
address inputs
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Address Multiplexing
Address multiplexing: use a small set of address input pins to accommodate the address components
A full address is applied in multiple parts at different times
i.e. two-dimensional array: row address first and column address second
same set of pins are used for both parts Advantage: reducing the number of pins for larger memory
Sequential Memory
Sequential-Access Memory: information stored is not immediately accessible but only at certain intervals of time
magnetic disk or tape
access time is variable
264
Cache Memory
265
LOCALITY
PRINCIPAL OF LOCALITY is the tendency to reference data items
that are near other recently referenced data items, or that
were recently referenced themselves.
TEMPORAL LOCALITY : memory location that is referenced once
is likely to be referenced multiple times in near future.
SPATIAL LOCALITY : memory location that is referenced once,
then the program is likely to be reference a nearby memory
location in near future.
CACHE MEMORY
Principle of locality helped to speed up main
memory access by introducing small fast
memories known as CACHE MEMORIES that hold
blocks of the most recently referenced
instructions and data items.
Cache is a small fast storage device that holds the
operands and instructions most likely to be used
by the CPU.
CACHE HITS / MISSES
Cache Hit: a request to read from memory, which can satisfy from the cache without using the main memory.
Cache Miss: A request to read from memory, which cannot be satisfied from the cache, for which the main memory has to be consulted.
HIT RATIO and
EFFECTIVE ACCESS TIMES
Hit Ratio : The fraction of all memory reads which are satisfied from the cache
LOAD-THROUGH
STORE-THROUGH
Load-Through : When the CPU needs to read a word from the memory, the block containing the word is brought from MM to CM, while at the same time the word is forwarded to the CPU.
Store-Through : If store-through is used, a word to be stored from CPU to memory is written to both CM (if the word is in there) and MM. By doing so, a CM block to be replaced can be overwritten by an in-coming block without being saved to MM.
WRITE METHODS
Note: Words in a cache have been viewed simply as copies of words from main memory that are read
from the cache to provide faster access. However
this view point changes.
There are 3 possible write actions: Write the result into the main memory Write the result into the cache Write the result into both main memory and cache
memory
Write Through: A cache architecture in which data is written to main memory at the same time as it is
cached.
Write Back / Copy Back: CPU performs write only to the cache in case of a cache hit. If there is a cache
miss, CPU performs a write to main memory.
275
PLAs
Programmable Logic Array
Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making/ breaking connections among the gates.
General purpose logic building blocks.
276
PLA
277
PLA
A 32 PLA with 4 product terms.
278
Design for PLA:
Example Implement the following functions using PLA
F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A
Personality Matrix
1 = asserted in term 0 = negated in term - = does not participate
Input Side:
1 = term connected to output 0 = no connection to output
Output Side: Outputs Inputs Product
t erm
Reuse of
t erms
A 1 -
1 -
1
B 1 0 -
0 -
C -
1 0 0 -
F 0 0 0 0 1 1
F 1 1 0 1 0 0
F 2 1 0 0 1 0
F 3 0 1 0 0 1
A B B C A C B C A
279
Example: Continued
F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A
Personality Matrix Outputs Inputs Product
t erm
Reuse of
t erms
A 1 -
1 -
1
B 1 0 -
0 -
C -
1 0 0 -
F 0 0 0 0 1 1
F 1 1 0 1 0 0
F 2 1 0 0 1 0
F 3 0 1 0 0 1
A B B C A C B C A
A B C
F0 F1 F2 F3
AB
BC AC BC A
Memory Hierarchies
Some fundamental and enduring properties of hardware and software: Fast storage technologies cost more per byte and have less
capacity
Gap between CPU and main memory speed is widening Well-written programs tend to exhibit good locality
These fundamental properties complement each other beautifully
They suggest an approach for organizing memory and storage systems known as a memory hierarchy
An Example Memory Hierarchy
registers
on-chip L1
cache (SRAM)
main memory
(DRAM)
local secondary storage
(local disks)
Larger,
slower,
and
cheaper
(per byte)
storage
devices
remote secondary storage
(distributed file systems, Web servers)
Local disks hold files retrieved
from disks on remote network
servers
Main memory holds disk
blocks retrieved from local
disks
off-chip L2
cache (SRAM)
L1 cache holds cache lines retrieved from
the L2 cache memory
CPU registers hold words retrieved from L1
cache
L2 cache holds cache lines retrieved
from main memory
L0:
L1:
L2:
L3:
L4:
L5:
Smaller,
faster,
and
costlier
(per byte)
storage
devices
