dld_question_bank WORD.docx

7/25/2019 dld_question_bank WORD.docx

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SRINIVASA INSTITUTE OF ENGINEERING AND TECHNOLOGYDEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK

SUBJECT NAME: DIGITAL LOGIC DESIGN Subject C!e:

YEAR: II CSE SEM: II

UNIT " I

NUMBER SYSTEMS

1) Define binary logic?

Binary logic consists of binary variables and logical operations. The variables are

designated by the alphabets such as A, B, C, x, y, , etc., !ith each variable having only t!o

distinct values" 1 and #. There are three basic logic operations" A$D, %&, and $%T.

') Convert (*+) to binary

* +

11# #11 1##

A#$ % &&''&&&''

*) Convert (-B' 1A) / to its deci0al euivalent.

$ 2 - x 1'3 B x 1

13 ' x 1

#3 1 x 1

13 A (1#) x 1

'

2 '*#+ 3 14 3 ' 3 #.#'5 3 #.#*-

2 ()*(+&&'

+) 6tate the different classification of binary codes?

1. 7eighted codes

'. $on !eighted codes

*. &eflective codes

+. 6euential codes

5. Alphanu0eric codes

. 8rror Detecting and correcting codes.

5) Convert #.+#'5 deci0al nu0bers to its octal euivalent.

#.+#'5 x 2 5.1'5

#.1'5 x 2 1.#

2 #.+# '5 1# 2 ,'+-&. *

) Convert #.1'-#' deci0al nu0ber to its hex euivalent


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Depart0ent"8C8


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#.1'-#' x 1 2 '.#'5

#.#'5 x 1 2 1.#

2 '+(&&/

4) Convert ''.+ to hexadeci0al nu0ber.

1 ''

1 1 1

#

#.+ x 1 2 1#.'+

#.'+ x 1 2 *.+

#.+ x 1 2 1*.++

.++ x 1 2 4.#+

A#$ % ,&/+ A 0 D 1. &/

) 6tate the steps involved in 9ray to binary conversion?

The :6B of the binary nu0ber is the sa0e as the :6B of the gray code nu0ber. 6o

!rite it do!n. To obtain the next binary digit, perfor0 an exclusive %& operation bet!een the bit

;ust !ritten do!n and the next gray code bit. 7rite do!n the result.

-) Convert gray code 1#1#11 into its binary euivalent.

9ray Code" 1 # 1 # 1 1

Binary Code" & & ' ' & '

1#) 6ubstract (# 1 # 1) ' fro0 (1 # 1 1) '

1 # 1 #

# 1 # 1

A#$2e3 % ' & & '

11) Add (1 # 1 #) ' and (# # 1 1) '

1 # 1 # # # 1 1

A#$2e3 % ,& & ' &. (

1')


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Discard end carry

A#$2e3 % /4(*(

1*) >ind '=6 co0ple0ent of (1 # 1 # # # 1 1) '

# 1 # 1 1 1 # # 1 1=s Co0ple0ent

3 1

# 1 # 1 1 1 # 1 # '=s co0ple0ent.

1+) 6ubstract 1 1 1 # # 1 ' fro0 1 # 1 # 1 1 ' using '=s co0ple0ent 0ethod

1 # 1 # 1 1

3 # # # 1 1 1 '=s co0p. of 1 1 1 # # 1

1 1 # # 1 # in '=s co0ple0ent for0

A#$2e3 ,' ' & & & ' .(

15) >ind the excess * code and -=s co0ple0ent of the nu0ber +#*1#

+ # *

# 1 # # # # # # # # 1 1 #

# 1 1 # # 1 1 # # 1 1 3

# 1 1 1 # # 1 1 # 1 1 # excess * code

45$ c678e6e#t & ' ' ' & & ' ' & ' ' &

1) 7hat is 0eant by bit?

A binary digit is called bit

14) Define byte? 9roup

of bits.

1) ist the different nu0ber syste0s?

i) Deci0al $u0ber syste0

ii) Binary $u0ber syste0

iii) %ctal $u0ber syste0

iv) /exadeci0al $u0ber syste0

1-) 6tate the abbreviations of A6C@@ and 8BCD@C code?

A6C@@A0erican 6tandard Code for @nfor0ation @nterchange.

8BCD@C8xtended Binary Coded Deci0al @nfor0ation Code.

'#) 7hat are the different types of nu0ber co0ple0ents?

i) r=s Co0ple0ent

ii) (r1)=s Co0ple0ent.

Depart0ent"8C8


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'') 9iven the t!o binary nu0bers 2 1#1#1## and 2 1####11, perfor0 the subtraction

(a) and (b) using 1s co0ple0ents.

a) A B 2 1#1#1## 1####11

2 1#1#1##

1s co0ple0ent of 2 3 #1111##

6u0 2 1##1####

8nd around carry 2 3 1

Answer: 9 Y % ''&'''&

b) 2 1####11 1#1#1##

2 1####11

1s co0ple0ent of 2 3 #1#1#11

6u0 2 311#111#

There is no end carry.

T;e3e$ Y 9 % ,&?$ c678e6e#t < &&'&&&'. % ''&'''&

Depart0ent"8C8

'1) 9iven the t!o binary nu0bers 2 1#1#1## and 2 1####11, perfor0 the subtraction

(a) and (b) using 's co0ple0ents.

a) 2 1#1#1##

's co0ple0ent of 2 #1111#1

6u0 2 1##1###1 Discard end

carry

Answer: 9 Y % ''&'''&

b) 2 1####11 's co0ple0ent of

2 3 #1#11##

6u0 2 11#1111 There is no end

carry, The :6B B@T @6 1.

A#$2e3 >$ Y9 % ,(?$ c678e6e#t < &&'&&&&. % ''&'''&


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UNIT " (

LOGIC GATES AND BOOLEAN AL@EBRA

'*) 7rite the na0es of basic logical operators.

1. $%T @$E8&T

'. A$D

*. %&

'+) 7hat are basic properties of Boolean algebra?

The basic properties of Boolean algebra are co00utative property, associative property

and distributive property.

'5) 6tate the associative property of boolean algebra.

The associative property of Boolean algebra states that the %& ing of several variables

results in the sa0e regardless of the grouping of the variables. The associative property is stated

as follo!s"

A3 (B3C) 2 (A3B) 3C

') 6tate the co00utative property of Boolean algebra.

The co00utative property states that the order in !hich the variables are %& ed 0aFes

no difference. The co00utative property is"

A3B2B3A

'4) 6tate the distributive property of Boolean algebra.

The distributive property states that A$D ing several variables and %& ing the result !ith

a single variable is euivalent to %& ing the single variable !ith each of the the several variables

and then A$D ing the su0s. The distributive property is"

A3BC2 (A3B) (A3C)

') 6tate the absorption la! of Boolean algebra.

The absorption la! of Boolean algebra is given by 32, (3) 2.

'-) 6i0plify the follo!ing using De :organs theore0 G((AB)C)

DH G((AB)C) DH 2 ((AB)C) 3 D G(AB) 2 A 3 BH2 (AB) C 3 D

2 (A 3 B )C 3 D

*#) 6tate De :organs theore0.

De :organ suggested t!o theore0s that for0 i0portant part of Boolean algebra.

They are,


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1) The co0ple0ent of a product is eual to the su0 of the co0ple0ents.

(AB) 2 A 3 B

Depart0ent"8C8


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') The co0ple0ent of a su0 ter0 is eual to the product of the co0ple0ents.

(A 3 B) 2 AB

*1) &educe A.AC

A.AC 2 #.C GA.A 2 1H

2 #

*1) &educe A(A 3 B)

A(A 3 B) 2 AA 3 AB

2 A(1 3 B) G1 3 B 2 1H

2 A.

*') &educe ABC 3 ABC 3 ABC

ABC 3 ABC 3 ABC 2 AC(B 3 B) 3 ABC

2 AC 3 ABC GA 3 A 2 1H

2 A(C 3 BC)

2 A(C 3 B) GA 3 AB 2 A 3 BH

**) &educe AB 3 (AC) 3 ABC(AB 3 C)

AB 3 (AC) 3 ABC(AB 3 C) 2 AB 3 (AC) 3 AABBC 3 ABCC

2AB 3 (AC) 3 ABCC GA.A 2 #H

2AB 3 (AC) 3 ABC GA.A 2 1H

2AB 3 A 3 C 2ABC G(AB) 2 A 3 BH

2A 3 B 3 C 3 ABC GA 3 AB 2 A 3 BH

2A 3 BC 3 B 3 C GA 3 AB 2 A 3 BH

2 A 3 B 3 C 3 BC

2A 3 B 3 C 3 B

2A 3 C 3 1

2 1 GA 3 1 21H

*+) 6i0plify the follo!ing expression 2 (A 3 B)(A 3 C )(B 3 C )

2 (A 3 B)(A 3 C )(B 3 C )

2 (AA 3 AC 3AB 3BC )(B 3 C) GA.A 2 #H

2 (AC 3 AB 3 BC)(B 3 C )

2 ABC 3 ACC 3 ABB 3 ABC 3 BBC 3 BCC

2 ABC 3 ABC

Depart0ent"8C8


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*5) 6ho! that ( 3 3 )( 3 )() 2 #

( 3 3 )( 3 )() 2 ( 3 3 )( 3 )( 3 ) GA 3 AB 2 A 3 BH

2 ( 3 )( 3 )() GA 3 A 2 1H

2 ( 3 )() GA.A 2 1H

2 . 3 ..

2 # GA.A 2 #H

*) Irove that ABC 3 ABC 3 ABC 3 ABC 2 AB 3 AC 3 BC

ABC 3 ABC 3 ABC 3 ABC2AB(C 3 C) 3 ABC 3 ABC

2AB 3 ABC 3 ABC

2A(B 3 BC) 3 ABC

2A(B 3 C) 3 ABC

2AB 3 AC 3 ABC

2B(A 3 C) 3 AC

2AB 3 BC 3 AC

2AB 3 AC 3BC ...Iroved

*4) Convert the given expression in canonical 6%I for0 2 AC 3 AB 3 BC

2 AC 3 AB 3 BC

2AC(B 3 B ) 3 AB(C 3 C ) 3 (A 3 A)BC

2ABC 3 ABC 3 ABC 3 ABC 3 ABC 3 ABC 3 ABC

2ABC 3 ABC 3ABC 3 ABC GA 3 A 21H

*) Define duality property.

Duality property states that every algebraic expression deducible fro0 the postulates of

Boolean algebra re0ains valid if the operators and identity ele0ents are interchanged. @f the dual

of an algebraic expression is desired, !e si0ply interchange %& and A$D operators and replace

1s by #s and #s by 1s.

*-) >ind the co0ple0ent of the functions >1 2 xy 3 xy and >' 2 x(y 3 y).

By applying De:organs theore0.

>1 2 (xy 3 xy) 2 (xy)(xy) 2 (x 3 y 3 )(x 3 y

3) >' 2 Gx(y 3 y)H 2 x 3 (y 3 y)

2 x 3 (y)(y)

2 x 3 (y 3 )(y 3 )Depart0ent"8C8


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+#) 6i0plify the follo!ing expression

2 (A 3 B) (A 2 C) (B 3 C)

2(A A 3 A C 3 A B 3 B C) (B 3 C)

2(A C 3 A B 3 B C) (B 3 C)

2A B C 3 A C C 3 A B B 3 A B C 3 B B C 3 B C C

2A B C

+1) 7hat are the 0ethods adopted to reduce Boolean function?

i) Jarnaug 0ap

ii) Tabular 0ethod or Kuine :cClusFey 0ethod

iii) Eariable entered 0ap techniue.

+') 6tate the li0itations of Farnaugh 0ap.

i) 9enerally it is li0ited to six variable 0ap (i.e) 0ore then six variable involving expression are

not reduced.

ii) The 0ap 0ethod is restricted in its capability since they are useful for

si0plifying only Boolean expression represented in standard

for0. +*) 7hat is a Farnaugh 0ap?

A Farnaugh 0ap or F 0ap is a pictorial for0 of truth table, in !hich the 0ap diagra0

is 0ade up of suares, !ith each suares representing one 0inter0 of the function.

++) >ind the 0inter0s of the logical expression 2 ABC 3 ABC 3 ABC 3 ABC

2 ABC 3 ABC 3 ABC 3 ABC

20# 3 01 30*

30 2L0(#, 1, *, )

+5) 7rite the 0axter0s corresponding to the logical expression

2 (A 3 B 3 C )(A 3 B 3 C)(A 3 B 3 C)

2 (A 3 B 3 C )(A 3 B 3 C)(A 3 B 3 C)

2:1.:*.:

2L :(1,*,)

+) 7hat are called don=t care conditions?

@n so0e logic circuits certain input conditions never occur, therefore the corresponding

output never appears. @n such cases the output level is not defined, it can be either high or lo!.

These output levels are indicated by M= orMd= in the truth tables and are called don=t care

conditions or inco0pletely specified functions.

Depart0ent"8C8


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+4) 7hat is a pri0e i0plicant?

A pri0e i0plicant is a product ter0 obtained by co0bining the 0axi0u0 possible

nu0ber of ad;acent suares in the 0ap.

+) 7hat is an essential i0plicant?

@f a 0in ter0 is covered by only one pri0e i0plicant, the pri0e i0plicant is said to be

essential

U#>t " II

+-. 7hat is a ogic gate?

ogic gates are the basic ele0ents that 0aFe up a digital syste0. The electronic gate is a

circuit that is able to operate on a nu0ber of binary inputs in order to perfor0 a particular logical

function.

5#. 9ive the classification of logic fa0ilies

logic fa0ilies

1. Bipolar '.


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'.


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Io!er dissipation is 0easure of po!er consu0ed by the gate !hen fully driven by all its

inputs.

#. 7hat is propagation delay?

Iropagation delay is the average transition delay ti0e for the signal to propagate fro0

input to output !hen the signals change in value. @t is expressed in ns.

1. Define noise 0argin?

@t is the 0axi0u0 noise voltage added to an input signal of a digital circuit that does not

cause an undesirable change in the circuit output. @t is expressed in volts.

'. Define fan in?

>an in is the nu0ber of inputs connected to the gate !ithout any degradation in the

voltage level.

*. 7hat is %perating te0perature?

All the gates or se0iconductor devices are te0perature sensitive in nature. The

te0perature in !hich the perfor0ance of the @C is effective is called as operating te0perature.

%perating te0perature of the @C vary fro0 ## C to 4## c.

+.7hat is /igh Threshold ogic?

6o0e digital circuits operate in environ0ents, !hich produce very high noise signals. >or

operation in such surroundings there is available a type of DT gate !hich possesses a high

threshold to noise i00unity. This type of gate is called /T logic or /igh Threshold ogic.

5. 7hat are the types of TT logic?

1. %pen collector output

'. Tote0Iole %utput

*. Tristate output.

. 7hat is depletion 0ode operation :%6?

@f the channel is initially doped lightly !ith ptype i0purity a conducting channel exists

at ero gate voltage and the device is said to operate in depletion 0ode.

4. 7hat is enhance0ent 0ode operation of :%6?

@f the region beneath the gate is left initially uncharged the gate field 0ust induce a

channel before current can flo!. Thus the gate voltage enhances the channel current and such a

device is said to operate in the enhance0ent 0ode.

. :ention the characteristics of :%6 transistor?

1. The n channel :%6 conducts !hen its gate to source voltage is positive.Depart0ent"8C8


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'. The p channel :%6 conducts !hen its gate to source voltage is negative

*. 8ither type of device is turned of if its gate to source voltage is ero.

-. /o! schottFy transistors are for0ed and state its use?

A schottFy diode is for0ed by the co0bination of 0etal and se0iconductor. The presence

of schottFy diode bet!een the base and the collector prevents the transistor fro0 going into

saturation. The resulting transistor is called as schottFy transistor. The use of schottFy

transistor in TT decreases the propagation delay !ithout a sacrifice of po!er dissipation.

4#. ist the different versions of TT

1.TT (6td.TT) '.TT (o! Io!er TT)

*./TT (/igh 6peed TT) +.6TT (6chottFy TT)

5.6TT (o! po!er 6chottFy TT)

41. 7hy tote0 pole outputs cannot be connected together.

Tote0 pole outputs cannot be connected together because such a connection 0ight

produce excessive current and 0ay result in da0age to the devices.

4'. 6tate advantages and disadvantages of TT

Adv"

8asily co0patible !ith other @Cs

o! output i0pedance

Disadv"

7ired output capability is possible only !ith tristate and open collector types 6pecialcircuits in Circuit layout and syste0 design are reuired.

4*. 7hen does the noise 0argin allo! digital circuits to function properly.

7hen noise voltages are !ithin the li0its of E$A(/igh 6tate $oise :argin) and E$J

for a particular logic fa0ily.

4+. 7hat happens to output !hen a tristate circuit is selected for high i0pedance.

%utput is disconnected fro0 rest of the circuits by internal circuitry.

45. 7hat is 1+### series.

@t is the oldest and standard C:%6 fa0ily. The devices are not pin co0patible or

electrically co0patible !ith any TT 6eries.

4. @0ple0ent the Boolean 8xpression for 8 O %& gate using $A$D 9ates.

Depart0ent"8C8


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UNIT " 0

COMBINATIONAL LOGIC CIRCUITS

44. Define co0binational logic

7hen logic gates are connected together to produce a specified output for certain

specified co0binations of input variables, !ith no storage involved, the resulting circuit is called

co0binational logic.

4. 8xplain the design procedure for co0binational circuits

1. The proble0 definition

'. Deter0ine the nu0ber of available input variables P reuired %I variables.

*. Assigning letter sy0bols to @% variables

+. %btain si0plified Boolean expression for each %I.

5. %btain the logic diagra0.

4-. Define /alf adder and full adder

The logic circuit that perfor0s the addition of t!o bits is a half adder. The circuit that

perfor0s the addition of three bits is a full adder.

-#. Dra! the logic 6y0bol and construct the truth table for the t!o input 8 O %& gate.


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1. Define Decoder?

Depart0ent"8C8


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A decoder is a 0ultiple input 0ultiple output logic circuit that converts coded inputs

into coded outputs !here the input and output codes are different.

'. 7hat is binary decoder?

A decoder is a co0binational circuit that converts binary infor0ation fro0 n input lines

to a 0axi0u0 of 'n out puts lines.

*. Define 8ncoder?

An encoder has 'n input lines and n output lines. @n encoder the output lines generate the

binary code corresponding to the input value.

+. 7hat is priority 8ncoder?

A priority encoder is an encoder circuit that includes the priority function. @n priority

encoder, if ' or 0ore inputs are eual to 1 at the sa0e ti0e, the input having the highest priority

!ill taFe precedence.

5. Define 0ultiplexer?

:ultiplexer is a digital s!itch. @f allo!s digital infor0ation fro0 several sources to be

routed onto a single output line.

. 7hat do you 0ean by co0parator?

A co0parator is a special co0binational circuit designed pri0arily to co0pare the

relative 0agnitude of t!o binary nu0bers.

4. ist basic types of progra00able logic devices.

1. &ead only 0e0ory

'. Irogra00able logic Array

*. Irogra00able Array ogic

. Define &%:

&ead only 0e0ory is a device that includes both the decoder and the %& gates !ithin a

single @C pacFage.

-. Define address and !ord"

@n a &%:, each bit co0bination of the input variable is called on address. 8ach bit

co0bination that co0es out of the output lines is called a !ord.

-#. 6tate the types of &%:

1. :asFed &%:.

'. Irogra00able &ead only :e0ory

*. 8rasable Irogra00able &ead only 0e0ory.

Depart0ent"8C8


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+. 8lectrically 8rasable Irogra00able &ead only :e0ory.

-1. 7hat is progra00able logic array? /o! it differs fro0 &%:?

@n so0e cases the nu0ber of don=t care conditions is excessive, it is 0ore econo0ical to

use a second type of 6@ co0ponent called a IA. A IA is si0ilar to a &%: in conceptQ

ho!ever it does not provide full decoding of the variables and does not generates all the

0inter0s as in the &%:.

-'. 7hich gate is eual to A$Dinvert 9ate?

$A$D gate.

-*. 7hich gate is eual to %&invert 9ate?

$%& gate.

-+. Bubbled %& gate is eual to

$A$D gate

-5. Bubbled A$D gate is eual to

$%& gate

UNIT " )

INTRODUCTION SEQUENTIAL CIRCUITS

-. 7hat are the classification of seuential circuits?

The seuential circuits are classified on the basis of ti0ing of their signals into t!o types.

They are,

1)6ynchronous seuential circuit.

')Asynchronous seuential circuit.

-4. Define >lip flop.

The basic unit for storage is flip flop. A flipflop 0aintains its output state either at 1 or #

until directed by an input signal to change its state.

-.7hat are the different types of flipflop?

There are various types of flip flops. 6o0e of the0 are 0entioned belo! they

are, &6 flipflop

6& flipflop

D flipflop

NJ flipflop

T flipflop


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Depart0ent"8C8


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--.7hat is the operation of &6 flipflop?

R 7hen & input is lo! and 6 input is high the K output of flipflop is set.

R 7hen & input is high and 6 input is lo! the K output of flipflop is reset.

R 7hen both the inputs & and 6 are lo! the output does not change

R 7hen both the inputs & and 6 are high the output is unpredictable.

1##.7hat is the operation of 6& flipflop?

R 7hen & input is lo! and 6 input is high the K output of flipflop is set.

R 7hen & input is high and 6 input is lo! the K output of flipflop is reset.

R 7hen both the inputs & and 6 are lo! the output does not change.

R 7hen both the inputs & and 6 are high the output is unpredictable.

1#1.7hat is the operation of D flipflop?

@n D flipflop during the occurrence of clocF pulse if D21, the output K is set and

if D2#, the output is reset.

1#'. 7hat is the operation of NJ flipflop?

R 7hen J input is lo! and N input is high the K output of flipflop is set.

R 7hen J input is high and N input is lo! the K output of flipflop is reset.

R 7hen both the inputs J and N are lo! the output does not change

R 7hen both the inputs J and N are high it is possible to set or reset the flipflop

(ie) the output toggle on the next positive clocF edge.

1#*. 7hat is the operation of T flipflop?

Tflipflop is also Fno!n as Toggle flipflop.

R 7hen T2# there is no change in the output.

R 7hen T21 the output s!itch to the co0ple0ent state (ie) the output

Depart0ent"8C8


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toggles.

1#+. Define race around condition.

@n NJ flipflop output is fed bacF to the input. Therefore change in the output results

change in the input. Due to this in the positive half of the clocF pulse if both N and J are high

then output toggles continuously. This condition is called Mrace around condition=.

1#5. 7hat is edgetriggered flipflop?

The proble0 of race around condition can solved by edge triggering flip flop.

The ter0 edge triggering 0eans that the flipflop changes state either at the positive edge

or negative edge of the clocF pulse and it is sensitive to its inputs only at this transition of the

clocF.

1#. 7hat is a 0asterslave flipflop?

A 0asterslave flipflop consists of t!o flipflops !here one circuit serves as a 0aster

and the other as a slave.

1#4.Define rise ti0e.

The ti0e reuired to change the voltage level fro0 1#S to -#S is Fno!n as rise ti0e(tr).

1#.Define fall ti0e.

The ti0e reuired to change the voltage level fro0 -#S to 1#S is Fno!n as fall ti0e(tf).

1#-.Define sFe! and clocF sFe!.

The phase shift bet!een the rectangular clocF !avefor0s is referred to as sFe! and the

ti0e delay bet!een the t!o clocF pulses is called clocF sFe!.

11#.Define setup ti0e.

The setup ti0e is the 0ini0u0 ti0e reuired to 0aintain a constant voltage levels at the

excitation inputs of the flipflop device prior to the triggering edge of the clocF pulse in order for

the levels to be reliably clocFed into the flip flop. @t is denoted as tsetup.

111. Define hold ti0e.

The hold ti0e is the 0ini0u0 ti0e for !hich the voltage levels at the excitation inputs

0ust re0ain constant after the triggering edge of the clocF pulse in order for the levels to be

reliably clocFed into the flip flop. @t is denoted as thold.

Depart0ent"8C8


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11'. Define propagation delay.

A propagation delay is the ti0e reuired to change the output after the application of the input.

UNIT " -

REGISTERS AND COUNTERS

11*.Define registers.

A register is a group of flipflops flipflop can store one bit infor0ation. 6o an nbit

register has a group of n flipflops and is capable of storing any binary infor0ationnu0ber

containing nbits.

11+.Define shift registers.

The binary infor0ation in a register can be 0oved fro0 stage to stage !ithin the register

or into or out of the register upon application of clocF pulses. This type of bit 0ove0ent or

shifting is essential for certain arith0etic and logic operations used in 0icroprocessors. This

gives rise to group of registers called shift registers.

115.7hat are the different types of shift type?

There are five types. They are,

6erial @n 6erial %ut 6hift &egister

6erial @n Iarallel %ut 6hift &egister

Iarallel @n 6erial %ut 6hift &egister

Iarallel @n Iarallel %ut 6hift &egister

Bidirectional 6hift &egister

11.8xplain the flipflop excitation tables for &6 >>.

&6 flipflop

@n &6 flipflop there are four possible transitions fro0 the present state to

the next state. They are,

# # transition" This can happen either !hen &262# or !hen &21 and62#. # 1 transition" This can happen only !hen 621 and &2#.

1 # transition" This can happen only !hen 62# and &21.

1 1 transition" This can happen either !hen 621 and &2# or 62# and &2#.

114.8xplain the flipflop excitation tables for NJ flipflop

@n NJ flipflop also there are four possible transitions fro0 present state to next state.

They are,


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# # transition" This can happen !hen N2# and J21 or J2#.

# 1 transition" This can happen either !hen N21 and J2# or !hen N2J21.

Depart0ent"8C8


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1 # transition" This can happen either !hen N2# and J21 or !hen N2J21.

1 1 transition" This can happen !hen J2# and N2# or N21.

11.8xplain the flipflop excitation tables for D flipflop

@n D flipflop the next state is al!ays eual to the D input and it is independent of the

present state. Therefore D 0ust be # if K n31has to #,and if Kn31 has to be 1 regardless

the value of Kn.

11-. 8xplain the flipflop excitation tables for T flipflop

7hen input T21 the state of the flipflop is co0ple0entedQ !hen T2#,the state of the

flipflop re0ains unchanged. Therefore, for # # and 1 1transitions T 0ust be # and

or # 1 and 1 # transitions 0ust be 1.

1'#. Define seuential circuit?

@n seuential circuits the output variables dependent not only on the present input variables but

they also depend up on the past history of these input variables.

1'1.9ive the co0parison bet!een co0binational circuits and seuential circuits.

Co0binational circuits 6euential circuits

1. :e0ory unit is not reuired 1. :e0ory unity is reuired

'. Iarallel adder is a co0binational circuit '. 6erial adder is a seuential circuit

1''. 7hat do you 0ean by present state?

The infor0ation stored in the 0e0ory ele0ents at any given ti0e define.s the present

state of the seuential circuit.

1'*. 7hat do you 0ean by next state?

The present state and the external inputs deter0ine the outputs and the next state of the

seuential circuit.

1'+. 6tate the types of seuential circuits?

1. 6ynchronous seuential circuits

'. Asynchronous seuential circuits

1'5. Define synchronous seuential circuit

@n synchronous seuential circuits, signals can affect the 0e0ory ele0ents only at

discrete instant of ti0e.

Depart0ent"8C8


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1'. Define Asynchronous seuential circuit?

@n asynchronous seuential circuits change in input signals can affect 0e0ory

ele0ent at any instant of ti0e.

1'4.9ive the co0parison bet!een synchronous P Asynchronous seuential circuits?

6ynchronous seuential circuits Asynchronous seuential circuits.

1.:e0ory ele0ents are clocFed flipflops 1.:e0ory ele0ents are either unlocFed flip

flops or ti0e delay ele0ents.

'. 8asier to design '. :ore difficult to design

1'.Define flipflop

>lip flop is a seuential device that nor0ally sa0ples its inputs and changes its outputs

only at ti0es deter0ined by clocFing signal.

1'-. Dra! the logic diagra0 for 6& latch using t!o $%& gates.

1*#. The follo!ing !ave for0s are applied to the inputs of 6& latch. Deter0ine the K

!avefor0 Assu0e initially K 2 1

/ere the latch input has to be pulsed 0o0entarily to cause a change in the latch output state, and

the output !ill re0ain in that ne! state even after the input pulse is over.

1*1.7hat is race around condition?

@n the NJ latch, the output is feedbacF to the input, and therefore changes in the output

results change in the input. Due to this in the positive half of the clocF pulse if N and J are both

high then output toggles continuously. This condition is Fno!n as race around condition.

1*'.7hat are the types of shift register?

1. 6erial in serial out shift register?

'. 6erial in parallel out shift register

*. Iarallel in serial out shift register

+. Iarallel in parallel out shift register

5. Bidirectional shift register shift register

1**.6tate the types of counter?

1. 6ynchronous counter

'. Asynchronous Counter

1*+.9ive the co0parison bet!een synchronous P Asynchronous counters.

Asynchronous counters 6ynchronous counters

Depart0ent"8C8

@n this type of counter flipflops are @n this type there is no connection bet!een


26/45

connected in such a !ay that output of 1st output of first flipflop and clocF input of

flipflop drives the clocF for the next flip the next flip flop

flop.

All the flipflops are $ot clocFed All the flipflops are clocFed

si0ultaneously si0ultaneously

1*5.The t pd for each flipflop is 5# ns. Deter0ine the 0axi0u0 operating freuency

for :%D *' ripple counter.

f 0ax (ripple) 2 5 x 5# ns 2 + :/

1*. 7hat are secondary variables?

present state variables in asynchronous seuential

circuits 1*4.7hat are excitation variables?

next state variables in asynchronous seuential

circuits 1*. 7hat is funda0ental 0ode seuential circuit?

input variables changes if the circuit is

stable inputs are levels, not pulses

only one input can change at a given ti0e

1*-. 7hat are pulse 0ode circuit?

inputs are pulses

!idth of pulses are long for circuit to respond to the input

pulse !idth 0ust not be so long that it is still present after the ne! state is reached

1+#. 7hat are the significance of state assign0ent?

@n synchronous circuitsstate assign0ents are 0ade !ith the ob;ective of circuit

reduction

Asynchronous circuitsits ob;ective is to avoid critical races

1+1. 7hen do race condition occur?

t!o or 0ore binary state variables change their value in response to the change in ip

variable

1+'.7hat is non critical race?

final stable state does not depend on the order in !hich the state variable changes

Depart0ent"8C8


27/45

race condition is not har0ful

1+*.7hat is critical race?

final stable state depends on the order in !hich the state variable changes

race condition is har0ful

1++. 7hen does a cycle occur?

asynchronous circuit 0aFes a transition through a series of unstable state

1+5.7hat are the different techniues used in state assign0ent?

shared ro! state assign0ent

one hot state assign0ent

1+.7hat are the steps for the design of asynchronous seuential circuit?

construction of pri0itive flo! table

reduction of flo! table

state assign0ent is 0ade

realiation of pri0itive flo! table

1+4.7hat is haard?

un!anted s!itching transients

1+.7hat is static 1 haard?

output goes 0o0entarily # !hen it should re0ain at 1

1+-.7hat is static # haard?

output goes 0o0entarily 1 !hen it should re0ain at #

15#. 7hat is dyna0ic haard?

output changes * or 0ore ti0es !hen it changes fro0 1 to # or # to

1 151.7hat is the cause for essential haards?

uneual delays along ' or 0ore path fro0 sa0e

input 151.7hat is flo! table?

state table of an synchronous seuential

net!orF 15'.7hat is 6: chart?

describes the behavior of a state 0achine

used in hard!are design of digital syste0s

15'.7hat are the advantages of 6: chart?

easy to understand the operation

east to convert to several euivalent for0s

Depart0ent"8C8


28/45

15*. 7hat is pri0itive flo! chart?

one stable state per ro!

15+.7hat is co0binational circuit?

%utput depends on the given input. @t has no storage ele0ent.

155.7hat is state euivalence theore0 ?

T!o states 6A and 6B, are euivalent if and only if for every possible input

seuence, the outputs are the sa0e and the next states are euivalent

i.e., if 6A (t 3 1) 2 6B (t 3 1) and A 2 B then 6A 2 6B.

15.7hat do you 0ean by distinguishing seuences?

T!o states, 6A and 6B of seuential 0achine are distinguishable if and only if their

exists at least one finite input seuence. 7hich, !hen applied to seuential 0achine causes

different output seuences depending on !hether 6A or 6B is the initial state.

154. Irove that the euivalence partition is uniue

Consider that there are t!o euivalence partitions exists " IA and IB, and IA ) IB. This

states that, there exist ' states 6i P 6; !hich are in the sa0e blocF of one partition and not in the

sa0e blocF of the other. @f 6i P 6; are in different blocFs of say IB, there exists at least on input

seuence !hich distinguishes 6i P 6; and therefore, they cannot be in the sa0e blocF of

IA.

15.Define co0patibility

6tates 6i and 6; said to be co0patible states, if and only if for every input seuence

that affects the t!o states, the sa0e output seuence, occurs !henever both outputs are specified

and regardless of !hether 6i on 6; is the initial state.

15-.Define 0erger graph.

The 0erger graph is defined as follo!s. @t contains the sa0e nu0ber of vertices as the

state table contains states. A line dra!n bet!een the t!o state vertices indicates each

co0patible state pair. @t t!o states are inco0patible no connecting line is dra!n.

1#.Define inco0patibility

The states are said to be inco0patible if no line is dra!n in bet!een the0. @f i0plied

states are inco0patible, they are crossed P the corresponding line is ignored.

11.8xplain the procedure for state 0ini0iation.

1. Iartition the states into subsets such that all states in the sa0e subsets are 1

euivalent.

Depart0ent"8C8


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'. Iartition the states into subsets such that all states in the sa0e subsets are ' euivalent.

*. Iartition the states into subsets such that all states in the sa0e subsets are * euivalent.

1'.Define closed covering

A 6et of co0patibles is said to be closed if, for every co0patible contained in the set, all

its i0plied co0patibles are also contained in the set. A closed set of co0patibles, !hich containsall the states of :, is called a closed covering.

1*.Define 0achine euivalence

T!o 0achines, :1 and :' are said to be euivalent if and only if, for every state in

:1, there is a corresponding euivalent state in :' P vice versa.

1+.Define state table.

>or the design of seuential counters !e have to relate present states and next states. The

table, !hich represents the relationship bet!een present states and next states, is called state

table.

15. Define total state

The co0bination of level signals that appear at the inputs and the outputs of the delays define

!hat is called the total state of the circuit.

1.7hat are the steps for the design of asynchronous seuential circuit?

1. Construction of a pri0itive flo! table fro0 the proble0 state0ent.

'. Iri0itive flo! table is reduced by eli0inating redundant states using the state

reduction*. 6tate assign0ent is 0ade

+. The pri0itive flo! table is realied using appropriate logic ele0ents.

14. Define pri0itive flo! table "

@t is defined as a flo! table !hich has exactly one stable state for each ro! in the table.

The design process begins !ith the construction of pri0itive flo! table.

1.7hat are the types of asynchronous circuits ?

1. >unda0ental 0ode circuits

'. Iulse 0ode circuits

1-.9ive the co0parison bet!een state Assign0ent 6ynchronous circuit and state assign0ent

asynchronous circuit.

Depart0ent"8C8


30/45

@n synchronous circuit, the state assign0ents are 0ade !ith the ob;ective of

circuit reduction. @n asynchronous circuits, the ob;ective of state assign0ent is to avoid critical

races.

14#.7hat are races?

7hen ' or 0ore binary state variables change their value in response to a change in an

input variable, race condition occurs in an asynchronous seuential circuit. @n case of uneual

delays, a race condition 0ay cause the state variables to change in an unpredictable

0anner.

141.Define non critical race.

@f the final stable state that the circuit reaches does not depend on the order in !hich the

state variable changes, the race condition is not har0ful and it is called a non critical race.

14'.Define critical race?

@f the final stable state depends on the order in !hich the state variable changes, the race

condition is har0ful and it is called a critical race.

14*7hat is a cycle?

A cycle occurs !hen an asynchronous circuit 0aFes a transition through a series

of unstable states. @f a cycle does not contain a stable state, the circuit !ill go fro0 one unstable

to stable to another, until the inputs are changed.

14+.ist the different techniues used for state assign0ent.

1. 6hared ro! state assign0ent

'. %ne hot state assign0ent.

145.7rite a short note on funda0ental 0ode asynchronous circuit.

>unda0ental 0ode circuit assu0es that. The input variables change only !hen

the circuit is stable. %nly one input variable can change at a given ti0e and inputs are levels and

not pulses.

14. 7rite a short note on pulse 0ode circuit.

Iulse 0ode circuit assu0es that the input variables are pulses instead of level. The !idth

of the pulses is long enough for the circuit to respond to the input and the pulse !idth 0ust not

be so long that it is still present after the ne! state is reached.

144.Define secondary variables

Depart0ent"8C8


31/45

The delay ele0ents provide a short ter0 0e0ory for the seuential circuit. The present

state and next state variables in asynchronous seuential circuits are called secondary

variables.

14. Define flo! table in asynchronous seuential circuit.

@n asynchronous seuential circuit state table is Fno!n as flo! table because of

the behaviour of the asynchronous seuential circuit. The stage changes occur in independent of

a clocF, based on the logic propagation delay, and cause the states to .flo!. fro0 one to another.

14-. A pulse 0ode asynchronous 0achine has t!o inputs. @f produces an output !henever t!o

consecutive pulses occur on one input line only. The output re0ains at 1 until a pulse has

occurred on the other input line. 7rite do!n the state table for the 0achine.

1#.7hat is funda0ental 0ode.

A transition fro0 one stable state to another occurs only in response to a change in the

input state. After a change in one input has occurred, no other change in any input

occurs until the circuit enters a stable state. 6uch a 0ode of operation is referred to as a

funda0ental 0ode.

11. 7rite short note on shared ro! state assign0ent.

&aces can be avoided by 0aFing a proper binary assign0ent to the state

variables. /ere, the state variables are assigned !ith binary nu0bers in such a !ay that only one

state variable can change at any one state variable can change at any one ti0e !hen a state

transition occurs. To acco0plish this, it is necessary that states bet!een !hich transitions occur

be given ad;acent assign0ents. T!o binary are said to be ad;acent if they differ in only one

variable.

1'. 7rite short note on one hot state assign0ent.

The one hot state assign0ent is another 0ethod for finding a race free state assign0ent.

@n this 0ethod, only one variable is active or hot for each ro! in the original flo! table, ie, it

reuires one state variable for each ro! of the flo! table. Additional ro! are introduced to

provide single variable changes bet!een internal state transitions.

Depart0ent"8C8


32/45

UNIT " -

PROGRAMMABLE LOGIC DEVICES

1*. 8xplain &%:

A read only 0e0ory(&%:) is a device that includes both the decoder and the %& gates

!ithin a single @C pacFage. @t consists of n input lines and 0 output lines.

8ach bit co0bination of the input variables is called an address. 8ach bit co0bination that co0es

out of the output lines is called a !ord. The nu0ber of distinct addresses possible !ith n input

variables is 'n

1+. 7hat are the types of &%:?

1.I&%:

'.8I&%:

*.88I&%:

15. 8xplain I&%:.

I&%: (Irogra00able &ead %nly :e0ory)

@t allo!s user to store data or progra0. I&%:s use the fuses !ith

0aterial liFe nichro0e and polycrystalline. The user can blo! these fuses by passing

around '# to 5# 0A of current for the period 5 to '#Us.The blo!ing of fuses is calledprogra00ing of &%:. The I&%:s are one ti0e progra00able. %nce progra00ed, the

infor0ation is stored per0anent.

1. 8xplain 8I&%:.

8I&%:(8rasable Irogra00able &ead %nly :e0ory)

8I&%: use :%6 circuitry. They store 1=s and #=s as a pacFet of charge in a

buried layer of the @C chip. 7e can erase the stored data in the 8I&%:s by exposing the chip to

ultraviolet light via its uart !indo! for 15 to '# 0inutes. @t is not possible to erase selective

infor0ation. The chip can be reprogra00ed.

14. 8xplain 88I&%:.

88I&%:(8lectrically 8rasable Irogra00able &ead %nly :e0ory)

88I&%: also use :%6 circuitry. Data is stored as charge or no charge on an

insulated layer or an insulated floating gate in the device.88I&%: allo!s selective

erasing at the register level rather than erasing all the infor0ation since the infor0ation


33/45

can be changed by using electrical signals.

1-. 7hat is &A:?

&ando0 Access :e0ory. &ead and !rite operations can be carried out.

1-#. Define &%:

A read only 0e0ory is a device that includes both the decoder and the %& gates

!ithin a single @C pacFage.

1-1. Define address and !ord"

Depart0ent"8C8


34/45

@n a &%:, each bit co0bination of the input variable is called on address. 8ach

bit co0bination that co0es out of the output lines is called a !ord.

1-'. 7hat are the types of &%:.

1. :asFed &%:.




1-*. 7hat is progra00able logic array? /o! it differs fro0 &%:?




0inter0s as in the &%:. 1-+.7hat

is 0asF progra00able?

7ith a 0asF progra00able IA, the user 0ust sub0it a IA progra0 table to the

0anufacturer.

1-5. 7hat is field progra00able logic array?

The second type of IA is called a field progra00able logic array. The user by

0eans of certain reco00ended procedures can progra0 the 8IA.

1-. ist the 0a;or differences bet!een IA and IA

IA"

1. Both A$D and %& arrays are progra00able and Co0plex

Costlier than IA

IA

1. A$D arrays are progra00able %& arrays are fixed

Cheaper and 6i0pler

1-4. Define ID.

Irogra00able ogic Devices consist of a large array of A$D gates and %& gates that

can be progra00ed to achieve specific logic

functions. 1-. 9ive the classification of IDs.

IDs are classified as I&%:(Irogra00able &ead %nly :e0ory), Irogra00able

ogic Array(IA), Irogra00able Array ogic (IA), and 9eneric Array ogic(9A)

1--. Define I&%:.

Depart0ent"8C8


35/45

I&%: is Irogra00able &ead %nly :e0ory. @t consists of a set of fixed A$D gates

connected to a decoder and a progra00able %& array.

'##. Define IA

IA is Irogra00able ogic Array(IA). The IA is a ID that consists of a

progra00able A$D array and a progra00able %& array.

'#1. Define IA

IA is Irogra00able Array ogic. IA consists of a progra00able A$D array and a fixed %&

array !ith output logic.

'#'. 7hy !as IA developed ?

@t is a ID that !as developed to overco0e certain disadvantages of IA, such as longer

delays due to additional fusible linFs that result fro0 using t!o progra00able arrays and 0ore

circuit co0plexity.

'#*. Define 9A

9A is 9eneric Array ogic. 9A consists of a progra00able A$D array and a fixed

%& array !ith output logic.

'#+. 7hy the input variables to a IA are buffered

The input variables to a IA are buffered to prevent loading by the large nu0ber of A$D

gate inputs to !hich available or its co0ple0ent can be connected.

'#5. 7hat does IA 1# specify ?

IA Irogra00able ogic Array

1# Ten inputs

Active %7 %uput

8ight %utputs

'#. 7hat is CID ?

CIDs are Co0plex Irogra00able ogic Devices. They are larger versions of IDs

!ith a centralied internal interconnect 0atrix used to connect the device 0acro cells together.

'#4.Define bit, byte and !ord.

The s0allest unit of binary data is bit. Data are handled in a bit unit called byte. A

co0plete unit of infor0ation is called a !ord !hich consists of one or 0ore bytes.

'#. /o! 0any !ords can a 1x 0e0ory can store ?

A 1x 0e0ory can store 1,*+ !ords of eight bits each

Depart0ent"8C8


36/45

'#-. Define address of a 0e0ory.

The location of a unit of data in a 0e0ory is called

address. '1#. Define Capacity of a 0e0ory.

@t is the total nu0ber of data units that can be stored.

'11. 7hat is &ead and 7rite operation ?

The 7rite operation stores data into a specified address into the 0e0ory and the &ead

operation taFes data out of a specified address in the 0e0ory.

'1'. 7hy &A:s are called as Eolatile ?

&A:s are called as Eolatile 0e0ories because &A:s lose stored data !hen the po!er is

turned %>>.

'1'.Define &%:.

&%: is a type of 0e0ory in !hich data are stored per0anently or se0i per0anently.

Data can be read fro0 a &%:, but there is no !rite operation

'1*. Define &A:.

&A: is &ando0 Access :e0ory. @t is a rando0 access read!rite 0e0ory. The data can

be read or !ritten into fro0 any selected address in any seuence.

'1+. ist the t!o categories of &A:s.

The t!o categories of &A:s are static &A:(6&A:) and dyna0ic &A: (D&A:).

'15. Define 6tatic &A: and dyna0ic &A:

6tatic &A: uses flip flops as storage ele0ents and therefore store data indefinitely as

long as dc po!er is applied. Dyna0ic &A:s use capacitors as storage ele0ents and cannot

retain data very long !ithout capacitors being recharged by a process called refreshing.

'1. ist the t!o types of 6&A:

1. Asynchronous 6&A:s

'. 6ynhronous Burst 6&A:s '14.ist

the basic types of D&A:s

>ast Iage :ode D&A:,8xtended Data %ut D&A:(8D% D&A:),Burst 8D%

D&A: and 6ynchronous D&A:.

'1. Define a bus

A bus is a set of conductive paths that serve to interconnect t!o or 0ore functional

co0ponents of a syste0 or several diverse syste0s.

Depart0ent"8C8


37/45

'1-. Define Cache 0e0ory

@t is a relatively s0all, highspeed 0e0ory that can store the 0ost recently used

instructions or data fro0 larger but slo!er 0ain 0e0ory.

''#. 7hat is the techniue adopted by D&A:s.

D&A:s use a techniue called address 0ultiplexing to reduce the nu0ber of address

lines.

''1.9ive the feature of


38/45

''-. 7hat are the types of &%: ?

1. :asFed &%:.




*##. 7hat is progra00able logic array? /o! it differs fro0 &%:?




0inter0s as in the &%:. *#1.7hat

is 0asF progra00able?

7ith a 0asF progra00able IA, the user 0ust sub0it a IA IA progra0 table to the

0anufacturer.

*#'.9ive the co0parison bet!een I&%: and IA.

I&%: IA

And array is fixed and %& array is Both A$D and %& arrays are

progra00able. Irogra00able.

Cheaper and si0ple to use. Costliest and co0plex than I&%:6.

Iart O B 2 (#,1,',,1#,11,1+,15)

ist all the 0in ter0s

Arrange the0 as per the nu0ber of ones based on binary euivalent

Co0pare one group !ith another for difference in one and replace the bit !ith dash.

Continue this until no further grouping possible.

The unchecFed ter0s represent the pri0e i0plicants.

> 2 7 3 3 7

') Deter0ine the pri0e i0plicants of the function

> (7,,,) 2 (1,+,,4,,-,1#,11,15)

ist all the 0in ter0s

Depart0ent"8C8


39/45

Arrange the0 as per the nu0ber of ones based on binary euivalent

Co0pare one group !ith another for difference in one and replace the bit !ith dash.

Continue this until no further grouping possible.

The unchecFed ter0s represent the pri0e i0plicants.

> 2 3 7 3 7 3 3 7 3 7

:ini0u0 6et of pri0e i0plicants > 2 3 7 3 3 7

*) 6i0plify the Boolean function using J0ap.

>(A,B,C,D,8) 2 (#,',+,,-,1*,'1,'*,'5,'-,*1)

>ive variables hence t!o variable F 0aps one for A 2 # and the other for A 2 1.

> 2 AB8 3 BD8 3 AC8

+) %btain the canonical su0 of products of the function 2 AB 3 ACD

2 AB (C 3 C)(D 3 D) 3 ACD (B 3 B)

2 ABCD 3 ABCD 3 ABCD 3 ABCD 3 ABCD

5) 6tate the postulates and theore0s of Boolean algebra.

3 # 2 V 1 2

3 2 1 V 2 #

3 2 V 2

3 1 2 1 V # 2 #

() 2

3 2 3 2

3 ( 3 ) 2 ( 3 ) 3 () 2 ()

( 3 ) 2 3 3 2 ( 3 ) ( 3 )

( 3 ) 2 () 2 3

3 2 ( 3 ) 2


40/45

>an out

Io!er dissipation

Iropagation Delay

$oise :argin

>an @n

%perating te0perature

Io!er supply reuire0ents

. 8xplain !ith neat diagra0 ho! an open collector TT operates.

Disadvantages of other fa0ilies

Diagra0 of open collector gate TT

Theory

7orFing principle

-. 8xplain the different applications of open collector TT.

7ired logic

Co00on bus syste0

Drive a la0p or relay

1#. 8xplain in detail about schottFy TT.


Diagra0 of schottFy TT

Theory

7orFing principle

Advantages

11.8xplain in detail about three state gate.


8xplanation about three state gate

Theory

7orFing principle

1'.8xplain !ith necessary diagra0s :%6 P C:%6.

I:%6

$:%6

C:%6

Diagra0s

Depart0ent"8C8


41/45

1*.Design a +bit binary addersubtractor

circuit. Basic euations

Co0parison of euations

Design using t!os co0ple0ent

Circuit diagra0

lip >lop

ogic Diagra0

15.Design a logic circuit to convert the BCD code to 8xcess O * code.

Truth Table for BCD to 8xcess O * conversion.

J0ap si0plification

ogic circuit i0ple0enting the Boolean 8xpression

1.Design and explain a co0parator to co0pare t!o identical !ords.

T!o nu0bers represented by A 2 A*A'A1A# P B 2 B*B'B1B#

@f t!o nu0bers eual I 2 AiBi

%btain the logic 8xpression .

%btain the logic diagra0.

14.Design a seuential detector !hich produces an output 1 every ti0e the input seuence 1#11

is detected.

Construct state diagra0

%btain the flo! table

%btain the flo! table P output table

Transition table

6elect flip flop

8xcitation table

ogic diagra0

Depart0ent"8C8


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1.. 8xplain in detail about serial in serial out shift register.

BlocF diagra0

Theoretical explanation

ogic diagra0

7orFing


43/45

Iroble0 created due to races

Classification of races

&e0edy for races

cycles

'*.. 8xplain the different 0ethods of state assign0ent

Three ro! state assign0ent

6hared ro! state assign0ent

>our ro! flo! table

:ultiple ro! state assign0ent

Irevention of races.

(a,b,c,d) 2

(#,1,*,+,,-,15) %btain the truth table

>ro0 the truth table realie the expressions for the outputs and inputs

&ealie the logic diagra0.

'.8xplain !ith neat diagra0s a &A: architecture.

Different :e0ories

Classification of 0e0ories

&A: architecture diagra0

Ti0ing !avefor0s

Coincident Decoding &ead

!rite operations

Depart0ent"8C8


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'4.8xplain in detail about IA and IA.

Basic &%:

Classification of I&%:

ogic difference bet!een Iro0 P IA

ogic diagra0 i0ple0enting a function

ogic difference bet!een Iro0 P IA

ogic diagra0 i0ple0enting a function

'.8xplain !ith neat diagra0s a &%: architecture.

Different :e0ories

Classification of 0e0ories

&%: architecture diagra0

Ti0ing !avefor0s

Coincident Decoding

&ead !rite operations

Depart0ent"8C8


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