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March 7 2006 Rice University Slide 1 doc.: IEEE 802.11-06/0466r0 Submission Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07 Notice: This document has been prepared to assist IEEE 802.11. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor grants a free, irrevocable license to the IEEE to incorporate material contained in this contribution, and any modifications thereof, in the creation of an IEEE Standards publication; to copyright in the IEEE’s name any IEEE Standards publication even though it may include portions of this contribution; and at the IEEE’s sole discretion to permit others to reproduce in whole or in part the resulting IEEE Standards publication. The contributor also acknowledges and accepts that this contribution may be made public by IEEE 802.11. Patent Policy and Procedures: The contributor is familiar with the IEEE 802 Patent Policy and Procedures < http:// ieee802.org/guides/bylaws/sb-bylaws.pdf >, including the statement "IEEE standards may include the known use of patent(s), including patent applications, provided the IEEE receives assurance from the patent holder or applicant with respect to patents essential for compliance with both mandatory and optional portions of the standard." Early disclosure to the Working Group of patent information that might be relevant to the standard is essential to reduce the possibility for delays in the development process and increase the likelihood that the draft publication will be approved for publication. Please notify the Chair <[email protected] > as early as possible, in written or electronic form, if patented technology (or technology under patent application) might be incorporated into a draft standard being developed within the IEEE 802.11 Working Group. If Authors: Name Address Company Phone Email Theodoros Salonidis 6100 Main St. #366 Houston, TX 77005 Rice Universi ty [email protected] Jingpu Shi 6100 Main St. #366 Houston, TX 77005 Rice Universi ty [email protected] Edward Knightly 6100 Main St. #380 Houston, TX 77005 Rice Universi ty [email protected] Joseph Camp 6100 Main St. #366 Houston, TX 77005 Rice Universi ty [email protected]
Transcript
Page 1: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 1

doc.: IEEE 802.11-06/0466r0

Submission

Modeling Imperfect Clock Synchronization in CSMA Wireless Networks

Date: 2006-03-07

Notice: This document has been prepared to assist IEEE 802.11. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein.

Release: The contributor grants a free, irrevocable license to the IEEE to incorporate material contained in this contribution, and any modifications thereof, in the creation of an IEEE Standards publication; to copyright in the IEEE’s name any IEEE Standards publication even though it may include portions of this contribution; and at the IEEE’s sole discretion to permit others to reproduce in whole or in part the resulting IEEE Standards publication. The contributor also acknowledges and accepts that this contribution may be made public by IEEE 802.11.

Patent Policy and Procedures: The contributor is familiar with the IEEE 802 Patent Policy and Procedures <http:// ieee802.org/guides/bylaws/sb-bylaws.pdf>, including the statement "IEEE standards may include the known use of patent(s), including patent applications, provided the IEEE receives assurance from the patent holder or applicant with respect to patents essential for compliance with both mandatory and optional portions of the standard." Early disclosure to the Working Group of patent information that might be relevant to the standard is essential to reduce the possibility for delays in the development process and increase the likelihood that the draft publication will be approved for publication. Please notify the Chair <[email protected]> as early as possible, in written or electronic form, if patented technology (or technology under patent application) might be incorporated into a draft standard being developed within the IEEE 802.11 Working Group. If you have questions, contact the IEEE Patent Committee Administrator at <[email protected]>.

Authors:Name Address Company Phone Email

Theodoros Salonidis 6100 Main St. #366

Houston, TX 77005Rice University

[email protected]

Jingpu Shi 6100 Main St. #366

Houston, TX 77005Rice University

[email protected]

Edward Knightly 6100 Main St. #380

Houston, TX 77005Rice University

[email protected]

Joseph Camp 6100 Main St. #366

Houston, TX 77005Rice University

[email protected]

Page 2: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 2

doc.: IEEE 802.11-06/0466r0

Submission

Motivation• Several CSMA MAC protocols use frame-based

synchronization– Increase aggregate throughput

• MMAC– Save Power

• SMAC– However: assume perfect synchronization

• Impact of imperfect synchronization not known• Our contribution

– Formally analyze performance under clock drift differences, carrier sense and topology asymmetries

– Consider fairness and starvation issues.

Page 3: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 3

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Submission

Synchronized CSMA Protocol

• Periodic transmission frames with fixed size, split in a contention phase and a data phase.

• Contend at the beginning of frame using CSMA + REQ/GRANT handshake

• If win contention, transmit until the end of frame

Page 4: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 4

doc.: IEEE 802.11-06/0466r0

Submission

Imperfect Synchronization

• Factors affecting performance– Clock drifts– Carrier Sense tx of previous cycle– REQUEST packet size

Page 5: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 5

doc.: IEEE 802.11-06/0466r0

Submission

Guard Time (GT) System

• Insert Guard Time at end of data phase• GT size > max clock drift in the network

– Carrier Sense tx of previous cycle is disabled– Clock drifts and REQ packet size still affect

performance

• Is a GT system better than a no GT system?

Page 6: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 6

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Submission

Starvation

• Starvation for slower flow 2– If clock drift > contention window of flow 1

• Persists whether GT is used or not

Page 7: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 7

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Submission

Single Cell Analysis Markov Chain Model

• Capture impact of clock drift differences• State x means node x transmits (# states = # nodes)• Memoryless property (chance of a flow winning

cycle k+1 depends on which flow transmits on cycle k)

• Stationary probabilities of MC = flow throughputs

2-node example

Page 8: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 8

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Submission

Single Cell Analysis Results (Fixed drifts)

• 10 flows, • W=32 minislots• Clock drifts spaced 10 mini-

slots apart

• Later flows get lower throughput

• Exponential decrease as clock drift increases

• Flows 32 mini-slots late from earliest flow starve

• Guard Time less fair

Page 9: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 9

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Submission

Example Analysis (GT system)

p12= p22 = P(x1 > + x2) p11=1 - p12*where x is chosen backoff and is drift p21=1 - p22

• Guard Times exacerbate the unfairness• Earlier Flow 1 always has the advantage

Page 10: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 10

doc.: IEEE 802.11-06/0466r0

Submission

Single Cell Analysis Results (Random drifts)

• 10 flows, W=32 mini-slots• Clock drifts drawn from

uniform distribution [0 to max clock drift]

• Measure lowest throughput as a function of max clock drift / W

• Even if clock drift less than contention window, exponential decrease of lowest throughput

Page 11: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 11

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Submission

Multi-hop Topologies

• More issues in addition to clock drift– Carrier sense (not all nodes sense the same thing)

– High collision due to hidden terminals from transmitter (gets worse as REQ packet size increases).

• Two simple scenarios to isolate and study in detail using our model– Flow in the Middle

– Information Asymmetry

Page 12: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 12

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Submission

Flow in the Middle Scenario

• Middle flow senses both outer flows but outer flows sense only the middle flow

• Middle flow can starve sensing misaligned transmissions of outer flows

• Model applies: use one state for outer flows and another state for middle flow

Page 13: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 13

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Submission

Flow in the Middle scenario

• Early outer flow and middle flow drifts = 0, W=32

• Throughputs as drift of late outer flow increases

No GT: Middle flow starves if outer flows relative drift > W

GT: Throughput of middle flow increases

No GTGT

Page 14: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 14

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Submission

Flow in the Middle scenario

• Relative drift of outer flows =16, W=32 mini-slots

• Throughputs as drift of middle flow increases

No GT

No GT: Middle flow: Steep decrease with a stable region C

A B C D

16

16a

GT

GT: Middle flow: Smoother decrease but no stable region

Page 15: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 15

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Submission

Information Asymmetry Scenario

• tx1 unable to sense flow 2• tx2 senses flow 1 (through GNT of rx1)• Flow 1:disadvantage even under perfect synchronization

– Can succeed only if its backoff + REQ packet < backoff of flow 2

• Disadvantage of flow 1 aggravated as REQ packet size increases

Page 16: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 16

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Submission

Information Asymmetry Scenario

• Fix drift of flow 1 to 0, REQ packet size = 16 mini-slots• Throughputs as drift of advantaged flow 2 increases

GBNo GB

No GT and GT: perform similarly (carrier sense no effect)

Cross-over point: when drift difference = REQ packet size

Page 17: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 17

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Submission

To GT or not to GT?

• Pros– Better fairness in single-hop

systems– Protection regions for clock

phase jitter

• Cons (multi-hop systems)– Flows may starve irrespective of

their own contention windows due to high clock drift difference of their outer flows

– Hard to exploit protection regions

– Two-hop max drift bound

No GT• Pros

– Easier to extend MC model to arbitrary topologies

– Allow for simpler solutions• Only address clock drift differences

and REQ packet size.

– One-hop max drift bound

• Cons– Guard Time overhead– Less fairness in single-hop

networks– No inherent protection against

clock phase jitter

GT

Page 18: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 18

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Submission

Counter-starvation algorithm for GT systems

• Goal– Achieve per-flow throughputs above a set of reference

slotted aloha rates

• Operation– Utilize a model for arbitrary topologies for GT systems to

adjust contention windows.– Rule: ask neighbors with higher throughput to increase their

contention windows by a certain factor

• Outcome– Proportionally fair minimum throughput guarantees.– Throughputs greater than the reference rates.

Page 19: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 19

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Submission

Counter-starvation Algorithm

Page 20: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 20

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Submission

Conclusions

• Single-hop networks– Starvation: if W < max clock drift– Min throughput: exponential decrease with max clock drift– GT system less fair than no GT system

• Multi-hop networks– No GT systems

• Offer protection regions against clock phase jitter, yet solutions harder to implement

• Starvation sensitive to clock drifts of two-hop neighborhood

– GT systems allow for simpler solutions with predictable performance at the expense of GT overhead.

• Distributed CW adjustment mechanism to counter starvation in a GT system

Page 21: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 21

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Submission

Backup Slides

Page 22: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 22

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Submission

Example Analysis(no GB system)

p12=P(x1 > + x2) p11=1 - p12p22=P(x1 > x2) p21=1 - p22Access Probability 2 = p12/(1 + p12 - p22 )

1 = 1 - 2 *where x is chosen backoff interval and is the clock drift

Page 23: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 23

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Submission

Counter Starvation Algorithm, Results (1)

• Only counter size of REQUEST packet

Page 24: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 24

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Submission

Counter Starvation Algorithm, Results (2)

• Counter everything

Page 25: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 25

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Submission

Single Cell Analysis Results (3)

• Random clock phases, Fairness index

Page 26: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 26

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Submission

General Topology, Analysis on Size of REQ Packet

• Compute lowerbound instead, which is tight• Open form and closed form expression

Page 27: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 27

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Submission

Multihop Analysis Lower Bound Validation

• 15 flows randomly placed in 1000x1000 region

Page 28: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 28

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Submission

Multihop Analysis Model Decoupling

• When flow i is contending with three different flows separately, the lowerbound (in this case the throughput ) is given by,

Page 29: Doc.: IEEE 802.11- 06/0466r0 Submission March 7 2006 Rice UniversitySlide 1 Modeling Imperfect Clock Synchronization in CSMA Wireless Networks Date: 2006-03-07.

March 7 2006

Rice UniversitySlide 29

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Submission

General Topology, Analysis on Clock Drift


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