This paper has been accepted for publication by 2016 IEEE 17th Workshop on Control and Modeling for Power Electronics, IEEE COMPEL. DOI: 10.1109/COMPEL.2016.7556751 Citation: S. Park and J. Rivas-Davila, "A design methodology for class-D resonant rectifier with parallel LC tank," 2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), Trondheim, 2016, pp. 1-6. IEEE Xplore URL: http://ieeexplore.ieee.org/document/7556751/
Transcript
This paper has been accepted for publication by 2016
IEEE 17th Workshop on Control and Modeling for Power
Electronics, IEEE COMPEL.
DOI: 10.1109/COMPEL.2016.7556751
Citation: S. Park and J. Rivas-Davila, "A design
methodology for class-D resonant rectifier with parallel LC
tank," 2016 IEEE 17th Workshop on Control and Modeling
for Power Electronics (COMPEL), Trondheim, 2016, pp.
1-6.
IEEE Xplore URL:
http://ieeexplore.ieee.org/document/7556751/
A Design Methodology for Class-D ResonantRectifier with Parallel LC Tank
Sanghyeon Park and Juan Rivas-DavilaElectrical Engineering
Abstract—This paper presents a design methodology for thetuning of a class-D half-wave resonant rectifier with a parallelLC resonant tank input network. Class-D resonant rectifiersoffer numerous advantages at high operating frequencies thatare leveraged here in the design of a high-voltage rectifier. Theabsence of a systematic design process, however, has been alimiting factor. Designers have been relying largely on parametricvariation during transient simulation to design a rectifier withresistive input impedance at the fundamental frequency of oper-ation. In this paper, we propose a systematic design procedurethat begins with universal design curves applicable to any rectifierdesign of this topology. This is followed by parameter selectionand a convergence check that ensures the rectifier operates withthe desired output voltage. Experimental results confirm thevalidity of the design method for both linear and nonlinear res-onant capacitances. Based on the outlined procedure, a 25 MHz500 V rectifier with resistive input impedance is designed andexperimentally verified.
I. INTRODUCTION
A class-D resonant rectifier with a parallel LC tank issuitable for high-voltage conversion at high switching fre-quencies (> 10 MHz) because of the lower voltage stresson the semiconductor devices and the lower equivalent inputimpedance at the fundamental of the switching frequency [1].Moreover, this type of rectifier achieves ZVS transitionsacross the diodes [2] for high efficiency operation. At highfrequencies is also possible to achieve larger voltage gains byconnecting in series the output of multiple capacitively isolatedrectifiers [3]. Unfortunately, current tuning techniques lack asystematic design approach that accounts for the non-linearbehavior of the junction capacitance of the diodes, and/or dontprovide a means to find parameters that achieve resistive inputimpedance [4]–[8]. Consequently, the tuning process has beenlengthy, and has not guaranteed the convergence of the outputvoltage to the intended value under realistic load conditions.
This paper presents a design methodology for a class-D resonant rectifier. The design curve based method allowsquick selection of circuit parameters with minimal calculation.The proposed methodology can also predict if the rectifierwill converge to the desired output voltage or settle into anunintended operating point. Design curves that are applicableto both linear and nonlinear capacitance are proposed andexperimentally verified. A rectifier designed by the proposed
is(t)L Cextra
Cj,1
Cj,2Cb
RLCoD2
D1
Zrect
(a) Class-D resonant rectifier
is(t)L C
Vo/2
VoD2
D1
Zrect
X
vX(t)
(b) Equivalent Circuit
Fig. 1: Class-D resonant rectifier and the equivalent circuit
methodology is built and tested to show that the circuit behavesas intended.
Section II provides the analysis on the rectifier operation andthe theoretical background of the proposed design methodol-ogy. Section III illustrates the design procedure by designinga 350 V 27 MHz current-driven rectifier with a resistiveinput impedance. Section IV presents experimental results tovalidate the provided circuit analysis and the design example.Section V concludes the paper.
when D2 is ON. Provided that Cb and Co are large enough topresent negligible impedance at the switching frequency, theirsteady-state behavior can be modelled as a DC voltage sourceof Vo/2 and Vo, respectively.
A. Rectifier Input Impedance
Fig. 2 shows the waveforms vX(t), is(t) and io(t) of theclass D resonant rectifier of Fig. 1a as well as the equivalentcircuits during the various commutation intervals within theswitching cycle.
is(t)L C
D1,D2 OFF
is(t)L
Vo/2
Vo
D2 ON
is(t)L
Vo/2D1 ON
io(t)
X
X
ϕ
ϕ
ϕ
vX(t)
io(t)
is(t)
D1
ON
D2
ON
D1D2
OFF
D1D2
OFF
D1D2
OFF
Φ
Vo
2π π
Is
Io = io(t) Io
θ
Fig. 2: The rectifier waveforms and equivalent circuits indifferent operation modes
Here we approximate the fundamental component of vX(t)waveform in Fig. 2 as a sine wave with Vo/2 amplitude andθ/2 phase offset. To justify this approximation, let us lookat two extreme cases of the rectifier operating states. At oneextreme, the resonant current in the LC tank is large and thecapacitor C is charged and discharged very fast. In this case,vX(t) takes the form of a square wave and the fundamentalcomponent of vX(t) is a sine wave having the amplitude of4π · (Vo/2) = 1.27(Vo/2). At the other extreme where theresonant current is small, the capacitor is charged slowly suchthat vX(t) barely reaches Vo (or 0) before it starts to decrease(or increase). Here vX(t) waveform is close to a triangle waveof which the fundamental component is a sine wave withthe amplitude of 8
π2 · (Vo/2) = 0.81(Vo/2). The analysis onthose two cases reveals that in all the possible operating statesbetween the two extremes the amplitude of the fundamentalcomponent of vX(t) can be approximated to Vo/2 with equalto or less than 27% error. Also, in either cases the phase offsetof the fundamental component sine wave is roughly θ/2 whereθ represents the phase interval where both D1 and D2 areoff. For that reason we approximate the phase offset of thefundamental component of vX(t) by θ/2.Zrect is defined as the input impedance of the rectifier
at the switching frequency. By the approximation above, themagnitude of the impedance |Zrect| is expressed as
|Zrect| ≈Vo2Is
where Is is the amplitude of the sinusoidal input current is(t).Also, the phase of the impedance Zrect can be approximatedby
Zrect ≈θ
2− Φ
where Φ is the phase offset of is(t).
B. Universal Design Curves
Fig. 3 shows a plot of the analytical solutions of the input-to-output current gain (Io/Is) (Fig. 3a) and the input impedancephase Zrect (Fig. 3b), plotted against θ and ω
√LC.
20 40 60 80 100 120 140 160
θ (deg)0.7
0.8
0.9
1.0
1.1
1.2
1.3
ω√ L
C
0.00
0.04
0.08
0.12
0.16
0.20
0.24
0.28
0.32
(a) Io/Is
20 40 60 80 100 120 140 160
θ (deg)0.7
0.8
0.9
1.0
1.1
1.2
1.3
ω√ L
C
100
75
50
25
0
25
50
75
100
(b) Zrect
Fig. 3: Analytical solution of the class-D resonant rectifier
The solutions are found by imposing the following fourconditions on the circuit of Fig. 1b: a) When D1 switches fromthe ON-state to the OFF-state (at φ = 0 in Fig. 2), the currentthrough D1 is zero, and b) the voltage across the inductor is−Vo/2; c) when D2 switches from the OFF-state to the ON-state (at φ = θ in Fig. 2), the voltage across the inductor isVo/2; and d) Half a cycle after D1 turns OFF (at φ = π inFig. 2), the current through D2 reduces to zero and turns D2
OFF for periodicity.
Fig. 4 shows the analytical solution of (Io/Is) and Zrectthat are plotted against a new design parameter u defined as
u := (ω√LC − 1)
Vo
Is√L/C
The definition of u is constructed such that (Io/Is) and Zrectplotted against u remain almost constant with respect to thevertical axis variable ω
√LC.
1.0 0.5 0.0 0.5 1.0u
0.7
0.8
0.9
1.0
1.1
1.2
1.3
ω√ L
C
0.00
0.04
0.08
0.12
0.16
0.20
0.24
0.28
0.32
(a) Io/Is
1.0 0.5 0.0 0.5 1.0u
0.7
0.8
0.9
1.0
1.1
1.2
1.3
ω√ L
C
100
75
50
25
0
25
50
75
100
(b) Zrect
Fig. 4: Analytical solution of the rectifier rearranged in termsof parameter u
Since Fig. 4 plots are roughly independent of ω√LC, they
can be approximated into two-dimensional plots in Fig. 5. Thedesign curves are universally valid for all class-D rectifierdesigns and are a convenient way of determining variouscircuit parameters during the rectifier design process.
The curves in Fig. 5 are valid even when the resonantcapacitor is nonlinear. The model’s validity with nonlinearcapacitance is important because significant portion, if not all,of the resonant capacitor may consist of highly nonlinear diodejunction capacitance. To make the model useful for nonlinearcapacitance, the effective capacitance Ceff
∣∣Vo
is introduced.Ceff
∣∣Vo
is defined as the total amount of charge circulatingin the LC resonant tank divided by the voltage swing Vo, orsimply put, the average of the C vs. V curve in the range of
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
u
(a) Io/Is
-90°
-60°
-30°
0°
30°
60°
90°
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
u
(b) Zrect
Fig. 5: Universal design curves for the class-D rectifier currentgain and phase
0 to Vo. In the class-D rectifier depicted in Fig. 1a, Ceff∣∣Vo
is calculated by the following equation:
Ceff∣∣Vo
= Cextra +2∫ Vo
0Cj(v)dv
Vo
where Cextra is parallel-connected linear capacitance andCj(v) is the diode junction capacitance at reverse voltage ofv across the diode. Ceff
∣∣Vo
is used in place of C to obtainu when curves in Fig. 5 are used to design a rectifier withnonlinear capacitance.
C. Rectifier Equivalent Circuit
The rectifier in Fig. 1b can be further simplified to theequivalent circuit of Fig. 6.
is(t)
Rrect
Zrect
jXrect VoIo
Fig. 6: Simplified circuit model of the class-D resonant recti-fier
The curves in Fig. 5 are used to determine the output currentIo, the input reactance Xrect and the input resistance Rrect.Once u is given, the corresponding Io/Is value is obtainedfrom Fig. 5a. |Zrect| is then obtained by noting that |Zrect| ≈Vo
2Isas discussed in Subsection II-A, thus
IoIs
=2IoVo· Vo
2Is≈ 2Io
Vo|Zrect|
Zrect for the given u is also found by simply looking up thecorresponding value in Fig. 5b. Finally, Rrect and Xrect arecalculated as |Zrect| cos Zrect and |Zrect| sin Zrect, respec-tively.
0pF
100pF
200pF
0.1V 1V 10V 100V 1000V
Ju
nc
tio
n C
ap
ac
itan
ce
Reverse Voltage
Fig. 7: Measured junction capacitance vs. reverse voltage plotof a C3D04060E SiC diode [9].
Xrect and Rrect may be tailored depending on the designgoal. To maximize the overall efficiency, Rrect should bemade as large as possible to minimize the influence of thedriver’s output resistance. If the design goal is to achievemaximum power transfer, Rrect should be made equal to thedriver’s output resistance. In either case, it is desirable tomake the input impedance purely resistive or cancel out jXrect
completely by adding an impedance −jXrect in series.
III. DESIGN OF A CLASS-D CURRENT-DRIVEN RECTIFIER
The design methodology described above is best illustratedby the following example. Consider designing a class-D reso-nant rectifier of Fig. 1a driven by a sinusoidal current source.We want the circuit to meet the following specifications:
• output voltage Vo = 350 V,• output current Io = 70 mA,• switching frequency f = 27 MHz,• parallel-connected linear capacitance Cextra = 107 pF;• use two C3D04060E SiC diodes [9] for D1 and D2, with
the measured C-V curve in Fig. 7;• the load at the output RL is a 5 kΩ resistor;• the input voltage is in phase with the input current at the
switching frequency f .
A. First Design
Since the circuit is to be driven by a current source, inorder for the voltage and the current to be in phase, Zrectshould be zero, which means u = −0.3 according to plotin Fig. 5b. Fig. 5a shows (Io/Is)
∣∣u=−0.3
= 0.3. Since therequired Io is 70 mA, we set the input current amplitude Isas Io/0.3 = 233 mA.
The resonant capacitance is the sum of Cextra and twodiodes’ junction capacitances Cj1(v) and Cj2(v), which arehighly nonlinear. To calculate Ceff
∣∣Vo
, we integrate Cj(v) ofC3D04060E [9] from zero to Vo = 350 V, multiply it bytwo (since Cj1(v) and Cj2(v) are identical), divide it by Voand add Cextra to get Ceff
∣∣350 V
= 166 pF. Combining the
obtained Ceff and the definition of u, L that makes u = −0.3is found to be 207nH.
Since the dc-blocking capacitor Cb and the output filtercapacitor Co should exhibit negligible impedance comparedto Ceff , we choose Cb = Co = 50 · Ceff ≈ 8 nF. Table Ishows component values of the designed circuit.
B. Convergence Analysis
The next step of the design process is to check the existenceof an undesired operating point. If such a point exists, therectifier driven by a sinusoidal current source might settle intoa steady-state operation of undesired Vo and Io. In order to seeif the designed circuit has any operating point other than theintended one, graphical analysis is carried out by drawing Iovs. Vo line and comparing it with the load line for RL = 5 kΩ.
Fig. 8 shows the load line (black dotted line), and therectifier Io vs. Vo curve (orange solid line). To draw thiscurve, Ceff
∣∣Vo
is evaluated for multiple values of Vo from0 V to 500 V. This array of Ceff
∣∣Vo
is entered into the
0mA
20mA
40mA
60mA
80mA
0V 100V 200V 300V 400V 500V
Ou
tpu
t C
urr
en
t
Output Voltage
Rectifier output current 5 kΩ load line
Fig. 8: Output current supplied by the 27 MHz rectifier (orangesolid line) designed in Subsection III-A, and the currentdrawn by the 5 kΩ resistive load (black dotted line). Threeintersections of two curves are marked by blue dots, from leftto right: the undesired convergence point, divergence point,and the desired convergence point. Blue arrows indicate thedirection to which the operating point moves.
definition of u to produce the array of u(Vo), which in turn isused in conjunction with Fig. 5a to find Io. The plot revealsone divergence point at (Vo, Io) = (216 V, 43 mA), and twoconvergence points at (54 V, 11 mA), (350 V, 70 mA). Whenthe output voltage is between 54 V and 216 V, the rectifierIo vs. Vo curve is drawn below the load line, meaning therectifier can’t supply a larger current than that consumed bythe load resistor, thus can’t push Vo all the way up to the targetoutput voltage 350 V. Not only the circuit might settle intothe undesired convergence point during the start-up, but alsoit becomes difficult to use bang-bang control since the output
TABLE I: The list of component values for the current-driven rectifier of Fig. 1a designed in Section III
Vo Io f D1, D2 Cextra RL Co, Cb L Is[V] [mA] [MHz] Part Number [pF] [kΩ] [nF] [nH] [mA]
350 70 27 C3D04060E 107 5 8 207 233
voltage might fall into the aforementioned voltage range andconverge at 54 V.
C. Redesign
Removing the unwanted convergence point requires changein at least one of the design specifications. Possible remediesinclude increasing Io, using diodes whose junction capacitancedecreases more gradually with voltage, decreasing Vo or f .Here we choose to increase Io from 70 mA to 200 mA andredesign the rectifier. By following the procedure describedabove, L changes to 202 nH, RL to 1.75 kΩ, and Is to667 mA. The corresponding analysis plot is shown in Fig. 9by the blue dotted line. The convergence point exists onlyat (Vo, Io) = (350 V, 200 mA), meaning that the circuitconverges to the desired operating point and the design iscomplete.
0mA
50mA
100mA
150mA
200mA
250mA
0V 100V 200V 300V 400V 500V
Ou
tpu
t C
urr
en
t
Output Voltage
Rectifier output current 1.75 kΩ load line
Fig. 9: Output current supplied by the 27 MHz rectifier (orangesolid line) redesigned in Subsection III-C, and the currentdrawn by the new 1.75 kΩ resistive load (black dotted line).The single intersection of two curves, marked by the bluedot, indicates the rectifier always converges to the desiredconvergence point.
IV. EXPERIMENTAL RESULTS
A. Universal Design Curves
Fig. 10 shows experimental verifications of proposed designcurves denoted by dotted lines. Three rectifiers are designedwith different resonant inductance, diodes, output voltages andswitching frequencies as specified in Table II. Data points aremarked on the plots to represent the measured operating stateof the rectifiers. The data distribution shows good correlation
TABLE II: Rectifier designs for universal design curve verifi-cations in Fig.10
Rectifier D1, D2 Cextra L Vo fNo. Part Number [pF] [nH] [V] [MHz]
TABLE III: Comparison of the rectifier model in Section IIIand the actual circuit in Fig. 11
Is at f Zrect at f Vo Io[mA] [degree] [V] [mA]
Model 667 0 350 200Experiment 878 1.6 350 203
with the proposed design curves, proving the validity of thepresented model.
B. Current-Driven Rectifier Implementation
The 70 W 27 MHz 350 V rectifier designed in Subsec-tion III-C is implemented and shown in Fig. 11. As plotted inFig. 12, the input voltage and current waveforms are in-phasewith phase difference of only 1.6.
The rectifier represents a resistive input impedance of251 Ω, which can be adjusted by adding an impedancematching network at the input. The efficiency of the rectifieris 80%. Most of the power loss is due to the large circulatingcurrent in the LC tank, which can be reduced by choosing asmaller Cextra value at the beginning of the design procedure.
V. CONCLUSION
This paper presented the design methodology of a class-Dresonant rectifier. The curve-based design method allows rapidselection of component values and detection of an undesiredconvergence points. Experiments were conducted to confirmthe proposed design curves. A current-driven rectifier basedon the proposed methodology was built and tested.
ACKNOWLEDGMENT
The authors would like to thank the Energy/Power Manage-ment Systems focus area of the SystemX Alliance for fundingthis work.
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0.00
0.10
0.20
0.30
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
u
model Rectifier 1
Rectifier 2 Rectifier 3
(a) Io/Is vs. u
-90°
-60°
-30°
0°
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60°
90°
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
u
model Rectifier 1
Rectifier 2 Rectifier 3
(b) Zrect vs. u
Fig. 10: Experimental verification of proposed universal design curves using three different rectifier designs specified in Table II.Proposed model curves are denoted by black dotted lines and corroborating experimental data are marked as colored markers.
input
L Cextra
Co
outputCb
D1
D2
RL
Fig. 11: Implementation of the 70 W 27 MHz 350 V current-driven rectifier designed in Subsection III-C
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-1.0A
-0.5A
0.0A
0.5A
1.0A
-250V
-125V
0V
125V
250V
0ns 37ns 74ns
Time
Input Voltage Input Current
Fig. 12: Measured input current (blue dotted line) and voltage(orange solid line) of the 27 MHz current-driven rectifier atthe steady state
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