2422 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 35, NO. 12, DECEMBER 19x8

[I41 T. F. Hasan, S. U. Katzman, and D. S. Perloff, “Automated electri- cal measurements of registration errors in step-and-repeat optical li- thography systems,” IEEE Trans. Electron Devices, vol. ED-27, pp. 2304-2312, 1980.

[I51 M. G. Buehler, S. D. Grant, and W. R. Thurber, “Bridge and van der Pauw sheet resistors for characterizing the linewidth of conduct- ing layers,” J . Electrochem. SOC., vol. 125, pp. 650-654, 1978.

[I61 D. Yen, L. W. Linholm, and M. G. Buehler, “A cross-bridge test structure for evaluating the linewidth uniformity of an integrated cir- cuit lithography system,’’ J. Elecrrochern. SOC. , vol. 129, pp. 2313- 2318, 1982.

Double-Layer Process for Wide Gate Recess Etch

P. LAMARRE AND M. P. ZAITLIN

Abstract-A new gate recess procedure for forming a wide gate re- cess is described. The technique uses a double layer of standard PMMA resist and a sensitive copolymer of PMMA. With this technique, the width of the recess (and hence the gate edge to n+ layer distance d, ) can be controlled by using different developers or by altering the ratio of polymers in the bottom layer. A numerical technique is used to model the breakdown voltage of FET’s having different gate recess widths, which indicates that the optimum distance d, is in the range of 0.2 to 0.7 pm depending on the thickness of the channel layer.

I . INTRODUCTION There have been many reports of improved resistance to short-

term burnout and long-term degradation in GaAs power FET’s by using a wide recess between the gate and the n+ layer [ 11-[4]. For the most commonly used gate etches, however, the distance d, be- tween the gate edge and the n+ layer is an uncontrolled variable and is determined by such factors as how well the PMMA resist adheres to the GaAs substrate. The distance d, varies from wafer to wafer and can often be in the range of 0.0 to 0.2 pm. This dis- tance is smaller than what would be considered optimum. Since deep recesses also tend to be wider ( i .e . , greater values of d, ), this is particularly a problem when shallow etches are required. There are techniques for fabricating wide gate recesses [5], [6], but they are complicated and difficult to control.

In this brief report we describe a simple procedure for creating a wide recess etch for an electron-beam-written gate using a double layer of a standard PMMA resist and a thin layer of a sensitive copolymer of PMMA. The width of the recess is controlled by varying the polarity of the developer and can be varied separately from the gate length. We have used a numerical technique to ex- amine the effect of the gate edge to n+ layer distance on breakdown voltage and conclude that the optimum value of d, for standard FET’s is the range of - 0.2-0.7 pm. This is very similar to the range of d, provided by the new recess etch.

11. EXPERIMENTAL Fig. I displays a new double-layer process for controlling the

gate recess. Fig. l(a) gives the starting configuration for this dou- ble-layer process. The top layer is approximately 1 p m of a stan- dard PMMA on top of a thin layer of a sensitive copolymer of PMMA. The copolymer of PMMA has been studied for some time and is fairly well understood [7]-[9].

During electron-beam exposure, electron scattering in the resist

Manuscript received March 21, 1988; revised June 20, 1988. The authors are with the Research Division, Raytheon Company, Lex-

IEEE Log Number 8824179. ington, MA 02173.

1.1 prn PMMA

COpOlyrner 0.1 pm

Equienergy PMMA

Fig. 1. A new double layer process for controlling the gate recess. (a) Starting condition. (b) Electron-beam exposure. (c) After development. (d) After gate recess etch. (e) After metal deposition. (f) After metal liftoff with wide gate recess.

yields an equienergy density contour [lo] as shown in Fig. I(b). The fact that the bottom layer is more sensitive combined with the higher dose shown in Fig. l(b) gives a strongly undercut resist profile with a single exposure and development as shown in Fig. l(c). Fig. 2(c) is an SEM micrograph of a resist sidewall using this process. The bottom opening, which may be manipulated with the developer, defines the gate recess etch as shown in Fig. l(d). The developers used were mixtures of ECA : ethanol and MIBK : isopropanol. The developers were chosen to control recess width (see Fig. 2). The top edge of the resist defines the gate me- tallization as shown in Fig. l (e) . the final liftoff with the wide gate recess is shown in Fig. l ( f ) .

Fig. 2 shows three SEM micrographs. Fig. 2(a) is from a wafer with the new process developed with ethylcellosolve acetate and ethanol. The wide recess is clearly evident. Fig. 2(b) is a micro- graph of a wafer also using the new process but developed with methyl isobutyl ketone and isopropanol. Notice that, in Fig. 2(a) and (b), the two micrographs display the same gate length, but the recess etch width is different. The difference in recess width is a function of the different developers and is related to their polarity. The developers were chosen by examining solvent formulating maps for the acrylic resins [ 1 11.

The recess etch width may also be modified by changing the ratio of polymers in the bottom layer. The bottom layer is a blend of solvents and polymers. ECA (ethyl cellosolve acetate) is the solution in which the polymers are suspended. The polymers are poly methyl methacrylate (PMMA) and a more sensitive copolymer of PMMA. Changing the ratio of polymers changes the relative sensitivity of the resist (i.e., adding more copolymer makes the resist more sensitive).

0018-9383/88/1200-2422$01 .OO 0 1988 IEEE

IEEE TRANSACTIONS ON ELECTROii DEVICES. VOL 35. NO I!. DECF.MBFR 19x8

(c) Fig. 2. Three SEM wafers demonstrating the new process. (a) Developed

with ECA and ethanol. (b) Developed with MIBK and isopropanol. (c) Typical resist profile from this process.

111. EFFECT ON BREAKDOWN VOl..I.AGE

The main benefit of this development is to provide FET's de- signed for power generation with an improved and more controlled gate-drain reverse breakdown voltage. Increasing the width of the gate recess effectively causes the gate-drain voltage to be dropped over a larger distance, resulting in a lower. average electric field and an enhanced breakdown voltage [4], [12]. The effect is espe- cially large for structures with thin channels (i .e. , low pinchoff voltages) because of their greater lateral spreading of the electric field.

We calculate the breakdown voltage by numerically solving Poisson's equation for an FET assuming a large negative voltage on the gate and a grounded source and drain [4] . The geometry of the FET is shown in the inset of Fig. 3 and has a gate situated directly on the channel where the n layer has been removed. The ionization rate is then determined from the electric field and inte-

N = I x 10'Em3

I I I

0 0 2 0.4 0 6 0 8

d, ( p m )

Fig. 3 . Normalized breakdown voltage V,,, for a CaAs MESFET as a func- tion of the gate edge to n + distance d,. The different curves correspond to different channel thicknesses. The label for each curve is the pinchoff voltage for that channel thickness. For the calculation, the n i layer is assumed to have a doping level of 2 x 10l8 cm-3 and a thickness of 0.16 pm. The geometry used for the calculation is shown in the inset.

grated between the gate and drain. The voltage is then varied until the ionization integral reaches unity. That gate voltage is then the breakdown voltage Vrh. Although there are no adjustable parame- ters to this calculation, the ionization rate in the high fields near the gate edge is extrapolated from measured values at lowcr fields. Consequently, the calculated ratio of breakdown voltages for two different geometries is more accurate than the absolute value cal- culated for the breakdown voltage itself. In Fig. 3 we show the breakdown voltage normalized to the case of an infinitely wide re- cess (which is equivalent to having no contact layer) V,,(n,ax). The values of Vrh( max) increase with decreasing channel thickness and range from 11.4 V for V,, = 5 . 5 V to 22 V for V,> = 1 V. The pinchoff voltage is defined as nyt '/2t.

The detrimental effect of having too narrow a gate recess is clear from the calculations. Even for the large pinchoff devices. having a gate to recess edge distance d, of less than - 0.2 pm results in a dramatic decrease in breakdown voltage. And, for the small pinch- off devices the effect is even more significant.

IV. DISCUSSION The effects of having too narrow a gate recess can be detected

during device fabrication. Occasionally wafers processed in our laboratory show breakdown voltages in the range of - 5 V instead of the more common 12-18 V . Invariably these wafers display a very narrow gate recess with very little space visible between thc gate edge and the recess edge when viewed in a scanning electron microscope.

As a tcst of this gate recess technique, one wafer was fabricated as described in the preceding section but with two sets of FET's having pinchoff voltages of - 2 and - 4 V. The FET's in one set were processed to have a value of d, of - 0.3 pin while thr other set was processed to have a much smaller value o f -0.1 prn. The breakdown voltages averaged over a total of 104 devices was 10-14 V for devices in the first set and only 7-9 V for dekicca in the second set in agreement with the model described here (see Fig. 4 ) . Thc uniformity of the wide gate recess process appears better

2424

1 4 ,

13-

0 0 8’

00

0 e.” 12- I doping level

El n = 4.5 x E17 2 0

IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 35, NO. 12. DECEMBER 1988

11:

10: Breakdown

(volts)

.* wide recess 0 .

t standard recess

. . - 4 - 3 - 2 - 1 0

Pinchoff (volts)

.!% I standard recess 1

Z=0.16mm

4 0 , . . . . , . . . . , . . . . , . . . . 4 - 3 - 2 - 1 0

Pinchoff (volts) Fig. 4. dc electrical measurements from two wafers that clearly shows the

increase in breakdown voltage from the wide gate recess etch process.

than the single-layer process (note the distribution of points in Fig. 4). More data are required to confirm this.

The same spreading of the gate-drain voltage over a longer dis- tance that improves the breakdown voltage should have other ad- vantages as well. The smaller electric field should reduce the tend- ency for thermal “hot” spot creation near the gate edge and also reduce any electromigration of impurities near the gate. Both “hot” spots and electromigration could be a source of device failure.

Although this technique is most useful for FET’s typically used for X-band with dopings of the order of 2 X 10” cm-3 and gate lengths of 0.5 to 1.0 pm, the technique has been successfully used with millimeter-wave FET’s. With a doping level of 4.5 X 10” cm-3 and 0.25-pm gates, a 160-pm FET produced 91 mW (0.57 W/mm) at 32 GHz at a gain of 5 . 5 dB and 27.3-percent power added efficiency. At the same frequency, a 300-pm FET produced 171 mW with a gain of 3.8 dB and an efficiency of 23.4 percent.

The only disadvantage associated with the wide gate etch would be a slightly increased parasitic resistance, and it is a minor factor for power FET’s. The increase comes from the current flowing an extra distance through the channel instead of through the more highly conducive contact layer. Taking 600 Q/square as a typical channel resistance, increasing the recess width even by as much as 0 .3 pm would only increase the parasitic resistance by less than 0.2 Q . mm. This would cause an effective decrease in g, by a factor of ( 1 + g , r ) or only a few percent.

REFERENCES

[ 11 S. H . Wemple et a [ . , “Long-term and instantaneous burnout in GaAs power FET mechanisms and solutions,” IEEE Trans. Electron De- vices, vol. ED-28, pp. 834-840, 1981.

[2] P. Saunier et a l . , “High-performance K-band GaAs power field-effect transistors prepared by molecular beam epitaxy,” Appl. Phys. Lett.,

[3] K. Katsukawa et al., “Failure analysis and reliability for X-band power GaAs FET,” NEC Res. Dev . , no. 71, pp. 82-87, Oct. 1983.

[4] M. P. Zaitlin, “Reverse breakdown in GaAs MESFET’s,” lEEE Trans. Electron Devices, vol. 33, pp. 1635-1639, 1986.

[5] H. M. Macksey et a l . , “Fabrication of n + ledge channel structure for GaAs FETs with a single lithography step,” Electron. Lett . , vol. 2 I , no. 21, Oct. 10, 1985.

[6] H. Fukui, “Optimization of low-noise GaAs MESFET’s,” IEEE Trans. Electron Devices, vol. Ed-27, pp. 1034-1037, June 1980.

[7] M. J. Hatzakis, “PMMA copolymers as high sensitivity electron re- sists,” Vue. Sei. Technol., Nov./Dec. 1979.

[8] E. D. Wolf er u l . , “Electron-beam fabrication of quarter-micron T- shaped-gate FETs using a new tri-layer resist system,’’ in IEDM Tech. Dig. , pp. 613-616, 1983.

[9] I. Haller et a l . , “Copolymers of methyl methacrylate and methacrylic acid and their metal salts as radiation sensitive resists,’’ J. Elecrro- chem. Soc., vol. 126, no. 1, Jan. 1979.

[ IO] N . S . Viswanathan et a l . , “Monte Carlo simulation of spatially dis- tributed beams in electron-beam lithography,” J . Vue. Sei. Technol., no. 6, Nov./Dec. 1975.

[ 111 Elvacite Acrylic Resins Properties and Uses, Product Info., E-61906. Rev. 3/84, DuPont Company.

[ 121 J. P. R. David et al., ‘Gate-drain avalanche breakdown in GaAs power MESFET’s,” IEEE Trans. Electron Devices, vol. ED-29, no. 10, Oct. 1982.

VOI. 42, pp. 966-968, 1983.

High-Temperature Latchup Characteristics in VLSI CMOS Circuits

F. S . SHOUCAIR

Abstract-A simple worst case analytical model of holding currents and an empirical model of trigger currents are reported and shown to agree with experimental measurements in the range of 25225°C. Whereas standard bulk CMOS inverters and ring oscillators are in- variably found to latchup near 125”C, their counterparts built on epitaxial wafers remain latchup free up to at least 250°C. These results add to an ongoing systematic effort to model high-temperature effects in integrated MOS technologies and provide worst case latchup infor- mation in the commerical temperature range and beyond.

I. INTRODUCTION Although latchup in CMOS technologies is now a relatively well

understood degradation mechanism, it remains an important con- sideration in the design of down-scaled VLSI processes. The most common precautions that help inhibit latchup are usually imple- mented as minimum “layout design rules” and generally limit the extent of down-scaling for a given process. Other precautionary measures including the use of guard rings, deep-trench isolations, or epitaxial layers lower sheet resistance and raise holding currents required to sustain latchup, but increase process complexity and may limit down scaling.

For a given CMOS structure, the two key parameters that deter- mine susceptibility to latchup are the parasitic bipolar transistors’ current gains and their associated distributed base-emitter shunting resistances. The magnitudes of both of these parameters have been shown to decrease significantly with decreasing temperature [2], [3]. Consequently, it has been suggested, and verified [ l ] , [2], that

Manuscript received March 3, 1988; revised August 15, 1988. The author is with the Department of Electrical Engineering, Brown

University, Providence, RI 02912. IEEE Log Number 8824216.

0018-9383/88/1200-2424$01 .OO 0 1988 IEEE