21
DP CTS Update and Overview Mike Engbretson GRL Chief Technology Engineer April 30, 2012
DP CTS Update and Overview Mike Engbretson GRL Chief Technology Engineer April 30, 2012
Agenda ¡ GRL Introduction
¡ VESA Specification Version Numbers
¡ DP 1.2 CTS Test Requirements
¡ Transition from DP1.2 to DP1.2a Specification Preview
2
3 3
• Only one DisplayPort Standard specification version number active at any given time • With the publication of DisplayPort Standard Specification Ver.1.2
in JAN 2010, Specification Ver.1.1a document was retired
• As for DPCD Revision Number (at DPCD Address 00000h), multiple revision numbers may co-exist • When people casually refer to a “DP1.1a” product, they actually
mean a DP device supporting DPCD Revision Number 1.1 only
DisplayPort Version Numbers
4 4
• Link and PHY Compliance Test Specifications following DisplayPort Standard Version Number • Ver.1.1a available
• NOTE: Link CTS Ver.1.1b with addition of audio transport test to be published in DEC 2010 ~ JAN 2010
• Phase 1 of Ver.1.2 covering some of the additional features in DisplayPort1.2 (e.g., HBR2, Audio HBR) going to GMR (General Membership Review) in DEC 2010 ~ JAN 2011
• Other DP-derivative standards (eDP and iDP) have their own version numbers • eDP Standard Ver.1.2 published in MAY 2010 • iDP Standard Ver.1.0 published in APR 2010
DisplayPort Standard Version Number (continued)
DisplayPort 1.2 Compliance Testing
¡ VESA Test Implementation Task Group has been formed to manage transition from DP1.1a to DP1.2 test program with regards to qualifying test solutions – Mike E. Chairman, Bob Crepps Vice-Chair.
¡ Some DP 1.2 source and sink products have already been tested and certified under DP1.2 requirements with agreed upon test plan between test lab and Bob Crepps.
¡ GRL recommends you test to the DP 1.2(a) requirements ¡ As a manufacturer, you will want to know if you meet DP1.2
requirements.
¡ Sink PHY testing must follow DP1.2a CTS requirements due to CTS issue
¡ If failures occur but pass DP 1.1a, you can still get approved under DP1.1a program until DP1.2 program is in place.
5
DisplayPort 1.2 Compliance Testing
¡ DP devices supporting only RBR/HBR are tested to DP 1.2 CTS since some RBR/HBR test items were updated in CTS 1.2 ¡ Testing of RBR/HBR is sometimes referred to as ‘DP 1.2 Core’
¡ DP logo does not differentiate between 1.1a or 1.2 or any feature differences. ¡ Example: a Sink that supports RBR/HBR carries the same logo as one
that supports HBR2.
6
DisplayPort 1.2 Compliance Testing
7
DisplayPort 1.2 Compliance Testing ¡ DP 1.2 Major Test Items ¡ 1.2 PHY RBR/HBR/HBR2
¡ Source Electrical: Realtime Scope (Tek and Agilent)
¡ Sink Electrical: AWG, BertScope, or J-BERT
¡ 1.1b Link Layer Test
¡ Link Negotiation Testing for HBR2
¡ EDID
¡ Interoperability (Various sources, sinks, cables)
¡ Refer to Interop CTS for list
¡ Other 1.2 functionality tested based on plan mutually agreed upon with DP Compliance Chair (Bob Crepps) and GRL
¡ DP ++ Major Test Items ¡ Dual Mode Eye Diagram Measurement to be added
8
DP1.2a DP Specification Preview
9
¡ Equalizer Changes for HBR and HBR2 ¡ In order to rationalize the Jitter and Eye Margins from TP1 >
TP2 > TP3 > TP3_Eq, new Equalizer values were defined.
¡ Specification change impacts DP1.2 PHY CTS, requiring a roll to DP1.2a PHY CTS.
¡ Both DP 1.2a Specification and DP1.2a PHY Specification will be released soon.
¡ HBR2 TP3_EQ Definitions ¡ DP1.2 – 2 Equalizers ¡ Source & Sink
What Changes in 1.2a DP Spec?
10
ωz = 0.64 x 106
¡ DP 1.2a - Single Equalizer for both
What Changes in 1.2a DP Spec? ¡ HBR Equalizer Definition
11
ωz = 0.725 x 106
What Changes in 1.2a DP PHY CTS? ¡ Reference to new TP3_Eq Equalizer values in DP 1.2a
Specification
¡ Eye Height for sources reduced from 120mV to 90mV ¡ Same value as Sink Stressed Eye Calibration
¡ Addition of TP1-TP2 ISI ¡ Required to achieve proper ISI at TP3_Eq
¡ Addition of DP++ (Dual Mode) Eye and Jitter Tests ¡ Omission from the DP1.2 Version
12
HBR/HBR2 Sink Calibration
Calibration Challenge!
Calibration Challenge ¡ ISI at TP3-Eq is a Function of: ¡ BERT Rise Time
¡ ISI Channel Used
¡ Cables and Connectors Used
¡ Equalizer Frequency Response
14
Method of Implementation ¡ Combine two ISI Channels into one.
¡ Example: JBERT with Opt. J20 ª 100ps TTCs
ª 6dB Attenuation
ª DC Block
ª 1 Meter SMA Cables
ª 28” ISI Channel (Opt. J20)
ª 1 Meter SMA Cables
ª Short SMA Cable/Connector for Calibration
ª Wilder DP Mated Pair Adapter
15
Cables/Connectors for TP3_Eq ISI Calibration ¡ No Short Cable = 196 mUI ISI
¡ Short Cable + SMA Barrel = 207 mUI ISI
¡ SMA-SMA Adapter = 219.8 mUI
16
SMA-SMA Adapter Short SMA
Cable
SMA-SMA Barrel
To Get HBR TP3_Eq ISI ¡ Replace 100ps TTC with 150ps TTC
¡ Reduce ISI Channel to 20”
17
Recommended ATC and TE Vendor Requirements ¡ Document TP3_Eq ISI Calibration Measurement for HBR2 and
HBR as part of Data Set ¡ Eye Diagram and ISI Measurement
¡ Measure ISI at TP3_Eq to Target Value +/- 5% of Specification ¡ 5% Tolerance to allow small differences in physical setup
¡ Next Step is to rationalize Crosstalk with single ISI channel.
18
What about DP in Thunderbolt? ¡ Does TBT Compliant mean DP Compliant? ¡ Section 3 of DP PHY CTS - DP Source (HBR/RBR)
¡ Section 7 of the HDMI 1.4 CTS – HDMI Source Testing
¡ Test DP++ electrical signals through a DP a compliant Dual Mode adapter
¡ Functional test spec takes the place of the DP Interop Spec.
¡ Link Layer has been Certified DP Compliant at the chip level
¡ GRL Certified
¡ One mini-DP connector – Can have 3 possible logos!
19
Features & Performance
Summary ¡ Current version of the DP Specification is DP1.2
¡ Compliance test program is in transition between 1.1a and 1.2(a)
¡ The difference between 1.2 and 1.2a DP Specification is the definition of the equalizer for TP3_Eq ¡ Resulting in changes in the DP PHY CTS from 1.2 to 1.2a
¡ DP (HBR/RBR) is a subset of Thunderbolt Testing and uses the same mDP connector and is being tested to the DP 1.2 logo requirements
20
Lab Location & Contact Santa Clara, California 3500 Thomas Road, Suite A Santa Clara, CA 95054 USA Boeblingen, Germany Herrenberger Str. 130 71034 Boeblingen, Germany Hsinchu, Taiwan 2F-1, No. 93, Shuiyuan St. Hsinchu 30069, Taiwan 新竹市水源街93號2F-1 Taipei, Taiwan 2F, No. 252, Sec. 1, Neihu Rd. Neihu Dist., Taipei City 11493, Taiwan 台北市內湖路一段252號2F (西湖捷運站2號出口旁)
Johnson Tan, CEO [email protected] Mike Engbretson, Chief Engineer [email protected] How Wu, Taiwan Business Manager [email protected] Sandy Chang, Taiwan Technical Director [email protected]
21
Your NEW Taiwan test labs for DP, TBT, HDMI, MHL, SATA, USB, and PCIe!
