44
1. Contents
1. DRAM General Backgrounds
1-1. DRAM?
1-2. Architecture
2. DRAM의 구성 및 주요 동작
2-1. Cell 동작
2-2. Data 동작
2-3. 내부 전원 동작
3. DRAM Design Trends
3-1. DDR/DDR2/DDR3
3-2. Package Approach & TSV
1-1. DRAM?
Page 3
• 메모리 종류 중에서 가장 큰 시장을 점유(2위 NAND Flash) – 2007년 기준 약 54% 점유, Nand/Nor Flash 약 26%, 11% 수준
• 종류 – MM(Main Memory) – 일반 PC, notebook, 일반가전, … – Server – 대용량 서버, 안정성, ASP high, … – Graphic – Graphic Card (nVidia, ATI, …), PS3, XBOX, Wii, … – Mobile – cellular phones, PDA, MID, … – 특수 용도 – 우주항공, 군용기기, 소량 고가…
• 대체적으로 규모의 경제(대박과 쪽박) • 다양한 제품군을 portfolio로 갖추는 것이 생존전략상 필요.
2013/11/8
Memory Cell 구조
Page 4
DRAM (Dynamic Random Access Memory)
SRAM (Static Random Access Memory)
NVM (Non-Volatile Memory)
DRAM
Cell Structure Norm. size
WL
BL BL BL
Vss
Vcc
WL
BL
FG
SRAM NVM 1 Tr. & 1 cap. = 1.0x 6 Tr. (4Tr. +2R) = 3.0x 1 Tr. = 0.6x
Application Main memory
Graphics Buffer,Cache Bios,Card memory
2013/11/8
BL
WL
1968년 R.H.Dennard US patent 3,387,286
Phillips 4K DRAM 양산화
1-Tr,1-Cap Cell (1X-1Y)
1. Word Line
Access Transistor Gate Control ( On/Off )
Storage Node의 High Data 전위보다 승압 된 전원 Level 사용
Poly Layer(또는 WSi2, W)
2. Bit Line
Data Transfer Line
Read/Write 공용
Half Vcore level Precharge for Power Saving
3. Access Transistor
Switch기능의 NMOS Transistor 1개
Refresh특성강화를 위해 Vt 높게 설정
4. Capacitor
Data 저장 장소
Storage Node의 Charge량에 의해 Data유지
REFRESH가 필요함.
1971년 2K DRAM
DRAM CELL
Page 5 2013/11/8
CPU & Memory Trend
Pentium 586
286
Conv. DRAM
Pentium PRO
EDO FPM
386
FPM
486
SDR EDO
PC 100
PC 133
DDR 266/333
Pentium II
Pentium III
Pentium 4
~ 1986 1989 2002 2000 1998 1994
60Mhz
125Mhz
250Mhz
500Mhz
1Ghz
2Ghz
10Mhz
Micro-processor
Memory Type(MHz)
Data
Rate
& C
PU S
peed
DDR2 533/667
2004
Quad
DDR3 1333/1600
P4 Dual core
3Ghz
2008
DDR4?
2006 2010
4Ghz
Hexa Octal
x2 x2 x2
Next Generation
Page 6 2013/11/8
1-2. DRAM Architecture (Core)
Page 7
분류 위치 기능
BLSA array Mem Cell array unit 외곽 B/L Sense Amplifier Array
WLD array Mem Cell array unit 외곽 W/L Driver Array
Sub-hole BLSA와 WLD array의 교차지점 BLSA 및 WLD 구동 신호의 driver, IO switch 포함
X-decoder W/L방향의Mem cell array 인접 W/L Decoder
X-Hole Bank와 Bank 사이 혹은
1 Bank의 center, X-dec 인접 W/L Decoder 및 BLSA 동작 관련 controller
Row 동작(Active, Precharge, Refresh) controller
Y-decoder B/L방향의Mem cell array 인접 Y-select(BLSA array중 data 입출력이 되는 BLSA를 선택) 신호의 decoder
Core
Y-Decoder
X-D
ec
& H
ole
X-D
ec
& H
ole
X-D
ec
& H
ole
X-D
ec
& H
ole
Y-Decoder Y-Decoder Y-Decoder
Y-Decoder Y-Decoder Y-Decoder Y-Decoder
ADD/CMD Peri. DQ Peri.
Dec/
Hole
WTD,DBSA Y-dec 하단 BLSA와 연결된 Local IO선의 Write Driver, Sense Amplifier(DBSA)
Cell Array 영역(혹은 Bank)에 인접한 회로부분을
Core 라고 통칭한다.
2013/11/8
1-2. DRAM Architecture (Peripheral)
Page 8
분류 비고 기능
CMD Dec CMD input 으로 부터 각종 기능의 command를 decoding
Add Latch Row/Col address에 동기 시킴 Address input에서 Row/Column Address로 전환.
X/Y Controller Row/Column operation 의 각종 기능 제어 회로
Data Controller Write/Read 동작 제어 회로
Input Buffer CMOS level swing으로 전환 Data Input Buffer 및 제어
Output Driver Data Output Driver 및 제어
AD
D/C
MD
Y-Decoder
X-D
ec
& H
ole
X-D
ec
& H
ole
X-D
ec
& H
ole
X-D
ec
& H
ole
Y-Decoder Y-Decoder Y-Decoder
Y-Decoder Y-Decoder Y-Decoder Y-Decoder
ADD/CMD Peri. DQ Peri.
DQ
Reference VREFC, VREFP 등 각 기능 block에서 사용하는 내부 전원의 기준(reference) 전원 생성
Core 이외의 영역으로서, Address/Command, Data
In/out 의 입출력 및 제어를 위한 회로부분을
Peripheral 이라고 통칭한다.
Pow
er
DLL DLL (Delay Locked Loop) 회로의 각종 기능 제어 회로
Generator VPP, VCORE, VBB 등 외부전원(VDD/VSS)으로부터 각 기능 block에서 사용하는 내부 전원 생성
2013/11/8
SDRAM에의 응용 ( parallel pipe line )
BL S/A
WL
BL BL#
Data Bus I/O Bus Data Sense Amp
Write Driver
Pipe Register
Data Input Register
Data Input Buffer
Data Output Buffer
I/O PAD & Port
YI
Read Path
Write Path cell
Pin<0:2> Pout<0:2>
실제 Digital CMOS Logic Circuit
Page 9 2013/11/8
in 20123Write/Read Timing Of Synchronous DRAM
tCK 3.75ns
PC133 SDR CL2
DDR-266 (PC 2100)
CL2
DDR2-533 CL4
tCK=7.5ns
DQ
DQ
tCK=3.75ns
READ
READ
READ
DQ
DQS /DQS
DQS
tCK=7.5ns
DQ
DQ
WRITE
DQ
DQS /DQS
DQS
WRITE
WRITE
Write Latency=0
Write Latency=1(CL-1)
Write Latency=AL+CL-1
TAA=15ns
TAA=15ns
TAA=15ns
tCK=7.5ns
tCK=7.5ns
DDR3-1066 CL8
tCK=1.875ns READ
TAA=15ns
DQ
DQS /DQS
WRITE
tCK 1.875ns DQ
DQS /DQS
Write Latency=AL+CL-1
Page 10 2013/11/8
DRAM SPEC
Page 11
• DRAM이 갖춰야 할 구조, functionalities, AC and DC characteristics, packages, and ball/signal assignments.
• JEDEC(Joint Joint Electron Device Engineering Council) • 주요 내용
– Package Ballouts – Addressing – Functionalities (act, write, read, precharge, 기타 commands…) – IO characters (AC setup/hold, Data setup/hold, …) – Voltage conditions – Pin cap, ..
• 모든 회로 설계는 SPEC을 기본적으로 만족해야 한다.
2013/11/8
DRAM SPEC
Page 12
EX) Clock to Data Strobe Relationship
2013/11/8
DRAM 설계 중점 사항
Page 13
• DRAM SPEC – 기본 자격, intel validation(인증, 홍보효과), 비즈니스 가부에 큰 영
향
• NET DIE 개수 & yield net die x yield가 중요. – Global 경쟁심화, chicken game
• Power 소비 – ASP, server, notebook, mobile, 점점 더 중요.
• Performance(성능) – ASP, Graphic market
2013/11/8
Page 14
BANK
CLK DLL
WL
BL BL
S/A
I/O Addr.
Vpp, Vbb, Vblp, Vcp, Vref
Column Dec.
RAS
CAS
WE
Control Circu
its
Row
Dec.
Sta
te m
ach
ine
DRAM Block Diagram.
DRAM의 구성 및 주요 동작
2013/11/8
Page 15
DRAM Cell의 동작원리 – Charge Sharing
WL
BL BL
S/A
2013/11/8
Unit Cell array Matrix
Page 16
CELL Array
Matrix SW
D
SA Array SH
CELL MAT S
WD
SA Array SH
CELL MAT S
WD
SA Array SH
CELL MAT S
WD
SA Array SH
CELL MAT S
WD
SA Array SH
CELL MAT S
WD
SA Array SH
Sub Word Line Driver
Sub Hole
Sense Amplifier Array
2013/11/8
Cell leakage
Page 17
1. Junction Leakage 성분
2. Cell to Cell Leakage 성분
3. Cell Tr. Off-Current
4. GIDL (Gate Induced Drain Leakage)
5. Dielectric Leakage
6. Gate TR. Oxide Leakage
7. Insulator (nitride, TEOS) Leakage
2013/11/8
AUTO REFRESH
8K cycle/64ms
When this command is input from the IDLE state, the synchronous DRAM starts auto-refresh operation. During the auto-refresh operation, refresh address and bank select address are generated inside the Synchronous DRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 8192times are required to refresh the entire memory. Before executing the auto-refresh command, all the bank must be IDLE state. In addition, since the Precharge for all bank is automatically performed after auto-refresh, no Precharge command is required after auto-refresh.
Refresh tRFC
Refresh tRFC
tREFi=7.8us
WRITE / READ 동작 Refresh tRFC
WRITE / READ 동작
AREF AREF AREF
WRITE / READ 동작
tREFi=7.8us
AREF PCG_ALL
tRP=15n tRFC=80n
ACT
Page 18 2013/11/8
SELF REFRESH
Self-Refresh Entry[SELF] : When this command is input during the IDLE state, the Synchronous DRAM starts self-refresh operation. After the exicution of this command, self-refresh continues while CKE is Low. Since self-refresh is performed internally and automatically, external refresh operations are unnecessary. Self-Refresh Exit[SELFX] : When this command is executed during self-refresh mode, the Sync DRAM can exit from self-refresh mode. After exiting from self-refresh mode, the Sync DRAM enters the IDLE state.
~7.8us
SREF
SREF PCG_ALL
tRP=15n
CLK
CKE
~7.8us ~7.8us
CLK
CKE
SREFX
SREFX
CKE
CLK
ACT
tRFC(@SDR)
200 clock cycle(@DDR)
Page 19 2013/11/8
2013/11/8
REFRESH를 하는 방법
Page 20
Refresh Issues : the Dynamic RAM
1 Cell Tr Circuit
W/L
B/L
SN
PL
SN - Jn Leak : ~10fA/cell
100 1000 10000 1E-4 1E-3
0.1
1
5
20 40 60 80
95
99
99.9
99.999 50 o C
77 o C
85 o C
Temperature dependence of Refresh Time
Cum
ula
tive F
ailure
Bits
[%]
tREF [msec]
253ms 346ms 1050ms
1.85s 2.92s 12s
About 0.65x degradation per 10 o C Temperature increase.
Page 21 2013/11/8
2013/11/8
COMMAND Decoder ( STATE Machine )
• Control Pin input Decoding
• To Define Internal state on DRAM
• To Address Multiplexing
Mode Decoder ( EMRS / MRS / TMRS )
• MRS명령 입력 시 내부 MRS Address Setting
ADDRESS Decoder
• ACT 명령 시 내부 Row Address Setting ( WL Selection )
• READ/WRITE 명령 시 내부 Column Address Setting ( Column Selection )
What is Decoder ?
• logic circuit that converts an N-bit binary input code into M outputs
• activated for only one of the possible combinations of inputs
• 2N possible input combination (N : # of input)
Decoder In DRAM
Page 22
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
OUT
(A03)
0
1
2
3
4
5
6
7
A0b A1b A2b
A0 A1b A2b
A0b A1 A2b
A0 A1 A2b
A0b A1b A2
A0 A1b A2
A0b A1 A2
A0 A1 A2
A0
A0b
A0
A1
A1b
A1
A2
A2b
A2
A02<0>
A02<1>
A02<2>
A02<3>
A02<4>
A02<5>
A02<6>
A02<7>
Decoder BASIC I (3x8 decoder)
Page 23 2013/11/8
single stage Decoder scheme 2stage Predecoder scheme
# of transistor = 20 x 1024 = 20,480
Large fanout requirement of buffers generating Xi’s
series-connected transistors limit discharge
# of transistor = 10 x 1024 + α = 12,000
Group 2 bits and predecoder the word using 2-bit segment
Decoder BASIC III
Page 24 2013/11/8
WL_D
EC
MWL 0
MWL 1
MWL 2
MWL 255
POLY
METAL
Metal Word Line Strapping
Word Line Architecture (example I)
Page 25 2013/11/8
px0
px2
px0
px2
px1
px3
px1
px3
MW
L_D
EC
mwlb 0
mwlb 1
mwlb 2
mwlb 64
mwlb
PX
PXB
SWL SWL
PX
mwl
mwlb
NMOS-TYPE CMOS-TYPE
Parallel Driving
Word Line Architecture (example II)
Page 26 2013/11/8
동작 파형
Page 27 2013/11/8
Internal Voltage 필요성
Page 28
BL
WL
C
T
VCC vs VPP
GND vs VBB*
1/2VCC vs 1/3
GND vs VBB
VCC vs VCORE
Vt loss
Leak, new
Power, Wl turn on,
leak
Power, Reliability
WL-ON
WL-OFF
VBLP
BULK
V-cell
Vss vs 1/2Vcore Reliability plate
Vref Interface I/O
Vext vs Vint Power, Reliability Vperi
2013/11/8
Internal Voltage Generator
VREF
Gen.
Peripheral Circuits
CLOAD
VDD
VPERI
S/A VCP
Memory(S/A) Array & Core(hole) Circuits
VPP
VBLP VBB
VDD
power up pwrup for initialize
ref. level
VPP
Gen.
Half-Vcc
Gen.(VBLP,VCP)
VBB
Gen. VDD
VCORE
Page 29 2013/11/8
DLL (Delay-Locked Loop)
Page 30
External CLK
Desired DQ Data #1 Data #2 Data #3 Data #4
Internal CLK (No DLL)
td1
Internal CLK (w/ DLL)
Data #1 Data #2 Data #3 Data #4 DQ
td2
td2
td1+td2 have a large variation over P.V.T corners.
eCLK Variable DELAY LINE
Delay Controler
D Q DRAM CORE
(Receiver)
Data Output Buffer
Delay Monitor(Replica)
Data
iCLK
CLKout
I/O Pad
Phase Detector
Data Latch
t1+t2
t2 t1 td
Analytically, we want to the delay between CLKout and eClk is ntCK-t2 (where n = integer)
DLL
2013/11/8
3. DRAM Design Trends
• Basic Trends – High Performance (tech shrink, cu metal, DLL, …)
– Low Power (tech shrink, cu metal, internal voltage)
– Low Cost (tech shrink, architecture, cell mat, 공정단순화, …)
• DDR2 – 4bit prefetch
– ODT (On-Die Termination)
• DDR3 – 8bit prefetch
– ZQ Calibration
– ODTS (On-Die Thermal Sensor)
– Write Levelization
Page 31 2013/11/8
ODT (DDR2, DDR3) ODT ?
DRAM controller가 독립적으로 termination 저항을 ON/OFF시킴으로써 Memory Channel의 Signal Integrity를 향상.
종류: Synchronous / Asynchronous Mode
One Rank Vs. Multi Rank Mode
One Rank mode : 자신의 ODT를 이용 data를 받음.
Multi Rank mode : 반대편 Rank의 ODT를 이용해 data를 받음.
ODT Mode Register and ODT Truth Table
ODT pin
0
1
DRAM Termination State
OFF
ON, (MR1 bits A2,A6,A9에 의해 disable 가능)
Mode Register 1 Rtt (ODT value)
A9 A6 A2
0 0 0 ODT Disable
0 0 1 RZQ/4 (eff 60ohm)
0 1 0 RZQ/2 (eff 120ohm)
0 1 1 RZQ/6 (eff 40ohm)
1 0 0 RZQ/12 (eff 20ohm)
1 0 1 RZQ/8 (eff 30ohm)
1 1 0 RFU
1 1 1 RFU
To other
circuitry
like RCV,
…
RTTp
u2
RTTp
u1
RTTp
d2
RTTp
d1
VSSQ
DQ, DQS, /DQS, DM
SW1
SW1
SW2
SW2
VDDQ
Page 32 2013/11/8
ZQ Calibration (DDR3)
Calibration on until comes out to X X Y
RZQ
240Ω
RonDRAM Inside DRAM Outside X
Y
It’s ZQ Calibration for compensating PVT variation
Page 33 2013/11/8
Write Leveling (DDR3)
MODULE
Page 34 2013/11/8
3-2. Package Approach & TSV
• Package Level Approach – MCP (Multi-Chip Package)
– TSV (Through Silicon Via)
MCP (Multi-chip Package) 20단 Nand Flash, Hynix, 2007 소형화, 고용량화, 다기능화에 유리
Page 35 2013/11/8
1. TSV Demands & Environments
Limitation to conventional scaling method
Design
rule
(nm
)
20
30
40
10
50
60
70
80
ArF Dry
ArF Imm.
SPT
EUV
DRAM
NAND
2007 2009 2011 2013
90
100
2015 2005
※ EUV (Extreme Ultra Violet) : Costs more than 100Billion Dollars/equipment
`07 `08 `09 `10 `11 `12 `13 `14 `15 `16
Bandwidth
Server Density
1.8V
1.5
1.35
1.1Gbps
1.3
2.7
1.9
8GB
16
64 GB
Demands for DRAMs
1.2 1.0V
32
0.8
※ Gbps (Giga Bit per Second) : Data Transfer Rate
* Source: Hynix Estimates
2.1
1.6
2.4
3.2Gbps
Operating Voltage
Scaling
Limit ??
Regardless of Scaling Limits, Demands for High Density DRAM and Higher Performance DRAM are growing …
Page 36 2013/11/8
2. TSV Memories
Main Memory
3DS
Mobile
WIO, WIO2, …
Graphics, Network
HBM, HMC
TSV : 200 ~ 400 ea TSV : 1500~2000 ea TSV : 2000 ~ 3000 ea
1. Maintaining Existing Infra 2. Low Cost Target 3. Low Bandwidth/Mid Power
1. Low Power 2. Multi Channel
1. Max Bandwidth 2. Multi Channel 3. P2P(Point-to-Point) 4. 2.5D & interposer
memory
memory
memory
memory
PKG Substrate
Core
Core
Core
Core
Base
Interposer
PKG Substrate
WIO2
WIO2
WIO2
WIO2
Controller
PKG Substrate
Page 37 2013/11/8
2-1. Main Memory 3DS – Main Memory Server
64GB DIMM Solution Required in 2013
2Gb(1Gx2) PKG
4Gb(2Gx2) PKG
8Gb(4Gx2) PKG
16Gb PKG
64GB
32GB
16GB
8GB 2013
2011
2009
2007 0%
20%
40%
60%
80%
100%
1GB 2GB
4GB
8GB
16GB
64GB
32GB
Targeted Range
High Density Module Development Schedule
(Source : MM Marketing)
Page 38 2013/11/8
64GB Server DIMM
8Gb 2H
DDP
4Gb 4Hi
TSV
8Gb DDP or 4Gb 4Hi 3DS ?
1. Cost
2. Power
3. RAS
4. Capacity
5. Latency
6. Bandwidth
Priority for Customers
2-1. Main Memory 3DS – Main Memory Server
Page 39 2013/11/8
2-2. Mobile WIO – Bandwidth Forecast
Wide IO
12.8GB/s
LPDDR3
6.4GB/s
LPDDR4
12.8GB/s
2012 2013 2014 2015 2016
WIO2
25.6GB/s
51.2GB/s
LPDDR3E
7.5GB/s
Ba
nd
wid
th [
GB
/s]
Good power efficiency
Graphics memory
High performance
System memory
※ Bandwidth : based on Mono die
Page 40 2013/11/8
2-2. Mobile WIO – Architecture & Ballout
JEDEC standard constraint (uBump, TSV)
Mobile
WIO, WIO2, …
TSV : 1500 ~ 2000 ea
1. Low Power 2. Multi Channel
WIO2
WIO2
WIO2
WIO2
Controller
PKG Substrate
WIO Bump Pattern
Bottom View WIO2 Quadrant Placement (dimension are micropillar center-to-center)
Page 41 2013/11/8
2-2. Mobile WIO – Mobile WIO Memory Trends
Wide IO Mono Wide IO for L3 Cache
LPDDR2 for System memory
SiP (Controller + Wide IO)
POP (High density LPDDR2 533MHz)
POP Memory (LPDDR2 533MHz)
x512 Wide IO SDR Controller x512 Wide IO SDR Controller
Wide IO TSV Wide IO for System memory
SiP (Controller + 2 or 4-Hi stack Wide IO)
Page 42 2013/11/8
2-3. Graphics & Consumer
Graphics, Network
HBM, HMC
1. Base-die: Re-drive layer, DFT circuits Conventional DRAM Process 2. KGSD Type, 2.5D & interposer 3. SiP(System in Package)
Core
Core
Core
Core
Base
Interposer
PKG Substrate
Core
Core
Core
Core
Base(Logic)
PKG Substrate
1. Base(Logic)-die: SERDES, DFT circuits High Speed Logic Process, Mem
Controller(opt.), High Power 2. Package Type
Page 43 2013/11/8
감사합니다.
DRAM 강국 Korea…
What next?
