Driving the Growth of Advanced Packaging: What Do We Need...

© 2013 TechSearch International, Inc.

Driving the Growth of Advanced Packaging: What Do We

Need to Meet Product Trends?

E. Jan Vardaman President

TechSearch International, Inc.

www.techsearchinc.com


PC and Mobile Product Growth

• Text

Source: TechSearch International, Inc. from various sources, including IDC PC, Media Tablet and Mobile Phone Trackers, March 2012


FCIP and WLP Growth Driven by Mobile Products

• Flip chip and wafer level packages (WLPs)

– Showing strong growth

– Growth in WLP market driven by mobile products (smart phones and tablets)

– Expansion in flip chip market driven by wireless

• CAPEX expansion

– Continued spending in by OSATs and Foundries

– Capacity for 300mm bumping (especially Cu pillar) and wafer level packaging

2012

15%

2017

21%

Total ICs = 190,100 million units

Total ICs = 243,500 million units

Source: IC Insights and TechSearch International, Inc.


Flip Chip Growth Drivers

• Flip chip growth of ~25% from 2012 to 2017 in units

– Microprocessors (all CPUs for PCs)

– ASICs, FPGAs, and DSPs

– Chipsets and Graphics

– Digital TV and other media products

– Many diodes, filters

• Trends toward copper pillar

• Micro bumps for 3D IC w/ TSV

• Future flip chip growth in wireless products

– Driven by form factor and performance

– BB & AP processors moving to flip chip

– Bottom package in PoP (application processor, many with SnAg bump moving to Cu pillar)

Source: TechSearch International,Inc.

Source: ChipWorks


Bumping Trends: Back to the Future

• Early IBM bump was copper ball

• Early were copper post with solder

– Citizen Watch

– Automotive electronics

• Widespread adoption of the high-Pb bump using evaporation process (C4 bump)

– Licensed and put into production by Motorola, AMD

– Cross licensing agreement with Intel, but plating process used in production

• Industry moved to electroplated bumps for flip chip

– Intel

– TI

– IBM, Motorola/Freescale Semiconductor, AMD, TSMC

• Industry moving to copper pillar process just as the it transitioned from evaporation to plating

– Transition started with Intel’s Presler (now all Intel is Cu pillar)

– Cu pillar increasingly used for many PoPs

– By 2013-14 move into high volume for many wireless products

– Many designs moving to Cu pillar at 28nm and beyond

Source: Chipworks.

Source: Amkor


Flip Chip Assembly: The Bump is Not the Hard Part • Conventional reflow process with pick-and-place tool

– Pick, place, reflow, and bond

– Pitch is limited to around 140 µm, some say 130µm pitch is possible but difficult to do in HVM

– Underfill is typically capillary flow

• Copper pillar (or column) with solder cap

– Bump pitch typically ≤140 µm, possible to go to 100 µm and even 40µm staggered bump pitch

– Most applications are ≤100 µm, but some are 110 or 120 µm

– Solder cap is typically SnAg, but other alloys possible

– Some cases capillary flow underfill, but most using non-conductive paste (NCP) and looking at non-conductive film (NCF)

– Requires high accuracy bonder, but trade-off is slower speed

• Some copper pillar applications are switching to thermo-compression (T/C) bond

– Underfill material will be non-conductive paste (NCP) or non-conductive film (NCF)

– Higher precision placement is required, ±2µm accuracy is comfortable for HVM

– T/C bonders >$1 million, throughput is slower

• Molded underfill considered for some T/C bond applications with ≤30µm bump pitch

– Especially when a small keep out zone is required, die size is small

Source: Chipworks


Thin is In!

Source: Adapted from ASE


Package-on-Package (PoP)

• Replaced stacked die with wire bond for

memory and logic

– Memory sourcing

– Test issues

• Individual packages are stacked on top of

each other

– Separate package for logic

– Separate package for memory

– Packages individually tested before

stacking

• Smartphones and tablets use PoP, some

digital cameras

• New developments enabling thinner

packages

– Embedded PoP with die embedded

in the substrate of the bottom

package

– eWLB versions using a fan-out

technology

Source: Amkor

Source: TI


Amkor’s TMV® PoP Roadmap

Source: Amkor


Growth in WLP Shipments

• Major application for WLP driven by mobile product such as smartphones, tablets

• Provides smaller, thinner package (low profile)

• CAGR of ~11% in units (2012 to 2017)

Source: TechSearch International,Inc.


Fan-Out Wafer Level Packages

• Reconstituted wafer and perimeter mold compound allows for redistribution of I/O beyond current chip footprint

• Considered an embedded package by some

• Fan-out WLP from ADL Engineering, Amkor, ASE, Deca Technologies, Freescale Semiconductor, FCI/Fujikura, J-Devices, NANIUM, Nepes, SPIL, STATS ChipPAC, TSMC, and YOUR NAME HERE

• Infineon eWLB (wireless operation acquired by Intel)

– Technology licensed by ASE, STATS ChipPAC, NANIUM

– Companies have installed production lines

Source: Infineon

• Achieved by conventional back-grinding process

• Thinner profile results in more compliant structure

• Better BLR, DT & TCoB performance

• In HVM

Source: STATSChipPAC


FO-WLP: Drivers

• Smaller form factor, lower profile package

– Similar to conventional WLP in profile (can be ≤0.4 mm)

– Thinner than flip chip package (no substrate)

– Excellent electrical and thermal performance

– Excellent high temperature warpage performance

– Fine L/S (10/10µm)

– Can enable a low-profile PoP solution as large as 15 mm x 15 mm

• Increased I/O density

– Originally marketed as an alternative to fine pitch fan-in WLP

• Multiple die in a low-profile package

– Die fabricated from different technology nodes can be assembled in one a single package

• Multi layer RDL with FO-WLP

– Higher routing level with more Iines and traces

– Shield and power dissipation needs

– Enabler of further form factor reduction


Enabling Growth of FO-WLP

• Applications

– Wireless products today

– Potential for memory, PMIC, ASIC, RF, controllers, media chips, medical devices, sensors

– Future possibility in automotive and other applications

• FO-WLP shipments of 616 million units in 2012

– Infineon (now Intel) wireless products

– Spreadtrum announced adoption in Jan. 2013 for China market

– Others

• Plenty of suppliers with lots of capacity for BIG companies

• Reliability

– Some companies have strict reliability JEDEC TCB (-55°C to 125°C) with no dielectric cracking

• Future growth requires cost reduction

– Panel process?

– Lower cost materials?

Source: TPSS

Intel Wireless Division

LTE analog baseband

5.32 x 5.04 x 0.7mm eWLB

127 balls, 0.4mm pitch


Drivers for 3D ICs Remain the Same

• High future cost of lithography

• Severe interconnect delay

– Noted in ITRS roadmap

• Bottleneck for higher bandwidth

• Device latency issues

• Power management, delivery, and distribution needs

• Demand for smaller form factor, low profile packages

Source: Intel

Source: Intel

Source: Renesas


Prototype Memory with TSV as Stacked WLP

• Flash memory R&D at IM Flash, Samsung, Toshiba, etc.

• DRAM prototypes and programs

– Micron/Elpida

– SK Hynix

– Samsung

– Nanya?

• Tezzaron high-speed SRAM memory in production

• IBM and Intel have agreements with Micron for cube

– Engineering samples promised….

Source: Tezzaron

Source: Elpida


Challenges for 3D IC High Volume Manufacturing

• Availability of commercial 3D EDA tools

– Floorplanning

– Routing

– Power/signal integrity

• Micro bumping and assembly for finer pitch

– Higher throughput for fine pitch bonding

• Wafer thinning, specifically the debonding step in the temporary bonding process

– Higher yields required

• Thermal, where logic is part of the stack

– Need cost effective thermal solution

– Thermally aware design tools

• Test methodology and solution

– KGD

– Yield

– Test methods

• Infrastructure related issues

– Logistics

– Supply chain handoff

• Reliability data to meet customer requirements

• Cost reduction compared to alternatives

– Cost/performance trade-off is key


Thermal Considerations

• DRAM expects uniform temperature of device

• Logic chip can generate hot spots caused by non-uniform duty cycle of

modules

Source: Intel


Current State of 3D/2.5D Cost

• Via fabrication and via fill have seen great improvement

• Yield is the biggest cost drive today

• Assembly yield of fine pitch micro bumped components on thin wafers or chips with TSVs is still low

– Any yield loss in this step is a problem because good die and interposers must be scrapped

• TSV process costs (via etch, fill, and reveal) are lower than RDL process costs

• Thin wafer bond/debond throughput is low and yield loss is expensive, although both cost drivers are expected to improve in the future

Source: SavanSys Solutions


Conclusions

• Thin products are driving thin package solutions

– Must meet steep ramp with high volume

• Growth in advanced packaging

– Where the margins are….

• Growth in the use of flip flip packages continues with migration from solder to Cu pillar for many devices

• Trend in WLP for mobile applications

– Conventional WLP

– FO-WLP

• 3D IC with TSV offers thin packaging solutions, but still has barriers

– Alternatives will be used

• Adoption of new technology

– Cost/performance trade-off

– Established infrastructure

• The road ahead requires new developments to lower packaging cost

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