DSP Builder Advanced Blockset Reference Manual · 101 Innovation Drive San Jose, CA 95134 DSP...

101 Innovation DriveSan Jose, CA 95134www.altera.com

DSP Builder Advanced BlocksetReference Manual

Software Version: 9.1 SP1Document Date: January 2010

http://www.altera.com

Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all otherwords and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and othercountries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap-plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use ofany information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version ofdevice specifications before relying on any published information and before placing orders for products or services.

MNL-01031-4.1

© January 2010 Altera Corporation

Contents

Chapter 1. IntroductionDesign Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Chapter 2. Base LibraryChannel Viewer (ChanView) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4Edit Params . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5Run ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8Run Quartus II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

Chapter 3. Filter LibraryFIR and CIC Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1Single Rate FIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4Interpolating FIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7Decimating FIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11Fractional Rate FIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15Interpolating CIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19Decimating CIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22

Chapter 4. FFT LibraryComplex Multiplier (ComplexMult) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2Complex Sample Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3Dual Twiddle Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5Negate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6Negate Parameterizable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6Butterfly I (BFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7Butterfly II (BFII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8Bit Reverse Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10Twiddle Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

Chapter 5. Waveform Synthesis LibraryComplex Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3Real Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5NCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

Chapter 6. ModelBus LibraryBus Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1Bus Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2Bus Stimulus File Reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3Register Bit (RegBit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4Register Field (RegField) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5Register Out (RegOut) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7Shared Memory (SharedMem) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

DSP Builder Advanced Blockset Reference Manual

iv Contents

Chapter 7. ModelPrim LibraryVector and Complex Type Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2Absolute Value (Abs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5Add SLoad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7AND Gate (And) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8Bit Combine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10Bit Extract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11Bit Reverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12Channel In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13Channel Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14Complex Conjugate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16Count Leading Zeros (CLZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17Compare Equality (CmpEQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–18Compare Greater Than (CmpGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–19Compare Less Than (CmpLT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20Compare Not Equal (CmpNE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20Constant (Const) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21Convert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–22CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–24Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–27Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–28Dual Memory (DualMem) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–29General Purpose Input (GPIn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–30General Purpose Output (GPOut) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–32Left Shift (LShift) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–33Look-Up Table (Lut) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–34Maximum Value (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–35Minimum Value (Min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–36Multiply (Mult) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–37Multiplexer (Mux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–38NAND Gate (Nand) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–39NOR Gate (Nor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–40NOT Gate (Not) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–41OR Gate (Or) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–42Sample Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–43Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–44Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–46Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–47Subtract (Sub) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–48Synthesis Information (SynthesisInfo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–49XNOR Gate (Xnor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–51XOR Gate (Xor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–52

Chapter 8. ModelVectorPrim LibrarySum of Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2

Appendix A. Categorized Block List

Alphabetical Index

Additional InformationRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

DSP Builder Advanced Blockset Reference Manual © January 2010 Altera Corporation

Contents v

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

© January 2010 Altera Corporation DSP Builder Advanced Blockset Reference Manual

vi Contents



1. Introduction

You can use the Altera® DSP Builder Advanced Blockset to develop production ready digital signal processing (DSP) solutions for Altera FPGAs using the MathWorks MATLAB and Simulink design tools. Memory-mapped interfaces are automatically built to control datapaths built from the highly efficient intellectual property (IP) blocks and custom logic used in the Simulink models.

You can use the blocksets to build your own ASSP replacement, reducing the cost per channel, and adding custom features to differentiate your product. The blocks can be plugged together to implement multi-channel, multi-rate DSP systems.

The blocks are parameterized using system level parameters, so that the tools have freedom to optimize the implementation based on the desired system throughput. This approach hides much of the hardware complexity allowing you to easily bridge the gap to implementation and focus on your design goals, not the implementation details.

Automated pipelining enables you to meet your desired clock rate, enabling timing closure at high clock rates.

Design FlowThe model based design flow supports in-place configuration of the IP blocks, so that development is accelerated. Bit width changes propagate through your design and re-simulating lets you see the bit and cycle-accurate impact in seconds.

VHDL for your design and testbench, plus scripts are created to let you easily simulate and synthesize your design, or include it as a system component.

A memory-mapped interface, is automatically created for the ModelIP blocks to easily enable interface microprocessors, and enclosing systems.

Design documentation is generated for the ModelIP blocks when you run a Simulink simulation and can be accessed in the MATLAB Help for each block.

LibrariesThe DSP Builder Advanced Blockset comprises six libraries:

■ Base library. This library contains basic blocks that allow you to control your design flow and run external synthesis and simulation tools.

■ FFT library. The fast Fourier transform library contains common blocks that support FFT design. It also includes support for a Radix-22 algorithm.

f For more information about the Radix-22 algorithm, refer to A New Approach to Pipeline FFT Processor – Shousheng He & Mats Torkleson, Department of Applied Electronics, Lund University, Sweden.


1–2 Chapter 1: IntroductionLibraries

■ Filter library. This ModelIP library contains several decimating and interpolating cascaded integrator comb (CIC), and finite impulse response (FIR) filters including single rate multi-rate and fractional rate FIR filters.

Multi-rate filters are essential to the up and down conversion tasks required in modern radio systems. Cost effective solutions to many other DSP applications also use multi-rate filters to reduce the multiplier count.

A memory-mapped interface allows coefficients to be read and written to directly, easing system integration.

■ Waveform Synthesis library. This ModelIP library contains a numerically controlled oscillator (NCO), complex mixer, and real mixer blocks.

Direct digital synthesis of accurate sine and cosine signals using a NCO is an essential part of radio receivers and transmitters converting to and from intermediate frequencies (IF). The NCO block can generate any number of sine and cosine signals at any fraction of the system clock frequency. Memory-mapped phase increments and offsets allow you to use the NCO flexibly in a system configuration. You can parameterize the NCO with arbitrary precision, to give over 150dB spurious-free dynamic range (SFDR) with 26-bit outputs.

The mixer blocks perform multiplications with real and complex inputs.

■ ModelBus library. This library provides memories and registers that you can access in your DSP datapath and via an external interface. You can use these blocks to configure coefficients or run-time parameters and read calculated values.

This library also provides blocks that you can use to simulate the bus interface in the Simulink environment.

■ ModelPrim (primitive) library. This library contains primitive operators such as add, multiply, and delay. It also includes signal type manipulation functions that support building hardware functions using the MathWorks fixed point types. You do not need to understand the details of the underlying FPGA architecture, as the primitive blocks are automatically mapped into efficient FPGA constructs.

You can design and debug your model quickly using zero-latency blocks, without having to track block latencies around your circuit, decreasing design time and reducing bugs.

You can let the synthesis tool pipeline your logic to give you the system clock frequency you need and take care of pipeline balancing. Arithmetic operators, such as adders, are pipelined to increase operating frequency. Register blocks and shared memories permit synthesis of the processor-datapath interface.

Your design remains portable between supported FPGA families, allowing you to future-proof your design investment.

1 Simulink 1-D vector and complex types are supported on some primitives.



2. Base Library

The Base library contains the following blocks:

■ Channel Viewer (ChanView)

■ Control

■ Device

■ Edit Params

■ Run ModelSim

■ Run Quartus II

■ Scale

■ Signals

Channel Viewer (ChanView)The ChanView block deserializes the bus on its inputs to produce a configurable number of output signals that are not time-division multiplexed (TDM).

You can use a ChanView block in a testbench to visualize the contents of the TDM protocol. It produces synthesizable RTL, so you can use it anywhere in your design.

When a single channel is input, the ChanView block strips out all the non-valid samples, thus cleaning up the display in the Simulink scope.

Note that the channel outputs are not aligned. For example, if you have input channels c0 and c1 on a single wire and view both channels, the output is as shown in Figure 2–1.

1 You can add delays after Channel Viewer blocks if you want to realign the channels.

Figure 2–1. Channel Viewer Output for Two Channels on a Single Wire


2–2 Chapter 2: Base LibraryChannel Viewer (ChanView)

ParametersTable 2–1 on page 2–2 shows the parameters for the Channel Viewer block.

Port InterfaceTable 2–2 shows the port interface for the Channel Viewer block.

Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 2–3 shows some typical Help messages issued for the Channel Viewer block.

Design ExampleThe demo_AD9856, demo_ddc, demo_duc, demo_dcic, demo_filters_flow_control, demo_firs, demo_fird, demo_firi, demo_firf, demo_firih, demo_fir_fractional, demo_fir_rrc, demo_icic, demo_iir, demo_nco, demo_mix, demo_complex_mixer, demo_scale, and demo_wimax_duc design examples include an example of the Channel Viewer block.

f For more information about the design examples, refer to the DSP Builder Advanced Blockset User Guide.

Table 2–1. Parameters for the Channel Viewer Block

Parameter Description

Number of input channels Specifies the number of unique channels the block can process. This parameter is not used unless the data bus is a vector or the TDM factor is greater than the number of channels. If the data bus is a vector, this value determines which vector element contains the correct channel.

Output channels A vector which controls the input channels to decode and present as outputs. The number of output ports equals the length of this vector, and each port corresponds to one channel in order.

Table 2–2. Port Interface for the Channel Viewer Block

Signal Direction Description

q Input The data input to the block. This signal may be a vector.

v Input Indicates validity of data input signals. If v is high then the data on the a wire is valid.

c Input Indicates channel of data input signals. If v is high, then c indicates which channel the data corresponds to.

cn Output Each output is a deserialized version of the channel contained in the time division multiplexed bus. The output value is updated on each clock cycle that has valid data when the channel matches the required channel.

Table 2–3. Messages for the Channel Viewer Block

Message Example Description

Written on Tue Feb 19 11:25:27 2008 Date and time when this file was run.

Latency is 2 The latency introduced by this block.

Port interface table Lists the port interfaces to the Channel Viewer block.

Resource utilization table Lists the resource utilization for the Channel Viewer block.


http://www.altera.com/literature/ug/ug_dsp_builder_adv.pdf


Chapter 2: Base Library 2–3Control

ControlThe Control block specifies information about the hardware generation environment, and the top level memory-mapped bus interface widths.

A Control block must be present at the top level of your model.

ParametersTable 2–4 shows the parameters for the Control block.

Table 2–4. Parameters for the Control Block


Generate hardware Turn on to enable output file generation.

Hardware destination directory

Specifies the root directory in which to write the output files. This location can be an absolute path or a relative path (for example, ../rtl). A directory tree is created under this root directory that reflects the names of your model hierarchy.

Create automatic testbenches (Note 1)

If this option is turned on, additional automatic testbench files are generated. These files capture the input and output of each block in a .stm file. A test harness (_atb.vhd) is created that simulates the generated RTL alongside the captured data. A script is generated (<model>_atb.do) that can be used to simulate in ModelSim and ensure bit and cycle accuracy between the Simulink model and the generated RTL.

Signal view depth A wave.do file is generated that you can use to open a Wave window in ModelSim. The wave.do file displays all important signals down to the specified level of hierarchy.

Turn on coverage in testbenches

If automatic testbenches are being created, this option controls whether ModelSim's code coverage tools are enabled (if available).

System address width

Specifies the bit width of the memory-mapped address bus (1–32, default=10).

System data width Specifies the bit width of the memory-mapped data bus (16 or 32, default=16).

System bus is: Specifies whether the memory-mapped address bus is Big Endian, or Little Endian.

CDelay RAM block threshold (Note 2)

Specifies the RAM block threshold in bits. If the number of logic cells required is greater than the specified value, the delay is implemented using RAM blocks. Any value less than 0 means use the default which is 20 bits.

CDualMem Dist RAM threshold (Note 2)

Specifies the Dual Memory RAM threshold in bits. If the number of logic cells required by a Dual Memory block is greater than the specified value, the delay is implemented using RAM blocks. Any value less than 0 means use the default which is 1,280 bits.

M-RAM threshold (Note 2)

Specifies the M-RAM threshold in bits. If the number of bits in memory is greater than the specified value, a M-RAM is used. Any value less than 0 means never use M-RAM or M144K.

Hard multiplier threshold (Note 2)

Specifies the hard multiplier threshold in bits. This is the number of logic elements you are willing to use to save a multiplier. If the specified value would be exceeded, hard multipliers are used. Any value less than 0 means always use hard multipliers.

Note to Table 2–4:

(1) For more information about this parameter, refer to the Comparison with RTL section in the DSP Builder Advanced Blockset User Guide.(2) For more information about these parameters, refer to the Basic Blocks section in the DSP Builder Advanced Blockset User Guide.




2–4 Chapter 2: Base LibraryDevice

Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 2–5 shows some typical Help messages issued for the Control block.

Design ExampleAll the design examples use the Control block.


DeviceThe Device block marks a particular Simulink subsystem as the top level of an FPGA device.

The tool generates project files and scripts that relate to this level of hierarchy. All blocks in subsystems below this level become part of the RTL design. All blocks above this level of hierarchy become part of the testbench.

You can insert multiple Device blocks in non-overlapping subsystems to use multiple FPGAs in the same design. Device families can be mixed freely.

Table 2–6 shows the parameters for the Device block.

Design ExampleAll the design examples use the Device block.


Table 2–5. Messages for the Control Block


Resource utilization table Lists the resource utilization for each subsystem in the current model.

Table 2–6. Parameters for the Device Block


Device family You can select the required target device family (Stratix®, Stratix GX, Stratix II, Stratix II GX, Stratix III, Stratix IV, Cyclone® II, Cyclone III, or Arria® II GX).

Family member Specifies the device member as free-form text or enter AUTO to allow automatic selection. If you enter free-form text, the name must start with EPxxx. For example: EP2C35F484C6.

Speed grade You can select the speed grade for the FPGA target. This selection helps the tool to balance the hardware size against the resources required to meet the clock frequency set in the Signals block.






Chapter 2: Base Library 2–5Edit Params

Edit ParamsThe Edit Params block is not available as a functional block in the Simulink library browser. However, you can create your own Edit Params block as a graphical shortcut to a MATLAB m-script that sets up and initializes your design.

Examples of Edit Params blocks are used in many of the design examples.

You can create an Edit Params block if you have created a MATLAB script defining workspace variables that you want to call when your model is loaded and/or initialized. This script should be specified in the PreLoadFcn and/or InitFcn callbacks that you can access by clicking Model Properties on the File menu:

■ To call your script automatically when your model is opened, add a PreloadFcn reference to your script in the Callbacks tab of your Model Properties in Simulink.

■ To call your script automatically at the start of a simulation run, add a InitFcn reference to your script in the Callbacks tab of your Model Properties in Simulink.

In the design examples, the names of the initialization scripts are derived from your model name: setup_<model name>.m. For example, setup_demo_firs.m as shown in Figure 2–2.

To create an Edit Params block that references this script, perform the following steps:

1. Drag a Subsystem block from the Simulink Commonly Used Blocks library.

2. Double-click on the Subsystem block to open it and delete the default In1 and Out1 ports. Close the Subsystem block.

3. Right-click on the Subsystem block, choose Block Properties and click the Callbacks tab.

Figure 2–2. Callbacks Tab in the Simulink Model Properties Dialog Box


2–6 Chapter 2: Base LibraryEdit Params

4. Choose OpenFcn in the Callback functions list (Figure 2–3).

5. If you have named your script using the format setup_<model name>.m, enter the following functions:

s = sprintf('edit setup_%s', eval('gcs'));

eval(s);

Alternatively, you can explicitly reference a script such as my_script.m by entering a function of the form:

eval(‘edit my_script.m’);

6. Click OK to close the Block Properties dialog box.

7. Rename the Subsystem block EditParams (or any name of your choice).

1 You can optionally hide the block name by right-clicking and clicking Hide Name on the popup menu.

Figure 2–3. Callbacks in the Subsystem Block Properties Dialog Box


Chapter 2: Base Library 2–7Edit Params

8. If you want to apply a graphic icon to your block, right-click and choose Mask Subsystem to display the Mask Editor dialog box (Figure 2–4).

9. Click the Icon tab and enter drawing commands using the following format:

image(imread('edit_params.png'));

color('w');

fprintf('Edit\nParams');

These commands reference the default icon for an Edit Params block, set the text color to white and specify the text overlay on the block. You can optionally specify your own custom graphic file, color, and text.

f For more information about drawing commands in the mask editor, refer to the Simulink Help.

10. Select Invisible from the Frame icon options.

11. Click on the Documentation tab and enter the Mask type: DSP Builder Advanced Blockset Ignored Block.

12. Click OK to close the Mask Editor.

1 You can also create an Edit Params block by copying an existing block from one of the design examples, and editing the block and mask properties to customize it for your model.

Figure 2–4. Mask Editor Dialog Box


2–8 Chapter 2: Base LibraryRun ModelSim

UsageDouble-click on the Edit Params block to open the script in the MATLAB text editor.

Design ExampleThe demo_AD9856, demo_complex_mixer, demo_ddc, demo_duc, demo_dcic, demo_filters_flow_control, demo_fird, demo_firf, demo_firi, demo_firih, demo_fir_fractional, demo_fir_rrc, demo_firs, demo_icic, demo_nco, demo_mix, demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_ifft_4096_natural, and demo_ifft_8192_natural design examples include an example of the Edit Params block.


Run ModelSimThe Run ModelSim block no works by stimulus capture, in the same way as the automatic testbenches (ATBs), and compares the Simulink simulation result to the ModelSim simulation.

UsageDrop the Run ModelSim block into the top-level of any design. Double-click the Run ModelSim block to launch the ModelSim tool with the user system as the top-level entity. ModelSim automatically starts compiling your design and runs a simulation for the same number of clock cycles as the Simulink simulation.

The simulation is compiled and loaded using the .do scripts that are generated when you run a Simulink simulation. The .do scripts are created in the hardware destination directory specified in the Control block. The generated files and scripts are created in a hierarchy of directories that match the hierarchy of your design and lower level scripts are called from the scripts in the top level directory.

Design ExampleAll the design examples use the Run ModelSim block.







Chapter 2: Base Library 2–9Run Quartus II

Run Quartus IIThe Run Quartus II block allows the automatic launching of the user system in the Quartus II software, where your design can be verified for performance and logic utilization.

UsageDrop the Run Quartus II block into the top-level of any design containing an Altera Device block. Double-click the Run Quartus II block to launch the Quartus II software with the user system as the top-level entity.

The Quartus II project file (.qpf), Quartus II settings file (.qsf), and Quartus II IP file (.qip) for the Quartus II project are created in your design directory that contains the .mdl file. These files contain all required references to the files in the hardware destination directory specified by the Control block that are generated when you run a Simulink simulation. After loading the project in the Quartus II software, you should check that the required device settings are selected. You can then compile your design by clicking Start Compilation on the Processing menu.

The project is compiled using the .tcl scripts in the hardware destination directory. The generated files and scripts are created in a hierarchy of directories that match the hierarchy of your design and lower level scripts are called from the scripts in the top level directory.

Design ExampleAll the design examples use the Run Quartus II block.


ScaleYou can use the Scale block to select part of a wide input word, performing various types of rounding, saturation and fixed point scaling, to produce an output of specified precision.

By default, the binary point is preserved so that the fixed point interpretation of the result has the same value, subject to rounding, as the fixed point interpretation of the input.

You can dynamically perform additional scaling, by specifying a variable number of bits to shift, allowing any power of two gain to be introduced.

1 Always use Scale blocks to change data types in preference to Convert blocks, because they vectorize, and automatically balance the delays with the corresponding valid and channel signals.




2–10 Chapter 2: Base LibraryScale

ParametersTable 2–7 shows the parameters for the Scale block.

Port InterfaceTable 2–8 shows the port interface for the Scale block.

Table 2–7. Parameters for the Scale Block


Output data type The type of the result. For example: sfix(16), uint(8).

Output scaling value The scaling of the result if the result type is fixed point. For example: 2^-15.

Rounding method There are three ways to perform rounding in cases where least significant bits are to be discarded:

■ Truncate: truncates the least significant bits. This has the lowest hardware usage, but introduces the worst bias.

■ Biased: rounds up if the discarded bits are 0.5 or above.

■ Unbiased: rounds up if the discarded bits are greater than 0.5, and rounds to even if the discarded bits equal 0.5.

Multiplication factor Modify the interpreted value by scaling it by this factor. This factor does not affect the hardware generated for the Scale block, but merely affects the interpretation of the result. For example: 1, 2, 3, 4, 8, 0.5.

Saturation method There are three ways to perform saturation in the cases where most significant bits are to be discarded:

■ None: No saturation is performed.

■ Asymmetric: The range of the number produced occupies the whole of the two's complement range (for example –1.0 to 0.999). There is one more negative number available, so this will introduce a slight bias.

■ Symmetric: The range of the result is clipped to between symmetrical boundaries (for example -0.999 and 0.999). This ensures no bias enters the dataflow.

Number of bits to shift left

A scalar or a vector that determines the gain of the result. A positive number indicates that the scale block introduces a gain to the input. A negative number means that the output signal is attenuated. A vector of gains allows the shift input signal to select which gain to use on a cycle per cycle basis. The value of the shift integer performs zero-based indexing of the vector. For example: 2, -4, [0 1 2 3]

Table 2–8. Port Interface for the Scale Block


a Input The data input to the block. If more channels are requested than can fit onto a single bus, then this signal is a vector. The bit width is inherited from the input wire.

a_v Input Indicates validity of data input signals. If a_v is high then the data on the a wire is valid.

a_chan Input Indicates channel of data input signals. If a_v is high, then a_chan indicates which channel the data corresponds to.

shift Input Indicates which element of the zero-based shift vector to use.

q Output The data output from the block. If more channels are requested than can fit onto a single bus, then this signal is a vector. The bit width is calculated as a function of the input bit width and the parameterization.

q_v Output Indicates validity of data output signals.


Chapter 2: Base Library 2–11Signals

Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 2–9 shows some typical Help messages issued for the Scale block.

Design ExampleThe demo_scale, demo_ddc, demo_duc, demo_AD9856, demo_filters_flow_control, demo_wimax_duc, and demo_fir_fractional design examples include an example of the Scale block.


SignalsThe Signals block specifies information about the system clock, reset, and memory bus signals used by the simulation model and the hardware generation. The names of the signals are used to generate the RTL.

You must include a Signals block at the top level of your model.

ParametersTable 2–10 shows the parameters for the Signals block.

q_chan Output Indicates channel of data output signals.

q_exp Output Indicates whether the output sample has saturated or overflowed.

Table 2–8. Port Interface for the Scale Block


Table 2–9. Messages for the Scale Block



Number of physical buses: 4 Depending on the input data rate, the number of data wires needed to carry the input data may be more than 1.

Calculated bit width of output stage: 16 The bit width of the (vectorized) data output.


Parameters table Lists the current rounding and saturation modes.

Port interface table Lists the port interfaces to the Scale block.

Resource utilization table Lists the resource utilization for the Scale block.




2–12 Chapter 2: Base LibrarySignals

Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 2–11 shows some typical Help messages issued for the Signals block.

Design ExampleAll the design examples use the Signals block.


Table 2–10. Parameters for the Signals Block


Clock Specifies the name of the system clock signal used in the RTL generation.

Clock frequency (MHz) Specifies the system clock rate for the system.

Clock margin (MHz) Specifies the margin requested to achieve a high system frequency in the fitter. The specified margin does not affect the folding options because the system runs at the rate specified by the Clock frequency parameter setting. Specify a positive clock margin if your design needs to be pipelined more aggressively (or specify a negative clock margin to save resources) when you do not want to change the ratio between the clock speed and the bus speed.

Reset Specifies the name of the reset signal used in the RTL generation.

Reset active Specifies whether the logic generated is reset with an active High or active Low reset signal.

Bus name Specifies the prefix used for the address, data and control signals in the generated control bus.

Separate bus clock (Note 1)

When this option is turned on, any processor-visible control registers are clocked by a separate control bus clock to facilitate timing closure.

Bus clock frequency (MHz)

Specifies the frequency of the separate processor interface bus clock (when enabled). This value is usually expressed as a fraction of the clock frequency and determines the amount of folding (time division multiplexing) that is performed to achieve optimum logic utilization.

Bus clock synchronous with system clock

When this option is on, the bus clock is synchronous with the system clock.


(1) This option should be off when using Cyclone families because these devices have limited multiple clock support in block RAMs and do not support a separate bus clock.

Table 2–11. Messages for the Signals Block


Parameters table Lists the system clock name, system clock rate, fitter target frequency, reset name and reset active parameters for the current model.




Chapter 2: Base Library 2–13Signals


2–14 Chapter 2: Base LibrarySignals



3. Filter Library

The Filter library contains the following blocks:

■ Single Rate FIR

■ Interpolating FIR

■ Decimating FIR

■ Fractional Rate FIR

■ Interpolating CIC

■ Decimating CIC

FIR and CIC FiltersThis chapter describes blocks that implement several finite impulse response (FIR) and cascaded integrator comb (CIC) filters. The filters share many common features and use advanced high-level synthesis techniques to generate filters with higher clock speeds, lower logic, multiplier, and memory counts. Using these high clock rates allows you to reduce your costs by choosing smaller FPGAs.

Common Features■ Filter length from 1 to 256 taps

■ Data input bit width from 2 to 32 bits

■ Data output bit width from 4 to 64 bits

■ Multi-channel (up to 1024 channels)

■ Powerful MATLAB integration

■ Simulink fixed point integration

■ Automatic pipelining

■ Plug and play connectivity

■ Simplified timing closure

1 Each channel is an independent data source. In an IF Modem design, two channels are required for the complex pair from each antenna.

Basic FIR Filter OperationEquation 3–1 shows the basic convolution operation performed by a single rate filter.

Equation 3–1.

where k = 0, 1,2, ..., n-1


3–2 Chapter 3: Filter LibraryFIR and CIC Filters

At each sample time k, the new output y, is calculated by multiplying coefficients a, by the recent past values of the input x.

Half-Band and L-Band Nyquist FIR FiltersSome filtering functions can use a half-band filter where nearly half of the coefficients are zero. The half-band support uses these extra zeros to further reduce the number of multipliers, and reduce the filter cost.

The generalized form of these filters are L-band Nyquist filters, where every Lth coefficient is zero counting out from the center tap. These structures are also supported and can often reduce the number of multipliers required in a filter.

Automatic PipeliningThe required system clock frequency, and the device family and speed grade are used to determine the maximum logic depth permitted in the output RTL. Functions such as adders are pipelined by splitting them into multiple sections with a registered carry between them. This pipelining decreases the logic depth allowing higher frequency operation.

Resource UtilizationThe FPGA resource utilization for a Single Rate FIR filter are shown in Figure 3–2.

The multiplier counts fall dramatically as the clock frequency increases, because each multiplier is able to perform more taps.

Figure 3–2. Typical FIR Filter Resource Usage


Chapter 3: Filter Library 3–3FIR and CIC Filters

Notice also that the number of logic resources has a bowl-shaped curve. This curve reflects the fact that at low frequencies there are more adders to cope with the extra multipliers used, while at high frequencies long adders have been pipelined into shorter sections, to meet the system clock frequency requirement. Some typical results are shown in the block descriptions for each type of filter.

High Speed OperationBecause the filter generator is responsive to the system clock frequency, timing closure is much easier to achieve. The generator uses heuristics that ensure the logic is capable of running at the desired system clock frequency on the FPGA. You can help timing closure by adding more clock margin, resulting in additional pipelining that shortens the critical paths.

The FPGA structures such as internal multiplier and memory delays determine the maximum clock frequencies.

ScalabilityIn some cases, the aggregate sample rate for all channels may be higher than the system clock rate. In these cases, the filter has multiple input and/or output buses to carry the additional data. This requirement is implemented in the Simulink block by increasing the vector width of the data signals.

ParameterizationThe system specification, including such factors as the channel count and sample rates, determines the main parameters for a filter. The remaining parameters such as data widths and system clock rates are inferred from the enclosing Simulink model. Any changes to these parameters ripple through your design, changing the system performance without you having to update all the components. You can express any of the parameters as MATLAB expressions, to rapidly parameterize a whole system.

The hardware generation techniques create efficient filters with combinations of parameters, such as a symmetric 3-band FIR filter with 7 channels and 100 cycles to execute a sample from each channel. Hardware generation is fast and can be run on-the-fly with every Simulink simulation, so that the edit simulation loop time is much reduced, improving productivity.

Coefficient GenerationYou can generate filter coefficients using a MATLAB function that is reloaded at run time using the memory-mapped interface registers. For example, the Simulink fixed-point object fi(fir1(49, 0.3),1,18,19).

ChannelizationThe input channel data format and output data channel format used by a FIR or CIC filter are shown in the generated help page for the block after you have run a Simulink simulation.


3–4 Chapter 3: Filter LibrarySingle Rate FIR

Single Rate FIRThe Single Rate FIR block implements a highly efficient multi-channel finite impulse response filter across a broad range of parameters directly from a Simulink model. A memory-mapped interface allows coefficients to be read and written to directly, easing system integration.

The Single Rate FIR block performs filtering on a stream of multi-channel input data and produces a stream of output data with increased sampling frequency.

You can use the Single Rate FIR block in a digital up converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed point types, and the output is the implied full precision fixed point type. You can reduce the precision by using a separate Scale block, which can perform rounding and saturation to provide the required output precision.

FeaturesThe Single Rate FIR block supports sample rates from 1 to 500, coefficient bit widths from 2 to 32 bits, half-band and L-band Nyquist filters, real and complex filters, and symmetry and anti(negative)-symmetry.

OperationEquation 3–1 on page 3–1 shows the basic convolution operation performed by a single rate filter.

ParametersTable 3–1 shows the parameters for the Single Rate FIR block.

Table 3–1. Parameters for the Single Rate FIR Block


Input rate per channel Specifies the sampling frequency of the input data per channel measured in millions of samples per second (MSPS).

Number of channels Specifies the number of unique channels to process.

Symmetry You can select Symmetrical or Anti-Symmetrical coefficients. Symmetrical coefficients can result in hardware resource savings over the unsymmetrical version.

Coefficients You can specify the filter coefficients using a Simulink fixed point object fi(0). The data type of the fixed point object determines the width and format of the coefficients. The length of the array determines the length of the filter. For example, fi(fir1(49, 0.3),1,18,19)

Base address The filter's coefficients can be memory-mapped into the address space of the system. This field determines the starting address for the coefficients. It is specified as a MATLAB double type (decimal integer) but you can use a MATLAB expression to specify a hexadecimal or octal type if required.

Read/Write mode The coefficients can be mapped as Read, Write, Read/Write, or Constant. This field determines the type of address decode to build.


Chapter 3: Filter Library 3–5Single Rate FIR

Filter CoefficientsYou can change filter coefficients at run time by writing to the memory-mapped interface. You do not need to create custom logic to deal with awkward update schemes.

You can set the base address of the memory-mapped coefficients using the Base address parameter and the filter coefficients set by entering a Simulink fixed point array into the Coefficients parameter. You can generate a vector of coefficients either by entering an array of numbers, or by using one of the many MATLAB functions to build the required coefficients.

f For more information about Simulink fixed point objects and MATLAB functions, refer to the MATLAB Help.

Port InterfaceTable 3–2 shows the port interface for the Single Rate FIR block.

Typical Resource UtilizationTable 3–3 shows some typical FPGA resource utilizations for a Single Rate FIR using Stratix III devices.

Table 3–2. Port Interface for the Single Rate FIR Block


a Input The data input to the block. If more channels are requested than can fit on a single bus, this signal is a vector. The bit width is inherited from the input wire.

v Input Indicates validity of the data input signals. If v is high, the data on the a wire is valid.


q Output The data output from the block. If more channels are requested than can fit on a single bus, this signal is a vector. The bit width is a function of the input bit width and the parameterization.

v Output Indicates validity of data output signals. (Note 1)

c Output Indicates channel of data output signals. (Note 1)

Notes to Table 3–2:

(1) The output data can be non-zero when v is low.

Table 3–3. Stratix III Fitter Results for a Single Rate FIR

Number of

Channels

Input Rate

(MSPS)

Number of

Coefficients

Comb ALUTs (Note 1)

Logic Registers

18×18 Multipliers

Block Memory

BitsMemory ALUTs

System Frequency

(MHz)

Frequency Achieved

(MHz)

1 5 40 247 425 2 4,200 121 200 281

1 5 40 257 600 2 4,200 133 400 467

1 5 47 263 435 2 5,880 121 200 263

1 5 47 273 611 2 5,880 133 400 433

16 5 40 879 2,961 10 0 1,563 200 249

16 5 40 492 952 4 13,056 141 400 442

16 5 47 1,050 3,523 12 0 1,837 200 248


3–6 Chapter 3: Filter LibrarySingle Rate FIR

Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 3–4 shows some typical Help messages issued for the Single Rate FIR block.

16 5 47 569 1,280 6 15,776 171 400 442

32 5 40 1,505 3,787 20 0 1,377 200 235

32 5 40 713 2,202 10 41,038 472 400 409

32 5 47 1,784 4,351 24 0 1,615 200 239

32 5 47 823 2,554 12 48,603 576 400 413


(1) Combinational adaptive look-up tables (ALUTs)

Table 3–3. Stratix III Fitter Results for a Single Rate FIR

Number of

Channels

Input Rate

(MSPS)

Number of

Coefficients

Comb ALUTs (Note 1)

Logic Registers

18×18 Multipliers

Block Memory

BitsMemory ALUTs

System Frequency

(MHz)

Frequency Achieved

(MHz)

Table 3–4. Messages for the Single Rate FIR Block



Single Rate Filter Version: $Revision: 1.111 $

The version number and revision for the Single Rate FIR Filter (Version 1, revision 111 in this example).

Number of physical input buses: 1 Depending on the input data rate, the number of wires needed to carry the input data may be more than 1. If so, the comb sections of the filter are duplicated (vectorized) to satisfy the data rate requirement.

Number of physical output buses: 2 Depending on the output data rate, the number of wires needed to carry the output data may be more than 1. If so, the output wires are duplicated (vectorized) to satisfy the data rate requirement. The output data rate is the product of the input rate and the interpolation rate.

Calculated bit width of output stage: 26 This is the bit width of the (vectorized) data output from the filter.

Number of different phases: 1 The number of different phases.

Implementation Folding: 3 The number of times that each multiplier is used per sample to reduce the implementation size.

Filter Utilization: 48/50 (96.00%) For some sample rates, the filter must be stalled internally for several cycles. The number of cycles used for active calculation is shown with the number of cycles determined by the sample rate relative to the system clock frequency.

Tap Utilization: 25/27 (92.59%) When some filters are folded, there may be extra unused taps. The extra taps increase the filter length with no hardware resource increase.


Parameters table Lists the system clock, clock margin, input sample rate, number of coefficients, number of channels, and type of symmetry parameters for the Single Rate FIR block.

Port interface table Lists the port interfaces to the Single Rate FIR block.

Input Data Format Displays the input channel data format.

Output Data Format Displays the output channel data format.


Chapter 3: Filter Library 3–7Interpolating FIR

Design ExampleThe demo_firs, demo_AD9856, and demo_wimax_duc design examples include an example of using the Single Rate FIR block.


Interpolating FIRThe Interpolating FIR block implements a highly efficient multi-channel finite impulse response filter across a broad range of parameters directly from a Simulink model. A memory-mapped interface allows coefficients to be read and written to directly, easing system integration.

The Interpolating FIR block performs filtering on a stream of multi-channel input data and produces a stream of output data with increased sampling frequency.

You can use the Interpolating FIR block in a digital up converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed point types, and the output is the implied full precision fixed point type. You can reduce the precision by using a separate Scale block, which can perform rounding and saturation to provide the required output precision.

FeaturesThe Interpolating FIR block supports rate changes from 2 to 64, coefficient bit widths from 2 to 32 bits, data output bit widths from 4 to 64 bits, half-band and L-band Nyquist filters, and symmetry and anti(negative)-symmetry, and real and complex filters.



The Interpolating FIR has a higher output sample rate than the input sample rate by a factor, I, the interpolation factor. Notionally, the interpolating FIR inserts I–1 zeroes for every input sample, thus raising the sample rate by a factor I.

Memory interface Lists the memory addresses for the FIR coefficient registers.

Resource utilization table Lists the resource utilization for the Single Rate FIR block.

Table 3–4. Messages for the Single Rate FIR Block





3–8 Chapter 3: Filter LibraryInterpolating FIR

The filtering is performed as in Equation 3–1. The physical implementation avoids performing multiplications with these zero samples reducing the filter cost.

Figure 3–3 shows how interpolating by 2 increases the sample rate of a sine wave input.

ParametersTable 3–5 shows the parameters for the Interpolating FIR block.

Figure 3–3. Interpolate by 2 Filter Increasing Sample Rate of a Sine Wave Input

Table 3–5. Parameters for the Interpolating FIR Block



Interpolation Specifies the interpolation rate. Must be an integer.


Symmetry You can select Symmetrical or Anti-Symmetrical coefficients. Symmetrical coefficients can result in hardware resource savings over the unsymmetrical version.

Coefficients You can specify the filter coefficients using a Simulink fixed point object fi(0). The data type of the fixed point object determines the width and format of the coefficients. The length of the array determines the length of the filter.

For example, fi(fir1(49, 0.3),1,18,19)


Read/Write mode You can map the coefficients as Read, Write, Read/Write, or Constant. This field determines the type of address decode to build.

Filter structure You can select Use All Taps, Half Band, or other specified band (from 3rd Band to 46th Band).


Chapter 3: Filter Library 3–9Interpolating FIR


You can set the base address of the memory-mapped coefficients using the Base address parameter and the filter coefficients set by entering a Simulink fixed point array into the Coefficients parameter. You can generate a vector of coefficients either by entering an array of numbers, or using one of the many MATLAB functions to build the required coefficients.


Port InterfaceTable 3–6 shows the port interface for the Interpolating FIR block.

Typical Resource UtilizationTable 3–7 shows some typical FPGA resource utilizations for an Interpolating FIR using Stratix III devices.

Table 3–6. Port Interface for the Interpolating FIR Block










Table 3–7. Stratix III Fitter Results for an Interpolating FIR

Number of

Channels

Input Rate

(MSPS)Interpolation

Rate

Comb ALUTs (Note 1)

Logic Registers

18×18 Multipliers

Block Memory

BitsMemory ALUTs

System Frequency

(MHz)

Frequency Achieved

(MHz)

1 5 2 207 395 2 2,496 87 200 283

1 5 2 226 573 2 2,496 99 400 483

1 5 5 229 446 2 0 183 200 260

1 5 5 142 397 2 3,100 46 400 506

16 5 2 967 2,586 12 0 1,049 200 248

16 5 5 722 1,950 6 8,636 596 400 407

16 5 5 801 2,887 20 0 1,278 200 233


3–10 Chapter 3: Filter LibraryInterpolating FIR

Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 3–8 shows some typical Help messages issued for the Interpolating FIR block.

16 5 5 367 1,407 10 10,074 334 400 429

32 5 2 1,899 5,094 24 0 2,098 200 235

32 5 2 1,050 4,337 12 0 2,048 400 402

32 5 5 1,604 5,668 40 0 2,575 200 215

32 5 5 683 2,680 20 21,488 645 400 421



Table 3–7. Stratix III Fitter Results for an Interpolating FIR

Number of

Channels

Input Rate

(MSPS)Interpolation

Rate

Comb ALUTs (Note 1)

Logic Registers

18×18 Multipliers

Block Memory

BitsMemory ALUTs

System Frequency

(MHz)

Frequency Achieved

(MHz)

Table 3–8. Messages for the Interpolating FIR Block



Interpolating Filter Version: $Revision: 1.111 $

The version number and revision for the Interpolating FIR Filter (Version 1, revision 111 in this example).



Calculated bit width of output stages: 26 This is the bit width of the (vectorized) data output from the filter.






Parameters table Lists the system clock, clock margin, input sample rate, number of coefficients, interpolation rate, number of channels, and type of symmetry parameters for the Interpolating FIR block.

Port interface table Lists the port interfaces to the Interpolating FIR block.




Chapter 3: Filter Library 3–11Decimating FIR

Design ExampleThe demo_firi, demo_firih, demo_fir_fractional, demo_filters_flow_control, demo_duc, demo_AD9856, and demo_wimax_duc design examples include an example of using the Interpolating FIR block.


Decimating FIRThe Decimating FIR block implements a highly efficient multi-channel finite impulse response filter across a broad range of parameters directly from a Simulink model. A memory-mapped interface is allows coefficients to be read and written to directly, easing system integration.

The Decimating FIR block performs filtering on a stream of multi-channel input data and produces a stream of output data with increased sampling frequency.

You can use the Decimating FIR block in a digital down converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed point types, and the output is the implied full precision fixed point type. You can reduce the precision by using a separate Scale block, which can perform rounding and saturation to provide the required output precision.

FeaturesThe Decimating FIR block supports rate changes from 2 to 64, coefficient bit widths from 2 to 32 bits, half-band and L-band Nyquist filters, real and complex filters, symmetry and anti(negative)-symmetry.



The Decimating FIR has a lower output sample rate than the input sample rate by a factor, D, the decimation factor. The decimating FIR discards D–1 out of D output samples, thus lowering the sample rate by a factor D.


Resource utilization table Lists the resource utilization for the Interpolating FIR block.

Table 3–8. Messages for the Interpolating FIR Block





3–12 Chapter 3: Filter LibraryDecimating FIR


Figure 3–4 on page 3–12 shows how decimating by 5 decreases the sample rate of a sine wave input.

ParametersTable 3–9 shows the parameters for the Decimating FIR block.

Figure 3–4. Decimating by 5 Filter Decreasing Sample Rate of a Sine Wave Input

Table 3–9. Parameters for the Decimating FIR Block



Decimation Specifies the decimation rate. Must be an integer.


Symmetry You can choose Symmetrical or Anti-Symmetrical coefficients. Symmetrical coefficients can result in hardware resource savings over the unsymmetrical version.







Chapter 3: Filter Library 3–13Decimating FIR



f For more information about Simulink fixed-point objects and MATLAB functions, refer to the MATLAB Help.

Port InterfaceTable 3–10 shows the port interface for the Decimating FIR block.

Typical Resource UtilizationTable 3–11 shows some typical FPGA resource utilizations for a Decimating FIR using Stratix III devices.

Table 3–10. Port Interface for the Decimating FIR Block










Table 3–11. Stratix III Fitter Results for an Decimating FIR

Number of

Channels

Input Rate

(MSPS)Decimation

Rate

Comb ALUTs (Note 1)

Logic Registers

18×18 Multipliers

Block Memory

BitsMemory ALUTs

System Frequency

(MHz)

Frequency Achieved

(MHz)

1 5 2 272 441 2 3,120 121 200 249

1 5 2 282 617 2 3,120 133 400 457

1 5 5 287 467 2 1,152 138 200 263

1 5 5 297 643 2 1,152 150 400 459

16 5 2 522 776 6 23,392 147 200 279

16 5 5 566 1,116 4 16,320 135 400 434

16 5 5 449 561 2 23,120 93 200 244


3–14 Chapter 3: Filter LibraryDecimating FIR

Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 3–12 shows some typical Help messages issued for the Decimating FIR block.

16 5 5 425 719 2 17,328 105 400 433

32 5 2 1,120 3,551 12 3,264 1,877 200 228

32 5 2 685 1,360 6 46,784 211 400 412

32 5 5 516 719 4 70.720 169 200 258

32 5 5 604 886 2 46,240 145 400 463



Table 3–11. Stratix III Fitter Results for an Decimating FIR

Number of

Channels

Input Rate

(MSPS)Decimation

Rate

Comb ALUTs (Note 1)

Logic Registers

18×18 Multipliers

Block Memory

BitsMemory ALUTs

System Frequency

(MHz)

Frequency Achieved

(MHz)

Table 3–12. Messages for the Decimating FIR Block



Decimating Filter Version: $Revision: 1.111 $

The version number and revision for the Decimating FIR Filter (Version 1, revision 111 in this example).


Number of physical output buses: 2 Depending on the output data rate, the number of data wires needed to carry the output data may be more than 1. If so, the output wires are duplicated (vectorized) to satisfy the data rate requirement. The output data rate is the product of the input rate and the interpolation rate.







Parameters table Lists the system clock, clock margin, input sample rate, number of coefficients, decimation rate, number of channels, and type of symmetry parameters.

Port interface table Lists the port interfaces to the Decimating FIR block.




Chapter 3: Filter Library 3–15Fractional Rate FIR

Design ExampleThe demo_fird, demo_fir_rrc, demo_fir_fractional, and demo_ddc design examples include an example of using the Decimating FIR block.


Fractional Rate FIRThe Fractional Rate FIR block implements a highly efficient multi-channel finite impulse response filter across a broad range of parameters directly from a Simulink model. A memory-mapped interface allows coefficients to be read and written to directly, easing system integration.

The Fractional Rate FIR block performs filtering on a stream of multi-channel input data and produces a stream of output data with increased sampling frequency.

You can use the Fractional Rate FIR in a digital down converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed point types, and the output is the implied full precision fixed point type. You can reduce the precision by using a separate Scale block, which can perform rounding and saturation to provide the required output precision.

FeaturesThe Fractional Rate FIR block supports interpolation rate changes from 2 to 64, decimation rate changes from 2 to 64, rational fractional rate changes, coefficient bit widths from 2 to 32 bits, half-band and L-band Nyquist filters, real and complex filters, and symmetry and anti(negative)-symmetry.


At each sample time, k, the new output y, is calculated by multiplying coefficients a, by the recent past values of the input x.

The Fractional Rate FIR has a modified output sample rate that differs from the input sample rate by a factor, I /D, where I is the interpolation rate and D is the decimation factor. Notionally, the fractional rate interpolates by a factor I by inserting (I–1) zeros before performing the filter operation. Then the FIR discards D–1 out of D output samples, thus lowering the sample rate by a factor D.


Resource utilization table Lists the resource utilization for the Decimating FIR block.

Table 3–12. Messages for the Decimating FIR Block





3–16 Chapter 3: Filter LibraryFractional Rate FIR


Figure 3–5 on page 3–16 shows how interpolating by 3 and decimating by 2 changes the sample rate of a sine wave input.

ParametersTable 3–13 shows the parameters for the Fractional Rate FIR block.

Figure 3–5. Sample Rate of a Sine Wave Input Interpolated by 3 and Decimated by 2

Table 3–13. Parameters for the Fractional Rate FIR Block



Interpolation Specifies the interpolation rate. Must be an integer.

Decimation Specifies the decimation rate. Must be an integer.


Symmetry You can choose Symmetrical or Anti-Symmetrical coefficients. Symmetrical coefficients can result in hardware resource savings over the unsymmetrical version.







Chapter 3: Filter Library 3–17Fractional Rate FIR

Filter CoefficientsYou can change filter coefficients by writing to the memory-mapped coefficients. You do not need to create custom logic to deal with awkward update schemes.



Port InterfaceTable 3–14 shows the port interface for the Fractional Rate FIR block.

Typical Resource UtilizationTable 3–15 shows some typical FPGA resource utilizations for a Fractional Rate FIR using Stratix III devices.

Table 3–14. Port Interface for the Fractional Rate FIR Block










Table 3–15. Stratix III Fitter Results for a Fractional Rate FIR

Number of

Channels

Input Rate

(MSPS)

Decimation / interpolation

rate

Comb ALUTs (Note 1)

Logic Registers

18×18 Multipliers

Block Memory

BitsMemory ALUTs

System Frequency

(MHz)

Frequency Achieved

(MHz)

1 5 2 / 5 138 248 2 2,100 34 200 2645

1 5 2 / 5 149 397 2 2,100 46 400 473

1 5 5 / 2 263 431 2 0 104 200 265

1 5 5 / 2 278 613 2 0 116 400 446

16 5 2 / 5 653 1,604 12 8,058 464 200 246

16 5 2 / 5 469 1,476 6 0 509 400 407

16 5 5 / 2 381 528 2 14,960 92 200 301

16 5 5 / 2 432 708 2 9,520 104 400 453


3–18 Chapter 3: Filter LibraryFractional Rate FIR

Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 3–16 shows some typical Help messages issued for the Fractional Rate FIR block.

32 5 2 / 5 1,319 3,180 24 16,116 947 200 233

32 5 2 / 5 942 3,124 12 0 1,056 400 405

32 5 5 / 2 773 1,227 4 29,920 223 200 258

32 5 5 / 2 526 852 2 29,920 143 400 466



Table 3–15. Stratix III Fitter Results for a Fractional Rate FIR

Number of

Channels

Input Rate

(MSPS)

Decimation / interpolation

rate

Comb ALUTs (Note 1)

Logic Registers

18×18 Multipliers

Block Memory

BitsMemory ALUTs

System Frequency

(MHz)

Frequency Achieved

(MHz)

Table 3–16. Messages for the Fractional Rate FIR Block



Interpolating Decimating Filter Version: $Revision: 1.111 $

The version number and revision for the Fractional Rate FIR Filter (Version 1, revision 111 in this example).









Parameters table Lists the system clock, clock margin, input sample rate, number of coefficients, interpolation rate, decimation rate, number of channels, and type of symmetry parameters for the Fractional Rate FIR block.

Port interface table Lists the port interfaces to the Fractional Rate FIR block.




Resource utilization table Lists the resource utilization for the Fractional Rate FIR block.


Chapter 3: Filter Library 3–19Interpolating CIC

Design ExampleThe demo_firf and demo_filters_flow_control design examples include an example of using the Fractional Rate FIR block.


Interpolating CICThe Interpolating CIC block implements a highly efficient multi-channel cascaded integrator-comb filter across a broad range of parameters directly from a Simulink model.

The Interpolating CIC block performs filtering on a stream of multi-channel input data and produces a stream of output data with increased sampling frequency.

You can use the Interpolating CIC block in a digital up converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed point types, and the output is the implied full precision fixed point type. You can reduce the precision by using a separate Scale block, which can perform rounding and saturation to provide the required output precision.

FeaturesThe Interpolating CIC block supports rate changes from 2 to 64.

OperationThe Interpolating CIC has a higher output sample rate than the input sample rate by a factor I, where I is the interpolation rate. Notionally, the Interpolating CIC inserts (I–1) zeros for every input sample thus raising the sample rate by a factor I. Figure 3–6 shows how interpolating by 5 increases the sample rate of a sine wave input.

Figure 3–6. Interpolate by 5 Filter Increasing Sample Rate of a Sine Wave Input




3–20 Chapter 3: Filter LibraryInterpolating CIC

ParametersTable 3–17 shows the parameters for the Interpolating CIC block.

Port InterfaceTable 3–18 shows the port interface for the Interpolating CIC block.

Typical Resource UtilizationTable 3–19 shows some typical FPGA resource utilizations for a Interpolating CIC using Stratix III devices.

Table 3–17. Parameters for the Interpolating CIC Block




Number of stages Specifies the number of comb and integrator stages.

Interpolation factor Specifies the interpolation factor. Must be an integer.

Differential delay Specifies the differential delay.

Final decimation You can optionally specify a final decimation by 2 to allow interpolation rates which are multiples of 0.5. The decimation works by simply throwing away data value. This option can be used only to reduce the number of unique outputs the CIC generates.

Table 3–18. Port Interface for the Interpolating CIC Block





bypass Input When this input is asserted, the input data is zero-stuffed and scaled by the gain of the filter. This option can be useful during hardware debug.






Table 3–19. Stratix III Fitter Results for a Interpolating CIC

Number of

Channels

Input Rate

(MSPS)Interpolation

Rate

Comb ALUTs (Note 1)

Logic Registers

18×18 Multipliers

Block Memory

BitsMemory ALUTs

System Frequency

(MHz)

Frequency Achieved

(MHz)

1 2 25 270 406 0 0 0 200 326

1 2 25 305 837 0 0 12 400 456


Chapter 3: Filter Library 3–21Interpolating CIC

Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 3–20 shows some typical Help messages issued for the Interpolating CIC block.

1 2 10 258 394 0 0 0 200 347

1 2 10 287 771 0 0 0 400 471

16 2 25 859 2,563 0 0 758 200 236

16 2 25 737 2,540 0 0 436 400 409

16 2 10 555 1,490 0 0 392 200 303

16 2 10 583 1,556 0 0 234 400 450

32 2 25 1,788 4,946 0 0 1,604 200 221

32 2 25 1,336 4,582 0 0 916 400 408

32 2 10 1,056 2,705 0 0 828 200 278

32 2 10 946 2,587 0 0 490 400 426



Table 3–19. Stratix III Fitter Results for a Interpolating CIC

Number of

Channels

Input Rate

(MSPS)Interpolation

Rate

Comb ALUTs (Note 1)

Logic Registers

18×18 Multipliers

Block Memory

BitsMemory ALUTs

System Frequency

(MHz)

Frequency Achieved

(MHz)

Table 3–20. Messages for the Interpolating CIC Block



Interpolating CIC Filter Version: $Revision: 1.20 $

The version number and revision for the Interpolating CIC Filter (Version 1, revision 20 in this example).

Number of physical input buses / combs: 1

Depending on the input data rate, the number of wires needed to carry the input data may be more than 1. If so, the comb sections of the filter are duplicated (vectorized) to satisfy the data rate requirement.


Number of integrators: 2 Depending on the input data rate and interpolation factor the number of integrator stages needed to process the data may be more than 1. If so, the integrator sections of the filter are duplicated (vectorized) to satisfy the data rate requirement.

Calculated output bit width: 26 This is the bit width of the (vectorized) data output from the filter.

Calculated stage bit widths: 17 18 19 20 20 20 22 23 24 26

Each stage in the filter has precise bit width requirements. These are listed here as N comb sections followed by N integrator sections.

Gain: 625 The gain through the CIC filter. CIC filters usually have large gains that must be scaled back.

Comb section utilization: 20 cycles used of 50 available (40.00%)

In the comb section, the data rate is lower, so more resource sharing can be performed. This message indicates the efficiency of the subtractor usage.


3–22 Chapter 3: Filter LibraryDecimating CIC

Design ExampleThe demo_icic, demo_filters_flow_control, demo_duc, and demo_AD9856 design examples include an example of using the Interpolating CIC block.


Decimating CICThe Decimating CIC block implements a highly efficient multi-channel cascaded integrator-comb filter across a broad range of parameters directly from a Simulink model.

The Decimating CIC block performs filtering on a stream of multi-channel input data and produces a stream of output data with decreased sampling frequency.

You can use the Decimating CIC block in a digital down converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed point types, and the output is the implied full precision fixed point type. You can reduce the precision by using a separate Scale block, which can perform rounding and saturation to provide the required output precision.

FeaturesThe Decimating CIC block supports rate changes from 2 to 64.

Integrator section utilization: 10 cycles used of 10 available (100.00%)

In the integrator section, the data rate is higher, so less resource sharing can be performed. This message indicates the efficiency of the adder usage.


Parameters table Lists the interpolation rate, number of stages, differential delay, number of channels, final decimation on output, clock frequency and input sample rate parameters for the Interpolating CIC block.

Port interface table Lists the port interfaces to the Interpolating CIC block.



Resource utilization table Lists the resource utilization for the Interpolating CIC block.

Table 3–20. Messages for the Interpolating CIC Block





Chapter 3: Filter Library 3–23Decimating CIC

OperationThe Decimating CIC has a lower output sample rate than the input sample rate by a factor D, where D is the decimation factor. Notionally, the decimating CIC discards (D–1) out of D output samples thus lowering the sample rate by a factor D. The physical implementation avoids performing additions leading to these discarded samples reducing the filter cost. Figure 3–7 shows how decimating by 5 decreases the sample rate of a random noise input.

ParametersTable 3–21 shows the parameters for the Decimating CIC block.

Port InterfaceTable 3–22 shows the port interface for the Decimating CIC block.

Figure 3–7. Decimate by 5 Filter Decreasing Sample Rate of a Random Noise Input

Table 3–21. Parameters for the Decimating CIC Block




Number of stages Specifies the number of comb and integrator stages.

Decimation factor Specifies the decimation factor 1/(integer). (An integer greater than 1 implies interpolation.)

Differential delay Specifies the differential delay.

Table 3–22. Port Interface for the Decimating CIC Block






Typical Resource UtilizationTable 3–23 shows some typical FPGA resource utilizations for a Decimating CIC using Stratix III devices.

Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 3–24 on page 3–25 shows some typical Help messages issued for the Decimating CIC block.


bypass Input When this input is asserted, the input data is zero-stuffed and scaled by the gain of the filter. This may be useful during hardware debug.






Table 3–22. Port Interface for the Decimating CIC Block


Table 3–23. Stratix III Fitter Results for a Decimating CIC

Number of

Channels

Input Rate

(MSPS)Decimation

Rate

Comb ALUTs (Note 1)

Logic Registers

18×18 Multipliers

Block Memory

BitsMemory ALUTs

System Frequency

(MHz)

Frequency Achieved

(MHz)

1 10 2 240 391 0 0 0 200 380

1 10 2 260 487 0 0 0 400 469

1 10 10 363 585 0 0 0 200 278

1 10 10 403 857 0 0 0 400 462

16 10 2 403 946 0 0 230 200 340

16 10 2 472 1,149 0 0 230 400 419

16 10 10 526 1,320 0 0 350 200 261

16 10 10 664 1,806 0 0 350 400 443

132 10 2 812 1,612 0 0 478 200 275

32 10 2 819 1,433 0 0 460 400 430

32 10 10 1,055 2,226 0 0 718 200 259

32 10 10 1,159 2,226 0 0 700 400 416




Chapter 3: Filter Library 3–25Decimating CIC

Design ExampleThe demo_dcic and demo_ddc design examples include an example of using the Decimating CIC block.


Table 3–24. Messages for the Decimating CIC Block



Decimating CIC Filter Version: $Revision: 1.20 $

The version number and revision for the Decimating CIC Filter (Version 1, revision 20 in this example).

Number of physical input buses / integrators: 1

Depending on the input data rate, the number of wires needed to carry the input data may be more than 1. If so, the integrator sections of the filter are duplicated (vectorized) to satisfy the data rate requirement.

Number of physical output buses / combs: 2

Depending on the output data rate, the number of wires needed to carry the output data may be more than 1. If so, the output wires are duplicated (vectorized) to satisfy the data rate requirement. The output data rate is the product of the input rate and the interpolation rate.

Number of integrators: 2 Depending on the input data rate and interpolation factor the number of integrator stages needed to process the data may be more than 1. If so, the integrator sections of the filter are duplicated (vectorized) to satisfy the data rate requirement.

Calculated output bit width: 26 This is the bit width of the (vectorized) data output from the filter.

Calculated stage bit widths: 17 18 19 20 20 20 22 23 24 26

Each stage in the filter has precise bit width requirements. These are listed here as N comb sections followed by N integrator sections.

Gain: 625 The gain through the CIC filter. CIC filters usually have large gains that must be scaled back.

Comb section utilization: 20 cycles used of 50 available (40.00%)

In the comb section, the data rate is lower, so more resource sharing can be performed. This message indicates the efficiency of the subtractor usage.

Integrator section utilization: 10 cycles used of 10 available (100.00%)

In the integrator section, the data rate is higher, so less resource sharing can be performed. This message indicates the efficiency of the adder usage.


Parameters table Lists the decimation rate, number of stages, differential delay, number of channels, clock frequency and input sample rate parameters for the Decimating CIC block.

Port interface table Lists the port interfaces to the Decimating CIC block.



Resource utilization table Lists the resource utilization for the Decimating CIC block.







4. FFT Library

The FFT library contains the following blocks in the Common folder:

■ Complex Multiplier (ComplexMult)

■ Complex Sample Delay

■ Dual Twiddle Memory

■ Negate

■ Negate Parameterizable

The following blocks are available in the Radix2 folder:

■ Butterfly I (BFI)

■ Butterfly II (BFII)

■ Bit Reverse Core

■ Twiddle Generator

1 The blocks in the Radix 2 folder support a hardware oriented Radix-22 algorithm based on a twiddle factor decomposition technique using butterfly structures.

f For more information about the Radix-22 algorithm, refer to A New Approach to Pipeline FFT Processor – Shousheng He & Mats Torkleson, Department of Applied Electronics, Lund University, Sweden.

The FFT library does not support the Simulink complex data-type or vectors.


4–2 Chapter 4: FFT LibraryComplex Multiplier (ComplexMult)

Complex Multiplier (ComplexMult)The ComplexMult block performs the complex product of two complex operands as shown by the following equation:

zr = ar × wr

The output of the block is at full precision.

ParametersThe ComplexMult block has no parameters.

Port InterfaceTable 4–1 shows the port interface for the ComplexMult block.

Design ExampleThe demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_natural, demo_ifft_8192_natural, demo_fft_4096_br, and demo_fft_8192_br design examples include an example of the ComplexMult block.


Table 4–1. Port Interface for the ComplexMult Block

Signal Direction Type Description

ar Input Any Fixed Point Type Real part of operand a

ai Input Any Fixed Point Type Imaginary part of operand a

wr Input Any Fixed Point Type Real part of operand w

wi Input Any Fixed Point Type Imaginary part of operand w

zr Output Derived Fixed Point Type (Note 1) Real part of the result

zi Output Derived Fixed Point Type (Note 1) Imaginary part of the result


(1) With worst case 8-bit growth applied.




Chapter 4: FFT Library 4–3Complex Sample Delay

Complex Sample DelayThe Complex Sample Delay block applies a user-specified delay Z to the incoming complex data stream as shown by the equations:

Out1 = In1 × (1/Z)Out2 = In2 × (1/Z)

The block conveniently accepts two samples to support complex data streams and is typically used in fully streaming FFT architectures.

The output type of this block is normally inherited (using an internal rule) and the type propagates through your design automatically. However, if you use the Complex Sample Delay block in a loop, you must specify the output type for at least one block in the loop as described in the following steps:

1. Click on the Complex Sample Delay block with the right mouse button and select Look Under Mask to reveal that the block is implemented by two primitive Sample Delay blocks:

2. Double click on each Sample Delay block and set the output data type mode using the parameters described for “Sample Delay” on page 7–43. You are warned that you are attempting to change the parameters of a library block. Click OK to confirm this dialog box.

ParametersTable 4–2 shows the parameters for the Complex Sample Delay block.

Port InterfaceTable 4–3 shows the port interface for the Complex Sample Delay block.

Table 4–2. Parameters for the Complex Sample Delay Block


Delay Specifies the delay.

Table 4–3. Port Interface for the Complex Sample Delay Block


In1 Input Inherited Fixed Point Type Data input 1

In2 Input Inherited Fixed Point Type Data input 2


4–4 Chapter 4: FFT LibraryComplex Sample Delay

Design ExampleThe demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, and demo_ifft_8192_natural design examples include an example of the Complex Sample Delay block.


Out1 Output Inherited Fixed Point Type (same as In1) Data output 1

Out2 Output Inherited Fixed Point Type (same as In2) Data output 2

Table 4–3. Port Interface for the Complex Sample Delay Block





Chapter 4: FFT Library 4–5Dual Twiddle Memory

Dual Twiddle MemoryThe Dual Twiddle Memory block calculates the complex twiddle factors associated with the evaluation of exp(-2pi.k1/N) and exp(-2pi.k2/N).

This block uses an efficient dual-port architecture to minimize the size of the internal lookup table while supporting the generation of two complex twiddle factors per clock cycle. k1 and k2 are provided at the input of the block, and they must be less than or equal to a synthesis time parameter N. The bit width and fixed point scaling of the twiddle factors should also be entered.

Because a cosine/sine wave has a range of [-1:1], you must provide at least two integer bits, and as many fractional bits as are appropriate. A good starting point is a twiddle bit width of 16 bits (enter 16 as the Precision), and a scaling of 2^-14 (enter 14 as the Scaling exponent). The resulting fixed point type is sfix16_en14 (2.14 in fixed point format).

ParametersTable 4–4 shows the parameters for the Dual Twiddle Memory block.

Port InterfaceTable 4–5 shows the port interface for the Dual Twiddle Memory block.

Table 4–4. Parameters for the Dual Twiddle Memory Block


Number of points (N) Specifies the number of points on the unit circle.

Precision Specifies the precision in bits of the twiddle factors.

Twiddle scaling exponent Specifies the fixed point scaling factor of the complex twiddle factor.

Table 4–5. Port Interface for the Dual Twiddle Memory Block


k1 Input Unsigned integer in range 0 to (N-1) Desired twiddle factor index

k2 Input Unsigned integer in range 0 to (N-1) Desired twiddle factor index

r1 Output Type determined by parameterization Real part of twiddle factor 1

i1 Output Type determined by parameterization Imaginary part of twiddle factor 1

r2 Output Type determined by parameterization Real part of twiddle factor 2

i2 Output Type determined by parameterization Imaginary part of twiddle factor 2


4–6 Chapter 4: FFT LibraryNegate

NegateThe Negate block negates the input value.

This is equivalent to a multiplication by (-1). The output of this block is of the same precision of the output, hence there is no protection against overflow when the input is the most negative value in that fixed point type.

A separate Negate Parameterizable block has the same function but with a parameterizable interface for use when you want to specify the input bit width or scaling factor.

1 When the decimal point is out-of-range (for example, bit width 16, with scaling 2-19) you must explicitly define the data type for the constant 0 to get the same output bit width as the input.

ParametersThe Negate block has no parameters.

Table 4–6 shows the parameters for the Negate Parameterizable block.

Port InterfaceTable 4–7 shows the port interface for the Negate block.

Negate ParameterizableRefer to the description of the Negate block.

Table 4–6. Parameters for the Negate Parameterizable Block


Bit width Specifies the data bit width.

Scaling Specifies the scaling factor.

Table 4–7. Port Interface for the Negate Block


x Input Any Fixed Point Type Data input

y Output Derived Fixed Point Type Data output


Chapter 4: FFT Library 4–7Butterfly I (BFI)

Butterfly I (BFI)The BFI block implements provides the Butterfly I functionality associated with the Radix-22 fully streaming decimate in frequency FFT architecture.

You should parameterize this block with the incoming data type to ensure that the necessary data precision is maintained. At the output, an additional bit of growth is applied.

The s port connects to the control logic. This control logic is the extraction of the appropriate bit of a modulo N counter. The value of s determines the signal routing of each sample and the mathematical combination with other samples.

ParametersTable 4–8 shows the parameters for the BFI block.

Port InterfaceTable 4–9 shows the port interface for the BFI block.

Design ExampleThe demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, and demo_ifft_8192_natural design examples include an example of the BFI block.


Table 4–8. Parameters for the BFI Block


Input bits Specifies the number of input bits.

Input scaling exponent Specifies the fixed point scaling factor of the input.

Table 4–9. Port Interface for the BFI Block


s Input Boolean or unsigned integer uint(1) Control pin

xr1 Input Type determined by parameterization Input from complex sample delay

xl1 Input Type determined by parameterization Input from complex sample delay

xr2 Input Type determined by parameterization Input from previous stage

xl2 Input Type determined by parameterization Input from previous stage

zr1 Output Type determined by parameterization Output to next stage

zl1 Output Type determined by parameterization Output to next stage

zr2 Output Type determined by parameterization Output to complex sample delay

zl2 Output Type determined by parameterization Output to complex sample delay




4–8 Chapter 4: FFT LibraryButterfly II (BFII)

Butterfly II (BFII)The BFII block implements block provides the Butterfly II functionality associated with the Radix-22 fully streaming decimate in frequency FFT architecture.

You should parameterize this block with the incoming data type to ensure that the necessary data precision is maintained. At the output, an additional bit of growth is applied.

The s port connects to the control logic. This control logic is the extraction of the appropriate bit of a modulo N counter. The value of s determines the signal routing of each sample and the mathematical combination with other samples.

The t port also connects to the control logic, but the extracted bit is different from the s port. The value of t determines whether an additional multiplication by –j occurs inside the butterfly unit.

ParametersTable 4–10 shows the parameters for the BFII block.

Port InterfaceTable 4–11 shows the port interface for the BFII block.

Table 4–10. Parameters for the BFII Block


Input bits Specifies the number of input bits.

Input scaling exponent Specifies the exponent part of the input scaling factor (2-exponent).

Table 4–11. Port Interface for the BFII Block


s Input Boolean Control pin

t Input Boolean Control pin

xr1 Input Type determined by parameterization Input from complex sample delay

xl1 Input Type determined by parameterization Input from complex sample delay

xr2 Input Type determined by parameterization Input from previous stage

xl2 Input Type determined by parameterization Input from previous stage

zr1 Output Derived fixed point type Output to next stage

zl1 Output Derived fixed point type Output to next stage

zr2 Output Derived fixed point type Output to complex sample delay

zl2 Output Derived fixed point type Output to complex sample delay


Chapter 4: FFT Library 4–9Butterfly II (BFII)

Design ExampleThe demo_fft256_radix4, demo_fft_4096_br, demo_fft_4096_natural, demo_fft_8192_br, and demo_ifft_8192_natural design examples include an example of the BFII block.





4–10 Chapter 4: FFT LibraryBit Reverse Core

Bit Reverse CoreThe Bit Reverse Core block performs buffering and bit reversal of incoming FFT frames.

A single synthesis time parameter specifies the length N of the fast Fourier transform.

Note that the digital reversal that is applied by this block is appropriate only for transform sizes that are an integer power of two. The block is double-buffered to support full streaming operation and accepts complex data.

ParametersTable 4–12 shows the parameters for the Bit Reverse block.

Port InterfaceTable 4–13 shows the port interface for the Bit Reverse block.

Design ExampleThe demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, and demo_ifft_8192_natural design examples includes an example of the Bit Reverse Core block.


Table 4–12. Parameters for the Bit Reverse Block


FFT Size Specifies the size of the FFT.

Table 4–13. Port Interface for the Bit Reverse Block


v Input Boolean Valid input signal

c Input Unsigned 8-bit integer Channel input signal

xr Input Any fixed point type Data input signal

xi Input Any fixed point type Data input signal

qv Output Boolean Valid output signal

qc Output Unsigned 8-bit integer Channel output signal

qr Output Any fixed point type Data output signal

qi Output Any fixed point type Data output signal




Chapter 4: FFT Library 4–11Twiddle Generator

Twiddle GeneratorThe Twiddle Generator block generates the appropriate sine/cosine coefficients that are multiplied by the streaming data in a Radix 22 architecture streaming FFT.

It should be fed at the input by a modulo N counter (where N is an integer power of two) and the appropriate complex sequence is generated at the output.

To parameterize this block, set the Counter bit width parameter with log2(N) and enter the bit width and fixed point scaling of the twiddle factors. Because a cosine/sine wave has a range of [-1:1], you must provide at least two integer bits, and as many fractional bits as are appropriate. A good starting point is a twiddle bit width of 16 bits (enter 16 as the twiddle bit width), and a scaling of 2-14 (enter 14 as the Twiddle scaling exponent). The resulting fixed-point type is sfix16_en14 (2.14 fixed point format).

ParametersTable 4–14 shows the parameters for the Twiddle Generator block.

Port InterfaceTable 4–15 shows the port interface for the Twiddle Generator block.

Design ExampleThe demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, and demo_ifft_8192_natural design examples include an example of the Twiddle Generator block.


Table 4–14. Parameters for the Twiddle Generator Block


Counter bit width Specifies the counter bit width.

Twiddle bit width Specifies the twiddle bit width.

Twiddle scaling exponent values Specifies the fixed point scaling factor of the complex twiddle factor.

Table 4–15. Port Interface for the Twiddle Generator Block


counter Input Any fixed point type Counter signal

wr Output Derived fixed point type Data output

wi Output Derived fixed point type Data output




4–12 Chapter 4: FFT LibraryTwiddle Generator



5. Waveform Synthesis Library

The Waveform Synthesis library contains the following blocks:

■ Complex Mixer

■ Real Mixer

■ NCO

The Complex Mixer block does not support the Simulink complex data-type. The in phase (real), and quadrature (imaginary) signals are input and output as separate signals.


5–2 Chapter 5: Waveform Synthesis LibraryComplex Mixer

Complex MixerThe Complex Mixer block performs a complex by complex multiply on streams of data. One important use for this function is frequency shifting a data stream in a digital up converter, where the first complex data is the i and q data and the second complex data is the cosine and sine data provided by an NCO.

The basic operation performed by the Complex Mixer block is to multiply a complex input stream by a synchronized complex data stream, sample by sample.

You can use this block in a digital up converter for a radio system or a general purpose DSP application. The data have fixed point types, and the output is the implied full precision fixed point type.

ParametersThe Complex Mixer performs element-by-element multiplication on n channels and m frequencies.

The system specification, including such factors as the channel count and sample rates, determines the main parameters for this block. The input sample rate of the block determines the number of channels present on each input wire and the number of wires:

Number of Channels per wire = Clock_Rate/Sample_Rate

Number of Wires = ceiling(Chan_Count×Sample_Rate/Clock_Rate)

For example, a sample rate of 60 MSPS and system clock rate of 240 MHz gives four samples to be time-division multiplexed on to each input wire.

If there are more channels than TDM slots available on a wire, the input wire is a vector of sufficient width to hold all the samples. Similarly, the number of frequencies (the number of complex numbers) determines the width of the sine and cosine inputs. The number of results produced by the Complex Mixer is the product of the sample input vector and the frequency vector. The results are time-division multiplexed on to the i and q outputs in a similar manner to the inputs.

Table 5–1 shows the parameters for the Complex Mixer block.

Table 5–1. Parameters for the Complex Mixer Block


Input Rate Per Channel (MSPS) The data rate per channel measured in millions of samples per second

Number of Complex Channels The number of complex input channels

Number of Frequencies The number of complex frequencies used in the multiplier


Chapter 5: Waveform Synthesis Library 5–3Complex Mixer

Port InterfaceTable 5–2 shows the port interface for the Complex Mixer block.

Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 5–3 shows some typical Help messages issued for the Complex Mixer block.

Design ExampleThe demo_complex_mixer, demo_duc, demo_wimax_duc design examples include an example of the Complex Mixer block.


Table 5–2. Port Interface for the Complex Mixer Block


i Input The real (in phase) half of the complex data input. If more channels are requested than can fit on a single bus, this signal is a vector. The bit width is inherited from the input wire.

q Input The imaginary (quadrature phase) half of the complex data input. If more channels are requested than can fit on a single bus, this signal is a vector. The bit width is inherited from the input wire.

v Input Indicates validity of data input signals. If v is high the data on the a wire is valid.

c Input Indicates channel of data input signals. If v is high, then c indicates the data channel data.

sin Input The imaginary part of the complex number. For example, the NCO's sine output.

cos Input The real part of the complex number. For example, the NCO’s cosine output.

i Output The in-phase (real) output of the mixer. This is (i × cos – q × sin). If more channels are requested than can fit on a single bus, this signal is a vector. The bit width is wide enough for the full precision result.

q Output The quadrature phase (imaginary) output of the mixer. This is (i × sin + q × cos). If more channels are requested than can fit on a single bus, this signal is a vector. The bit width is wide enough for the full precision result.

v Output Indicates validity of data output signals.

c Output Indicates channel of data output signals.

Table 5–3. Messages for the Complex Mixer Block




Port interface table Lists the port interfaces to the Complex Mixer block.

Resource utilization table Lists the resource utilization for the Complex Mixer block.




5–4 Chapter 5: Waveform Synthesis LibraryReal Mixer

Real MixerThe Real Mixer block performs a real by complex multiply on streams of data. One important use for this function is creating quadrature data from an antenna input, where the real data is the antenna data and the complex data is the cosine and sine data provided by an NCO.

The basic operation performed by the Real Mixer block is to multiply a real input stream by a synchronized complex data stream, sample by sample.

This might be used in a digital down converter for a radio system or a general purpose DSP application. The data have fixed point types, and the output is the implied full precision fixed point type.

ParametersThe Real Mixer performs element-by-element multiplication on n channels and m frequencies.

The system specification, including such factors as the channel count and sample rates, determines the main parameters for this block. The input sample rate of the block determines the number of channels present on each input wire and the number of wires:

Number of Channels per wire = Clock_Rate/Sample_Rate

Number of Wires = ceiling(Chan_Count×Sample_Rate/Clock_Rate)

For example, a sample rate of 60 MSPS and system clock rate of 240 MHz gives four samples to be time-division multiplexed on to each input wire:

If there are more channels than TDM slots available on a wire, the input wire is a vector of sufficient width to hold all the samples. Similarly, the number of frequencies (the number of complex numbers) determines the width of the sine and cosine inputs. The number of results produced by the Real Mixer is the product of the sample input vector and the frequency vector. The results are time-division multiplexed on to the i and q outputs in a similar way to the inputs.

Table 5–4 shows the parameters for the Real Mixer block.

Table 5–4. Parameters for the Real Mixer Block


Input Rate Per Channel (MSPS) The data rate per channel measured in millions of samples per second

Number of Channels The number of real input channels

Number of Frequencies The number of real frequencies used in the multiplier


Chapter 5: Waveform Synthesis Library 5–5Real Mixer

Port InterfaceTable 5–5 shows the port interface for the Real Mixer block.

Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 5–6 shows some typical Help messages issued for the Real Mixer block.

Design ExampleThe demo_ddc and demo_mix design examples include an example of the Real Mixer block.


Table 5–5. Port Interface for the Real Mixer Block


a Input The real data input to the block. If more channels are requested than can fit on a single bus, this signal is a vector. The bit width is inherited from the input wire.

v Input Indicates validity of data input signals. If v is high the data on the a wire is valid.

c Input Indicates channel of data input signals. If v is high, then c indicates the data channel.

sin Input The imaginary part of the complex number. For example, the NCO's sine output.

cos Input The real part of the complex number. For example, the NCO’s cosine output.

i Output The in-phase (real) output of the mixer. This is (a × cos). If more channels are requested than can fit on a single bus, this signal is a vector. The bit width is wide enough for the full precision result.

q Output The quadrature phase (imaginary) output of the mixer. This is (a × sin). If more channels are requested than can fit on a single bus, this signal is a vector. The bit width is wide enough for the full precision result.

v Output Indicates validity of data output signals.

c Output Indicates channel of data output signals.

Table 5–6. Messages for the Real Mixer Block




Port interface table Lists the port interfaces to the Mixer block.

Resource utilization table Lists the resource utilization for the Mixer block.




5–6 Chapter 5: Waveform Synthesis LibraryNCO

NCOA numerically controlled oscillator (NCO) or digitally controlled oscillator (DCO) is an electronic system for synthesizing a range of frequencies from a fixed time base. NCOs are useful when a continuous phase sinusoidal signal with variable frequency is required, such as when receiving the signal from a NCO-based transmitter in a communications system.

The NCO block uses an octant-based algorithm with trigonometric interpolation.

The basic operation performed by the NCO is to accumulate a phase angle in an accumulator. This angle is used as a lookup into sine and cosine tables to find a coarse sine and cosine approximation. This is usually implemented using a ROM. A Taylor series expansion of the small angle errors refines this coarse approximation to produce accurate sine and cosine values. The NCO block uses folding to produce multiple sine and cosine values if the sample rate is an integer fraction of the system clock rate.

You can use this block in a digital up or down converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed-point types, and the output is the implied full precision fixed-point type.

An NCO sometimes needs to synchronize its phase to an exact cycle. The phase and sync inputs are used for this purpose. The sync input is a write enable for the channel (address) specified by the chan input when the new phase value (data) is available on the phase input. You may need some external logic (which could be implemented as a primitive subsystem) to drive these signals. For example, you could prepare a sequence of new phase values in a shared memory and then write all the values to the NCO on a synchronization pulse. This option is particularly useful if you want an initial phase offset in the upper sinusoid. You can also use this option to implement efficient phase shift keying (PSK) modulators in which the input to the phase modulator varies according to a data stream.

ParametersThe system specification, including such factors as the channel count, sample rates, and noise floor, determines the main parameters for this block. All the parameters can be expressed as MATLAB expressions, making it easy to parameterize a complete system.

The hardware generation techniques create very efficient NCOs and is fast enough to be updated with every Simulink simulation, so the edit-simulation loop time is much reduced, improving productivity.

Table 5–7 shows the specification parameters for the NCO block.

Table 5–7. Specification Parameters for the NCO Block


Output Rate Per Channel (MSPS)

The sine and cosine output rate per channel measured in millions of samples per second.


Chapter 5: Waveform Synthesis Library 5–7NCO

Phase Increment and InversionThe Phase Increment and Inversion parameter allows you to specify the phase increment values that control the frequencies of the sinusoidal wave signals generated during simulation. You can also choose whether to invert the generated sinusoidal signals. This parameter is closely related to the Output Rate per Channel and the Accumulator Bit Width parameters. To achieve a desired frequency (in MHz) from the NCO block, you must specify a phase increment value defined by:

Phase Increment Value = (Frequency) * 2(Accumulator Bit Width) / (Output Data Rate)

This value must fall within the range specified by the Accumulator Bit Width parameter. For example, for an accumulator bit width of 24 bits, you can specify a phase increment value less than 224.

You can specify the phase increment values in a vector format that generates multichannel sinusoidal signals. The length of the vector determines how many channels (frequencies) of data are generated from the NCO block. For example, a length of 4 implies that four channels of data are generated.

When the design uses the NCO for super-rate applications (NCO frequency is higher than output data rate), for example direct RF DUC, use multiple channels (in evenly distributed phases). The phase increment value is:

Phase increment value = mod((frequency)/(output data rate), 1)×2(accumulator bit width)

The modulus function limits the phase value to be less than 1 and prevents interfering with the inversion bits.

Output Data Type The output width in bits of the NCO. The bit width controls the internal precision of the NCO. The spurious-free dynamic range (SFDR) of the waves produced is approximately 6.02 × bit width. The 6.02 factor comes from the definition of decibels with each added bit of precision increasing the SFDR by a factor of 20×log10(2).

Output Scaling Value This value interprets the output data in the Simulink environment. The power of 2 scaling provided lets you specify the range of the output value.

Accumulator Bit Width Specifies the width of the memory-mapped accumulator bit width. This governs the precision with which the NCO frequency can be controlled. The width is limited to the range 15–30 for use with a 32-bit memory map (shared by other applications such as a Nios II processor). The top two bits in the 32-bit width are reserved to control the inversion of the sine and cosine outputs. A width of 30 bits gives an accumulator precision of 0.02794 Hz. However, you can select Constant for the Read/Write Mode to allow the width to increase to 40 bits. This width results in an accumulator precision of 0.000027 MHz.

Phase Increment and Inversion

A vector that represents the step in phase used between each sample. This vector controls the frequencies generated during simulation. The length of the vector determines how many channels (frequencies) of data are generated from the NCO. The unit of the vector is one (sine or cosine) cycle. For information about using this parameter, refer to “Phase Increment and Inversion” on page 5–7.

Phase Increment and Inversion Memory Map

Specifies where in the memory-mapped space the NCO registers are mapped. For information about using this parameter, refer to “Phase Increment Memory Registers” on page 5–8.

Read/Write Mode Specifies whether the NCO phase increment and inversion registers are mapped as Read, Write, Read/Write, or Constant.

Table 5–7. Specification Parameters for the NCO Block




When the input is in matrix format (with multiple rows of vectors), the NCO block is configured as a multi-bank NCO for frequency hopping used in multi-carrier designs. The number of rows in the matrix represents the number of banks of frequencies (of sine and cosine waves) that are generated for a given channel. An additional bank input and b output port are automatically added to the NCO block.

1 There is no upper limit to the number of rows in the matrix and you can specify any number of frequency banks. However, you should carefully monitor the resource usage to ensure that the specified design fits into the target device.

You can also use the Phase Increment and Inversion parameter to indicate whether the generated sinusoidal signals are inverted. For an accumulator bit width of 24 bits, you can add two bits (the 25th and 26th bits) to the phase increment value for a given frequency. These bits indicate if the sine (26th bit) and cosine (25th bit) are inverted.

Phase Increment Memory RegistersYou can use the Phase Increment and Inversion Memory Map parameter to specify the base address of the memory-mapped space where the NCO registers are mapped. The System Data Width specified in the Control block and the Accumulator Bit Width specified in the NCO block determines the number of registers required for each phase increment value. You can specify the System Data Width to be either 16 or 32 bits. If the Accumulator Bit Width is larger than the System Data Width, then two registers are required to store each phase increment value.

The NCO block only supports one or two registers for each phase increment value. If one register is required for each phase increment value, the phase increment value for the first frequency is written into the base address, the second value into the next address (base address + 1) and so on. If two registers are required, the base address and the next address (base address + 1) are used for the first value with each address storing part of the value. The next pair of addresses are used to store the next value and so on.

For example, for a System Data Width of 16, Accumulator Bit Width of 24 and Phase Increment and Inversion Memory Map base address of 1000, addresses 1000 and 1001 are used to store the phase increment value for the first frequency. Address 1001 stores the lower 16 bits (15 .. 0) and address 1000 stores the remaining 8 bits (23 .. 16). If four channels of sinusoidal signals are generated, addresses 1002 and 1003 are used for the second channel, addresses 1004 and 1005 for the third channel, addresses 1006 and 1007 for the fourth channel.

In summary:

<total addresses required> = <number of registers per value> × <number of channels>

When the phase increment and inversion memory map registers (in write mode) are written, the new value takes effect immediately.

If the application is a super-rate operation (like direct RF DUC) and multiple channels NCO are configured for a new center frequency, the phase increment value for each channel should first be configured. The phases offsets of all channels are then synchronized at the same time by asserting the sync pulse.

To minimize the duration of disruption, you may use two banks of phase increment registers. The new phase increment registers bank is switched first. Then, the sync pulse can be applied to synchronize the new phase offsets.



f For a detailed example showing how to parameterize the NCO block, refer to the ModelIP Tutorial in the DSP Builder Advanced Blockset User Guide.

Frequency HoppingYou can use the NCO block to configure multiple banks of pre-defined frequencies for frequency hopping. If you specify a matrix comprising multiple rows of vectors as the Phase Increment and Inversion values, the NCO is configured for multiple banks with the number of banks being defined by the number of rows of vectors specified by inputs to the Phase Increment and Inversion parameter. A bank input and b output are automatically added to the NCO block. It also allocates phase increment memory registers for the multiple banks of frequencies automatically.

You can use the Avalon-MM interface to access (read/write) the phase increment memory registers in the same way as for a single bank with the register address for the ith bank frequencies starting from:

<base address> + (i -1) × <number of registers per value> × <number of channels>.

You can use the bank input as the index to switch the generated sinusoidal waves to the specified set (bank) of predefined frequencies.

1 Ensure that the bank input is restrained between the range (0 .. <number of banks> -1). Unreliable outputs from the NCO block can be expected if the bank input exceeds the number of banks.

When using an Avalon-MM interface to access (read or write) the phase increment memory registers, ensure that you only write to the inactive banks (banks which are not equal to the index specified by the input bank port). The dual-port memory used by the NCO block is in DONT_CARE mode when reading and writing to the same address. The active bank is used by the NCO block to read the phase increment value and writing to the active bank may cause unreliable values to be read out may pass out unexpected sinusoidal signals through the memory interface.

The read data, from the address where the new values are being written to, may also be unreliable because of the memory type used inside the NCO block. Only use read data from banks where they are not written to at the same time.

Results TabThe Results tab shows the implications of your parameter settings. Table 5–8 describes the parameters displayed in the Results tab.

Table 5–8. Results Tab Parameters for the NCO Block


Expected SFDR The SFDR in decibels relative to the carrier (dBc): (Output Data Type Width) × 20 × log10(2).

Accumulator precision Accumulator precision in Hz: 106 × (Output Rate) / 2(Accumulator Bit Width+1).

Frequency Frequency in MHz: (Output Rate) × [Phase Increment And Inversion] / 2(Accumulator Bit Width).

# outputs per cycle The number of outputs per cycle is the width of the vector of output signals: Physical channels out = ceil(length[Phase Increment and Inversion]) / ((System Clock Frequency) / (Output Rate)))

log2 of look-up table The number of address bits used in the internal look-up tables.




Port InterfaceTable 5–9 shows the port interface for the NCO block.

Typical Resource UtilizationSome typical FPGA resource utilizations for a NCO using Stratix III devices are shown in Table 5–10.

Table 5–9. Port Interface for the NCO Block


chan Input Indicates the channel. If v is high, then chan indicates which channel the data corresponds to.

v Input Indicates validity. If v is high, then new data is generated.

phase Input Specifies the phase offset. The size of this port should match the wire count of the NCO. (Note 1)

sync Input Specifies the phase sync. The size of this port should match the wire count of the NCO output. When asserted, the phase offsets of all channels are synchronized to the phase inputs. This signal has no effect to the phase increment and inversion registers. When this signal is used, you may need to initialize the offsets upon system power-up or reset. (Note 1)

bank Input This input is available when you specify a matrix of predefined vectors for the phase increment values. You can use this input to switch to the bank of predefined frequencies. For information about using this signal, refer to “Frequency Hopping” on page 5–9.

sin Output The sine data output from the block. If more channels are requested than can fit on a single bus, this signal is a vector. The bit width is a function of the input bit width and the parameterization.

cos Output The cosine data output from the block. If more channels are requested than can fit on a single bus, this signal is vector. The bit width is a function of the input bit width and the parameterization.

(Note 1)

v Output Indicates validity of the data output signals.

c Output Indicates channel of the data output signals.

b Output Indicates the bank used by the output signals. This output is available when you specify a matrix of predefined vectors for the phase increment values.


(1) The number of sines/cosines per cycle is limited to 1–16 outputs. Use multiple NCO blocks if more outputs are required.

Table 5–10. Stratix III Fitter Results for a NCO

Number of Frequencies

Input Rate

(MSPS)Accumulator

Width

Comb ALUTs (Note 1)

Logic Registers

18×18 Multipliers

Block Memory

BitsMemory ALUTs

System Frequency

(MHz)

Frequency Achieved

(MHz)

2 100 22 269 549 4 9,280 50 200 356

2 200 22 310 820 4 9,280 67 400 492

2 100 26 293 569 4 9,280 50 200 360

2 200 26 361 944 4 9,280 71 400 466

3 67 22 271 572 4 9,312 50 200 313

3 133 22 313 843 4 9,312 67 400 460

3 67 26 295 596 4 9,312 50 200 368

3 133 26 363 971 4 9,312 71 400 450

4 50 22 274 576 4 9,344 72 200 344

4 100 22 319 851 4 9,344 89 400 467



Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 5–11 shows some typical Help messages issued for the NCO block.

Design ExampleThe demo_nco, demo_ddc, demo_duc, demo_AD9856 and demo_wimax_duc design examples include an example of the NCO block.


4 50 26 298 600 4 9,344 76 200 337

4 100 26 370 981 4 9,344 95 400 461



Table 5–10. Stratix III Fitter Results for a NCO

Number of Frequencies

Input Rate

(MSPS)Accumulator

Width

Comb ALUTs (Note 1)

Logic Registers

18×18 Multipliers

Block Memory

BitsMemory ALUTs

System Frequency

(MHz)

Frequency Achieved

(MHz)

Table 5–11. Messages for the NCO Block




Port interface table Lists the port interfaces to the NCO block.

Resource utilization table Lists the resource utilization for the NCO block.







6. ModelBus Library

The ModelBus library contains the following blocks:

■ Bus Slave

■ Bus Stimulus

■ Bus Stimulus File Reader

■ Register Bit (RegBit)

■ Register Field (RegField)

■ Register Out (RegOut)

■ Shared Memory (SharedMem)

The ModelBus library does not support the Simulink complex data-type or vectors.

Bus SlaveThe Bus Slave block provides direct access to the signals on the processor interface bus.

Any accesses to the memory region encapsulated by the base address (described by the Memory Name parameter) and size (described by the Number of Words parameter) over the bus is output over the a, d and w outputs.

You must provide logic to generate any appropriate response connected to the rd and rv inputs, which is then returned over the processor interface.

ParametersTable 6–1 shows the parameters for the Bus Slave block.

Table 6–1. Parameters for the Bus Slave Block


Memory Name Specifies the memory region. Can be an expression but must evaluate to an integer address.

Read/Write Mode Specifies the mode of the memory as viewed from the processor:

■ Read: Processor can only read over specified address range.

■ Write: Processor can only write over specified address range.

■ Read/Write: Processor can read or write over specified address range.

■ Constant: Processor cannot access specified address range. This option continues to reserve space in the memory map.

Number of Words to Address

Specifies the address range to be accessed via this block.

Description Text describing what is at the specified address.


6–2 Chapter 6: ModelBus LibraryBus Stimulus

Port InterfaceTable 6–2 shows the port interface for the Bus Slave block.

Bus StimulusTogether with the Bus Stimulus File Reader block, the Bus Stimulus block provides a mechanism to simulate accesses over the processor interface in the Simulink environment.

The Bus Stimulus block performs hidden accesses to the registers and shared memory blocks in the memory hierarchy of your model It is effectively an interface that allows another block to read and write to any address. The address and data ports act as though an external processor reads and writes to your system.

The Bus Stimulus block transmits data from its input ports (address, writedata and write) over the processor interface, and thus modifies the internal state of the memory-mapped registers and memories as appropriate. Any response from the simulated processor interface is output on the readdata and readvalid output ports.

A simple example of using the Bus Stimulus block is to connect constants to the address and data inputs; a pulse on the write port then writes the data to any register mapped to the specified address. Putting a counter on the address input then provides all the data in every memory location on the readdata port. The readvalid output indicates whether an address was mapped.

ParametersTable 6–3 shows the parameters for the Bus Stimulus block.

Evaluated Address Expression

Displays the evaluated value of the Memory Name expression when you click Apply.

Sample Time Specifies the Simulink sample time.

Table 6–1. Parameters for the Bus Slave Block


Table 6–2. Port Interface for the Bus Slave Block


rd Input 16-bit or 32-bit unsigned integer Read data

rv Input Boolean Read data valid

a Output Derived fixed point type Bus address

d Output 16-bit or 32-bit unsigned integer Write data

w Output Boolean Write enable


Chapter 6: ModelBus Library 6–3Bus Stimulus File Reader

Port InterfaceTable 6–4 shows the port interface for the Bus Stimulus block.

Bus Stimulus File ReaderTogether with the Bus Stimulus block, the Bus Stimulus File Reader block provides a mechanism to simulate accesses over the processor interface in the Simulink environment.

The Bus Stimulus File Reader block reads a stimulus file (.stm) and generates signals that match the Bus Stimulus block.

A bus stimulus file describes a sequence of transactions to occur over the processor interface, together with expected read back values. This block reads such files and produces outputs for each entry in the file.

Table 6–3. Parameters for the Bus Stimulus Block



Table 6–4. Port Interface for the Bus Stimulus Block


address Input Unsigned integer Address to access

writedata Input 16-bit or 32-bit unsigned integer Write data

write Input Boolean Write enable

readdata Output 16-bit or 32-bit unsigned integer Read data

readvalid Output Boolean Read data valid


6–4 Chapter 6: ModelBus LibraryBus Stimulus File Reader

Bus stimulus files are automatically written for any blocks that have processor mapped registers when you simulate a design. Any design with useful register files generates a bus stimulus file that you can use to bring your design out of reset (all registers 0). You can also write your own bus stimulus files with the following format:

MemSpace Address WriteData WE ExpReadData Mask

where

MemSpace: Specifies the memory space (the format supports multiple memory spaces).

Address: The word address.

WriteData: The data to write if any.

WE: Perform a write when 1.

ExpReadData: The expected read data. The value that is read from a location is checked against this value to allow self checking tests.

Mask: When the expected read data is checked, only the bits in this mask are checked. This allows you to read, write, or check specified bits in a register.

During simulation, any mismatch between the expected read data (as described in the bus stimulus file) and the incoming read data (provided by the BusStimulus block) is highlighted and a warning is issued.

ParametersTable 6–5 shows the parameters for the Bus Stimulus File Reader block.

Port InterfaceTable 6–6 shows the port interface for the Bus Stimulus File Reader block.

Table 6–5. Parameters for the Bus Stimulus File Reader Block


Enabled Turn on to enable reading of the bus stimulus file data.

Stimulus File Name Specifies the file from which to read bus stimulus data.

Log File Name Specifies the file to store a log of all attempted bus stimulus accesses.

Space Width Specifies the width of the memory space as described in the bus stimulus file. (This must be same as the width specified in the Control block.)

Addr Width Specifies the width of the address space as described in the bus stimulus file. (This must be the same as the width specified in the Control block.)

Data Width Specifies the width of the data width as described in the bus stimulus file (must be same as Control).


Table 6–6. Port Interface for the Bus Stimulus File Reader Block


readdata Input 16-bit or 32-bit unsigned integer Read data.

readvalid Input Boolean Read data valid.

space Output Unsigned integer Memory space from file.


Chapter 6: ModelBus Library 6–5Register Bit (RegBit)

Register Bit (RegBit)The Register Bit block provides a register bit accessible in your model and via the processor interface.

The Register Name field specifies the address of the register and must evaluate to an unsigned integer. The Bit parameter determines the location of the register bit in the memory-mapped word.

ParametersTable 6–7 shows the parameters for the Register Bit block.

Port InterfaceTable 6–8 shows the port interface for the Register Bit block.

address Output Unsigned integer Address from file.

writedata Output 16-bit or 32-bit unsigned integer Data from file.

write Output Boolean Write signal from file.

readexpected Output 16-bit or 32-bit unsigned integer Expected read data from file.

mask Output 16-bit or 32-bit unsigned integer Mask value from file.

checkstrobe Output Boolean Indicates when the readexpected and mask signals should be checked against readdata.

endofstimulus Output Boolean Generated signal to indicate when the end of the bus stimulus file is reached.

Table 6–6. Port Interface for the Bus Stimulus File Reader Block


Table 6–7. Parameters for the Register Bit Block


Register Name Specifies the address of the register. Must evaluate to an integer address.






Bit Specifies the bit location of the memory-mapped register in a processor word (allows different registers to share same address).

Initial Value Specifies the initial state of the register.

Description Text describing the register. The description is propagated to the generated memory map.


Table 6–8. Port Interface for the Register Bit Block


q Output Boolean Data


6–6 Chapter 6: ModelBus LibraryRegister Field (RegField)

Design ExampleThe demo_regs, demo_ddc and demo_duc design examples include an example of using the Register Bit block.


Register Field (RegField)The Register Field block provides a register field accessible in your model and via the Processor Interface.

The Register Name field specifies the address of the register and must evaluate to an unsigned integer.

The Most Significant Bit and Least Significant Bit parameters determine the size and location of the register bits in the memory-mapped word.

ParametersTable 6–9 shows the parameters for the Register Field block.

Port InterfaceTable 6–10 shows the port interface for the Register Field block.

Table 6–9. Parameters for the Register Field Block








Most Significant Bit

Specifies the MSB of the memory-mapped register in a processor word (allows different registers to share same address).

Least Significant Bit

Specifies the LSB of the memory-mapped register in a processor word (allows different registers to share same address).

Register Output Type

Specifies the data type that is being stored in the register. The size should equal (MSB–LSB+1).

Register Output Scale

Specifies the data type that is being stored in the register.

Initial Value Specifies the initial state of the register.


Modal Behavior Turn on this option if you want to enable modal behavior.





Chapter 6: ModelBus Library 6–7Register Out (RegOut)

Design ExampleThe demo_regs, demo_agc, demo_ddc, and demo_duc design examples include an example of using the Register Field block.


Register Out (RegOut)The Register Out block provides a register field accessible in your model and via the Processor Interface.

The Register Name field specifies the address of the register and must evaluate to an unsigned integer.

The Most Significant Bit and Least Significant Bit parameters determine the size and location of the register bits in the memory-mapped word.

ParametersTable 6–11 shows the parameters for the Register Out block.

Port InterfaceTable 6–12 shows the port interface for the Register Out block.

Table 6–10. Port Interface for the Register Field Block


q Output Any fixed point type. Data

Table 6–11. Parameters for the Register Out Block








Most Significant Bit

Specifies the MSB of the memory-mapped register in a processor word (allows different registers to share same address).

Least Significant Bit

Specifies the LSB of the memory-mapped register in a processor word (allows different registers to share same address).


Modal Behavior Turn on if you want to enable modal behavior.





6–8 Chapter 6: ModelBus LibraryShared Memory (SharedMem)

Design ExampleThe demo_regs design example include an example of using the Register Out block.


Shared Memory (SharedMem)The Shared Memory block provides a memory block accessible in your model and via the Processor Interface.

The length of the Initial Data 1-D array determines the size of the memory. You can optionally initialize the generated HDL with this data.

ParametersTable 6–13 shows the parameters for the Shared Memory block.

Table 6–12. Port Interface for the Register Out Block


d Input Any fixed point type Data

w Input Boolean Write data

Table 6–13. Parameters for the Shared Memory Block


Memory Mapped Address

Specifies the address of the memory block. Must evaluate to an integer address.






Initial Data Specifies the initialization data. The size of the 1-D array determines the memory size.

Initialize Hardware Memory Blocks with Initial Data Contents

Turn on when you want to initialize the generated HDL with the specified initial data.

Description Text describing the memory block. The description is propagated to the generated memory map.

Memory Output Type

Specifies the data type that is being stored in the memory block.

Memory Output Scale

Specifies the scale factor to be applied to the data stored in the memory block.





Chapter 6: ModelBus Library 6–9Shared Memory (SharedMem)

Port InterfaceTable 6–14 shows the port interface for the Shared Memory block.

Design ExampleThe demo_regs and demo_agc design examples include an example of using the Shared Memory block.


Table 6–14. Port Interface for the Shared Memory Block


a Input Unsigned integer Address

wd Input Any fixed point type Write data

we Input Boolean Write enable

rd Output Any fixed point type Read data




6–10 Chapter 6: ModelBus LibraryShared Memory (SharedMem)



7. ModelPrim Library

The ModelPrim library contains the following primitive blocks:

■ Absolute Value (Abs)■ Add■ Add SLoad■ AND Gate (And)■ Bit Combine■ Bit Extract■ Bit Reverse■ Channel In■ Channel Out■ Count Leading Zeros (CLZ)■ Compare Equality (CmpEQ)■ Compare Greater Than (CmpGE)■ Compare Less Than (CmpLT)■ Compare Not Equal (CmpNE)■ Complex Conjugate■ Constant (Const)■ Convert■ CORDIC■ Counter■ Delay■ Dual Memory (DualMem)■ General Purpose Input (GPIn)■ General Purpose Output (GPOut)■ Left Shift (LShift)■ Look-Up Table (Lut)■ Maximum Value (Max)■ Minimum Value (Min)■ Multiply (Mult)■ Multiplexer (Mux)■ NAND Gate (Nand)■ NOR Gate (Nor)■ NOT Gate (Not)■ OR Gate (Or)■ Sample Delay■ Select■ Sequence■ Shift■ Subtract (Sub)■ Synthesis Information (SynthesisInfo)■ XNOR Gate (Xnor)■ XOR Gate (Xor)


7–2 Chapter 7: ModelPrim LibraryVector and Complex Type Support

Vector and Complex Type SupportThe ModelPrim and ModelVectorPrim libraries provide automatic support for arrays and complex types.

These modes of operation are engaged using type propagation, and provide a convenient automatic method for generating repeated design elements to operate on all the data elements within vector and complex signals.

Blocks automatically determine whether the data they are processing is in scalar or vector format and operate accordingly.

In an analogous manner, using complex data (where it is supported) automatically cause blocks to be internally generated to process both real and imaginary data elements.

The hardware elements generated by these processes are then fully incorporated into the optimization schemes available within Advanced DSP Builder.

There are no restrictions on the combination of vector and complex modes.

Vector Type Support This topic describes element by element mode and mathematical vector mode.

Element by Element ModeThe blocks in the primitive library exhibit an element by element mode of operation when used with vector types.

This mode provides a convenient way to generate a uniform array to handle each element of data in a vector signal, without having to manually instantiate multiple blocks.

Internally, identical block instantiations are generated, one for each element in the vector signal. The vector width is propagated through the simulink system.

This mode of operation can be engaged in one of the following two ways:

■ Driving the block with a vector signal

■ Initializing the block with a vector of values. Only available for blocks that can be initialized with a user-specified value

The following restrictions exist on the vectors used:

■ Vector signals must be of uniform type

■ Signals associated with a block must either be vectors of identical width, or scalar

In the case, where a scalar value is used with vectors, copies of the single scalar value are used with each of the data elements in the vector signal.

This behavior is analogous to the scalar expansion that occurs with Simulink blocks.

Mathematical Vector ModeThe blocks in the primitive vector library perform mathematical operations when used with vector data.


Chapter 7: ModelPrim Library 7–3Vector and Complex Type Support

The outputs generated are potentially a function of any or all of the inputs. Vector width is not necessarily propagated.

The sum of elements block exhibits this behavior.

Interactions with SimulinkYou may use Simulink Mux and Demux to manipulate signals within Advanced DSP Builder designs.

Complex SupportSome blocks are capable of automatically processing complex data.

This mode provides a convenient way to simultaneously generate data and control pathways for the real and imaginary components.

For each complex value, two identical block instantiations are internally generated, for the real and imaginary components.

The complex nature of the data is propagated. Strictly real signals are expanded to provide a value for the imaginary component when used with complex data. The exact behavior depends on the nature of the port associated with the real signal. The real value is duplicated for control or address signals. The real and imaginary parts of complex data are subject to identical control signals. A zero imaginary value is generated for real data signals used in a complex data context. Real data values, x, are expanded, when required, to x + 0i.

RestrictionsNot all primitive blocks support complex data. Data signals are the only signal type permitted to be complex. An error message is issued if an attempt is made to drive control or address signals with complex values.

Interactions with SimulinkSome elements of the Simulink environment are available for use with the primitive blocks.

■ Simulink Complex to Real-Imag and Real-Imag to Complex. These blocks may be used to manipulate complex signals within Advanced DSP Builder designs.

■ Simulink Scopes. Simulink Scope blocks can display signals, but they do not directly support complex data. Attempting to view complex data generates a type propagation error.

Use a Complex to Real-Imag block to convert the complex signal.

You can use the complex Simulink function complex(x,y) to generate initialization values. This function is a useful way to ensure data is always treated as complex.

Generating a complex value with zero imaginary element. Simulink automatically converts complex values of form (x + 0i) to real values, which can cause type propagation errors. The complex() function can resolve this problem.

Use complex (x,0) to ensure such data is treated as complex.


7–4 Chapter 7: ModelPrim LibraryAbsolute Value (Abs)

Absolute Value (Abs)The Abs block outputs the absolute value of the input:

q = abs(a)

ParametersTable 7–1 shows the parameters for the Abs block.

Port InterfaceTable 7–2 shows the port interface for the Abs block.

Design ExampleThe demo_agc design example includes an example of using the Abs block.


Table 7–1. Parameters for the Abs Block


Output data type mode

Determines how the block sets its output data type:

■ Inherit via internal rule: The number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical.

■ Inherit via internal rule with word growth: The number of fractional bits is the maximum of the number of fractional bits in the input data types. The number of integer bits is the maximum of the number of integer bits in the input data types plus one. This additional word growth allows for subtracting the most negative number from 0 which would exceed the maximum positive number that can be stored in the number of bits of the input.

■ Specify via dialog: You can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1)

■ Boolean: The output type is Boolean.

Output data type Specifies the output data type. For example, sfix(16), uint(8).

Output scaling value

Specifies the output scaling value. For example, 2^-15.


(1) If you use the Abs block in a loop, you must specify the output type for at least one block in the loop.

Table 7–2. Port Interface for the Abs Block

Signal Direction Type DescriptionVector Data Support

Complex Data Support

a Input Any fixed point type

Operand Yes No

q Output Derived fixed point type

Result Yes No




Chapter 7: ModelPrim Library 7–5Add

AddThe Add block outputs the sum of the inputs:

q = a + b

If there are two or more inputs, the Add block outputs the sum of the inputs:

q = a + b + ...

For a single vector input, the Add block outputs the sum of of elements:

q = an

For a single scalar input, the Add block outputs the input value:

q = a

ParametersTable 7–3 shows the parameters for the Add block.

Port InterfaceTable 7–4 shows the port interface for the Add block.

Table 7–3. Parameters for the Add Block











Number of Inputs Specifies the number of inputs.


(1) If you use the Add block in a loop, you must specify the output type for at least one block in the loop.

Table 7–4. Port Interface for the Add Block




Operand 1 Yes Yes


7–6 Chapter 7: ModelPrim LibraryAdd

Design ExampleThe demo_agc, demo_fibonacci, demo_idct8x8, demo_iir, demo_QAM256, demo_regs, and demo_duc design examples include an example of using the Add block.


b Input Any fixed point type

Operand 2 Yes Yes


Result Yes (scalar output in one input case).

Yes

Table 7–4. Port Interface for the Add Block






Chapter 7: ModelPrim Library 7–7Add SLoad

Add SLoadThe Add SLoad block performs the following function:

q = s ? v : (a + b)

If the s input is low, output the sum of the first 2 inputs, a + b, else if s is high, then output the value v.

ParametersTable 7–5 shows the parameters for the Add SLoad block.

Port InterfaceTable 7–6 shows the port interface for the Add SLoad block.

Table 7–5. Parameters for the Add SLoad Block












(1) If you use the Add SLoad block in a loop, you must specify the output type for at least one block in the loop.

Table 7–6. Port Interface for the Add SLoad Block

Signal Direction Type Description Vector Data Support Complex Data Support

a Input Any fixed point type Operand 1 Yes Yes

b Input Any fixed point type Operand 2 Yes Yes

s Output Any fixed point type Synchronous load Yes No

v Output Any fixed point type Value to load if s is true Yes Yes

q Output Derived fixed point type Result Yes Yes


7–8 Chapter 7: ModelPrim LibraryAND Gate (And)

Design ExampleThe demo_duc design example includes an example of using the Add SLoad block.


AND Gate (And)The And block outputs the logical AND of the input values.

If the number of inputs is set to 1, then the logical and of all the individual bits of the input word is output.

ParametersTable 7–7 shows the parameters for the And block.

Port InterfaceTable 7–8 shows the port interface for the And block.

Design ExampleThe demo_duc design example includes an example of using the And block.


Table 7–7. Parameters for the And Block


Number of inputs Specifies the number of inputs.










(1) If you use the And block in a loop, you must specify the output type for at least one block in the loop.

Table 7–8. Port Interface for the And Block


unnamed Input Any fixed point type Operands 1 to n Yes No


Result Yes No






Chapter 7: ModelPrim Library 7–9Bit Combine

Bit CombineThe Bit Combine block outputs the bit concatenation of the input values:

((h << bitwidth(i)) | i)

ParametersTable 7–9 shows the parameters for the Bit Combine block.

Port InterfaceTable 7–10 shows the port interface for the Bit Combine block.

Design ExampleThe demo_idct8x8 and demo_QAM256 design examples include an example of using the Bit Combine block.


Table 7–9. Parameters for the Bit Combine Block











(1) If you use the Bit Combine block in a loop, you must specify the output type for at least one block in the loop.

Table 7–10. Port Interface for the Bit Combine Block


i Input Any fixed point type Operand Yes No

h Input Any fixed point type Operand Yes No

q Output Derived fixed point type Result Yes No




7–10 Chapter 7: ModelPrim LibraryBit Extract

Bit ExtractThe Bit Extract block outputs the bits extracted from the input, and recast as the specified data type:

q = (a >> LSB)

ParametersTable 7–11 shows the parameters for the Bit Extract block.

Port InterfaceTable 7–12 shows the port interface for the Bit Extract block.

Design ExampleThe demo_agc, demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, demo_QAM256, demo_regs, and demo_duc design examples include an example of using the Bit Extract block.


Table 7–11. Parameters for the Bit Extract Block










Least Significant Bit Position from Input Word

Specifies the bit position from the input word used as the LSB in the output word.


(1) If you use the Bit Extract block in a loop, you must specify the output type for at least one block in the loop.

Table 7–12. Port Interface for the Bit Extract Block


a Input Any fixed point type Operand Yes No





Chapter 7: ModelPrim Library 7–11Bit Reverse

Bit ReverseThe Bit Reverse primitive block reverses the bits at the input. The MSB is output as the LSB.

ParametersThe Bit Reverse block has no parameters.

Port InterfaceTable 7–13 shows the port interface for the Bit Reverse block.

Design ExampleThe demo_fft16_radix2 and demo_fft256_radix4 design examples include an example of using the Bit Reverse block.


Table 7–13. Port Interface for the Bit Reverse Block







7–12 Chapter 7: ModelPrim LibraryChannel In

Channel InThe Channel In block delineates the input boundary of a synthesizable primitive subsystem.

The Channel In block passes its input through to the outputs unchanged, with types preserved. The main purpose of this block is to indicate to the tools that these signals arrive synchronized from their source, so that the synthesis tool can interpret them.

ParametersTable 7–14 shows the parameters for the Channel In block.

Port InterfaceTable 7–15 shows the port interface for the Channel In block.

Design ExampleThe demo_agc, demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fibonacci, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, demo_iir, demo_AD9856, and demo_duc design examples include an example of using the Channel In block.


Table 7–14. Parameters for the Channel In Block


Number of data signals Specifies the number of data signals on this block.

Table 7–15. Port Interface for the Channel In Block

Signal Direction Type Description Vector Data SupportComplex Data Support

v Input Boolean Valid input signal No No

c Input uint(8) Channel input signal No No

0, 1, 2, ... Input Any fixed point type

A number of input data signals

Yes Yes

v Output Boolean Valid signal No No

c Output uint(8) Channel signal No No

0, 1, 2, ... Output Any fixed point type

A number of data signals

Yes Yes




Chapter 7: ModelPrim Library 7–13Channel Out

Channel OutThe Channel Out block delineates the output boundary of a synthesizable primitive subsystem.

The Channel Out block passes its input through to the outputs unchanged, with types preserved. The main purpose of this block is to indicate to the tools that these signals must be synchronized. The synthesis tool can ensure this.

After running a simulation in Simulink, the additional latency that is added to meet the specified timing constraints for your model is shown on the block. (Any delay explicitly added to your model, by for example a Sample Delay block, is not included in this latency.)

1 You can also access the value of the latency parameter by typing a command of the following form on the MATLAB command line:

get_param(gcb,’latency’)

ParametersTable 7–16 shows the parameters for the Channel Out block.

Port InterfaceTable 7–17 shows the port interface for the Channel Out block.

Table 7–16. Parameters for the Channel Out Block


Number of data signals Specifies the number of data signals on this block.

Table 7–17. Port Interface for the Channel Out Block


v Input Boolean Valid output signal No No

c Input 8-bit unsigned integer

Channel output signal No No

0, 1, 2, ... Input Any fixed point type

A number of output data signals

Yes Yes

v Output Boolean Valid signal No No

c Output 8-bit unsigned integer

Channel signal No No

0, 1, 2, ... Output Any fixed point type

A number of data signals

Yes Yes


7–14 Chapter 7: ModelPrim LibraryChannel Out

Design ExampleThe demo_agc, demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fibonacci, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, demo_iir, demo_AD9856, and demo_duc design examples include an example of the Channel Out block.





Chapter 7: ModelPrim Library 7–15Complex Conjugate

Complex Conjugate The Complex Conjugate block outputs the complex conjugate of its input value.

If a = x + yi,

q = x - yi

If the input value is real, an unchanged real value is output

q = a

ParametersTable 7–3 shows the parameters for the Complex Conjugate block.

Port InterfaceTable 7–19 shows the port interface for the Complex Conjugate block.

Table 7–18. Parameters for the Complex Conjugate Block












Table 7–19. Port Interface for the Complex Conjugate Block




Operand Yes Yes


Result Yes Yes


7–16 Chapter 7: ModelPrim LibraryCount Leading Zeros (CLZ)

Count Leading Zeros (CLZ)The CLZ block counts the leading zeroes of the input, and outputs that count.

ParametersTable 7–20 shows the parameters for the CLZ block.

Port InterfaceTable 7–21 shows the port interface for the CLZ block.

Table 7–20. Parameters for the CLZ Block











(1) If you use the CLZ block in a loop, you must specify the output type for at least one block in the loop.

Table 7–21. Port Interface for the CLZ Block




Operand Yes No


Number of consecutive zero bits in input word starting from the MSB

Yes No


Chapter 7: ModelPrim Library 7–17Compare Equality (CmpEQ)

Compare Equality (CmpEQ)The CmpEQ block outputs true if and only if the two inputs have the same value:

a == b

ParametersThe CmpEQ block has no parameters.

Port InterfaceTable 7–22 shows the port interface for the CmpEQ block.

Design ExampleThe demo_duc, demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, and demo_ifft_8192_natural design examples include an example of the CmpEQ block.


Table 7–22. Port Interface for the CmpEQ Block




q Output Boolean Result Yes Yes




7–18 Chapter 7: ModelPrim LibraryCompare Greater Than (CmpGE)

Compare Greater Than (CmpGE)The CmpGE block outputs true if and only if the first input is greater than or equal to the second input:

a >= b

ParametersThe CmpGE block has no parameters.

Port InterfaceTable 7–23 shows the port interface for the CmpGE block.

Design ExampleThe demo_agc design example includes an example of the CmpGE block.


Table 7–23. Port Interface for the CmpGE Block


a Input Any fixed point type Operand 1 Yes No

b Input Any fixed point type Operand 2 Yes No

q Output Boolean Result Yes No




Chapter 7: ModelPrim Library 7–19Compare Less Than (CmpLT)

Compare Less Than (CmpLT)The CmpLT block outputs true if and only if the first input is less than the second input:

a < b

ParametersThe CmpLT block has no parameters.

Port InterfaceTable 7–24 shows the port interface for the CmpLT block.

Compare Not Equal (CmpNE)The CmpNE block outputs true if the two inputs do not have the same value:

a ~= b

ParametersThe CmpNE block has no parameters.

Port InterfaceTable 7–25 shows the port interface for the CmpNE block.

Table 7–24. Port Interface for the CmpLT Block





Table 7–25. Port Interface for the CmpNE Block




q Output Boolean Result Yes Yes


7–20 Chapter 7: ModelPrim LibraryConstant (Const)

Constant (Const)The Const block outputs a specified constant value.

ParametersTable 7–26 shows the parameters for the Const block.

Port InterfaceTable 7–27 shows the port interface for the Const block.

Design ExampleThe demo_duc, demo_fir_fractional, demo_agc, demo_filters_flow_control, demo_fft_4096_br, demo_fft_8192_br, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, demo_iir, demo_regs, and demo_wimax_duc design examples include an example of the Const block.


Table 7–26. Parameters for the Const Block










Value Specifies the constant value.


(1) If you use the Const block in a loop, you must specify the output type for at least one block in the loop.

Table 7–27. Port Interface for the Const Block


q Output Any fixed point type Constant value. Yes Yes




Chapter 7: ModelPrim Library 7–21Convert

ConvertThe Convert block performs a type conversion of the input, and outputs the new data type.

You can optionally perform truncation, biased, or unbiased rounding if the output data type is smaller than the input. The LSB must be a value in the bit width of the input type.

ParametersTable 7–28 shows the parameters for the Convert block.

For example, for Add or Mult block, you can select the output word-length and fractional part using dialog.

Specifying the output type using dialog in this way should be viewed as a casting operation, which does not preserve the numerical value, but rather the underlying bits. This method never adds hardware to a block— just changes the interpretation of the output bits.

So, for example, a multiplier with both input data-types sfix16_En15 naturally has output type sfix32_En30. If the you select output format sfix32_En28, the output numerical value is effectively multiplied by four. For example, 1*1 input gives an output value of 4.

If the you select output format sfix32_En31, the output numerical value is effectively divided by two. For example 1*1 input gives an output value of 0.5.

Table 7–28. Parameters for the Convert Block




■ Inherit via internal rule—the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical.

■ Specify via dialog—you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1)

■ Boolean—the output type is Boolean.




Rounding method Determines the rounding mode:

■ Truncate: Discard any bits that fall below the new least significant bit.

■ Biased: Add 0.5 LSB and then truncate. This rounds towards infinity.

■ Unbiased: If the discarded bits equal 0.5 LSB of the new value then round towards the even integer, otherwise perform add 0.5 LSB and then truncate. This prevents the rounding operation introducing a DC bias where 0.5 always rounds towards positive infinity.

Saturation The Convert block allows saturation, which has an optional clip detect output that outputs 1 if any clipping has occurred. Saturation choices are none, symmetric, or asymmetric


(1) If you use the Convert block in a loop, you must specify the output type for at least one block in the loop.


7–22 Chapter 7: ModelPrim LibraryConvert

If you want to change data-type format in a way that preserves the numerical value, use a convert block, which adds the corresponding hardware. Adding a convert block directly after a primitive block lets you specify the data-type to preserve the numerical value.

So for example a Mult block followed by a Convert block, with input values 1*1 always give output value 1.

Port InterfaceTable 7–29 shows the port interface for the Convert block.

Design ExampleThe demo_agc, demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, demo_ifft_8192_natural, demo_fft16_radix2, demo_fft256_radix4, demo_iir, and demo_regs design examples include an example of the Convert block.


Table 7–29. Port Interface for the Convert Block


a Input Any fixed point type Data Yes Yes

q Output Specified fixed point type

Data Yes Yes




Chapter 7: ModelPrim Library 7–23CORDIC

CORDICThe CORDIC block performs a coordinate rotation using the coordinate rotation digital computer algorithm.

The CORDIC algorithm is a is a simple and efficient algorithm to calculate hyperbolic and trigonometric functions. It calculates the trigonometric functions of sine, cosine, magnitude and phase (arctangent) to any desired precision. A CORDIC algorithm is useful when you do not want to use a hardware multiplier, because the only operations it requires are addition, subtraction, bit shift and lookup.

The CORDIC algorithm is generally faster than other approaches when you do not want to use a hardware multiplier, or you want to minimize the number of gates required. Alternatively, when a hardware multiplier is available, table-lookup and power series methods are generally faster than CORDIC.

CORDIC is based on rotating the phase of a complex number, by multiplying it by a succession of constant values. The multiplications can all be powers of 2, and can be done using just shifts and adds in binary arithmetic. Therefore no actual multiplier function is needed.

During each multiplication, a gain occurs equal to:

where i represents the ith iterative step.

The total gain of the successive multiplications has a value of:

where n is the number of iterations.

This total gain can be calculated in advance and stored in a table. Additionally, it can be noted that:

The CORDIC block implements the these iterative steps using a set of shift-add algorithms to perform a coordinate rotation.

The CORDIC block takes four inputs, where the x and y inputs represent the (x, y) coordinates of the input vector, the p input represents the angle input, and the v represents the mode of the CORDIC block. It supports the following modes:

■ The first mode rotates the input vector by a specified angle.

■ The second mode rotates the input vector to the x-axis while recording the angle required to make that rotation.


7–24 Chapter 7: ModelPrim LibraryCORDIC

The x and y inputs must have the same bit width. The input bit width of the x and y inputs determines the number of stages (iterations) inside the CORDIC block, unless you explicitly specify an output bit width smaller than the input bit width in the block parameters.

The CORDIC gain is completely ignored to save time and resource. The bit width of the x and y inputs automatically grows by two bits inside the CORDIC block to account for the gaining factor of the CORDIC algorithm. Hence the x and y outputs are two bits wider than the input and you must handle the extra two bits in your design, if you have not specified the output bit width explicitly through the block parameters. You can compensate for the CORDIC gain outside the CORDIC block.

The p input is the angular value and has a range between –π and +π, which requires at least three integer bits to fully represent the range. The v input determines the mode. You can trade-off between accuracy for size (and efficiency) by specifying a smaller output data width to reduce the number of stages inside the CORDIC block.

ParametersTable 7–30 shows the parameters for the CORDIC block.

Port InterfaceTable 7–31 shows the port interface for the CORDIC block.

Table 7–30. Parameters for the CORDIC Block








Output scaling value Specifies the output scaling value. For example, 2^-15.


(1) If you use the CORDIC block in a loop, you must specify the output type for at least one block in the loop.

Table 7–31. Port Interface for the CORDIC Block


x Input Any fixed point type x coordinate of the input vector

Yes Yes

y Input Any fixed point type y coordinate of the input vector

Yes Yes

p Input Any fixed point type Required angle of rotation in the range between –π and +π

Yes Yes

v Input Any fixed point type Selects the mode of operation (0 = rotate by angle, 1 = rotate to x-axis)

Yes Yes


Chapter 7: ModelPrim Library 7–25CORDIC

x Output Any fixed point type x coordinate of the output vector

Yes Yes

y Output Any fixed point type y coordinate of the output vector

Yes Yes

p Output Any fixed point type Angle through which the coordinates were rotated

Yes Yes

Table 7–31. Port Interface for the CORDIC Block



7–26 Chapter 7: ModelPrim LibraryCounter

CounterThe Counter block maintains a counter and outputs the value each cycle.

The input is a counter enable and allows irregular counters to be implemented. The counter is initialized to the value provided, and counts with the given modulo, with the step size provided.

count = _initial_value;

while (1) { if (en) count = (count + _step_size) % _modulo}

ParametersTable 7–32 shows the parameters for the Counter block.

Port InterfaceTable 7–33 shows the port interface for the Counter block.

Design ExampleThe demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, demo_ifft_8192_natural, and helloWorld design examples include an example of the Counter block.


Table 7–32. Parameters for the Counter Block










Counter setup A vector that specifies the counter in the format:

[<initial_value> <modulo> <step size>]

For example, [0 32 1]


(1) If you use the Counter block in a loop, you must specify the output type for at least one block in the loop.

Table 7–33. Port Interface for the Counter Block


en Input Boolean Count enable Yes No


Result Yes No




Chapter 7: ModelPrim Library 7–27Delay

DelayThe Delay block outputs a delayed version of the input.

1 This block is deprecated. New designs should use the Sample Delay block.

ParametersTable 7–34 shows the parameters for the Delay block.

Port InterfaceTable 7–35 shows the port interface for the Delay block.

Design ExampleThe demo_AD9856, wcdma_multichannel_duc_mixer, wimax_ddc_1rx, and demo_duc design examples include an example of the Delay block.


Table 7–34. Parameters for the Delay Block










Number of delays Specifies the number of delays.


(1) If you use the Delay block in a loop, you must specify the output type for at least one block in the loop.

Table 7–35. Port Interface for the Delay Block


a Input Any fixed point type Operand Yes Yes


Result Yes Yes




7–28 Chapter 7: ModelPrim LibraryDual Memory (DualMem)

Dual Memory (DualMem)The DualMem block models a dual interface memory structure. The first data interface (inputs d, a, and w), can be read or written. The second data interface (specified on the second address input) is read only. The memory size is inferred from the size of the initialization array.

The behavior of read during write cycles of the memories depends on which interface you are reading from:

■ Reading from q1 while writing to interface 1 gives the new data on q1 (write first behavior).

■ Reading from q2 while writing to interface 1 gives the old data on q2 (read first behavior).

Turning on the DONT_CARE option may give a higher fMAX for your design, especially if the memory is implemented as a MLAB. When this option is on, the output is not double-registered (and therefore, in the case of MLAB implementation, uses fewer external registers), and you gain an extra half-cycle on the output. The current setting is indicated by the word FAST (on) or SLOW (off) overlaid on the block symbol. The default is off, which outputs old data for read-during-write.

f For more information about this option, refer to the Read-During-Write Output Behavior section in the RAM Megafunction User Guide.

ParametersTable 7–36 shows the parameters for the DualMem block.

Table 7–36. Parameters for the DualMem Block


Output data type mode Determines how the block sets its output data type:





Output scaling value Specifies the output scaling value. For example, 2^-15.

Initial contents Specifies the initialization data. The size of the 1-D array determines the memory size.

Use DONT_CARE when reading from and writing to the same address

Turning this option on, may produce faster hardware (that is, a higher fMAX) but with uncertain read data in hardware if you are simultaneously reading from and writing to the same address. Ensure that the same address is not read from and written to at the same time to guarantee valid read data.


(1) If you use the DualMem block in a loop, you must specify the output type for at least one block in the loop.


http://www.altera.com/literature/ug/ug_ram.pdf

Chapter 7: ModelPrim Library 7–29General Purpose Input (GPIn)

Port InterfaceTable 7–37 shows the port interface for the DualMem block.

Design ExampleThe demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, demo_ifft_8192_natural, and demo_duc design examples include an example of the DualMem block.


General Purpose Input (GPIn)The GPIn block models a general purpose input to a synthesizable subsystem. It is similar to the Channel In block but has no valid or channel inputs.

If the width is greater than one, the multiple inputs are assumed to be synchronized.

ParametersTable 7–38 shows the parameters for the GPIn block.

Table 7–37. Port Interface for the DualMem Block


d Input Any fixed point type Data to be written for interface 1

Yes Yes

a Input Unsigned integer Address to read/write from for interface 1

Yes No

w Input Boolean Write is enabled for interface 1 when 1, read is enabled for interface 1 when 0

Yes No

a Input Unsigned integer Address to read from for interface 2

Yes No

q1 Output Fixed point type Data out from interface 1 Yes Yes

q2 Output Fixed point type Data out from interface 2 Yes Yes

Table 7–38. Parameters for the GPIn Block


Number of data signals Specifies the number of input and output signals.




7–30 Chapter 7: ModelPrim LibraryGeneral Purpose Input (GPIn)

Port InterfaceTable 7–39 shows the port interface for the GPIn block.

Design ExampleThe demo_QAM256 design example includes an example of the GPIn block.


Table 7–39. Port Interface for the GPIn Block


a, b, ... Input Any fixed point type

Operands 1 to n Yes Yes

a, b, ... Output Same type as input Data is passed through unchanged.

Yes Yes




Chapter 7: ModelPrim Library 7–31General Purpose Output (GPOut)

General Purpose Output (GPOut)The GPOut block models a general purpose output to a synthesizable subsystem. It is similar to the Channel Out block but has no valid or channel inputs.

If the width is greater than one, the multiple outputs are generated and are guaranteed to be synchronized.

ParametersTable 7–40 shows the parameters for the GPOut block.

Port InterfaceTable 7–41 shows the port interface for the GPOut block.

Design ExampleThe demo_QAM256 design example includes an example of the GPOut block.


Table 7–40. Parameters for the GPOut Block


Number of data signals Specifies the number of input and output signals.

Table 7–41. Port Interface for the GPOut Block


a, b, ... Input Any fixed point type

Operands 1 to n Yes Yes

a, b, ... Output Same type as input Data is passed through unchanged.

Yes Yes




7–32 Chapter 7: ModelPrim LibraryLeft Shift (LShift)

Left Shift (LShift)The LShift block outputs the left shifted version of the input value.

The shift is specified by the input b:

q = (a << b)

The width of the data type a determines the maximum size of the shift. Shifts of more than the input word width result in an output of 0.

ParametersTable 7–42 shows the parameters for the LShift block.

Port InterfaceTable 7–43 shows the port interface for the LShift block.

Table 7–42. Parameters for the LShift Block











(1) If you use the LShift block in a loop, you must specify the output type for at least one block in the loop.

Table 7–43. Port Interface for the LShift Block






Chapter 7: ModelPrim Library 7–33Look-Up Table (Lut)

Look-Up Table (Lut)The Lut block outputs the contents of a look-up table, indexed by the input.

q = LUT[a]

The size of the table is determined by the size of the initialization array.

ParametersTable 7–44 shows the parameters for the Lut block.

Port InterfaceTable 7–45 shows the port interface for the Lut block.

Design ExampleThe demo_agc, demo_fft16_radix2, demo_fft256_radix4, demo_QAM256, and helloWorld design examples include an example of the Lut block.


Table 7–44. Parameters for the Lut Block










Output value map Specifies the location of the output values. For example, round([0;254]/17).


(1) If you use the Lut block in a loop, you must specify the output type for at least one block in the loop.

Table 7–45. Port Interface for the Lut Block



q Output Derived fixed point type Result Yes Yes (via output value map)




7–34 Chapter 7: ModelPrim LibraryMaximum Value (Max)

Maximum Value (Max)The Max block outputs the maximum of the inputs:

q = max(a, b)

ParametersTable 7–46 shows the parameters for the Max block.

Port InterfaceTable 7–47 shows the port interface for the Max block.

Table 7–46. Parameters for the Max Block











(1) If you use the Max block in a loop, you must specify the output type for at least one block in the loop.

Table 7–47. Port Interface for the Max Block






Chapter 7: ModelPrim Library 7–35Minimum Value (Min)

Minimum Value (Min)The Min block outputs the minimum of the inputs:

q = min(a, b)

ParametersTable 7–48 shows the parameters for the Min block.

Port InterfaceTable 7–49 shows the port interface for the Min block.

Table 7–48. Parameters for the Min Block











(1) If you use the Min block in a loop, you must specify the output type for at least one block in the loop.

Table 7–49. Port Interface for the Min Block






7–36 Chapter 7: ModelPrim LibraryMultiply (Mult)

Multiply (Mult)The Mult block outputs the product of the inputs:

q = a × b

ParametersTable 7–50 shows the parameters for the Mult block.

Port InterfaceTable 7–51 shows the port interface for the Mult block.

Design ExampleThe demo_regs, demo_agc, demo_idct8x8, demo_iir, demo_AD9856, and demo_duc design examples include an example of the Mult block.


Table 7–50. Parameters for the Mult Block











(1) If you use the Mult block in a loop, you must specify the output type for at least one block in the loop.

Table 7–51. Port Interface for the Mult Block








Chapter 7: ModelPrim Library 7–37Multiplexer (Mux)

Multiplexer (Mux)The Mux block allows a variable number of inputs and outputs the selected input, or zero if the select value is invalid (outside the number of data signals).

1 You can make a multiple input multiplexer by combining more than one mux2 blocks in a tree or by using a Select block.

ParametersTable 7–52 shows the parameters for the Mux block.

Port InterfaceTable 7–53 shows the port interface for the Mux block.

Table 7–52. Parameters for the Mux Block


Number of data signals

The input type for s is an unsigned integer of width log2(number of data signals). Boolean is also allowed in the case of two data inputs.




■ Specify via dialog: You can set the output type of the block explicitly using additional fields that are available when this option is selected. 1






(1) If you use the Mux block in a loop, you must specify the output type for at least one block in the loop.

Table 7–53. Port Interface for the Mux Block


s Input Any fixed point type Select input Yes No

0 Input Any fixed point type Input 0 Yes Yes

1 Input Any fixed point type Input 1 Yes Yes



7–38 Chapter 7: ModelPrim LibraryMultiplexer (Mux)

Design ExampleThe demo_fft_4096_br, demo_fft_8192_br, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, demo_AD9856, and demo_duc design examples include an example of the Mux block.





Chapter 7: ModelPrim Library 7–39NAND Gate (Nand)

NAND Gate (Nand)The Nand block outputs the logical NAND of the input values:

q = ~(a & b)

If the number of inputs is set to 1, then output the logical NAND of all the individual bits of the input word.

ParametersTable 7–54 shows the parameters for the Nand block.

Port InterfaceTable 7–54 shows the port interface for the Nand block.

Table 7–54. Parameters for the Nand Block












(1) If you use the Nand block in a loop, you must specify the output type for at least one block in the loop.

Table 7–55. Port Interface for the Nand Block






7–40 Chapter 7: ModelPrim LibraryNOR Gate (Nor)

NOR Gate (Nor)The Nor block outputs the logical NOR of the input values:

q = ~(a | b)

If the number of inputs is set to 1, then output the logical NOR of all the individual bits of the input word.

ParametersTable 7–56 shows the parameters for the Nor block.

Port InterfaceTable 7–57 shows the port interface for the Nor block.

Table 7–56. Parameters for the Nor Block












(1) If you use the Nor block in a loop, you must specify the output type for at least one block in the loop.

Table 7–57. Port Interface for the Nor Block






Chapter 7: ModelPrim Library 7–41NOT Gate (Not)

NOT Gate (Not)The Not block outputs the logical NOT of the input value:

q = ~a

ParametersTable 7–58 shows the parameters for the Not block.

Port InterfaceTable 7–59 shows the port interface for the Not block.

Design ExampleThe demo_fft_4096_br, demo_fft_8192_br, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, and demo_duc design examples include an example of the Not block.


Table 7–58. Parameters for the Not Block











(1) If you use the Not block in a loop, you must specify the output type for at least one block in the loop.

Table 7–59. Port Interface for the Not Block







7–42 Chapter 7: ModelPrim LibraryOR Gate (Or)

OR Gate (Or)The Or block outputs the logical OR of the input values:

q = a | b

If the number of inputs is set to 1, then output the logical OR of all the individual bits of the input word.

ParametersTable 7–60 shows the parameters for the Or block.

Port InterfaceTable 7–61 shows the port interface for the Or block.

Design ExampleThe demo_fft_4096_br, demo_fft_8192_br, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, and demo_duc design examples include an example of the Or block.


Table 7–60. Parameters for the Or Block












(1) If you use the Or block in a loop, you must specify the output type for at least one block in the loop.

Table 7–61. Port Interface for the Or Block








Chapter 7: ModelPrim Library 7–43Sample Delay

Sample DelayThe Sample Delay block outputs a delayed version of the input.

ParametersTable 7–62 shows the parameters for the Sample Delay block.

Port InterfaceTable 7–63 shows the port interface for the Sample Delay block.

Design ExampleThe demo_agc, demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fibonacci, demo_idct8x8, demo_ifft_4096_natural, demo_ifft_8192_natural, and demo_iir design examples include an example of the Sample Delay block.


Table 7–62. Parameters for the Sample Delay Block










Number of delays Specifies the number of samples to delay.


(1) If you use the Sample Delay block in a loop, you must specify the output type for at least one block in the loop.

Table 7–63. Port Interface for the Sample Delay Block


a Input Any fixed point type Data input Yes Yes

q Output Derived fixed point type Data output Yes Yes




7–44 Chapter 7: ModelPrim LibrarySelect

SelectThe Select block outputs one of the data signals (a, b, ...) if its paired select input (0, 1, ...) has a non-zero value.

q = 0 ? a : (1 ? b : d)

If all select inputs are 0, it outputs the default value d. At most one select input should be high at a time.

ParametersTable 7–64 shows the parameters for the Select block.

Port InterfaceTable 7–65 shows the port interface for the Select block.

Table 7–64. Parameters for the Select Block










Number of cases Specifies the number of non-default data inputs.


(1) If you use the Select block in a loop, you must specify the output type for at least one block in the loop.

Table 7–65. Port Interface for the Select Block


d Input Any fixed point type

Default input Yes Yes

0, 1, 2, ... Input Boolean One-hot select inputs Yes No

a, b, c, ... Input Any fixed point type

Data input Yes Yes


Result Yes Yes


Chapter 7: ModelPrim Library 7–45Select

Design ExampleThe demo_regs, and demo_agc design examples include an example of the Select block.





7–46 Chapter 7: ModelPrim LibrarySequence

SequenceThe Sequence block outputs a Boolean pulse of configurable duration and phase.

The input acts as an enable for this sequence. Notionally, this block is initialized with an array of booleans of length period. The first step_value entries are zero, and the remaining values are one.

A counter steps along this array, one entry at a time, and indexes the array. The output value is the contents of the array. The counter is initialized to initial_value. The counter wraps at step period, back to zero, to index the beginning of the array.

ParametersTable 7–66 shows the parameters for the Sequence block.

Port InterfaceTable 7–67 shows the port interface for the Sequence block.

Design ExampleThe demo_fft_4096_br, demo_fft_8192_br, demo_idct8x8, demo_fft_4096_natural, and demo_ifft_8192_natural design examples include an example of the Sequence block.


Table 7–66. Parameters for the Sequence Block










Sequence setup A vector that specifies the counter in the format: [<initial_value> <step_value> <period>]

For example, [0 50 100]


(1) If you use the Sequence block in a loop, you must specify the output type for at least one block in the loop.

Table 7–67. Port Interface for the Sequence Block


a Input Boolean Sequence enable Yes No





Chapter 7: ModelPrim Library 7–47Shift

ShiftThe Shift block outputs the logical right shifted version of the input value if unsigned, or outputs the arithmetic right shifted version of the input value if signed. The shift is specified by the input b:

q = (a >> b)

The width of the data type b determines the maximum size of the shift.

Shifts of more than the input word width result in an output of 0 for non-negative numbers and (0 – 2-F) for negative numbers (where F is the fraction length).

ParametersTable 7–68 shows the parameters for the Shift block.

Port InterfaceTable 7–69 shows the port interface for the Shift block.

Design ExampleThe demo_regs, and demo_agc design examples include an example of the Shift block.


Table 7–68. Parameters for the Shift Block











(1) If you use the Shift block in a loop, you must specify the output type for at least one block in the loop.

Table 7–69. Port Interface for the Shift Block



b Input Unsigned integer Operand 2 Yes No





7–48 Chapter 7: ModelPrim LibrarySubtract (Sub)

Subtract (Sub)The Sub block outputs the difference between the inputs:

q = a – b.

ParametersTable 7–70 shows the parameters for the Sub block.

Port InterfaceTable 7–71 shows the port interface for the Sub block.

Design ExampleThe demo_regs, demo_agc, demo_idct8x8, demo_iir, and demo_AD9856 design examples include an example of the Sub block.


Table 7–70. Parameters for the Sub Block












(1) If you use the Sub block in a loop, you must specify the output type for at least one block in the loop.

Table 7–71. Port Interface for the Sub Block








Chapter 7: ModelPrim Library 7–49Synthesis Information (SynthesisInfo)

Synthesis Information (SynthesisInfo)The SynthesisInfo block controls the synthesis flow for the current model.

After running a simulation in Simulink, the Help page for the SynthesisInfo block shows the latency, port interface and estimated resource utilization for the current primitive subsystem.

ParametersTable 7–72 shows the parameters for the SynthesisInfo block.

Port InterfaceThe SynthesisInfo block has no inputs or outputs.

Updated HelpAfter running a simulation, the Help pages are updated with specific information about each instance of a block. Table 7–73 shows some typical Help messages issued for the Synthesis Info block.

Table 7–72. Parameters for the SynthesisInfo Block


Synthesis Style (Note 1)

You can select the following synthesis styles:

■ Scheduled: This option uses a pipelining and delay distribution algorithm that creates fast hardware implementations from an easily described untimed block diagram.

■ WYYSIWYG: (Default) This option is useful when you want full control over the pipelining in a system. Every primitive that requires registering (for example, adders and multipliers) must be followed immediately by a Delay primitive. If insufficient delay is provided, an error occurs.

Constrain Latency (Note 2)

This option is available when the Scheduled synthesis style is selected and allows you to select the type of constraint and to specify its value. The specified value can be a workspace variable or an expression but must evaluate to a positive integer.

You can select the following types of constraint:

■ >: Greater than

■ >=: Greater than or equal to

■ =: Equal to

■ <=: Less than or equal to

■ <: Less than


(1) For more information about these styles, refer to “ModelPrim Blocks” in the DSP Builder Advanced Blockset User Guide.(2) For more information about constraining latency, refer to “Using latency Constraints” in the DSP Builder Advanced Blockset User Guide.

Table 7–73. Messages for the SynthesisInfo Block


Written on Tue Feb 19 11:25:27 2008 Date and time when this file was run

Latency is 16 The latency introduced by the current subsystem




7–50 Chapter 7: ModelPrim LibrarySynthesis Information (SynthesisInfo)

Design ExampleThe demo_regs, demo_agc, demo_fft16_radix2, demo_fft256_radix4, demo_fibonacci, demo_idct8x8, demo_iir, demo_QAM256, demo_AD9856 and demo_duc design examples include an example of the SynthesisInfo block.


Port interface table Lists the port interfaces to the current subsystem

Resource utilization table Lists the resource utilization for the current subsystem

Table 7–73. Messages for the SynthesisInfo Block




Chapter 7: ModelPrim Library 7–51XNOR Gate (Xnor)

XNOR Gate (Xnor)The Xnor block outputs the logical XNOR of the input values:

q = ~(a XOR b)

If the number of inputs is set to 1, then output the logical XNOR of all the individual bits of the input word.

ParametersTable 7–74 shows the parameters for the Xnor block.

Port InterfaceTable 7–75 shows the port interface for the Xnor block.

Table 7–74. Parameters for the Xnor Block












(1) If you use the Xnor block in a loop, you must specify the output type for at least one block in the loop.

Table 7–75. Port Interface for the Xnor Block






7–52 Chapter 7: ModelPrim LibraryXOR Gate (Xor)

XOR Gate (Xor)The Xor block outputs the logical XOR of the input values:

q = (a XOR b)

If the number of inputs is set to 1, then output the logical XOR of all the individual bits of the input word.

ParametersTable 7–76 shows the parameters for the Xor block.

Port InterfaceTable 7–77 shows the port interface for the Xor block.

Table 7–76. Parameters for the Xor Block












(1) If you use the Xor block in a loop, you must specify the output type for at least one block in the loop.

Table 7–77. Port Interface for the Xor Block







8. ModelVectorPrim Library

The ModelPrim library contains the sum of elements block that specifically operate on vector signals, rather than replicate functionality based on vector widths as with other primitive blocks. Primitive subsystems use these blocks with ModelPrim library blocks.


8–2 Chapter 8: ModelVectorPrim LibrarySum of Elements

Sum of ElementsThe Sum of Elements block outputs the sum of the elements within its single data input.

q = an

If the input is a scalar, the Sum of Elements block outputs an unchanged value.

q = a

ParametersTable 8–1 shows the parameters for the Sum of Elements block.

Port InterfaceTable 8–2 shows the port interface for the Sum of Elements block.

Table 8–1. Parameters for the Sum of Elements Block






■ Specify via dialog: You can set the output type of the block explicitly using additional fields that are available when this option is selected.






Table 8–2. Port Interface for the Sum of Elements Block




Operand Yes Yes


Result No (scalar output only).

Yes



A. Categorized Block List

This appendix lists the blocks in each of the libraries in the Altera DSP Builder Advanced Blockset.

BaseThe Base library includes the following blocks:

■ Channel Viewer (ChanView)

■ Control

■ Device

■ Edit Params

■ Run ModelSim

■ Run Quartus II

■ Scale

■ Signals

Filter The Filter library includes the following blocks:

■ Single Rate FIR

■ Interpolating FIR

■ Decimating FIR

■ Fractional Rate FIR

■ Interpolating CIC

■ Decimating CIC

FFTThe FFT library includes the following blocks:

■ Complex Multiplier (ComplexMult)

■ Complex Sample Delay

■ Dual Twiddle Memory

■ Negate

■ Negate Parameterizable

■ Butterfly I (BFI)

■ Butterfly II (BFII)

■ Bit Reverse Core


A–2 Appendix A: Categorized Block List

■ Twiddle Generator

Waveform SynthesisThe Waveform Synthesis library includes the following blocks:

■ Complex Mixer

■ Complex Mixer

■ Real Mixer

■ NCO

ModelBusThe ModelBus library includes the following blocks:

■ Bus Slave

■ Bus Stimulus

■ Bus Stimulus File Reader

■ Register Bit (RegBit)

■ Register Field (RegField)

■ Register Out (RegOut)

■ Shared Memory (SharedMem)

ModelPrimThe ModelPrim library includes the following blocks:

■ Absolute Value (Abs)

■ Add

■ Add SLoad

■ AND Gate (And)

■ Bit Combine

■ Bit Extract

■ Bit Reverse

■ Channel In

■ Channel Out

■ Count Leading Zeros (CLZ)

■ Compare Equality (CmpEQ)

■ Compare Greater Than (CmpGE)

■ Compare Less Than (CmpLT)

■ Compare Not Equal (CmpNE)

■ Constant (Const)


Appendix A: Categorized Block List A–3

■ Convert

■ CORDIC

■ Counter

■ Delay

■ Dual Memory (DualMem)

■ General Purpose Input (GPIn)

■ General Purpose Output (GPOut)

■ Left Shift (LShift)

■ Look-Up Table (Lut)

■ Maximum Value (Max)

■ Minimum Value (Min)

■ Multiply (Mult)

■ Multiplexer (Mux)

■ NAND Gate (Nand)

■ NOR Gate (Nor)

■ NOT Gate (Not)

■ OR Gate (Or)

■ Sample Delay

■ Select

■ Sequence

■ Shift

■ Subtract (Sub)

■ Synthesis Information (SynthesisInfo)

■ XNOR Gate (Xnor)

■ XOR Gate (Xor)

ModelVectorPrim■ Sum of Elements


A–4 Appendix A: Categorized Block List



Alphabetical Index

AAbs block 7–4Add block 7–5Add SLoad block 7–7And block 7–8

BBFI block 4–7BFII block 4–8Bit Combine block 7–10Bit Extract block 7–11Bit Reverse Core block 4–10Bit Reverse primitive block 7–12Bus Slave block 6–1Bus Stimulus block 6–2Bus Stimulus File Reader block 6–3

CChannel In block 7–13Channel Out block 7–14ChanView block 2–1CLZ block 7–17CmpEQ block 7–18CmpGE block 7–19CmpLT block 7–20CmpNE block 7–20Complex Mixer block 5–3Complex Sample Delay block 4–3ComplexMult block 4–2Const block 7–21Control block 2–3Convert block 7–22CORDIC block 7–24Counter block 7–27

DDecimating CIC block 3–22Decimating FIR block 3–11Delay block 7–28Device block 2–4Dual Twiddle Memory block 4–5DualMem block 7–29

EEdit Params Block 2–5

FFractional Rate FIR block 3–15

GGPIn block 7–30GPOut block 7–32

IInterpolating CIC block 3–19Interpolating FIR block 3–7

LLShift block 7–33Lut block 7–34

MMax block 7–35Min block 7–36Mult block 7–37Mux2 block 7–38

NNand block 7–39NCO block 5–7Negate block 4–6Negate Parameterizable block 4–6Nor block 7–40Not block 7–41

OOr block 7–42

RReal Mixer block 5–5Register Bit block 6–4Register Field block 6–5Register Out block 6–7Run ModelSim block 2–8Run Quartus II block 2–9

SSample Delay block 7–43Scale block 2–10Select block 7–44Sequence block 7–46Shared Memory block 6–8Shift block 7–47Signals block 2–12Single Rate FIR block 3–4Sub block 7–48


Index–2

SynthesisInfo block 7–49

TTwiddle Generator block 4–11

XXnor block 7–51Xor block 7–52



Additional Information

Revision History The following table displays the revision history for this user guide.

How to Contact AlteraFor the most up-to-date information about Altera® products, refer to the following table.

Date Version Changes Made

January 2010 9.1 SP1 ■ Changed ModelPrim folding (time-division multiplexing), which is now controlled through the Channel In and Channel Out blocks

■ Updated Run ModelSim block description

■ Updated resource usage tables

■ Removed Channel Reorganizer block

■ Updated Mux block description

November 2009 9.1 ■ Added ModelPrim vector support and ModelPrim complex type support

■ Added ModelVectorPrim library for vector processing primitives

■ Updated generalization of ModelPrim Mux to more than two data signals

■ Added support for saturation and clip detect on ModelPrim Convert

■ Removed restrictions on the stimulus blocks used in the run ModelSim flow and included a comparison of ModelSim and Simulink results.

March 2009 9.0 Updated NCO block.

November 2008 8.1 Added description of the Edit Params block, information about coefficient generation and the channelization format for the FIR and CIC blocks. Updated the descriptions of the NCO, Bus Stimulus, Bus Stimulus File Reader, CORDIC, and Dual Memory blocks.

May 2008 8.0 First release of this reference manual.

Contact (Note 1)Contact Method Address

Technical support Website www.altera.com/support

Technical training Website www.altera.com/training

Email [email protected]

Product literature Website www.altera.com/literature

Non-technical support (General) Email [email protected]

(Software Licensing) Email [email protected]

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.


http://www.altera.com/support

http://www.altera.com/training

mailto:[email protected]

http://www.altera.com/literature/



Info–2 Additional InformationTypographic Conventions

Typographic ConventionsThis document uses the typographic conventions shown in the following table.

Visual Cue Meaning

Bold Type with Initial Capital Letters

Indicates command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box.

bold type Indicates directory names, project names, disk drive names, file names, file name extensions, and software utility names. For example, \qdesigns directory, d: drive, and chiptrip.gdf file.

Italic Type with Initial Capital Letters Indicates document titles. For example, AN 519: Stratix IV Design Guidelines.

Italic type Indicates variables. For example, n + 1.

Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file.

Initial Capital Letters Indicates keyboard keys and menu names. For example, Delete key and the Options menu.

“Subheading Title” Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, “Typographic Conventions.”

Courier type Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. Active-low signals are denoted by suffix n. Example: resetn.

Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI).

1., 2., 3., anda., b., c., and so on.

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

■ ■ Bullets indicate a list of items when the sequence of the items is not important.

1 The hand points to information that requires special attention.

c A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

w A warning calls attention to a condition or possible situation that can cause you injury.

r The angled arrow instructs you to press the Enter key.

f The feet direct you to more information about a particular topic.


Date post:	12-Jun-2020
Category:	Documents
Upload:	others
View:	11 times
Download:	1 times

DSP Builder Advanced Blockset Reference Manual · 101 Innovation Drive San Jose, CA 95134 DSP...

Documents