Dual-gate charge sensing in charge-coupled devices G.S. Hobson, R. Longstone and R.C. Tozer Indexing term: Charge-coupled devices Abstract: A novel technique is described for linear sensing of charge in tapped charge-coupled devices. It uses two gates. One is biased by a voltage source and one is floating, but both are coupled by surface-potential equilibrium. It is shown, experimentally and theoretically, that this technique has better linearity and dynamic range than floating-gate sensing. It has the same ease of peripheral circuit implementation as a floating-gate structure. 1 Introduction Realisation of tapped delay lines with surface channel charge-coupled devices (c.c.d.) requires a method of non- destructively sensing the charge in successive stages. 1 Two techniques are commonly used and are illustrated in Figs. 1 and 2. Constant-voltage sensing (Fig. 1) is carried out when charge is transferred under an electrode which is maintained at constant voltage by a virtual-earth charge amplifier. The output voltage is determined by the feedback capacitor out s,o 2 p-Si Fig. 1 Schematic of constant-voltage charge sensing V R<H "out SiO, p-Si Fig. 2 Schematic of floating-gate charge sensing and the charge induced on the sensing electrode by the minority carrier-signal charge at the Si/SiO 2 interface. 1 The feedback capacitor must have its voltage reset periodically to avoid leakage charge significantly affecting V out . Provided that the capacitance of the SiO 2 insulator is significantly larger than that of the depletion layer in the semiconductor this technique gives good linearity in trans- ducing charge to voltage. As the operating conditions of the sense electrodes are essentially the same as those of the charge-transfer electrodes this technique does not degrade the dynamic range from that available in an untapped device. Its disadvantage is the complexity of providing the virtual-earth amplifier in m.o.s. technology. In the floating-gate technique 2 illustrated in Fig. 2 the sensing electrode is initially reset to an appropriate voltage before it receives the transferred charge. Arrival of this charge then causes a change of surface potential at the Si/SiO 2 interface and this is capacitively coupled to the output via the SiO 2 capacitance. The relative circuit simplicity of this technique is attractive, but it suffers non- linearity and saturation problems. At its simplest the load- ing impedance is infinite so that all the minority signal charge at the Si/SiO 2 interface is stored on the depletion capacitance of the semiconductor. Accordingly, the surface potential at the Si/SiO 2 interface, and the depletion layer width, change more sensitivity with stored charge than is the case with a constant voltage-biased .electrode. The depletion layer completely collapses with less stored charge than that necessary for saturation under one of the transfer electrodes of the c.c.d. so that a limitation is placed on the charge handling of the device. The dependence of the depletion-layer capacity on surface potential also causes significant nonlinearity in the transduction of stored charge to output voltage. Both of these problems can be alleviated somewhat by including some capacitance (including the inevitable stray capacitance) in parallel with the sensing "RC •out Paper T241 S, first received 2nd June and in revised form 30th August 1978 The authors are with the Department of Electronic & Electrical Engineering, The University of Sheffield, Mappin Street, Sheffield SI 3JD, England Fig. 3 Schematic of dual-gate charge sensing SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6 207 0308-6968/78/060207+08 $ 01-50/0
Transcript
Dual-gate charge sensing incharge-coupled devices
G.S. Hobson, R. Longstone and R.C. Tozer
Indexing term: Charge-coupled devices
Abstract: A novel technique is described for linear sensing of charge in tapped charge-coupled devices. It usestwo gates. One is biased by a voltage source and one is floating, but both are coupled by surface-potentialequilibrium. It is shown, experimentally and theoretically, that this technique has better linearity anddynamic range than floating-gate sensing. It has the same ease of peripheral circuit implementation as afloating-gate structure.
1 Introduction
Realisation of tapped delay lines with surface channelcharge-coupled devices (c.c.d.) requires a method of non-destructively sensing the charge in successive stages.1 Twotechniques are commonly used and are illustrated in Figs. 1and 2. Constant-voltage sensing (Fig. 1) is carried out whencharge is transferred under an electrode which is maintainedat constant voltage by a virtual-earth charge amplifier. Theoutput voltage is determined by the feedback capacitor
out
s,o2
p-Si
Fig. 1 Schematic of constant-voltage charge sensing
VR<H"out
SiO,
p - S i
Fig. 2 Schematic of floating-gate charge sensing
and the charge induced on the sensing electrode by theminority carrier-signal charge at the Si/SiO2 interface.1
The feedback capacitor must have its voltage resetperiodically to avoid leakage charge significantly affectingVout. Provided that the capacitance of the SiO2 insulatoris significantly larger than that of the depletion layer in thesemiconductor this technique gives good linearity in trans-ducing charge to voltage. As the operating conditions ofthe sense electrodes are essentially the same as those ofthe charge-transfer electrodes this technique does notdegrade the dynamic range from that available in anuntapped device. Its disadvantage is the complexity ofproviding the virtual-earth amplifier in m.o.s. technology.
In the floating-gate technique2 illustrated in Fig. 2 thesensing electrode is initially reset to an appropriate voltagebefore it receives the transferred charge. Arrival of thischarge then causes a change of surface potential at theSi/SiO2 interface and this is capacitively coupled to theoutput via the SiO2 capacitance. The relative circuitsimplicity of this technique is attractive, but it suffers non-linearity and saturation problems. At its simplest the load-ing impedance is infinite so that all the minority signalcharge at the Si/SiO2 interface is stored on the depletioncapacitance of the semiconductor. Accordingly, the surfacepotential at the Si/SiO2 interface, and the depletion layerwidth, change more sensitivity with stored charge than isthe case with a constant voltage-biased .electrode. Thedepletion layer completely collapses with less stored chargethan that necessary for saturation under one of the transferelectrodes of the c.c.d. so that a limitation is placed on thecharge handling of the device. The dependence of thedepletion-layer capacity on surface potential also causessignificant nonlinearity in the transduction of stored chargeto output voltage. Both of these problems can be alleviatedsomewhat by including some capacitance (including theinevitable stray capacitance) in parallel with the sensing
"RC
•out
Paper T241 S, first received 2nd June and in revised form 30thAugust 1978The authors are with the Department of Electronic & ElectricalEngineering, The University of Sheffield, Mappin Street, SheffieldSI 3JD, England Fig. 3 Schematic of dual-gate charge sensing
SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6 207
0308-6968/78/060207+08 $ 01-50/0
electrode2 so that the operation tends towards constant-voltage sensing with some c.c.d. charge being stored on theseries combination of the SiO2 capacitance and this extracapacitance. A reduction of sensitivity is then inevitable.
This paper describes dual-gate sensing; a technique whichcombines the best features of both the above techniques,like the constant-voltage and floating-gate techniques justdescribed dual-gate sensing applies to surface-channeldevices only. The sensing electrodes are illustrated in Fig. 3.One is driven at a constant voltage equal to the c.c.d. clockvoltage and the second is a floating gate which is reset tothe same voltage before arrival of the signal charge. Whenthis charge is transferred to the electrode pair it causes thesurface potential under them to rise. The combined effectsof surface-potential equilibrium between the electrodes andthe more sensitive rise of surface potential for a givenquantity of charge under the floating electrode causes thegreater part of the charge to be stored under the constant-voltage electrode. Therefore, the relationship betweensignal charge and surface potential is dominated by thegood linearity properties of the constant-voltage biasedelectrode, and the surface potential can be detected at thefloating gate with its relatively simple circuit requirements.In effect the extra electrode replaces the virtual-earthcharge amplifier required in constant-voltage sensing.
Charge transfer from the dual-sensing electrodes may beachieved by reducing the clock voltage of the first electrodeto zero followed by setting the second (floating) electrodeto zero voltage. Preset of the floating gate to the full clockvoltage would occur after the next charge-transfer event.The clock waveforms and charge-transfer sequences areillustrated in Figs. 4 and 5, respectively.
2 Analysis of sensitivity, saturation and linearity fordual-gate sensing
The equivalent circuit of the dual-gate sensing configurationis shown in Fig. 6. Cx is the SiO2 capacitance under the
VRC sense
t, t2 h t.
Fig. 4 Clock waveform scheme for dual-gate sensing
208
constant-voltage electrode and C3 is the correspondingcapacitance under the floating gate. C4 is the inevitablestray capacitance and desired loading capacitance at theoutput and is assumed constant. C2 is the nonlinearcapacitance of the depletion layer under both electrodes.The charge q on C2 is functionally related to the surfacepotential Vs by
hAx + A2
(1)
where Ax and A2 are, respectively, the areas of theconstant-voltage and floating electrodes. For a uniformlydoped Si substrate1
hAx+A2
D
A, +A-(2)
where
D =
e,e0
2NAeese0(3)
€j and es are the relative permittivities of the SiO2 and Si,respectively, d is the SiO2 thickness and NA is theacceptor density in the Si substrate. For NA = 1021m~3,d= 10"7m,e7 = 3-9 and e s = 11-7,D is equal to 3-6 V"1.
In Fig. 6, qx, q2, q$ and q5 are the charges present afterreset of the electrodes and before arrival of signal charge.They include fixed charges at the Si/SiO2 interface which
'RC
$2 #1
1 ry77///z\ V//////A r
X//////A W7,
Fig. 5 Charge transfer for dual-gate sensing
SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6
cause a nonzero flat-band voltage VFB (Reference 3).Qsi + Qs2 + Qsi a r e t n e t n r e e components of the signalcharge qsig.
-q, • q
- q , - q"si
• q , -q
- q ,
s2
- q s3• q . -q s3 vout
' s 3
- q ,
Fig. 6 Charges and voltages.on a dual gate
The electrostatic equations corresponding to Fig. 4 areI si / rr Ty \ /A \
= V. (5)
Qs Vout
Qsig = Qsl + Qs2 + Qsl
(6)
(7)
(8)
In the following analysis, we define flatband conditions asthose where the depletion region is just removed withVB ~ VFB a nd no signal charge is present.
Saturation occurs for removal of the depletion region bysignal charge with electrode bias VB. Two saturationconditions are relevant. qmax is the value of qsig under bothelectrodes when saturation of the sensing structure occurs.Qsig max is the value of qsig when saturation occurs underone of the c.c.d. transfer electrodes. In this case it is takento be equal to the saturation charge under C\ so thatQsig max = Ci(VB— VFB). Using these definitions,eqns. 4—8 may be rearranged to give the following relation-ship for a uniformly doped substrate
Vout =
j7c+c3
(vs-vs0)+vB (9)
2\C,+CS
+ C3
D ,
D1
\Qmax Qsig)
(C, + C.)
]_
4 x +CS
2 1
1/2
(10)
\Qmax Qsig)
(Ci + C.)SlgJ _ CSC3 1
+ C.) 2D
cx(yB-vFB (ID
In eqns. 9, 10 and 11, Cs is the series combination of C3
and C4 and Vs0 is the surface potential when qsig — 0.Typical results are shown in Figs. 7 and 8. It can be seen
that capacitive loading decreases the detection sensitivityand increases the available dynamic range. One defect ofdual-gate sensing is the extra chip area required by the extragate. For the curves continuing on to sensing-gate satu-
1
6
5
enO
?3
>- 2
outp
3 _
\j
-1
- 2
N
C,=1 C3-0
0-1 0-2 0-3 0-4 05 06
"sig "sig max
C
>->= 2
C
07
3 = 1
"~-
3=1 C
sC,=1
0 ^
,C
.= 2
^—
1
3=1
•
= 1 C 3
^ ^
C4 = 0
1-1
=1
1-2
= 1
1-3
1/
15
13
11
9
en5 70
"3
f30
01
~ 1
-2
^ ^ ^ ^
X C, = 2X . C3-I
C, =1 C3-O C4 = 0
0-1 0-2 0-3 0-4 0-5 0 6 0-7q . /q^sig ^sig max
3 = 1 C
— i, ,,
^ ^
C A = 1
c,=i
v- ^ ' C l = 1 C3
C3=1 C, = 0
-=1
*•»—
1-2 1-3
Fig. 7 Calculated variation of output voltage with signal chargefor dual-gate sensing as a function of capacitance ratios
VpB is taken as — 3 V in all casesa VB = 7 V; N& = 1021 m"3. C4 = 0 corresponds to an unloaded
floating-gate section, C4 = 2 corresponds to a capacitive load ofapproximately twice the individual electrode capacity. C, = 2corresponds to a biased electrode whose area is twice that of thesensing-gate section. C3 -»• 0; C« = 0 is the asymptotic limitcorresponding to constant voltage sensing and may be regardedas a reference characteristic
SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6
^s ig ' 'sig maxNA= 2 5x10'w "
Fig. 8 Effect of substrate doping on the sensing characteristic fora loaded (C4 = 1) and an unloaded fC4 = 0) sensing-gate section
209
ration at qsjg/qsig max > 1, the sensing-gate areas could bereduced relative to transfer-gate areas by this excesssaturation ratio if layout rules permitted. Fig. 8 shows thatsubstrate doping does not have a strong effect on thedetection sensitivity, dynamic range and linearity, but smallimprovements in performance occur for weaker substratedoping.
3 Analysis of sensitivity, saturation and linearity forfloating-gate sensing
The analysis is similar to that of Section 2 using the circuit,charges and voltages of Fig. 9. As before, C4 is assumedconstant. In this case the output voltage is reset to VB
before arrival of the charge to be sensed and qsigmax is
v . - q . 's2
Vout
Fig. 9 Charges and voltages on a floating-gate sensing circuit
taken as C3(VB — VFB). This will overestimate qSigmax bya factor of approximately 2 when the normal reset to VB/2is used for floating-gate operation. The following results areobtained:
* out ~ + C (vs-vs0)+vB (12)
s 2 l e i D
4 CC3\ 1 | 1 /C3\ 2 1
(13)
qmax qsig \ _
c.{[4D(VB-VFB)+l)1/2-\}
(VB - VFB)
Typical calculated behaviour is illustrated in Fig. 10. Forsmall capacitive loading the high sensitivity coupled withreduced dynamic range and poor linearity can be clearly
seen.
4 Measured sensing performance
We did not have the facility to make devices with the dual-gate sensing structure but it has been possible to use a32-lap 3-phase c.c.d. designed for floating-gate sensing to
(0
0 0 02 04 0 6 0 8 10 12 U 1-6 18 20 2 2\g max
Fig. 10 Calculated variation of output voltage with signal chargefor floating-gate sensing as a function of substrate doping andcapacitive loading
iii
iii
iii
iii
iii
iii
iii
iiiivV
vi
c3
"A"AciNA
NA
NA
c,NA
NANA
c\c4c4c4c4c.
= 1, C4 = 4= 4 X 1021
= 1O2'= 2-5 X 1 0 "
= 1, C4 = 2= 4 X 1021
= 1021
= 2-S X 1 0 "— 1, C4 1= 4 X 1021
= 1021
= 2-5 X 1 0 "
= 0-25, NA -= 0-25, NA == 0-1, NA == 0 - 2 5 , ^ == 0 1 ,NA == 0 1 .NA =
-4 X 1021
= 102 '4 X= 2-5- 102
= 2-5
1021
X 101
X 10
-5iO2 tp-Si
U^) Fig. 11 Floating-gate sensing structure of the available c.c.d.used in the experiments
210 SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6
practically evaluate dual-gate sensing. Each third electrodehad an on-chip, reset f.e.t. and buffer as illustrated inFig. 11. In order to transfer charge correctly and to senseit with the dual-gate technique it was necessary to use amodified clock sequence whose waveforms are illustratedin Fig. 12. Corresponding charge-transfer sequences are
A \
V z\. \t, t , t . t. t<M l2 l3 % l5 l6 time
Fig. 12 Modified clock waveforms to give dual-gate sensing
illustrated in Fig. 13. After charge has been transferredunder the second-phase (02) electrode the floating gate(03) electrode is reset to 03. which is typically half theclock-voltage amplitude using VRC to open the reset f.e.t.and VR to define the voltage. No charge is stored under 03
at this time. After opening-circuiting the reset f.e.t. the 02
clock voltage is then reduced so that charge equilibrateswith the same surface potential under 02 and 03. Duringthis time Vout is a measure of the charge stored under thedual 02/03 gate structure. This valid output was sampledand held for each clock cycle by off-chip circuitry. Afterthe sensing period, 03 is again reset to the full clock voltageand the 02 clock voltage falls to zero, so that all the chargeis contained under 03. Normal charge transfer follows withapplication of the full clock voltage to 0i and the clockvoltage on 03 is reduced to zero. This modified procedurefor assessing the feasibility of the technique does not allow
L,,Tzzz ^
Fig. 13 Successive stages of charge transfer in experiments withdual-gate sensing.
At time 14, the two surface potentials under 03 correspond tozero signal charge and to the signal charge indicated by shadingunder the normally clocked electrodes
the dynamic range of the signal charge to be as large as thatunder a normal transfer electrode but this defect would notbe present in a device designed for dual-gate sensing.
The substrate acceptor doping of the available deviceswas ~ 4 x 1021 m~3 which is higher than desired for thebest dual-gate sensing. However, encouraging results wereobtained, as shown in Fig. 14, for the relationship betweeninjected charge and output voltage. With the input voltageapplied to the first gate of the c.c.d., charge was injectedunder the second gate in a conventional fill-and-spilltechnique.1 This second gate had a full clock amplitude inthe normal 3-phase transfer sequence. The abrupt decreaseof output voltage for small input voltage occurs when theinput diode cannot carry out the fill process.
In Fig. 14 the input gate voltage is used as a linearmeasure of the signal charge to be sensed so that maximuminput-gate voltage corresponds to minimum signal charge,as is usual for a conventional fill-and-spill technique. Thethree sets of results in Fig. 14 illustrate the charge-sensingsensitivity and the dynamic range as a function of 02. and03. for a clock voltage amplitude of 18 V. The regions tothe extreme left and right of the curves where there is zerocharge input to the c.c.d. were used to identify the zerolevel of the output voltage. Dual-gate sensing is occurringin the substantially linear regions in the right-hand half ofFig. 14, where output voltage increases with decreasingsignal charge (increasing input voltage) as will be justifiedin the following comments. The maximum linear range of
input gate voltage0 1 2 3 U 5 6 7 8 9 10 11 12 13 K 15 16
3 0 1 3 U 5 6 7 8 9 10 11 12 13 K 15 16 17 18 19 20input gate voltage
Fig. 14 Dual-gate sensing characteristics
a <p2.= 5 Vb 02|. = 8 Vc 02'. = 12 V
SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6 211
output was obtained with 02. = 8 V and 03. = 7 V. When aflatband voltage of approximately — 3V to — 5V isallowed for
'FB 05)
which is to be expected if there is a linear relationshipbetween charge stored and surface potential. We expect02- and 03. to be equal for optimum performance so thatcharge equilibrium between the two electrodes can occurfor small-signal charges. The small differences between 02.and 03. for optimum performance (they are less than the1 V apparent in Fig. 14 when care is taken to obtain theoptimum characteristic rather than a representative rangeof characteristics) may be attributed to differences in theinsulator and electrode details of 02 and 03, caused bythem being laid down in different steps of the deviceprepaiation, or may be attributed to overlap of these twoelectrodes causing the setting of 02. to slightly modifythe previous setting of 03. owing to capacitive coupling.For a substantially linear relationship between surfacepotential and stored charge we expect eqn. 15 to be trueso that the maximum possible charge can be stored under02 while 03. is being set and the same charge can be storedunder 02 and 03 (but predominantly under 02) while theoutput voltage is valid after both 02. and 03. have been set.This 50% dynamic range limitation, which has similaritiesto that of 2^-phase operation,3 need not occur in a deviceconstructed for dual-gate sensing with a pair of electrodesin the 03 position for 3-phase clocking.
If 02. was larger than 03. there would be a zero offset ofundetected charge which was necessary to make the surfacepotential under 02 electrode equal to that corresponding to03l-. This effect can be seen in Fig. 14. The saturation in theoutput voltage for a given 03. occurs for an input signalwhich is substantially independent of 02. because saturationis determined by the input, whereas the zero of outputvoltage occurs for an input signal which depends nearlylinearly on 02. in the region of the characteristics wheredual-gate sensing is occurring, showing that small levels ofsignal charge are not sensed by the dual-gate process when02. is too large.
If 03; was larger than 02., small levels of signal chargewould only lie under 03 during sensing so that a purefloating-gate sensing would occur. This effect can be seen inthe nonlinear but more sensitive detection regions at theright-hand extreme of Figs. 14 when 02. < 03..
The flat characteristics occurring in Fig. 14 for 02. = 5 Vand 03. = 5 V, 6 V and 7 V arecausedby saturation effects atlow output voltages in the on-chip circuitry. The character-istics to the left of Fig. 14, where the output voltageapparently decreases with increasing signal charge(decreasing input voltage), do not have a full explanationbut appear to be related to minority charge trapping andrecombination when majority carriers are allowed toapproach the Si/SiO2 interface following saturation effectsand depletion-layer removal under the sensing electrode.Under these conditions the charge smearing in the c.c.d. isobserved to be far worse than in the case when signals areconfined to the linear, dual-gate, sensing region. Thisrequired the curves in Fig. 14 to be taken from the firsttapping point of the c.c.d.
The c.c.d. was designed for floating-gate charge sensingso, for comparison, the performance under these conditionsis illustrated in Fig. 15. The linearity was poor for the fill-
and-spill input as described above (see right-hand side ofFig. 14) so fill-and-spill input was performed into a float-ing gate (the second gate of the c.c.d. as above) which hadpreviously been set to half the clock voltage. Much-improved linearity was then obtained owing to matchingof the floating-gate characteristics at the input andoutput. Results in Fig. 15 were obtained under theseconditions. The output floating gates were also set tohalf the clock voltage before the sensing period so thatthe c.c.d. was operated under a 2?-phase clock sequence.1
The detection sensitivity obtained is about twice that ofdual-gate operation but the dynamic range is approxi-mately halved even though the optimum setting potentialsfor the sensing electrodes were the same for both dual-gateand floating-gate sensing.
3 4 5 6 7 8input gate voltage
Fig. 15 Floating-gate sensing characteristic
Or
o
E-20X)
j-30-
-40-
-50-
10
4 6input voltage amplitude
Fig. 16 2nd and 3rd harmonic distortion for dual-gate sensing
4>2i = 9-5 V; <p3. = 6-5 V and floating-gate sensing with 0 3 . = 10-8 V.The input sine wave is superimposed on a d.c. level to give sym-metrical clipping at saturationo 2nd harmonic floating gateA 3rd harmonic floating gate° 2nd harmonic dual gateV 3rd harmonic dual gate
212 SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6
5 Distortion measurements and analysis
In the apparently linear detection regions of Figs. 14 and15 it is not clear whether dual-gate sensing or floating-gatesensing is the most linear. Accordingly, experiments werecarried out to measure the harmonic distortion of a sinewave whose frequency was much lower than the samplingrate of the c.c.d. To minimise the effect of charge smearing,distortion measurements were taken on signals at the firsttap of the device, but saturation was defined most clearly bythe onset of obvious waveform clipping at the 32nd tap sothat any large-signal nonlinear smearing effects did notinfluence the results. Second and third harmonic distortionperformance as a function of signal amplitude normalisedto output signal saturation are shown in Fig. 16. In bothcases it can be seen that there is a 5 dB to 10 dB decrease ofharmonic distortion for dual-gate sensing when comparedwith floating-gate sensing.
In order to predict the harmonic generation we used
+ q! sin (16)
to generate the 2nd- and 3rd-harmonic expressions by smallsignal expansions of eqns. 9-11 for dual-gate sensing and ineqns. 12-14 for floating-gate sensing. The saturationcondition was theoretically defined by qi = Qsigmaxl^-For linear charge injection the harmonic distortion pre-dicted by eqn. 16 is significantly less for dual-gate sensing.In Figs. 7, 8 and 10 dual-gate sensing with Cx = C3 = C4 ismore sensitive than floating-gate sensing with C4 = 4C3.In Fig. 18 dual-gate sensing is also seen to cause lessdistortion than floating-gate sensing for the sameconditions. The particular capacitive values were chosen togive approximately the same capacitive loading relative tothe floating-gate in each case. In this theoretical comparisonthe floating-gate in each technique had the same resetvoltage which also corresponds to our experimentalconditions.
Predicted results shown in Fig. 17 compare well withthose measured, both in the magnitude of the distortion
and in its improvement with dual-gate sensing. The theor-etical improvement appears better than that obtainedexperimentally since we modified the fill-and-spill processto give better linearity in floating-gate sensing. When weused the same fill-and-spill process (into a constant voltagegate) for both sensing techniques the measured distortionfor floating-gate sensing was degraded by approximately15 dB. In our devices the loading capacity of the peripheralcircuits is estimated from area considerations to be betweenhalf and one times the sensing electrode capacity.
Predicted distortion performance over a wider range ofparameters is shown in Figs. 18 and 19.
6 Discussion of results
We have shown that dual-gate sensing is more linear thanfloating-gate charge sensing in c.c.d. even though it has thesame peripheral circuit simplicity. The dynamic range
Fig. 18 Predicted relationship between input and output at thefundamental, second harmonic and third harmonic for floating-gateand dual-gate sensing for NA = 2-5 X 10™ m'3 and NA~4X1021 m"3
Fig. 19 Dependence of predicted distortion on capacitive loadingfor dual-gate sensing. NA -4 X 10il m'3
SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6 213
limitations encountered in floating-gate operation are alsoremoved. Capacitive loading causes similar sensitivityreduction in both cases (less reduction in dual gate) but it isnot a necessary feature to provide good linearity for dual-gate sensing as it is in floating-gate sensing.2
The disadvantage of dual-gate sensing is the extraSi-device area that it requires for the extra electrode, eventhough this may not be important in devices with consider-able parallel-tap processing circuitry where small stagelengths in the c.c.d. may be difficult to interface.Also the improved saturation characteristics of dual-gatesensing will allow the electrode area to be reduced ifphotolithographic rules will allow this. The area reductionpossible is inversely proportional to the ratio qSigmax/Qmaxillustrated in Figs. 7 and 8. When compared with constant-voltage charge sensing the total electrode-area increase is anadvantage because it replaces the necessary on-chip charge-sensing amplifier.
The predicted performance is best for the lowestsubstrate doping which reduces the influence of the non-
linear depletion-layer capacitance. However, for peripheralsensing circuitry which causes a capacitive loading whichapproaches the sensing electrode capacity the influence ofdoping is not large. This feature should help to providepredictable sensing characteristics.
7 Acknowledgments
This work was supported by a UK Science ResearchCouncil Research Grant. The authors would like to thankD. McCaughan of RSRE, Malvern, for supplying devices.
8 References
1 HOBSON, G.S.: 'Charge-coupled devices', Proc. IEE, 1977, 124,(11R), pp. 925-945
2 MACLENNAN, D.J., MAVOR, J. and VANSTONE, G.F.:Technique for realising transversal filters using charge-coupleddevices', ibid., 1975, 122, (6), pp. 615-619
3 HOBSON, G.S.: 'Charge transfer devices' (to be published byEdward Arnold)
214 SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6
