Dual-Gate TFT for 3-DFlash Memory

Andrew Walker

Schiltron Corporation

December 4th 2009

Contents

• The Gathering Storm• The Inevitability of 3-D Flash• The Contenders for the Crown• Charge Trap Flash in 3-D• The Schiltron Solution Explained• Prototype Process Flow • Physical Results• Electrical Results• Conclusions• Acknowledgements

The Gathering Storm

Worldwide NAND Flash Memory Consumption by Major End Use Application

Source: In-Stat Report “Flash Applications Drive Strong Revenues Worldwide” Dec. 2008

The Gathering Storm

• NAND Flash market > $50B by 2014 • BUT…..• Classic NAND Flash within 2 years of brick wall

– 1 final technology node at sub-30nm half-pitch– Multi-bit per cell exhausted

• 3-D inevitable• IEDM Dec. 2009:

– First time with dedicated 3-D nonvolatile memory session– 3-D Charge-Trap-Flash-based in 4 out of 6 papers (ST,

Toshiba, Macronix, Kaist)– One 3-D PCM (Intel/Numonyx)– One NEMS mechanical memory (Kaist)

The Gathering Storm

• NAND Floating Gate Challenges– ONO does not scale– Tunnel oxide does not scale– Inter-cell interference

• Coupling Ratio collapses

Required floating gate height to suppress inter-polyparasitic coupling and the effect on the coupling ratio

Source: Y. Shin, Samsung, Symp. VLSI Circuits 2005

The Inevitability of 3-D Flash

• Lateral scaling:– A method that complicates a semiconductor process but

increases the number of good die per wafer– Cost increase due to process complexity more than offset by

cost decrease due to increased good die per wafer

• Monolithic 3-D Stacking:– Logical alternative to lateral scaling – Also increases process complexity but increases the number

of die per wafer

• What is the Real Cost Advantage of 3-D Stacking ?– Process complexity and cost increase– Yield may decrease– Number of die per wafer increases

The Inevitability of 3-D Flash

• Equation for cost of good 3-D die divided by cost of good 2-D die• Y – yields• NL – number of memory device layers• F – minimum half pitch• MLC – number of electrical bits per cell• Co – base wafer cost without memory processing• Ccrit_mask – cost of each critical memory masking layer and process• Ncrit_mask – number of critical masking layers• Z – rate of increase in wafer cost between generations• n – number of generations between 3-D and 2-D processes

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Source: A.J. Walker, IEEE Trans. Semi. Manuf. May 2009

The Inevitability of 3-D Flash

Source: A.J. Walker, IEEE Trans. Semi. Manuf. May 2009

The Inevitability of 3-D Flash

The Contenders for the Crown

• Resistance Change Approaches– Phase Change Memory (PCM) –

Intel/Numonyx– Simple Metal Oxide –

SanDisk/Toshiba ?– Perovskite - Unity ?– Solid-State Electrolytes - Axon

• At least 2 masking steps per device layer

• Probably 3

The Contenders for the Crown• Charge Trap Flash in Vertical Plane

– Vertical Recess Array Transistor (VRAT) - Samsung– Bit Cost Scalable (BiCS) - Toshiba

Source: Symp. VLSI Technology 2009

The Contenders for the Crown• Charge Trap Flash in Horizontal Plane

– TANOS - Samsung– TFT (BE)-SONOS - Macronix– Dual-Gate TFT SONOS - Schiltron

Source: Jung et al., IEDM 2006

Charge Trap Flash in 3-D

• Vread-pass > Vtprog (max) + margin• Vprog-pass > Vtprog (max) + margin

• Applies to both lateral and vertical NAND CTF

N+N+ N+N+

Vread

To Bit LineSource

ONO

Vread-pass Vread-pass

Inversion channel

Pass disturbs onselected string

Charge Trap Flash in 3-DFG scaling problems at

< 30nm

Nitride Storage

Need good worst-casestring current Read Pass Disturb

Thicken up tunnel oxide

Need high erase voltage

Thicken up blocking oxide(Al2O3)

Use high Work Function gate (TaN)

Need high program voltage

Program/pass disturb

Thicken up tunnel oxide

Optimization Circle

• Serious read pass and program pass disturbs remain• High program/erase voltages• MLC extremely challenging• Classic NAND blocks the advantages of classic SONOS

Charge Trap Flash in 3-D

Vread_pass (V)

Lifetime = time to shift erased Vtby 3V

Source: C.-H. Lee at al., Symp. VLSI Technology 2006

The Schiltron Solution Explained

• Vread-pass decoupled from Vtprog (max)• Vprog-pass decoupled from Vtprog (max)

N+N+ N+N+

Vread_pass

Vread

Vread_pass

To Bit Line

OFF

Inversion channel and depletion region providinggood shielding of memory charge from pass voltages

Source

DG structure with close electrostaticinteraction between top and bottom

devices providing good short channelcontrol

ONOSecond Gate

First Gate

Prototype Process Flow

• Test chip developed and laid out • Process architecture and recipes developed• Processed in Silicon Valley Technology Center (SVTC), San

Jose• First silicon functional• Smallest feature size < 50 nm

Prototype Process Flow

Silicon wafer

Nitride etch stopon oxide

HDP Oxide

Prototype Process Flow

Oxide trench etchand poly dep

Prototype Process Flow

PolySilicon CMP1(forms GATE1)

Prototype Process Flow

After polysilicon CMP1(forms GATE1)

Prototype Process Flow

X

Y

HDP oxide dep and channel trench etch

Prototype Process Flow

32 cell string after channel trench etch

Prototype Process Flow

X

Y

Gate1 oxide formationand channel a-Si dep

Prototype Process Flow

a-Si CMP2(forms active channels)

X

Y

Prototype Process Flow

Over 13 wafers: 16nm average oxide loss with 3sigma of 6nm

After CMP2

Prototype Process Flow

X

Y

ONO formation

Prototype Process Flow

X

Y

GATE2 deposition

Prototype Process Flow

X

Y

GATE2 litho & etch

Prototype Process Flow

64 cell string after 2nd gate formation

Prototype Process Flow

X

Y

Source/drain implantand low-temp anneal

Prototype Process Flow

XTEM perpendicular to wordline gate direction

CMP1 CMP2

Prototype Process Flow

XTEM perpendicular to channel direction

CMP1

CMP2

Physical Results

350 A channelthickness

48nm gatelength

45nm channel width “nanowire”

Physical Results

0 50 100 150 2001015

1016

1017

1018

1019

1020

Ant

imon

y C

once

ntra

tion

(/cm

3)

Depth (nm)

Electrical Results

500Shee

t Res

ista

nce

(Ohm

/sq)

Anneal Temperature (C)

550 600 650 700 750 800 8501000

1200

1400

1600

1800

2000

Anneal time = 1 min

Electrical Results

-210-12

10-11

10-10

10-9

10-8

10-7

10-6

-1 0 1 2 3 4 5

Sour

ce-D

rain

Cur

rent

(A)

First Gate Voltage (V)

Second Gate Voltage (V)

432

1

0-1

-4-3

-2

W/L = 50nm/65nmdch ~ 35nmVds = 0.5V

1st

2nd

Electrical Results

0

1

2

3

4

1 10 100 1000

Seco

nd G

ate

Thre

shol

d Vo

ltage

(V)

Duration of 9V Application to First Gate (s)

N+N+

Vpass =9V

Programmed memory cell

Electrical Results

MidcellGate voltage

OFF

OFFOFF

ON with read pass voltage ON with read pass voltage

Bit Line Source

64 cell cell string (W/L=45nm/48nm Devices)

Electrical Results

-1 0 1 2 3 4 510-10

10-9

10-8

10-7W

orst

-Cas

e St

ring

Cur

rent

(A)

Read-Pass Voltages (V)

64 cell stringW/L = 45nm/47nm

dch ~ 35nmVds = 1V

2

3

45678

Second Gate Voltage on Mid-Cell (V)

All memory devices offexcept mid-cell

Mid-cell first gate at -3V

Electrical Results64 cell string

W/L = 45nm/47nmdch ~ 35nm

Mid-cell first gate at -3V

All memory devicesoff except mid-cell

Mid-cell second gateat 3V

Wor

st-C

ase

Strin

g C

urre

nt (n

A)

String Source-Drain Voltage (V)0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

20406080

100120140160180200 Read-Pass Voltage (V)

3

4

5

6

7

8

Electrical ResultsW

orst

-Cas

e St

ring

Cur

rent

(nA

)

Read-Pass Voltage (V)

0

800

100

200

300

400

500

600

700

2 3 4 5 6 7 8

64 cell

32 cell

16 cell

8 cellW/L = 45nm/47nmdch ~ 35nmVds=1.1V

Mid-cell first gate at -3V

All memory devicesoff except mid-cell

Mid-cell second gate at 3V

Electrical ResultsTh

resh

old

Volta

ge (V

)

Number of Cycles

1

2

3

4

10 102 103 104 105

32 cell stringW/L = 45nm/47nm

dch ~ 35nmVprog/Verase = 17.5V 100us / -13V 400ms

Read-pass voltage = 7VProgram-pass voltage = 7V

Erase-pass voltage = 6V

Electrical ResultsTh

resh

old

Volta

ge (V

)

Time at 85C (s)

0

1

2

3

10 102 106 108

4

104

After 105 cycles10 years

Conclusions

• 3-D stackable and inherently scalable• Existing materials and methods

– No new materials or material breakthroughs required– Program/erase close to existing approaches

• Ideal for both stand-alone (NAND replacement) and embedded

• No pass disturbs– Shielding gets rid of the bane of all Charge Trap Flash

NAND• Concept shown on silicon at W and L < 50nm with 64

bit strings– IEDM Dec. 2008 – IEEE Trans. Semicon. Manufacturing May 2009 – 3D cost

model– IEEE Trans. Electron Devices Nov. 2009

Acknowledgements

• Professors Endoh and Nishi for the invitation to speak at this Workshop

• TJ Rodgers at Cypress Semiconductor and CJ Koomen for initial investment

• R. Rhoades at Entrepix for CMP expertise• L. Liang at Precision TEM • A. Chatila at MEMC for constant support• L. Marques for constant support