Pass Transistor Logic

1Dynamic CMOS Logic2Dynamic CircuitsDomino LogicDual-rail Domino LogicKeepersMultiple-output Domino Logic (MODL)NP Domino Logic

2133Logic function is implemented by the PDN onlyNo. of transistors is N+2 Smaller in area than static CMOSFull swing outputs (VOL = gnd and VOH = VDD)Non-ratioedFaster switching speedPower dissipation should be betterNeeds precharge clock.Dynamic CMOS Logic3134Dynamic CMOS Precharge-Evaluate LogicReduced Transistor Count=0 C precharges to VDD (output is not available during precharge) =1 C selectively discharges to 0 (output is only available after discharge is complete)VDDnMOSLogicinputsCVoutMeMpInternal capacitancettVoutprechargeprechargeevaluate5Dynamic CMOS Precharge-Evaluate LogicAn ExampleVDDVoutMeMpA1A2A3B1B2Vout is high when =0Vout = (A1 A2A3 +B1B2)6Dynamic CMOS Precharge-Evaluate LogicCascading ProblemEvaluate:Me1, Me2 ONMp1, Me2 OFFProblem: All stages must evaluate simultaneously one clock does not permit pipelining of stages.VDDnMOSLogicVout11st stage1Vout2VDD2ndVout1 does not switch fromttVouttVoutcorrect stateerroneous stateprechargeevaluate1 to 0 fast enoughinputsMe1Me2Mp1Mp27High Performance Dynamic CMOS CircuitsDomino CMOS LogicVDDnMOSLogicVoutVDDinputsXprechargeevaluate1tStatic inverter serves to buffer the logic part of the circuit from its output load=0 X precharges to VDD, and Vout = 0.=1X remains high, and Vout remains low.X discharges to 0, and Vout changes from 0 to 1.8Domino CMOS LogicVDDnMOSLogicinputsVDDnMOSLogicX1VDDnMOSLogicX2X3ttX1tprechargeevaluatetX2X3evaluatetevalMax number gates limited: total propagation delay < teval9Domino CMOS Logic (Cont.)The problem in cascading conventional dynamic CMOS occurs when one or more inputs make a 1 to 0 transition during evaluation.Domino circuits can fix the above problemDuring the evaluation, each buffer output can make at most one transition (from 0 to 1), and thus each input of all subsequent logic stages can also make at most one (0 to 1) transition.X3VDDnMOSLogicinputsVDDnMOSLogicX1VDDnMOSLogicX210Domino CMOS Logic The LimitationsThe static CMOS and domino gates can be used together. The limitation: the number of inverting static logic stages in cascade must be even, to let the inputs of next domino stage can have only 0 to 1 transitions during the evaluation.Can implement only non-inverting logic .Due to precharge use, can suffer from charge sharing during the evaluation which may cause erroneous outputs.The problem will be described in the next slide, and several solutions will be presented later.

11Domino CMOS Logic - Charge SharingAssume that all inputs are low initially, and the voltage across C2=0VDuring the precharge, C1 is charged to VDDIf transistor N switches from 0 to 1 during the evaluation phase, the charge initially stored in C1 will be shared by C2. Therefore, the value of VX will reduced. VDDVoutVDDVXC1C2VX = VDDC1/(C1+C2)Keep C2