This Application Note describes how to build a microcontroller with dynamic bus size for implementing complex statemachines and processing functions either as part of a system, or for use during development and test.
Xilinx Family
XC4000 and derivatives
Demonstrates
X-BLOX™ module generator
Using RAM and PROM
Table of ContentsFeatures ................................ ................................ ... 1
Using the PSM Design Files ................................ 10
FeaturesDynamic bus width — 1 to n bits
16 Data Registers
16 I/O Ports
Flexible instruction set
• Add and Subtract• Logical OR, AND, and XOR• Load, In, Out
• Jump group, shift and rotate sets
Program ROM — Dynamic depth from 16 to 256instructions
Typically >3 MIPS performance
Unique architecture for highly compact design inXC4000 device
OverviewMicrocontrollers are common in many digital systems.The relatively low cost of these complex devicesmakes them ideal for certain applications. The deci-sion to include a microcontroller in a design is oftenvery clear because it transforms the design effort froma logic design into more of a software design.
Xilinx FPGA devices offer similar flexibility for all theother logic functions required in such systems. Thesewould include special high performance circuits, or sig-nal conditioning for the microcontroller.
With the ever increasing size and reductions in cost ofFPGA devices, it is now possible to implement a com-plete system on one device. The microcontroller andassociated software can be replaced by a complexstate machine dedicated to the function. However,such state machines are often difficult to develop.Consequently, a microcontroller usually remains a dis-crete device, unless board space is at a premium.
A microcontroller is often used for diagnostics and testfunctions in a system. Small programs are easy towrite, and very flexible.
This application note offers an alternative to discretemicrocontrollers by providing a microcontroller macrofor an XC4000. This microcontroller macro may beused for board test and diagnostics, regardless of thefunction the device will perform after reprogramming. Itis also useful in systems where the control logic is toocomplex for hardware logic, but almost too simple forsoftware. Some applications requiring high securitysuch as data encryptors may also incorporate thismacro.
The macro, named 'PSM', is a programmable statemachine. The macro’s name conveys its potential use.Although full featured, the macro is limited by theamount of FPGA device that the designer is willing toconvert to program ROM.
A good efficient instruction set and the ability to avoidthe constraints of a fixed bus width make programs
Dynamic Microcontroller in an XC4000 FPGA
PRELIMINARY 2
compact. During diagnostics and test, the entire de-vice is available to the user for this function, and thesize of the program ROM is not an issue. In a systemapplication, the code complexity is the deciding factor.
Demand for a Compact Archite ctureWhen developing the PSM macro, silicon efficiencywas the primary focus. High performance circuits willalways be implemented as dedicated circuits. Hence,all design decisions for this macro favor optimizationsfor minimum area (low CLB count), with processingspeed a second priority.
The major design task was to define the functionality ofthe microcontroller. This is defined by:
The bus width
The instruction set
Each affects silicon efficiency in two ways—the size ofthe processing core, and the size of the program (andthe corresponding program ROM) to carry out the se-quence of operations.
The data bus determines the width of all data pathsand processing elements such as the ALU and dataregisters. However, a suitably wide data bus simplifiesthe program code. For example, the addition of two16-bit values is only one instruction in a 16-bit micro-processor, but is two instructions in an 8-bit version.Clearly this decision also effects the overall systemperformance.
The complexity and the range of available instructionsimpacts the amount of logic required for the data pathsand processing elements. Too small a range of in-structions—or the inability to manipulate data effec-tively—results in long programs, with poor systemperformance, that require large program ROMs. Suit-able instructions lead to efficient programs.
Consequently, the ability to choose the precise data
bus width required for a system, and the availability ofa highly efficient set of instructions result in a usablemicrocontroller macro.
Exploiting FPGA FeaturesThis microcontroller design exploits various XC4000FPGA features including:
Arithmetic carry logic — ALU Add and Subtractfunctions, program counter
ROM — Program memory
RAM — Data registers
These features, and the ultimate flexibility of an FPGA,offer some significant advantages.
Traditional microprocessors and microcontrollers holdtheir program code in standard EPROMs. This ap-proach results in variable length instructions and theadded complexity of op-code and operand fetch cycles.Furthermore, the data bus is a shared resource for themanipulation of program code and the processing ofdata.
The FPGA architecture permits the program code andthe data bus to be separated. This allows the data busto be a different width from that required for the in-struction codes. In fact, it permits the data bus to bethe width most suitable for the application. Further-more, the FPGA can implement any width of ROM toaccommodate the program instructions. Having aROM wider than the normal eight bits enables the in-struction and operands to be defined in a single accessfor compact and fast system performance.
Practical Aspects of ImplementationThe instruction set and its encoding provides the key tothe processor architecture. However, a few basic de-cisions must be made.
Constant ROM
Data RegistersInput Ports
ALU
Output Ports
Jump VectorROM
ProgramROM
ProgramCounter Control
Flags
Instruction BusAddress BusJump Bus
Dynamic Data Busses
Figure 1. Dynamic microcontroller architecture.
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X-BLOX™ provides a design entry method where thedata path bus widths can be changed, and for the cor-responding synthesized logic. X-BLOX is the preferredmethod for the design of this macro.
The XC4000 CLB RAM feature provides the ideal solu-tion for building the data registers in the microcontrol-ler. This makes the 16 registers extremely space effi-cient because a CLB contains two 16x1 RAMs.
Many processors include an accumulator in theirstructure. This has the advantage of implied instruc-tions, which remove the need for two operands per in-struction. Unfortunately it also results in a high per-centage of instructions which simply move values intoand out of the accumulator. It is important to keep theprogram code small in an FPGA, and hence all opera-tions directly access the registers.
Program code is efficient when all the bits of the en-coded instructions and operands are used. The abilityto express the instruction and all the operands in asingle access also leads to simple control circuits forthe processor. All instructions are limited to a singleaccess by making the program ROM the necessarywidth—knowing that there is a space advantage ofshallow-but-wide ROMs over deep-but-narrow ROMs inthe XC4000 FPGA.
Instructions and EncodingSome factors are already determined by the previouslystated architectural decisions. Others are defined bythe actual functionality. Four main instruction typesemerge for data processing, and one for program flowcontrol, considering the number of registers and theaccess required by each instruction. These instructiontypes are shown in Table 1.
In most cases, a resultant value needs to be stored.Although it is possible to specify a third location, theadditional operand information adds too much extralogic. Hence, the result will generally be placed backinto Register A.
With 16 registers to access, four bits of encoded in-struction are need to specify each register access. Atotal of eight bits are therefore dedicated to operandspecification in a Type 1 instruction.
Table 1. Function TypesType Function
Type 1 Function of Register A withRegister B
Type 2 Function of Register A with aconstant value
Type 3 Function of Register A with I/Oport access
Type 4 Data manipulation of Register AType 5 Program flow control and
flag testing
For Type 3 instructions, Register A is again specifiedby four bits. Another easy architectural decision is thenumber of I/O ports. Sixteen ports can be specified bythe same four bits used to access register B in a Type1 instruction.
The specified constant in Type 2 instructions is aproblem. Constants relate to the data processing, andhence are as wide as the data bus. Normally a fetchcycle is used to access the next memory location forthe bits required to define the constant. In this macro,where dynamic bus width is desirable, a fetch cyclewould place an upper limit on the bus width, and wastememory bits for smaller bus sizes.
The solution is to permit 16 pointers (defined by fourbits) to a ROM. This ROM holds up to 16 constants ofthe same width as the data bus. A program thereforeconsists of:
A main instruction memory of fixed width, and
A separate constant memory of data bus width.
All Type 1, 2 and 3 instruction operands are thereforedefined by only eight bits.
The actual operations need to be encoded. The bitsrequired to encode the operations are directly related tothe number of instructions. Too few instructions resultin long programs, and too many result in an overly-large processor.
A minimum instruction set provides the largest numberof functions with the least amount of instruction over-lap—e.g. comparison can be done with a subtract in-struction. This instruction set is organized into the fol-lowing instruction types:
Figure 2. Defining the address bus range on the PSM macro symbol.
This results in 17 basic instructions, although those ofType 4 and 5 require several variations. It would ap-pear that five bits are required to encode the full rangeof instructions. However the encoding of Type 4 and 5instructions can use some of the eight operand bitsfrom the other instruction types which allows just fourbits to encode the operation.
Type 4 instructions only require access to one register.The remaining four operand bits are available to definethe shift or rotate process required. Shift and rotateare then encoded by one instruction code reducing thebasic instruction count to 16. Instructions can now berepresented by a total of 12 bits.
The remaining challenge is to implement the Type 5instruction within the same 12 bits. The four bits of theoperation code already define this as a jump instruc-tion, leaving the eight operand bits.
It is possible to use eight bits to specify a relative jumpof -128 to +127. This is sufficient for small programs,but would not leave any bits to encode the condition forthe jump. Reducing the number of bits allocated torelative addressing would be very limiting. Absoluteaddressing presents the same problem as defining aconstant did for Type 3 instructions. However the samesolution is applicable, and hence four bits are used asa pointer to a small memory containing up to 16 jumpvectors. The jump memory need only be wide enoughto support the size of the program.
The testing of flags defines the remaining four bits on aType 5 instruction. ZERO and CARRY flags providesuitable flow control to the user.
The actual encoding of all instructions keeps the logicto a minimum. Controlling the data flow and process-ing directly with the status of bits reduces size and in-creases performance. The complete instruction encod-ing follows.
Type 1 and 2 instructions — Arithmetic and LoadFunctions1 1 CODEOp_code | 1 0 9 8 | 7 6 5 4 | 3 2 1 0 |------- ------------------------------------ADD sx,sy 1 1 0 1 x x x x y y y ySUB sx,sy 1 1 0 0 x x x x y y y yOR sx,sy 1 0 0 0 x x x x y y y yAND sx,sy 1 0 0 1 x x x x y y y yXOR sx,sy 1 0 1 0 x x x x y y y yLD sx,sy 1 0 1 1 x x x x y y y yADD sx,c 0 1 0 1 x x x x c c c cSUB sx,c 0 1 0 0 x x x x c c c cOR sx,c 0 0 0 0 x x x x c c c cAND sx,c 0 0 0 1 x x x x c c c cXOR sx,c 0 0 1 0 x x x x c c c cLD sx,c 0 0 1 1 x x x x c c c c | | | | | | | | Select operation | | | | ---------------- | | | |__ 1 - Add | | | | 0 - Subtract | | | |__ 0 0 - OR | | |____}-----------> 0 1 - AND | | 1 0 - XOR | | 1 1 - LOAD | | | |______ 0 - Logical or load operation | 1 - Arithmetic operation | |________ 0 - 'sx' and constant 1 - 'sx' and 'sy'
Notes:
‘c' is a 4 bit pointer (cccc) to a constant table.
'sx' is any one of 16 registers represented by 4 bits(xxxx).
'sy' is any one of 16 registers represented by 4 bits(yyyy).
The result of operation is placed into 'sx'.
All commands effect ZERO and CARRY flags ex-cept LOAD.
ADD and SUB commands will include the value ofthe carry flag in the calculation.
Type 3 Instructions — Ports1 1 CODEOp_code | 1 0 9 8 | 7 6 5 4 | 3 2 1 0 |------- ------------------------------------IN sx,p 1 1 1 0 x x x x p p p pOUT sx,p 1 1 1 1 x x x x p p p p
Notes:
'sx' is any one of 16 registers represented by 4 bits(xxxx).
'p' is a 4 bit port address (pppp).
flags : no effect.
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Type 4 Instructions — Shift and Rotate group1 1 CODEOp_code | 1 0 9 8 | 7 6 5 4 | 3 2 1 0 |------- ------------------------------------SR0 sx 0 1 1 0 x x x x 1 1 1 0SR1 sx 0 1 1 0 x x x x 1 1 1 1SRX sx 0 1 1 0 x x x x 1 0 1 XSRA sx 0 1 1 0 x x x x 1 0 0 XRR sx 0 1 1 0 x x x x 1 1 0 XSL0 sx 0 1 1 0 x x x x 0 1 1 0SL1 sx 0 1 1 0 x x x x 0 1 1 1SLX sx 0 1 1 0 x x x x 0 1 0 XSLA sx 0 1 1 0 x x x x 0 0 0 XRL sx 0 1 1 0 x x x x 0 0 1 X | | | | direction 0 - left ___| | | | 1 - right | | | | | | select bit to move in | | | | | | 0 0 - carry flag | | | 0 1 - msb _____| | | 1 0 - LSB _______| | 1 1 - Forced value | | Forced value of bit to shift in_______|
Notes :
'sx' is any one of 16 registers represented by 4 bits(xxxx).
ZERO and CARRY flags may be effected.Functions:
• SR0 — shift right zero, forcing 0 into MSB, carrytakes value from LSB.
• SR1 — shift right one, forcing 1 into MSB, carrytakes value from LSB.
• SRX — shift right extended, MSB copied intoMSB, carry takes value from LSB.
• SRA — shift right arithmetic, carry moved intoMSB, carry takes value from LSB.
• RR — rotate right, LSB moved into MSB, carrytakes value from LSB.
• SL0 — shift left zero, forcing 0 into LSB, carrytakes value from MSB.
• SL1 — shift left one, forcing 1 into LSB, carrytakes value from MSB.
• SLX — shift left extended, LSB copied into LSB,carry takes value from MSB.
• SLA — shift left arithmetic, carry moved intoLSB, carry takes value from MSB.
• RL — rotate left, MSB moved into LSB, carrytakes value from MSB.
JP j 0 1 1 1 0 X 0 X j j j jJP Z,j 0 1 1 1 0 X 1 1 j j j jJP C,j 0 1 1 1 1 1 0 X j j j jJP NZ,j 0 1 1 1 0 X 1 0 j j j jJP NC,j 0 1 1 1 1 0 0 X j j j jJP GT,j 0 1 1 1 1 0 1 0 j j j jJP LT,j 0 1 1 1 1 0 1 1 j j j j | | | | | | | |_zero flag status | | |_look at zero flag | |_carry flag status |_look at carry flag
Notes:
'j' is a 4 bit pointer (jjjj) to a jump vector table.
Conditional jumps -
• Z — Jump if ZERO flag set
• NZ — Jump if NOT ZERO
• C — Jump if CARRY flag set
• NC — Jump if NO CARRY
• GT — Jump if GREATER THAN
• LT — Jump if LESS THAN
• GT and LT apply after a 'SUB sx, ? ' such thatthe test is applied to 'sx'. i.e. sx < ?
flags : no effect.
Programming ExampleThe following is an example of a program written tomultiply two 4-bit numbers and provide an 8-bit result.Based on the resulting 8-bit product, it is more efficientto implement an 8-bit data bus. The schematic designfor this function is shown in Figure 6 on page 12. Thedesign is intended for the XC4000 demonstration board(containing a single 84-pin PLCC socket for anXC4003PC84C or XC4005PC84C device).
;;Program for 4 bit Multiply on Demo Board;START: LD s3,04 ;4 bits to multiply
LOOP: SR0 s0 ;test bit of low nibbleJP NC,NO_ADD ;bit was zeroOR s1,s1 ;clear carry flagADD s2,s1 ;accumulate result
NO_ADD: SRA s2 ;shift resultSUB s3,01 ;JP NZ,LOOP ;test if all 4 bits usedOUT s2,1 ;display outputJP START ;repeat
Figure 3. Multiply program written in PSMBLE.
The macro connects to the rest of the circuit in such away that port connections define the data bus width tobe synthesized by X-BLOX. The program address
Dynamic Microcontroller in an XC4000 FPGA
PRELIMINARY 6
range must be set by attaching a BUS_DEF symbol tothe PROG_ADDR_RANGE bus input on the macro andadjusting the 'BOUNDS=' parameter on the BUS_DEFsymbol as shown in Figure 2. This parameter may beadjusted later if the program turns out to be smaller orlarger than expected.
The design is then processed using the XACT™ 5.0FPGA development system. The results is three ROMtemplate files for the user’s program code.
PROGRAM.MEM contains the main instructions.
CONSTANT.MEM defines any data constants re-quired.
JUMP.MEM contains the vectors for any jump in-structions.
The names of these files may be changed by re-defining the ‘FILE=‘ attribute on the X-BLOX PROMsymbols within the macro. The internal details of thePSM macro, including the X-BLOX data paths andROMs, are shown in Figure 7 and Figure 8.
An assembler, called 'PSMBLE', is written in QBASICand is included with the demonstration designs (seePSMBLE Assembler for PSM for details on using it).The program generates the required three data filesfrom assembly code, simplifying the task of creatingthe constant pointers and jump vectors.
When the MEM files are ready, the XACT tools areused again to process the design including the ROMdata definitions.
Size and PerformanceBoth size and performance of a dynamic macro aredifficult to evaluate, but here are some guidelines.
The control logic is very simple because of the instruc-
tion encoding. In fact only about ten CLBs carry outthe instruction decoding and implement the controlstate machine. Although the absolute performancedepends on the maximum clock frequency, the statemachine dictates the number of clock cycles (t-states)required to perform each instruction:
All instructions excluding JUMP group require sixcycles.
JUMP group (condition true or false) require onecycle.
The size of the program counter and JUMP ROM de-pend on the size of the program in the PROGRAMROM. However, at one CLB per address bit, no morethan eight CLBs are ever used for these combinedelements.
The instruction format minimizes the size of programs,and hence the size of the PROGRAM ROM. The ROMhas a fixed width of 12 bits, but the depth is defined bythe PROG_ADDR_RANGE on the PSM macro.
The ROMs are built from function generators in theXC4000 CLBs. Fundamentally, 16 or 32 addressablelocations are available. Larger memories are formedby combining CLBs. When the PSM macro is only aportion of the overall design, the user will want to keepthe program relatively short in order to minimize thenumber of CLBs used for program storage. However,when the whole device is turned into a microcontrollerfor test purposes, then all CLBs are available to holdmuch longer and possibly less efficient programs.
The values shown in Table 2 indicate the number ofCLBs required for programs of a given depth.
It is possible to adjust the DEPTH value in thePROGRAM.MEM file to further minimize the number ofCLBs. For example, if only 135 program instructionsare required, then setting DEPTH=135 reduces the
Figure 4. Compiler report from PSMBLE showing jump vector and constant pointer assignments.
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number of CLBs from 126 to only 73 CLBs—eventhough address bus is still 7:0.
The dynamic data paths have the largest effect on sizeand performance. The design maps very well into thearchitecture using no more than five CLBs per bit, in-cluding the constant ROM and the RAM based regis-ters.
Table 2. Design Size as a Function ofAddress Range.
ProgramSize
ProgramAddressRange
CLB count
16 3:0 632 4:0 1264 5:0 30128 6:0 60256 7:0 126
Performance of this macro was a secondary consid-eration. The primary focus was on minimum CLBcount. However, preliminary results indicate that thecombined effect of instruction encoding, pipelined de-sign, and X-BLOX implementation produces two tothree times the performance of a typical 8-bit microcon-troller.
The macro operates at up to 23 MHz in an XC4000-5device. In most designs, however, the clock frequencyis much lower. Under typical test applications, per-formance is usually of little consideration. In theseapplications, the macro can be clocked with the internal8 MHz (nominal) clock source.
PSMBLE Assembler for PSMThis section describes the PSMBLE assembler for thePSM macro described earlier.
PSMBLE.BAS is written for QBASIC on the PC, and issupplied in original uncompiled format to allow modifi-cations by the user. This provides a way to comple-ment any changes made to the standard PSM macro.
Though careful effort makes this program easy to use,it has not received any official quality testing. Pleasehelp to improve this program by reporting any problemsencountered.
What does it do?
The program can be executed from within QBASIC, orby invoking QBASIC with
qbasic /run psmble
Syntax table------------
[ ] means optional[ ... ] means option may be repeated{ a | b } means that one of the enclosed must be specified[a-z] means in the range specified.::= means 'is defined by'.
jump = JP [ { C | NC | Z | NZ | GT | LT } , ] label
second_op = { reg_spec | constant }
constant = hex_char [ hex_char... ]
hex_char = { [0-9] | [A-F] }
comment = [ any characters ]
Figure 5. Syntax table.
Dynamic Microcontroller in an XC4000 FPGA
PRELIMINARY 8
The program asks for the name of your assembly codefile, and then processes it.
It takes only a few seconds to carry out the single passprocess, followed by another few seconds resolving thejump addresses.
PSM requires that constants and jump addresses beseparated from the main program code. It also en-sures that no more than a maximum of 16 differentconstants or jump vectors are specified.
The program produces three files called:
program.dat
constant.dat
jump.dat
These files contain the data needed for the correspond-ing MEM files used by X-BLOX in the macro sche-matic. It is a simple task to paste this data into eachMEM file following the word 'DATA', and recompile thedesign.
Helpful Files
During the assembly process, PSMBLE creates sev-eral files to aid program development, debugging andverification:
compile.log
A complete listing of the compiled program with ad-dress and instruction codes. This file is a completereconstruction of the original file, and consequently canbe used to verify the assembly process.
constant.tab
Lists all the constants specified in the program againstthe pointer value (0 to F hex) to which they have beenassigned.
jump.tab
Lists all the labels used in JUMP instructions againstthe vector number (0 to F hex) to which they havebeen assigned.
label.tab
Lists every label specified and its address. The pro-gram has a limit of 100 labels, but only 16 can actuallybe referenced in jump instructions.
jumpaddr.tab
Lists how the jump vectors and labels are resolved toform addresses used in the jump.mem file.
format.prg
This file is a formatted copy of the original program andmay be adopted as a replacement for the originalsource file. It also acts as a verification of howPSMBLE interpreted the assembly program.
How to Write a Program for PSMAll the instructions are described in detail earlier in theapplication note. Complete syntax tables are providedin Figure 5.
List of Instructions
In this list of all instructions, '2B7' is used as a con-stant, 'ken' is used as a label, and '5' is used as a portnumber.Arithmetic Shift and Rotate ---------- ----------------
ADD s1,s2 SR0 s1 ADD s1,2B7 SR1 s1 SUB s1,s2 SRX s1 SUB s1,2B7 SRA s1 RR s1 Logical SL0 s1 ------- SL1 s1 SLX s1 OR s1,s2 SLA s1 OR s1,2B7 RL s1 AND s1,s2 AND s1,2B7 Jump XOR s1,s2 ---- XOR s1,2B7 LD s1,s2 JP ken LD s1,2B7 JP Z,ken JP C,ken Port JP NZ,ken ---- JP NC,ken JP GT,ken IN s1,5 JP LT,ken OUT s1,5
Case sensitivity
Upper and lower cases are accepted. The assemblerconverts all characters to upper case.
Tabs and Spaces
Tabs and spaces can be used freely to format the pro-gram. They are removed during processing.
Constants
Constants are interpreted in hexadecimal only, andhence only characters 0-9 and A-F are valid. Thedesigner must ensure that the data bus width settingfor the PSM macro is large enough to support theconstants specified in the assembly program.
Registers
The use of a register in an instruction is indicated bythe letter 's' before the single hexadecimal character 0to F representing which of the 16 registers is to beused. Most instructions expect the first operand to be aregister, but the second operand is assumed to be aconstant if 's' is not used.
Labels
Labels can use any alpha-numeric combination.Spaces are removed, but the underscore ('_') charactercan be used as a separator. There is no fundamental
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limit to the length of labels, but labels longer than 15characters make the compile.log file untidy.
Jumps
Jumps must be performed using labels. For each labelused in a jump instruction, a corresponding label mustappear in the program.
Comments
Any characters specified after a semicolon (';') until theend of the line are assumed to be a comment and areignored. Comments are retained in the compile.logfile. Any character can be used in a comment, butcontrol characters inserted by some text editors maygive unexpected results.
Interesting Ideas and ExamplesFollowing are a few ideas that may help in the use ofPSM and this assembler. If you have any more ideas,please send them in.
Labels do not have to be on the same line as aninstruction
As seen in the earlier example, labels do not have tobe on the same line as an instruction. By placing themon a line with a comment introducing a procedure, pro-grams become very readable.
Example:mult_by_8 : ;multiply the value in S3 by 8 SL0 s3 SL0 s3 SL0 s3
which seems to make much more sense thanmult_by_8 : SL0 s3 ;multiply the value in S3 by 8 SL0 s3 ;using a shift to multiply by 2 SL0 s3 ;three times.
Avoid multiple labels at one address
Multiple labels can be defined to a single address loca-tion. Although PSMBLE can process them, referencingdifferent labels in jump instructions causes unneces-sary jump pointers to be assigned. A review of thejumpaddr.tab indicates duplicate addresses.
Take care of Carry flag
ADD, SUB, SRA and SLA all use the carry flag duringdata processing. If you do not wish the carry flag tohave an effect, there are several options:
1. Shift instructions are very flexible, and where pos-sible, you should force a '1' or '0' into the registerinstead of the carry flag. For example, use 'SL0s4' instead of 'SLA s4' if you definitely want toforce a zero into the LSB.
2. Perform any logical function (AND, OR, XOR) be-fore the carry flag operation. All logical functionshave the effect of clearing the carry flag; hence by
ordering instructions carefully, the desired effect isachieved without wasting instructions.
3. The carry flag can be cleared by using a logical ORof any register with itself. This step preserves data,but may also affects the zero flag, which may ormay not be useful. For example, 'OR s4,s4'clears the carry flag.
Obtaining more constants
If your program uses more than 16 constants, there areseveral tricks to obtain more.
First, avoid using zero, ‘0’, as a constant by clearingany register with the XOR instruction. For example, toeffectively load register s2 with zero, execute:
XOR s2,s2
It may also be possible to form the constant you needfrom those you already have and hold it in an unusedregister. Look at various kinds of instructions to makethe value required. The following are some examplesof values created from the constants 3 and 5:
Assume
LD s3,3LD s5,5
then the following operations creates these new values
Finally, use any unused input ports to read an externalROM containing further constants the same way as theinternal constant ROM.
PSM does not support a CALL and RETURN sy s-tem
A manual approach to call and returns functions ispossible, but it adds instructions to a program. Decidewhether duplicating the subroutine in straight code issmaller than the effect of making the subroutine call.
The suggested method only requires four instructionsper call, but also uses up some jump vectors. Re-member, the PSM only permits 16 jump vectors in to-tal.
The concept is to load a register before making the'call' such that the return can be made logically.Sometimes unique data passed to the sub-routine canalso be used to indicate the point of return.
Dynamic Microcontroller in an XC4000 FPGA
PRELIMINARY 10
Example:call_from_A: LD sF, 01 ;return flag
JP sub_routinereturn_to_A: ;continue the program
call_from_B: LD sF, 02 ;return flagJP sub_routinereturn_to_B: ;continue the program
call_from_C: LD sF, 03 ;return flagJP sub_routine
return_to_C: ;continue the programsub_routine: ;instructions to perform sub routine
SUB SF,01JP Z, return_to_ASUB SF,01JP Z, return_to_BJP Z, return_to_C
External hardware interacting with PSM
PSM is an imbedded micro-controller, and all the sig-nals are available to be connected to other logic. Thismeans that other 'external' processes can be triggeredby the PSM instructions without actually using 'IN' and'OUT' instructions.
Example:
A program is assembled and a particular process isonly activated by a jump to address 34. Clearly, thisaddress will then appear on the 'CURRENT_ADDR'bus. Other hardware can be controlled to operate orstop by decoding Address 34 on ‘CURRENT_ADDR’.This technique reduces the number of instructions re-quired and improves performance.
ConclusionsThis application note introduces a novel microproces-sor macro which can be used in two obvious ways:
As an imbedded processor in a complex design.
To convert an FPGA into a microcontroller duringproduction test or field diagnostics.
This application note also demonstrates ways to exploitthe architectural features of an XC4000 FPGA. X-BLOX synthesis provides a logical schematic and asimple method of accessing the density and perform-ance of the device.
Finally, Xilinx FPGAs offer total flexibility. This macromay provide a basis for your own custom processordesign. The instructions can be adapted to meet yourunique system requirements.
Using the PSM Design FilesThis design is available on the Programmable LogicBreakthrough ‘95 CD-ROM. This section describeswhat software is required to run the design and thesteps involved. Also, please read through the Limita-tions and Restrictions section.
Software Requirements
The following software is required to process this de-sign:
VIEWdraw or VIEWdraw-LCA schematic editor.This software is required in order to make modifica-tions to the schematics.
Xilinx XACT 5.0 FPGA development system, includ-ing the PPR place and route program and the X-BLOX module generator.
The QBASIC BASIC interpreter, available with MS-DOS, is required to run the PSMBLE assembler.
Using the Design on Your System
1. Create a new directory called PSM on your harddisk.
2. Copy the files and sub-directories from the/MISCAPPS/MICROCNT/DESIGNS directory onthe Programmable Logic Breakthrough ‘95 CD-ROM into your PSM directory.
3. Edit the VIEWDRAW.INI file. Make sure that theVIEWlogic® design library pointers are set appro-priately for your machine. You will find the librarypointers near the end of the file.
Limitations and Restrictions
WARNING: THIS IS AN UNTESTED DESIGN.
Xilinx, Inc. does not make any representation or war-ranty regarding this design or any item based on thisdesign. Xilinx disclaims all express and implied war-ranties, including but not limited to the implied fitness ofthis design for a particular purpose and freedom frominfringement. Without limiting the generality of theforegoing, Xilinx does not make any warranty of anykind that any item developed based on this design, orany portion of it, will not infringe any copyright, patent,trade secret or other intellectual property right of anyperson or entity in any country. It is the responsibilityof the user to seek licenses for such intellectual prop-erty rights were applicable. Xilinx shall not be liable forany damages arising out of or in connection with theuse of the design including liability for lost profit, busi-ness interruption, or any other damages whatsoever.
Design Support and Feedback
This application note may undergo future revisions andadditions. If you would like to be updated with newversions of this application note, or if you have ques-tions, comments, or suggestions please send an E-mailto
or a FAX addressed to "PSM Application Note Devel-opers" sent to
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IMPORTANT: Please be sure to include which ver-sion of the application note you are using. The versionnumber is in the lower right-hand corner of page 1.
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Figure 6. Four-bit multiplier design using PSM macro.
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Figure 7. The internal details of the PSM macro. Many portions of the design use X-BLOX.
Dynamic Microcontroller in an XC4000 FPGA
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Figure 8. More internal details of the PSM macro. Many portions of the design use X-BLOX.
