Dynamic Voltage (IR) Drop Analysis and Design Closure: Issues andChallenges

Nithin S K, Gowrysankar Shanmugam, Sreeram ChandrasekarTexas Instruments India

E-mail: {nithin,gowrysankar,sreeram}@ti.com

Abstract—Dynamic voltage (IR) drop, unlike the staticvoltage drop depends on the switching activity of the de-sign, and hence it is vector dependent. In this paper wehave highlighted the pitfalls in the common design closuremethodology that addresses static IR drop well, but of-ten fails to bound the impact of dynamic voltage dropsrobustly. Factors that can affect the accuracy of dynamicIR analysis and the related metrics for design closure arediscussed. A structured approach to planning the powerdistribution and grid for power managed designs is thenpresented, with an emphasis to cover realistic applicationscenarios, and how it can be done early in the design cy-cle. Care-about and solutions to avoid and fix the Dynamicvoltage drop issues are also presented. Results are from in-dustrial designs in 45nm process are presented related tothe said topics.

Keywords—Dynamic voltage Drop, DvD, Dynamic IR,Peak power, Power switch, VCD, Power gate, SDF.

I. Introduction

Designing an optimal power grid which is robust acrossmultiple operating scenarios of a chip continues to be a ma-jor challenge.[1][2][3] The problem has magnified with tech-nology shrinking allowing more performance to be packedin a smaller area, from one node to another [4]. The powerdistribution on a chip needs to ensure circuit robustnesscatering to not only to the average power / current re-quirements, but also needs to ensure timing or reliability isnot affected due to Dynamic IR drop, caused by localizedpower demand and switching patterns. [5]

Further, amongst today’s devices power managementtechniques like power gating and switch power supplies arethe norms [6][7][8]. In the case of switched power sup-plies, typically, power switch cells are uniformly distributedacross the standard cell logic (logic gates) area of the floor-plan. There may be further sub-divisions in the switchedpower grid in the form of power domains, depending on thegranularity of power gating [10]. These power switches addan additional dimension to the power distribution problemas they often limit the response of the power grid to dy-namic power or current needs. While the power distribu-tion robustness can be improved easily by increasing thenumber of power switches, it has an impact on the off-mode leakage (Iddq) and hence battery life in handheldapplications. So clearly, the requirement is also to mini-mize the number of switches used as well as minimize thesignal routing resources utilized on the power grid.

This paper discusses the issues related to design closure

and signoff (timing, IR Drop, EM, reliability etc.) com-prehending Dynamic IR drop effects realistically. On onehand, the factors that introduce pessimism in Dynamicvoltage drop analysis have to be removed, while on theother we must ensure the methodology ensures robust cov-erage of various silicon conditions and design operatingscenarios. We then discuss power distribution and powergrid planning methodology, and highlight the various as-pects that need to be taken care of, from the early stagesof design implementation. We also demonstrate some ofthe systematic power grid enhancements like robust au-tomated switch placement and switched supply resistanceminimization through DRC-aware power metal fill. Allthe discussions and results are based on production im-plementations of low power application processors for mo-bile and hand-held devices. The designs include high fre-quency CPU cores, multimedia subsystems (like imagingand video). The numbers quoted are from the analysisand/or simulation.

The structure of the paper is as follows. In section II ,the commonly followed Dynamic IR methodology and itspitfalls are highlighted with design results. In section IIIthe issues related to analysis accuracy and signoff method-ology are discussed. Section IV then elaborates how wewent about planning the power distribution and the tech-niques used to ensure silicon robustness in the tolerant toDynamic IR drop.

II. Common Design Closure Methodology and ItsPitfalls

A. Overview Of Static Vs Dynamic IR Drop

Static IR drop is average voltage drop for the de-sign.[12][13], whereas Dynamic IR drop depends on theswitching activity of the logic[11], hence is vector depen-dent. Dynamic IR drop depends on the switching time ofthe logic, and is less dependent on the a clock period. Thisnature is illustrated in Fig 1. The Average current dependstotally on the time period, where as the dynamic IR dropdepends on the instantanious current which is higher whilethe cell is switching.

Static IR drop was good for signoff analysis in oldertechnology nodes where sufficient natural decoupling ca-pacitance from the power network and non-switching logicwere available. Where as Dynamic IR drop Evaluates theIR drop caused when large amounts of circuitry switch si-multaneously, causing peak current demand[1][14]. Thiscurrent demand could be highly localized and could bebrief within a single clock cycle (a few hundred ps), and

Fig. 1. Average Current Over A Window

could result in an IR drop that causes additional setup orhold-time violations. Typically, high IR drop impact onclock networks causes hold-time violations, while IR dropon data path signal nets causes setup-time violations.

B. Deficiencies Found By Dynamic Analysis On A“Good” Power Grid

A typical power grid and power switches (count and dis-tribution) are designed for average power or in other wordsthey are designed to meet static IR drop targets and notfor Dynamic IR drop. In the initial stage of the design,the grid robustness is checked only with the Static IR dropresult. This is because of late availability of use case scenar-ios (Voltage change dump (VCD) files). For the example,the switch and metal grid densities in the notches regioncan satisfy the static IR drop criteria, because the averagepower density in this region is not significant.

But when a particular application is run, notch areacould have higher power density because of localizedswitching in that area and the switches combined withmetal grid (Switched supply is distributed to cells by lowerlayers like MET2 and MET3) may not be enough to sup-port the current density in the notch area. Because ofwhich there can be very high dynamic IR drop. Refer toNotch area as shown in Fig. 2, Here due to less number ofswitch cells combined with not so robust power grid is themain cause of high dynamic IR drop. As described by thefigure, Switch Voltage drop and MET3 voltage drop arethe dominant factors in the overall voltage drop. A similaranalogy on the power density can be extended to largerregion.

Refer to Fig. 3, With the original MET3 grid, static IRdrops was within the budget. However, to meet the dy-namic IR drop goals, an increase of the MET3 (MET3 Gridis Vertical) grid density by 3 times, was needed. The dropacross the MET3 and related vias reduced by 50%, afterthe improvement. This is another example of a robustnessissue which was missed in static analysis.

As discussed earlier, the number of power switches is cal-

Fig. 2. Effect Of Low Switch Density In Notch

Fig. 3. Effect Of MET3 Grid On Dyanmic IR drop

Fig. 4. Closer View Of Dynamic IR Drop

culated based on the static IR drop requirement. For ourdesign, with the switch density that is calculated as peraverage power, and with “calculated” optimal cell densityand optimal decap density, our expectation is to have a

good dynamic voltage drop. Static IR drop and vectorlessdynamic results runs were within the budgets. Vectorlessdynamic IR drop was 70mV, but vector based dynamic IRdrop was 153 mV, which is beyond the budget. The maincause for such high voltage drop was localized switching.The high dynamic IR drop region has very high power den-sity and hence this region has high current requirement,which is not fulfilled by the existing power switch densityin that region, and as a result there is high Dynamic voltagedrop. The High IR drop region has reasonably good decapdensity and has low utilization as shown in the Fig. 4. Thisindicates that the affected region is not really a case of apoorly designed power grid, but more of an exceptionallyhigh power density, due to the design architecture com-bined with the placement of cells. In any case, the powergrid has to eventually be able to support the design’s powerdemands in that region, which requires a different approachas will be discussed later.

III. Accuracy Of Analysis

A. Comprehending Delays In Gate Simulation

There are several factors that affect the accuracy of thedynamic IR analysis, and how closely it represents the na-ture of actual Silicon behavior. One of the key requisites isto generate a realistic VCD (a file format that captures theswitching information) which accounts for the real cell andinterconnect delays (typically done by annotating an SDFin the gate simulation). Such a simulation captures the re-alistic spread of switching activity in the design. The othercommon approach is to use a VCD from a zero-delay simu-lation, along with the timing windows from STA analysis,which often results in non-realistic Dynamic IR drop thatcan be pessimistic or optimistic. Refer to Fig. 5 (SDF An-notated VCD) and Fig. 6 (Without SDF annotated VCD).

It shows a drop close to 175 mV with a VCD generatedwith SDF, versus Vs 141 mV from analysis using a VCDwithout SDF annotation. In this case, 175mV is the morerealistic result for the given application. Also, the analysisneeds to be done for more than 1 cycle because this wouldexpose more weak spots and allow sufficient pre-simulationtime for the decap effects to be comprehended more accu-rately.

B. Comprehending Realistic Glitch Propagation

Glitches arising out of combinational logic switching cancause a large amount of instantaneous switching. It is im-portant to factor the effect of such switching, with con-sideration to which of these glitches would die down orpropagate, considering cell and interconnect delays underrealistic conditions. If the glitches are very narrow, thechances of them getting filtered out by the inertial delayof the path stages (cell + interconnect) is very high. Wefiltered out glitches much smaller than the stage delay, andlet those comparable to (or larger than) the stage delaypropagate. The glitches in between were kept as ’x’. Wefound that the pessimism in the dynamic voltage drop re-duced by 20% by using this approach.

Fig. 5. Dynamic IR Drop: SDF Annotated VCD

Fig. 6. Dynamic IR Drop: Without SDF Annotated VCD

C. Choice Of Technology Specs For Signoff

Often, worst case conditions are chosen for timing, elec-trical and reliability checks to ensure robust silicon opera-tion. However, it is also critical to strike a balance betweenpicking bounding conditions and being overly pessimistic.In an effort to get results closer to realistic silicon condi-tions, and to detect potentially silicon fails, we selectivelyevaluated designs under both worst case and non-worst-case conditions. For example if we compare the effect ofthe worst via resistance spec against the nominal via specs,the drop across vias alone reduce by 50%, as show in Fig. 7.With Via resistance and Metal resistances typically being

Fig. 7. Via Drop: Worst corner Vs Nom Corner

uncorrelated, it is a pessimistic assumption to consider thatall vias and metal layers would be in the worst case corner.With sufficient characterization data, we can apply a lesspessimistic analysis condition for dynamic IR analysis.

D. Voltage Annotated Timing Closure

Timing impact has been analyzed with dynamic voltageannotation in the STA tool. The voltage annotated timingviolations on one particular design before any fixes can beseen in Table I. It was ensured that the frequency goalswere met by fixing these violations, either addressing thevoltage drop itself, or at least by improving timing slackon those paths.

Design Worst Slack (ps) Failing End Points

IP1 -251 370IP2 -347 95IP3 -30 8IP4 -37 2

TABLE I

Dynamic IR Drop Annotated Timing

IV. Methodology For power Grid Design For Ro-bust Dynamic IR

In this section, the care-about in planning the power dis-tribution (grid, switches) for power managed designs arediscussed. Knowledge of the design operating scenariosand architecture play a key role in ensuring the robust-ness across scenarios. Some techniques to improve powergrid robustness through simple physical implementationschemes such as power metal fill and decap planning arealso touched upon.

A. Choosing The Right Average Power

The choice of the average power value for which thepower distribution is designed for is critical. It is commonpractice to design for the average power seen in the use casethat consumes the highest power. However, there can be asub-window within the application window, for which theaverage power is much higher than that of the entire usecase time. It is obvious that the grid has to support this

Fig. 8. Average Power Vs Peak Average Power

higher average power during the high-power sub-window,else the device would not function as per design. An exam-ple of this is shown in Fig. 8, where the application averagepower is about 214 mW where as the average power over asub-window is 367mW. This sub window extends over a fewhundred clock cycles. In this case, the grid has to support367 mW of average power and not 214mW. Hence, choos-ing the right average power for designing the grid wouldhelp the design scale up to not just dynamic voltage dropissues, but even to sustain the average cases more robustly.

B. Early Dynamic IR Analysis

One of the difficulties in evaluating the dynamic IR im-pact on SOCs or complex designs (IPs) is to get vectorsfor sufficient scenarios, and to get them in time to detectissues before the design tapes out. Our Early Analysis flowaddresses this issue. In this flow, the switching activity of asub IP is integrated at the top level, and switching activityat the top level is created, for use in dynamic IR analysis.Using this flow, we were able to identify certain architec-tural hot-spots for dynamic IR drop, like cases of crossbarinterconnects interacting with shared memories having veryhigh power density. The results obtained from this flow

Fig. 9. Dynamic IR Drop Profile Using Early Analysis Flow

Fig. 10. Dynamic IR Drop Profile From Full Subsystem Simulation

were found to correlate well with the analysis done withthe complete simulation done at the top level of the sub-system itself. Both cases are shown in Fig. 9 and Fig. 10,where we can notice both the magnitude and the profileof the dynamic IR results match closely (The first map isbased on the sub-design switching ported to the top levelwhile the second map is with switching information fromfull design simulation ). This technique can be extendedto SOC’s, to do vector based dynamic IR drop analysisaccurately.

C. Power Switch Density And Placement

For designs with power switches, in most cases, highvoltage drop is because of lesser number of switches thanneeded for localized power density in certain regions. Fromcommon power analysis methods, it is possible to get a

Fig. 11. Region Based Switch Density

list of IPs/Modules which consume more power than therest of the design. This means that these IPs/Modulesneed higher current. Which implies that there is a need formore switches in these modules. Typically standard cells ofsub IPs/Modules are placed within close proximity. Henceplanning a higher switch density in this area will make thearea better in terms of dynamic IR drop. Covering morescenarios (More VCD) will excite different parts of designand hence will show any weakness in the power network.Refer to Fig. 11 for region based switch density. Coveringmore scenario will also show the area where the voltagedrop is low (cool area), the regions which do not have highIR drop region. In the cool area, switch density can be re-duced by removing some of the switches. This will help inreducing the leakage power of the design in standby mode.

D. Switch Placement In Floorplan Channels /Boundaries

Channels (between macro cells) and floorplan edges orboundaries are often weak spots in a design’s power dis-tribution scheme. It was highlighted earlier how a channelwith power switches placed a bit far from the high switch-ing activity logic gave rise to a dynamic IR hot spot (Referto Fig. 2). To address such issues, we have implementedan automated bounding scheme where all the standard celllogic area in the floorplan is surrounded by power switchesat the boundaries. Refer to Fig. 12. The switch cell bound-ing is done over the corners of channel, making it morerobust to voltage drop variations.

E. Using Design Knowledge To Reduce DynamicIR

In one of our design, the architecture of the design wassuch that, a group of registers banks switching simultane-ously, and these banks would switch in every cycle. Alsothese groups of register banks and associated cells are phys-ically placed close to each another. The Clock to some ofthe flops were skewed so as to stagger the switching whichwill reduce the switching activity (These timing paths hadhigh positive slacks). This will reduce the peak currentrequirement and hence reduce the peak drop. Refer to

Fig. 12. Switch Density In Notches

Fig. 13. Staggering Switching Activity To Reduce Dynamic IR Drop

Fig. 13, the switching activity last for around 200ps, whereas the clock period is higher, Thus we have used the designknowledge to reduce switching activity.

F. Power/Ground Metal Fill

Experiment %Drop % Improvement

Without Metal Fill 9.3 -Metal Fill on 2 Layers 8.4 0.9

Metal Fill on All layers 7.3 2

TABLE II

Using Power/Ground Metal Fill to improve power grid

robustness

Another technique we followed was Power/Ground Metalfill. After the design is frozen, final step is to add metalfill in the areas where the free metal tracks are available.These inserted metal straps are connected power or ground.Refer to Fig. 14. By doing so, the power and ground gridbecomes stronger and hence would help in reducing voltagedrop. Refer to Table.1. We have seen that as much as 0.9%(0.9% of supply voltage) improvement in voltage drop when

Fig. 14. Metal density without Vs with Metal fill

the metal fill is done on 2 layers and 2% improvement whenmetal fill was done on all layers.

G. Other Methods To Reduce Dynamic IR Drop

Load and Slew violation will not only cause crosstalkbut also cause high power. This is because, there will behigh current requirement for higher loads/slews. Hencefixing load/slew violation will help in reducing dynamicvoltage drop. Another method to reduce Dynamic IR dropis haloing of Clock tree cells, and adding decaps near thesecells. This will help in reducing the voltage drop in clocktree cells due to switching.

V. Conclusion

We have highlighted the common issues faced in the de-sign closure of power managed designs . Key accuracyand signoff methodology issues were addressed and im-provements made in replicating actual device operatingconditions in analysis. A comprehensive set of techniquesadopted in our designs to create a robust power grid, and toensure device timing robustness considering dynamic volt-age drop, was presented. This covered the choice of thecorrect power values, power switch planning, using designknowledge and power routing techniques.

A. Future Work

The main area of our ongoing work is with respect tocomprehending the impact of dynamic IR on timing behav-ior of the device - path level, and timing yield. Anotherarea of study is on the coverage of multiple scenarios with-out having to simulate each of them (which is impossible,and hence vector based analysis is not complete today).Further, dynamic IR impact on test modes are presentlybeing studied. Efforts are on to correlate analysis and sili-con measurements to establish a close link between analysisand real device operation.

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