E. Sicard - ultra deep submicron

Ultra-Deep submicron technology

Etienne Sicard

Insa

etienne.sicard@insa-tlse.fr

http://intrage.insa-tlse.fr/~etienne

E. Sicard - ultra deep submicron

• Ultra-deep submicron technology• Specific features • Embedded Memory• Magnetic RAM• SOI• conclusion

Summary

E. Sicard - ultra deep submicron

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pentium

pentium II

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Pentium IV

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1. Ultra-deep submicron technology

Itanium

07

Micron Sub-micron Deep-submicron

UltraDeep-sub

micron

Nano

E. Sicard - ultra deep submicron

1. Ultra-deep submicron technology

• Multiple technological options to optimize performance• Faster & bigger chips• Agreements to handle tremendous costs

(ST,Philips,Motorola,TSMC)

E. Sicard - ultra deep submicron

2. Specific features

Improved tretch isolation

Multiple MOS options

Multiple metal layers

Stacked vias Low K dielectric to reduce couplingsCopper to speed up

signal transport

High K dielectric to reduce leakage

E. Sicard - ultra deep submicron

2. Specific features

3-6 MOS options

• High Speed: normal MOS

• Very high speed: critical

path

• Low leakage: for low power

• High voltage: for I/Os

• Double-gate: for

embedded EEPROM

• RF : optimized for GHz

amplifiers

E. Sicard - ultra deep submicron

High Voltage

Low Leakage

High Speed

Ultra High SpeedEEProm

Application-oriented MOS deviceSame basic mechanism

MRamRF

New physical properties in EEPROM and MRam

2. Specific features

E. Sicard - ultra deep submicron

2.5V1.2V

High Speed High Voltage

1.2V

Low leakage

1.2V1.2V

2.5V

1.2V

2. Specific features

1.8V 2.5V

Example in 0.12µm technology

E. Sicard - ultra deep submicron

2. Specific features

Option layer

Option layer properties

Simple access to low leakage, high voltage and isolated Pwell

E. Sicard - ultra deep submicron

2. Specific featuresLow leakage

High speed

High voltage

Simulation of the 3 MOS options

E. Sicard - ultra deep submicron

2. Specific features

High speed Low leakage

Small Ion reduction

Low leakage MOS has higher Vt, slight Ion reductionLow leakage MOS has 1/100 Ioff of high speed MOS

Ioff ~10nA Ioff ~100pA

E. Sicard - ultra deep submicron

2. Specific features

Type of MOS Effective

channel length

(µm)

Oxide

thickness

Ioff Ion

Ultra-high

speed

0.07 16 Å Very

high

Very

high

High speed 0.09 16 Å High High

Low leakage 0.09 24 Å Low Medium

High voltage 0.2 50 Å Low Low

0.1µm process (TSMC+ST+IBM+…)

Each MOS is optimized for a target customer applicationTowards a world-wide standard process which will ease design

E. Sicard - ultra deep submicron

Cmos Embedded memories

Volatile

eDRAM SRAM

Non volatile

ROM EEPROM FRAM

• 80% of a system-on-chip• Bottleneck for bandwidth

3. Embedded Memory

E. Sicard - ultra deep submicron

Parasitic capacitance: 2fF Specific capacitance: 3-30fF

CB

CS

3. Embedded Memory

E. Sicard - ultra deep submicron

3. Embedded Memory

2nd Poly

Floating Poly

Used in EPROM, EEPROM and Flash memories

Double-Gate MOS

E. Sicard - ultra deep submicron

3. Embedded Memory

Double-Gate MOS

Gate discharged

Ids

Vds

Single gate

Double gate

Gate charged

Ids

Vds

Single gate

E. Sicard - ultra deep submicron

12V

3. Embedded Memory

Double-Gate MOS: write/erase by tunneling0V

0Vdd

Accelerate

“Hot” electron Tunneling

12V

“Cold”electron Tunneling

write eraseDense but slow

E. Sicard - ultra deep submicron

4. Magnetic RAM

Dense, fast, non-volatile: universal memory

2 stage magnetic states

Silicium, Cobalt et Nikel

A high magnetic field changes the state of the material equal toI=5mA

E. Sicard - ultra deep submicron

Principles:

Write: i/2 on the line, i/2 on the column gives a current

high enough to change the state

Read: i/4 on the line, i/4 on the column and monitor the

attenuation of current due to magnetic state

Principles:

Write: i/2 on the line, i/2 on the column gives a current

high enough to change the state

Read: i/4 on the line, i/4 on the column and monitor the

attenuation of current due to magnetic state

Line

Column

i/2

i/2

i/4Write

Read

i/2

i/2

Erase

i/4

4. Magnetic RAM

E. Sicard - ultra deep submicron

The next major evolution?

Less capacitance

Less distance between nMOS and pMOS

Less leakage

CMOS compatible

>50% faster circuits

Kink effectFully or partially depleted?

5. Silicon-On-insulator

E. Sicard - ultra deep submicron

6. Conclusion

• The ultra-deep submicron technologies introduce new features

• Low leakage MOS targeted for low power

• High voltage MOS introduced for I/O interfacing

• Double-poly MOS for EPROM/Flash memories

• Embedded memory are key components for System-on-chip

• Magnetic RAM to become the “universal memory”

• SOI has many promising features, some design issues pending