E silicon track b

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All you need to know about chip design, testing & manufacturing

Israel, May 4, 2010

Advanced Floorplanning and Clock Tree Techniques For Handling

Large Regular Structures

Paul Dudek – Sr. Physical Design Engr.

J. Bhasker - Architect

eSilicon Corporation

2Israel, May 4, 2010

Introduction

Some complex and timing critical chip layout designs require user manual guidance in order to workaround tool limitations.

This presentation will provide a few examples of chip layout challenges and type of solutions that have been used at eSilicon.


Topics covered

Xbar overview

Buffer/FF Stages

Critical Routing

Clock Tree


Xbar Overview

hierarchical blocks:>350

overall size :10 mm x 12 mm.

P&R cell count:7 million

Outport blocks

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26 25

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input_port blocks


Xbar Overview – actual layout


Buffer/FF Stages Between Hierarchical Blocks

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.

. . .

Center block

Hierarchical block pins weredistributed and manually adjustedto later drive custom routing andrepeater buffer and FF cells (inside the channels betweenthe blocks) placement .



inpu

t _p

ort input _port

. . .

outport

. . .

outport

Repeater buffers were driving hundredsof signals from left-to-right, right-to-left,top-to-bottom and bottom-to-topand needed to be placed at exact locations.



The buffer/flop repeater stages were grouped and madeinto temporary hierarchical blocks.

Hierarchical blocks

Temporary hierarchical block(flattened after floorplanning stage)

Custom routing from/toThe repeater stages.



Actual view of the repeatercells within a single Xbar column.


Main benefits of creating temporary hierarchical blocks vs. creating fenced cell regions:

1. Ease of adding custom routing which was based on the hierarchical and temporary block pin locations. It would have been difficult to add routing based on cells “randomly” clustered in a fenced region.

2. Ease of placing cells at an exact location inside the temporary blocks. A separate script was written to place the cells in a stepping pattern to prevent overlaps, with placement based on the block pin locations.




Repeater cells forvertical routing

Repeater cells forhorizontal routing

Hierarchical blocks

Final view of the flattened temporary blocks repeater stages.


M9 custom verticalsignal routes

M8 custom horizontalsignal routes

‘Center’ hierarchical blocks

All custom critical routing was done in thick M8 and M9 above the hierarchical blocks. The blocks had M7 PG mesh with max, 70% util.

Critical Routing - ‘thick’ M8/M9


Xbar customrouting corner view

M9 custom verticalsignal routes

M8 custom horizontalsignal routes

Critical Routing


M8/M9 ‘thick metal’VSS/VDD mesh

M8/M9 routing tracks(or routing grids)

Note the M8/M9 PGmesh was built in suchway that only 1 signalroute could be routedin-between, resulting in automatic pre-built shielding for all critical routes.

Critical Routing - shielding


Critical Routing - summary

Benefits of custom routing on M8/M9:

1. Resistance of thick M8/M9 layers was about 6x less than for other layers allowing “strong” buffers to drive them over long distances without slew degradation.

2. With M8/M9 PG mesh in every other track, the custom routes were automatically shielded – by construction.

3. Small hierarchical blocks were easily built with six signal layers plus M7 PG max mesh coverage, thus eliminating any xtalk with M8/M9 custom routes from above.


Clock “sync” cells attempting to balance the clock tree skewmade the skew worse. This was due to the narrow channels between the xbar hierarchical blocks.

Clock Tree

Clock treeskewbalance cells

Existingrepeatercells


Custom clock tree was builtusing a script placing clockinverter cells up to 64quadrants, after whichautomatic CTS was run to toolbuilt the remaining tree.

Clock Tree


Same as previous picture,but showing all the hierarchicalblocks.

Clock Tree


Example of one of the 64 quadrants.

Hierarchicalblocks

“Flylines” showing targetconnections

Clock driver cell for blocks’clock pins

Clock Tree


Example of one of the 64 quadrants.

Hierarchicalblocks

“Flylines” showing targetconnections

Clock driver cell for FF cells

Clock Tree


Clock tree – 1st attempt.(showing flylines to the finaltargets)

Each quadrant was dividedequally, where the channelswere “split” in the centerassigning half the FFs to onequadrant and the other half tothe other.

Tool was unable to balancethe skew between thequadrants.

Clock Tree


Clock tree – 2nd attempt.

The channel FF cells “split” inthe center was removed and“whole” channels were assignto a given quadrant.

Skew has improved but thetool was still unable to balancethe skew between thequadrants.

Clock Tree


Clock Tree

Clock tree – 3rd attempt.

The custom H-tree wasmoved to minimize wirelength to the final targets.

Tool was able to provide localskew of 120p and global skewof 180p.Target skew was 200 ps.


Clock Tree3 attempts comparison.


Tool Usage

Magma tool set made it possible to complete this complex design in about 8 month period from initial netlist handoff to tapeout.

Magma straightforward TCL database access greatly simplified custom script implementation.

One can guide the tool with critical cell placement and routing to work around tool limitations.


Conclusion

Complex design structures such as a crossbar require user guidance and ability to manipulate layout database structure.

Scripting allows quick update of layout database for each incremental revision of the netlist.

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All you need to know about chip design, testing & manufacturing

Israel, May 4, 2010

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E silicon track b

Education