1. the way customer using today: 1：transfer brd（TLK1501）+ switch brd（TLK1501）+ control brd（Lattice SERDES）2：switch brd（TLK1501）+ control brd（Lattice SERDES）The connection btw the two brds in the two way are all through fiber, the fiber length is inside 100m；Question 1：TLK1501 TX side IDLE1、IDLE2 code is controlled by the pin or not?

i.e. , when TX_EN=0，TX_ER=0, they will sendK28.5+D5.6（IDLE1）or K28.5+D16.2（IDLE2）, is it controlled by TXD？They use FPGA control TLK1501 TX_EN、TX_ER and TXD，the detail code is as below：i.e when idle status, send C5BC，before data is transmit, they send 50BC first, and then send the effective data:always@(posedge txclk or negedge rst_n) if(!rst_n) begin txd_data_opt_package1 <= 16'hc5bc ; txd_er_opt_package1 <= 1'd0 ; txd_en_opt_package1 <= 1'd0 ; end else if(((~package_en_opt1_d1) && (package_en_opt1)) || ((ddr_switch_en_valid_opt0 == 1'd1) && (ddr_switch_en_valid_opt0_d1 == 1'd0))) begin txd_data_opt_package1 <= 16'h50bc ; txd_er_opt_package1 <= 1'd0 ; txd_en_opt_package1 <= 1'd0 ; end else begin if(package_en_opt1_d1) begin txd_data_opt_package1 <= package_data_d1; txd_er_opt_package1 <= 1'd0 ; txd_en_opt_package1 <= 1'd1 ; end else if(ddr_switch_en_valid_opt0_d1 == 1'd1)

begin txd_data_opt_package1 <= ddr_switch_en_data_opt0_d1; txd_er_opt_package1 <= 1'd0 ; txd_en_opt_package1 <= 1'd1 ; end else begin txd_data_opt_package1 <= 16'hc5bc ; txd_er_opt_package1 <= 1'd0 ; txd_en_opt_package1 <= 1'd0 ; end endthe detail timing as below：

But at receiver side（1501 receiver），they will see：

i.e: the data parsed at receiver side has different timing with TX FPGA side, it seems 1501 tx IDLE is controlled by internally, not affect by external TXD；QUESTION2：about 1501 receiver sync status machine.

In 1501 d/s：The TLK1501 has a synchronization-state machine which is responsible for handling link initialization and synchronization. Upon power up or reset, the state machine enters the acquisition (ACQ) state and searches for IDLE. Upon receiving three consecutive IDLEs or carrier extends, the state machine enters the synchronization (SYNC) state. If, during the acquisition process, the state machine receives valid data or an error propagation code, it immediately transitions to the SYNC state.

I,e, when receiver continuous 3 IDLE code or 3 continuous K23.7 code at ACQ status will

enter SYNC statys；Or get 1 valid data or 1 error propagation(K30.7) code at ACQs status will enter SYNC

status；At sync status get one invalid code will get into check status ； at check status get 4 continuous valid code will get back to SYNC；At check status get 3 invalid code will into ACQ；question：

1）K28.5 is using for word align，to find the data border from serial data, recover the data, it is described in the standard as below:

Then is it aligned with standard that at ACQ status getting 1 valid data or 1Error

Propagation（K30.7）will get into SYNC status?

2）in check status，how about the output of RX_DV、RX_ER、RXD?

3. about comma code sync: there are several description in 1501 d/s：Description1：1501 only recognize K28.5 negative code to do link syncIn the user guide, there is such description:” before TLK1501 normal transmit data, it need sync. Normally, TLK1501 will has sync through detecting K28.5 IDLE code. According to 8B/10B code rule, K28.5 has two code, one is 0011111010（RD-polarity，Running Disparity），the other is 1100000101（RD+ polarity）. TLK1501 only recognize 0011111010，1100000101 as invalid sync code when doing sync. Because it is 16bit, according to the rule, a whole sync code

should be K28.5+D5.6 or K28.5+D16.2 ， but the final sync code should be K28.5+D16.2. according to 8b/10 coding rule, in one frame, all the byte polarity need has a sum of 0, every by RD polarity should be decided according to last RD polarity, if last byte is RD-, next one should be RD+ or 0, so when sending sync code, if last data is RD- polarity, then K28.5

code will be RD+ , ie 1100000101，but it will not recognize this K28.5 code. For getting RD- K28.5 (0011111010),RD+ K28.5 need be followed by a 0 polarity data, i.e 5.5 with RD of 0 , i.e.1010010110. then K28.5+D5.6 RD will be RD+, next K28.5 should be RD-, i.e 0011111010, plus one RD+ D16.2, then K28.5+D16.2 has RD of 0, TLK1501 will keep sending K28.5+D16.2 till sync. TLK1501 has two control method for sending sync code, one is for controlling TX-EN, TX-ER to 00 to force TX side send sync code.

Description 2：Because there is error code in the link, they may make non-comma code to comma code, it will cause the boundary of the byte to be wrong , to avoid the case, comma detecting circuit will be closed only after receiving and sync to the right comma code. Only will re-launch the comma detection circuit when the sync status is loss.

Description 3：When TLK1501 is working at TRX mode（LCKREFN pin is 1），receiver side receive wrong data and enter the sync capture mode, TLK1501 state machine will control TX send sync

code.

question：a）how to control the polarity of the K code of TLK1501 ？default sending K28.5 negative code？how about the sending sequence of IDLE1 and ILDE2？because the TX and RX has coupling，what’s the rule of sending IDLE code when the receiver side at ACQ status？and what’s the rule for non ACQ status？b）at ACQ status, could we guarantee when the corresponding side receiving 3 continuous K28.5 negative code to get into SYNC status？c）because other serdes has no limitation of recognize 0011111010 , and no coupling btw tx and rx, and according to 802.3 IDLE code polarity need be related with last word, when this side 1501 receiving is broken, and tx side serdes unknown, the IDLE code sent by TX may

not meet 3 001111101， will this cause problem? What’s the resolve solution?

d）is there a rule on that during initial status, SERDES need send K28.5 negative code？e）according to the description of 1501, RX side at ACQ， TX need send IDLE code, customer do the test as below: control brd （ FPGA SERDES ） do not send IDLE code, only send D code, they will get below waveform at transfer brd（1501）interface：

The 8181 in the plot which is not sent by TX, showing that does it mean 1501 is not sync?

Idle status, the control brd receive normal IDLE code:

But the transfer brd control 1501 to send message data, in theory the control brd should not receive data, but in the real situation, it can receive normal data, detail as below:

4. one issue description：Transfer brd（TLK1501）+control brd（Lattice SERDES）At control brd, the rule of sending data is as below: IDLE status sending C5BC ，and send 50BC before sending normal data.Sometimes In the transfer brd 1501, the RX side will find the situation of RX_DV=1，RX_ER=1，RXD=50BC, detail as below:

Question: why such status will shows up: RX_DV=1 ， RX_ER=1 ？ what’s the status of 1501 receiver side is in now？