CORRESPONDENCE

Fig. 2. Diagram of an implementation of the zero-crossing intervalinterface for the PDP-8/L computer.

since the input inhibit prohibits a zero-crossing from affecting thedevice until at least one clock period. The overflow flag is clearedwhenever the zero-crossing flag is cleared.

Also shown in Fig. 2 is the method by which the input inhibit isaccomplished. The one-shot is variable by means of an extrnaladjustment and must be set prior to using the interface.A selective divider circuit is used in conjunction with a one MHz

crystal clock to provide for variations in count rate consistent withthe maximum length of zero-crossing interval to be measured. Thisalso is set with an external adjustment prior to using the interface.

Circuit diagrams and complete documentation for this interfaceare available upon request.

IV. CONCLUSIONS

The inteface technique described is a very efficient method ofextracting zero-crossing interval measurements from a continuous-time waveform. With a single I/O instruction, this interface providesa time measurement corresponding to the previous zero-crossinginterval length. The time savings over A/D samnpling and linearinterpolation between successive samples differing in sign is obvious.This interface accomplishes a zero-crossing interval measurement inless time (and probably more accurately) than is generally requiredto obtain a single A/D sample.

REFERENCES

[11 K. H. Davis, R. Biddulph, and S. Balashek, "Automatic recognitionof spoken digits," J. Acoust. Soc. Amer., vol. 24, pp. 637-642, Nov.1952.

12] G. D. Ewing and J. F. Taylor, "Computer recognition of speechusing zero-crossing information," IEEE Trans. Audio Electroacoust.,vol. AU-17, pp. 37-40, Mar. 1969.

13] D. R. Reddy, "Computer recognition of connected speech," J.Acoust. Soc. Amer., vol. 42, pp. 329-347, Aug. 1967.

[41 W. Bezdel and H. J. Chandler, '.'Results of an analysis and recogni-tion of vowels by computer using zero-crossing data," Proc. Inst.Elec. Eng., vol. 112, pp. 2060-2066, Nov. 1965.

[5] W. Bezdel and J. S. Bridle, "Speech recognition using zero-crossingmeasurements and sequence information," Proc. Inst. Elec. Eng.,vol. 116, pp. 617-623, Apr. 1969.

16] T. Sakai and S. Doshita, "The automatic speech recognition systemfor conversational sound," IEEE Trans. Electron. Comput., vol.EC-12, pp. 835-846, Dec. 1963.

17] R. J. Niederjohn and I. B. Thomas, "Computer recognition of thecontinuant phonemes in connected english speech," IEEE Trans.Audio Electroacoust., vol. AU-21, pp. 526-535, Dec. 1973.

[8I B. Saltzberg and N. R. Burch, "A rapidly convergent orthogonalrepresentation for EEG time'series and related methods of auto-matic analysis," in IRE WESCONS Conv. Rec., 1959, part 8, pp.35-43.

[9] --, "Period analytic estimates of moments of the power spectrum:A simplified EEG time domain procedure," Electroencephalogr,Clin. Neurophysiol., vol. 30, pp. 568-570, 1971.

[101 G. Dumermuth, P. J. Huber, B. Kleiner, and T. Gasser, "Numericalanalysis of electroencephalographic data," IEEE Trans. AudioElectroacoust., vol. AU-18, pp. 404-411, Dec. 1970.

[11] N. R. Burch, "Period analysis of the electroencephalogram on ageneral purpose digital computer," Ann. N. Y. Acad. Sci., vol. 115,pp. 827-843, July 1964.

[121 C. L. Yeager, D. Heilbron, and H. D. Kurland, "Computer classi-flcations of clinical electroencephalograms," Navy Progress Rep.NO-0014-70C-0248, 1972.

113] J. S. Bendat, Principles and Applications of Random Noise Theory.New York: Wiley, 1958.

[14] H. Press and J. C. Houbolt, "Some applications of generalizedharmonic analysis to gust loads on airplanes," J. Aerosp. Sci., vol.22, p. 17-26, Jan. 1955.

[151 R. B. Niederjohn, "A mathematical comparison of axis-crossinganalysis techniques which have been applied to automatic speechrecognition," in Proc. Milwaukee Symp. Automat. Contr., Mar.1974, pp. 296-303.

Easily Tested Three-Level Gate Networks for T or Moreof N Symmetric Functions

JOHN P. ROBINSON AND CHARLES W. HOFFNER, II

Abstract-This correspondence considers three-level AND/ORgate realizations for T or more of N symmetric functions and givesa design procedure. The procedure can be used to design relativelylarge networks. The three-level realizations require substantiallyfewer test patterns for fault detection, gates, and gate inputs thanthe minimum two-level network. For example, the minimum two-level network for the 3 or more out of 12 functions requires 286 testpatterns, 67 gates, and 726 gate inputs while the three-level realiza-tion presented requires 27 test patterns, 25 gates, and 96 gate inputs.

Index Terms-Partition, symmetric functions, testing, three-levellogic.

I. INTRODUCTION

T or more of N symmetric functions are important in realizingcoding techniques for error control or for security [1]. Proceduresfor synthesizing minimum gate two- and three-level AND-OR logicnetworks that realize a logic function are well known [2}-[4].This correspondence considers realizations for a class of functionswhose synthesis exceeds the practical limitations of both of thesewell-known procedures. While such functions can be realized by asingle threshold gate, there may be advantages in AND-OR realiza-tions as many threshold gate circuits are relatively complex orrelatively slow.A T or more of N symmetric function F of N variables xi,i =

1,2,... ,N, has the value 1 if T or more of the xi have value 1.The properties of interest for such functions using two-level

AND/OR realizations are as follows.1) The minimum test set for detecting all single stuck-at-1 or

stuck-at-0 faults consists of all input variable combinations with Tones and T -1 ones for a total of

(N + 1

test patterns.2) All products of T variables form

/N\

Manuscript received July 28, 1970; revised March 15, 1,974. Thisresearch was supported by the Office of Naval Research under ContractN00014-68-A-0500 and the National Science Foundation under Con-tract GK-2940.

J. P. Robinson is with the Department of Electrical Engineering,University of Iowa, Iowa City, Iowa 52242.

C. W. Hoffner, II, was with the Department of Electrical Engineering,University of Iowa, Iowa City, Iowa 52242. He is now with Bell Labora-tories, Columbus, Ohio 43213.

331

IEEE TRANSACTIONS ON COMPUTERS, MARCH 1975

x1 0 0 0

X2 0 ° 1

x3 0 1 1

x4 - 1 0

x5 1 0 -

x6 1 1 *1

(a)

F

(b)Fig. 1. Three-level network for the 2 or more of 6 function. (a) Al

matrix. (b) Realization.

essential prime implicants; all sums of N - T + 1 variables form

N

essential prime implicates.3) For N + 1 < 2T the minimum network is the AND-OR form,

when N + 1 > 2T the OR-AND form is minimum, finally if N +1 = 2T both types are minimal.

II. DESIGN PROCEDURE

A three-level network in this correspondence is either a sum ofproducts of sums (OR-AND-OR) or a product of sums of products(AND-OR-AND). Initially, we will develop the properties of theOR-AND-OR structure, then state the dual results for AND-OR-AND.

Assuming that F is a T-or-more of N function imposes restrictionson a OR-AND-OR network. First each AND-gate has at least T inputs;that is, each such gate forms the product of at least T sums. If an

ND-gate forms the product of exactly T sums then 1) these T sums

must be disjoint, that is, each xi can be included in at most one

of these sums; and 2) each of these sums must contain at least one

of the xi and no more than N - T + 1 of the xi.We will assume that each AND gate has exactly T inputs. While

the results can be extended to the case of more than T inputs, theresults do not seem to be useful. Under this assumption the problemhas an interesting set theoretic formulation.

Definition: A decomposition of a set I S I is a collection of disjointsubsets called blocks. When the set union of the blocks is {S}, thedecomposition is a partition.

Let {XI be the set of imputs xi. Each input level OR-gate sums a

subset of IXI; thus, there is a subset corresponding to each inputlevel oR-gate. If an AND-gate forms a product of exactly T sums,then the collection of subsets of {X corresponding to these sums

is clearly a decomposition. Thus a decomposition can be used tospecify T sums whose product is formed by an AND-gate. In general,

there will be a decomposition corresponding to each AND-gate and ablock corresponding to each input oR-gate.A decomposition will be written as an N row column vector.

The T blocks of the decomposition will be numbered 0 throughT - 1. The entry in the ith row is the number of the block thatcontains xi or a dash if xi is not included in any block. A set of Pdecompositions will be written as an N by P matrix M. The followinglemma clearly follows.Lemma 1: An M matrix specifies a realization for F if and only

if each subset of T rows fromM has at least one column that containsall T numbers.For example the M matrix in Fig. 1 (a) with T = 2, N = 6, and

P = 3 has the property that any two rows has at least one columnwhere both 0 and 1 appear. Thus the network in Fig. 1 (b) cor-responding to M realizes the 2 or more of 6 function. Fig. 2 givesa more complex example. Note that in Fig. 2 the decompositions arepartitions as there are no dashes in M.

III. THE CASES T = 2, T = 3, AND N = 2T

Case 1: For T = 2 the condition on M from Lemma 1 simplyrequires that no two rows of M be the same treating dash as aDON'T CARE. Thus for N < 2", M can be constructed with at mostm columns. The realization specified by M requires at most 3m + 1gates.For N = 2m and P = m, 3 (log2N) + 1 gates and (N + 3) (log2N)

gate inputs are required for this three-level realization. For com-parison the minimum gate two-level realization requires N + 1gates and N2 gate inputs.

Case 2: For T = 3 the vector space concept will be used to con-struct M. If M is a vector space, a set of m linearly independentrow vectors is called a basis B for M if each row ofM can be obtainedby summing rows of B. The condition on M requires that for anythree vectors in the row space of B there is at least one column inwhich all three vectors are different. Vector addition is componentby component modulo 3 addition.

It will be assumed that M has 3m rows and that the leftmost m

332

CORRESPONDENCE

x1

x2x3

x4x5

x6

x7X8

x9xio

xix12

(a)

(b)

Fig. 2. An example. (a) M matrix. (b) Realization.

columns of M include all 3m ternary row vectors of length m. Thenany basis for the rows of M can be reduced to the form B = [I Q]where I is an identity matrix of size m.

Consider the matrix G,

G= .

G is the generator matrix for a ternary single-error-correcting code;each pair of vectors differ in three columns. Since there are onlyfour columns, there must be at least one column in which a tripleof vectors are all different.

Although there may not be a single column of I in which threevectors from M are all different, there will always be some pair ofcolumns of I in which three vectors are all different. Consequentlythe condition on M is satisfied if, for each pair of columns in I,there are two columns in Q such that G is a submatrix of the fourcolumns, and the four columns are all zero elsewhere. Then for anytriple of vectors it is always possible to find four columns of B suchthat each pair of the triple differ in three of these four columns.When B is constructed in this way,

P =m+2 ()=m±+2 (2) (m) (mr-1) = m2.2,

For m = 2, B = G, P = 4, and N = 9; for m = 3, P = 9, N = 27,and

-1 0 0 1 0 1 2 0 1-

B J 1 0 1 1 0 1 2 0o;

L0o0 1 0 ] 1 0 1 2i

for m = 4, P = 16, N = 81, and

1 0 0 0 1 0 0 1 1 0 2 0 0 1 2 0

0 1 0 0 1 1 0 0 0 1 1 2 0 0 0 2B=

0 0 1 0 0 1 1 0 1 0 0 1 2 0 1 0

_-0 0 0 1 0 0 1 1 0 1 0 0 l 2 0 1-The realization specified by B requires 4m2 + 1 gates.For N = 3m, m = log3N so that 4(10g3N)2 + 1 gates and

(N + 4) (log2 N)2 gate inputs are required for this three-levelrealization. For comparison the minimum gate two-level realiza-tion requires 2(N) (N - 1) + 1 gates and 2(N) (N -1)2 gateinputs.Note that for this construction, P = n2 when 2-3m-1 < N < 3m,

P = m2- 1 when 4.3m-2 < N < 2.3m-1, and so on. And, whenN = 3m, each block contains exactly 3m-lxi. The M matrix for whichG is a basis is shown in Fig. 3 (a). Some M matrices with unequalblock sizes, obtained by ad hoc search, are shown in Fig. 3 (b)- (e).

Case 3: For N = 2T an M matrix will be given for T = 3, 4, 5,6, and 7. These are the threshold functions whose minimum gatetwo-level realizations require the most gates. These matrices wereobtained in an ad hoc manner, using various results about error-correcting codes and circulant matrices to reduce the enumerationrequired by Lemma 1.

SorI.nc M matrices for N = 2T are shown in Fig. 4.The l matrices Fig. 4(c) and (d) are examples where all T-P

blocks are not different. When several blocks are the same, the ANDgates can share input OR gates..When each block contains at least two xi and the ith row of M

consists of P (i - 1)s, for 1 < i < T, the realization specified byM requires T2 input OR gates and P AND gates. When the ith rowof M consists of P(i - 1)s for 1 < i < T and the remaining Trows of M can be partitioned into circulant matrices, M will bewritten in abbreviated form by listing one column from eachcirculant. Thus Fig. 5(a) is the abbreviated form of Fig. 4(d).

IV. TESTING FOR DETECTION

Since the three-level realizations presented require considerablyless logic compared to the minimum two-level case, one wouldexpect a similar reduction in the number of test patterns requiredto verify correct operation for the same fault model. We will de-

0 1 2 2 l 0

0 0 l 2 2 1

l o o 1 2 2

2 1 o o l 2

2 2 l- o 1

1 2 2 l 0 0

0 2 l l 2 0

0 12 1

0 0 2 l l 2

2 o o 2 1 1

l 2 o o 2 l

1 l 2 0 o 2

2 l l 2 o o

333

IEEE TRANSACTIONS ON COMPUTERS, MARCH 1975

0 0000 1110 222

1 012

1 2011 120

2 0212 102

2 210

0 000000 111110 22222

l11

1

1

222

2

12

012122 0 1 2 1

1 2 0 1 2

2 1 2 0 1

1 2 1 2 0

0 2 1 2 11 0 2 1 2

2 1 0 2 1

1 2 1 0 2

2 1 2 1 0

0 000000 111110 22222

1 01122

1 201121 220111 122011 1 1 2 2 0

2 022112 102212 110222 211022 22110

O 1 1 1 2 2 22 0 1 1 1 2 22 2 0 1 1 1 22 2 2 0 1 1 11 2 2 2 {) 1 l1 1 2 2 2 0 11 1 1 2 2 2 0

0 2 2 2 1 } 11 0 2 2 2 1 11 1 0 2 2 2 11 1 1 0 2 2 22 1 1 1 0 2 2

22011102

2 2 2 1 1 1 0

0 1 2 1 2 1 22 0 1 2 1 2 1

1 2 0 1 2 1 221201211 2 1 20 1 221212011 2 1 2 1 20

021 21211021 2122 1 0 2 1 2 1

1 2 1 0 2 1 2

2 1 2 1 0 2 1

1 2 1 2 1 0 2

2 1 2 1 2 1 0

Fig. 3. Some M matrices for T = 3.

o o o

111222

0 2 1

102210

0000 00

1111 102 2 2 2 0 1

3333 11

0321 22

1032 232103 32

3210 33

(a) N = 9. (b) N = 13. (c) N = 13. (d) N = 14. (e) N = 14.

0000 00 00

1111 11 11

2222 22 22

3333 33 33

0321 03 32

1032 20 132103 12 013210 31 20

Fig. 4. M matrices for N = 2T and T = 3,4,5. (a) T = 3. (b) T = 4. (c) T = 4. (d) T = 5.

000 012345661 45 556o01'234213 2345601

3 5 1 6012 3 4 5426 45601235 6 43 4 5 6 0 1 2

632 1234560

Fig. 5. Abbreviated M matrices for N = 2T and T = 5,6,7. (a) T = 5.(b) T 6. (c) T 7.

monstrate that the reduction in test size is about the same as thereduction in total gate inputs.The conventional single stuck-at-one (s-a-1) or stuck-at-zero

(s-a-O) fault class will be assumed, i.e., the malfunctions or errors

can be described by some gate input or output lead fixed at a logic1 or 0. This model seems adequate fo'r some problems in real circuits,e.g., a lead shortened to ground or an open input lead in TTL.'Itis probable that the relationships, to be developed for single s-a-i

or s-a-O fault detection,' extend to other gate fault modes, multiplefaults, and fault location.We will consider the problem of miniizing the number of test

patterns required to detect all single s-a-I or s-a-0 faults. Themaximum number of single faults detectable by a single test in a

three-level OR-AND-OR tree is indicated in Fig. 6. Simple countingmethods lead to the following results.Lemma 2: For a tree network each decomposition implies at

least as many s-a-0 tests as the maximum block size and none of thesetests can be shared with another decomposition. ThusE 'P oi s-a-Otests are needed where i is the maximum block size in the ith de-

1/

0/0 1/0

1/00

(a)

0/1

0/1 0/1

0/1 1 01

0/1 0/1

0/1

(b)

Fig. 6. Maximum test configuration for a tree network, correct' value/fault value. (a) Stuck-at-zero. (b) Stuck-at-one.

composition. For a network with internal fan-out at least P s-a-O

tests are required.At least T s-a-1 tests and less than TP s-a-1 tests are needed.Table I summarizes some of the properties of the proposed

00000 ooo0 o

22222 22222

333 33 3 '33 35344444 44444

04321 02L31310432 3024121043 130243.2104 4130243210 24130

0F0j1 3

3442

00000 00000l 1 1 1 5 3 3 3 3 52 2 2 5 1 1 1 1 5 3

3 3 5 2 2 4 4 5 1 1

45O33 254445 444 5 2 2 2 2

334

-335IEEE TRANSACTIONS ON COMPUTERS, MARCH 1975

TABLE ICOMPARISON OF MINIMUM TWO-LEVEL AND-OR NETWORK AND THEPROPOSED THREE-LEVEL OR-AND-OR NETWORK FOR T OR MORE

OF N FUNCTIONS

Mlinimum Two-Level

TotalInputs

TestsL2

Proposed THREE-LEVEL

GatesTotalInputs

Tests a

LB

2 8 9 64 36 10 33 14 14

2 12 13 144 78 13 56 20 20

2 2m 2m+ 1 22r ( 1+) 3m + 1 m(2m + 3) | m2m 1 + 2 m2m1 +2

3 6 16 75 35 13 30 9 9

3 9 37 288 120 17 52 1.5 17

3 12 67 726 286 25 96 27 27

l)3m m r3 £1 2 2 m2 r-i3 3 ||

21+1

2) (3 _1) 4m + 1 m(3m +4) m23 +3 **

4 I 8 57 336 126 25+ 72 12 14

4 8 57 336 126 31* 78 16 20

5 10 211 1,470 462 36 110 15 15

6 12 793 4,752 1,712 97 492 66 66

7 14 3,004 21,021 6,435 120 658 77 77

LB = Lower bound from Lemmas 2 and 3.

2mUpper bound is 2m greater than LB.

+

Using Fig.4(c).*

Using Fig. 4(b) .

three-level networks. Note that the actual value of the minimumtest length L3 is close to the lower bound. L3 was found using searchprocedures and the properties of M.

V. CONCLUSIONS

The results presented for OR-AND-OR networks can be convertedusing duality to AND-OR-AND structures. The function realized bythe dual network is clearly a N + 1 - T or more of N functions.The suboptimal design procedure presented is based on the con-

struction of an N by P matrix with entries 0,1, .,T - 1, havingthe property that any subset of T rows has some column with allT numbers. Such matrices seem relatively easy to construct. Ageneral construction for T = 2 and T = 3 is given. The resultingrealizations obtained require substantially fewer tests for fault

detection, gates, and total inputs than the minimum two-levelnetwork. It has been shown that for the T or more of N switchingfunctions, a three-level AND-OR realization may be economicallyfeasible even though the minimum gate two-level realization forthe same function is not.

REFERENCES

[11 W. W. Peterson and E. J. Weldon, Jr., Error-Correcting Codes.Cambridge, Mass.: Mass. Inst. of Tech. Press, 1972.

[21 E. J. McCluskey, Introduction to the Theory of Switching Circuits.New York: McGraw-Hill, 1965.

[3] A. Grasselli and J. F. Gimpel, "The synthesis of three-level logicnetworks," Digital Syst. Lab., Dep. Elec. Eng., Princeton Univ.,Princeton, N. J., Tech. Rep. 49, 1966.

[41 J. F. Gimpel, "The minimization of TANT networks," IEEE TransElectron. Comput., vol. EC-16, pp. 18-38, Jan. 1967.

T N Gates