Ec 1318 Microprocessor and Applications

EC 1318 – MICROPROCESSOR AND APPLICATIONS – C.S – L / MCT – SKCET1

PREPARED BY C.SIVAKUMAR – L – MCT - SKCET

EC 1318 MICROPROCESSOR AND APPLICATIONS

Vth SEM MECHATRONICS ENGINEERING

MATERIAL FOR WEAKER STUDENTS

Prepared By, C.SIVAKUMAR,

L / MCT



2 MARKS QUESTIONS 1. What is Microprocessor? 2. What are the basic units of a microprocessor? 3. Define hardware and software? 4. What is an assembly language? 5. What is a low level language? 6. What is a high level language? 7. Differentiate compiler and an interpreter? 8. What is assembler? 9. What is cross assembler programs? 10. Define operating system? 11. What is Microcomputer? 12. What are the advantages of an assembly language in comparison with

high level languages? 13. What are the advantages of high level language in comparison with the

assembly languages? 14. Draw the block diagram of a microcomputer 15. Define bit, byte, word and instruction 16. What is a bus? 17. Define MPU 18. List the four operations commonly performed by the MPU? 19. Define the address bus 20. Mention the steps; the MPU needs to communicate with the peripheral. 21. Define data bus 22. Why 8085 is known as 8 – bit microprocessor? 23. Define control bus? 24. Why is the data bus bidirectional? 25. Why is the address bus unidirectional 26. How much memory location can be addressed by a microprocessor with n

address lines? 27. Specify the four control signals commonly used by the 8085 MPU? 28. How a 8085 microprocessor can qualify as an MPU. 29. List the four categories of 8085 instructions that manipulate data. 30. How many instructions are available in 8085 instruction set? 31. How 8085 microprocessor operations are classified? 32. Define opcode and operand? 33. How 8085 instructions are classified according to the work size or byte

size? 34. What is addressing and what are the addressing modes available in 8085. 35. Explain the immediate addressing with an example 36. Direct Addressing.



37. Explain register addressing with an example? 38. What is register indirect addressing? Give an example. 39. Explain the implied addressing with an example. 40. In which unit arithmetic and logical operations are performed and where

the result is stored? 41. Which group of instruction affects the flag? 42. What are the arithmetic instructions that do not affect the

flag? 43. What are the flags affected by 8 – bit increment and

decrement instructions? 44. List the instructions that effect only carry flag. 45. List the various instruction that can be used to clear

accumulator? 46. Why the program counter and the stack pointer are 16 – Bit

registers? 47. What is machine cycle?

48. What are the machine cycles available in 8085 Microprocessor?

49. What is T - State? 50. What is flag? 51. Write the 8085 machine cycle status and control signals. 52. How 8085 can be used as an MPU? 53. Define mnemonics? 54. What is Opcode fetch cycle? 8/16 MARKS QUESTIONS

1. Draw and explain the operation of 8085 MPU and its architecture 2. Draw and Explain the pin configuration of 8085 3. Write a program to transfer a block of data from one location to the other. 4. Write an assembly language program to add or subtract 2-8 bit numbers. 5. Write an assembly language program to multiply and divide two 8 – bit

numbers. 6. Write an assembly language program to convert a two digit BCD(8-bit) data to

binary data. 7. Write an assembly language program to convert an 8-bit binary data to BCD.

The binary data is stored in 4200H. Store the hundred’s digit in 4251H. store the ten’s and unit’s digits in 4250H.

8. Write an assembly language program to find the 7-segment LED code for a 2-digit BCD data, by using look up table. The BCD data is stored in 4200H. Store the 7-segment code in 4201H and 4202H.

9. Write an assembly language program to add or subtract two 16 bit numbers.

10. Write a program to sort the numbers in ascending and descending orders.



TWO MARKS

1. What is Microprocessor? Microprocessor is a multipurpose, programmable clock driven register based

electronic device that reads binary information from a storage device called memory; accepts binary data as input and processes data according to those instructions, and provides results.

2. What are the basic units of a microprocessor?

The basic units or blocks of a microprocessor are, ALU An array of registers Control unit

3. Define hardware and software? Hardware: Te physical components of a system are called hardware Software: A set of instructions written to perform a particular task is called a program, and a group of programs is called software. 4. What is an assembly language?

An assembly language is a language which uses English – like words. Assembly language is microprocessor specific i.e programs written in assembly language are not transferable from one machine to another assembly language is machine dependent. Eg; 8085

5. What is a low –level language?

Low level language is a language which user the binary 0 and 1. All the microprocessor understands only the binary.

6. What is a high level language?

Programming languages that are intended to be machine independent are high level languages. Instruction used in those languages is known as statements.

Example: BASIC, C, C++ and Java 7. Differentiate compiler and an interpreter?

Compiler or an interpreter programs accept English like statements as their input, called the source code and translates it into the machine language called the object code.

The primary difference between compiler and an assembler is that, The compiler reads the entire program first and translates it into the object code that

is executed by the microprocessor.



Interpreter reads are instruction at a time, produces its object code and executes the instruction before reading the next instruction.

8. What is assembler?

The assembler is a program that translates the mnemonics entered by the ASCII keyboard into the corresponding binary machine codes of the microprocessor.

9. What is cross assembler programs? Cross – assemblers can be used to translate the 8085 mnemonics into appropriate

machine codes.

10. Define operating system? The interaction between the hardware and the software is managed by set of

programs called an operating system of a computer, it overseas all the operation of the computer.

11. What is Microcomputer?

It is a computer that is designed using a microprocessor as its CPU. It include microprocessor, memory and I / O (Input / Output)

12. What are the advantages of an assembly language in comparison

with high level languages? Te assembly language programs are compact and require less space. They are more

efficient than the high – level language programs. 13. What are the advantages of high level language in comparison with the assembly languages?

The primary advantage of high – level language is in troubleshooting (debugging) programs. It is much easier to find errors in a program written in a high – level language than to find them in a program written in an assembly language.

14. Draw the block diagram of a microcomputer

It is possible to build the CPU on single chip, this came to be known as microprocessor. A computer with a microprocessor as its CPU is known as a microcomputer.

15. Define bit, byte, word and instruction Bit : Bit is a binary digit 0 or 1. Byte : Byte is a group of 8 bits. Nibble : Nibble is a group of bits the computer recognizes and process at a time. Instruction: A instruction is a binary pattern designed inside a microprocessor to perform a specific function.



16. What is a bus? Bus is a group of conducting lines that carries data, address and control signals.

17. Define MPU The terms microprocessor and microprocessor unit (MPU) are often used synonymously. MPU implies a complete processing unit width the necessary control signals. Because of the limited number of available pins on a microprocessor package, some of signals (Such as control and multiplexed signals) need to be generated by using discrete devices to make the microprocessor a complete functional unit or MPU. 18. List the four operations commonly performed by the MPU?

The MPU performs primarily operations 1. Memory Read: Reads data (or instructions) from memory. 2. Memory Write: Write data (or instructions) into memory 3. I / O Read : Accept data from input devices. 4. I / O Write : Sends data to output devices.

19. Define the address bus:

The address bus is a group of 16 lines ( A0 to A15) used to identify a peripheral or a memory location. It carries a 16 bit address.

20.Mention the steps, the MPU needs to communicate with the

peripheral. 1. Identify the peripheral or the memory location (with its address) 2. Transfer binary information (data and instructions) 3. Provide timing or synchronization signals.

These functions are performed by a three sets of communication lines called buses.

i. address bus ii. Data bus iii. Control bus

21. Define data bus:

The data bus is a group of eight lines used for data flow. It performs the transferring of binary information.

22. Why 8085 is known as 8 – bit microprocessor?

8085 Microprocessor has 8 data lines. So it is known as 8 – bit microprocessor. 23. Define control bus?

Control bus is not a group of lines like address or data buses, but individual lines that provide a pulse to indicate an MPU operation.

These signals are used to identify a device type with which the MPU intends to communicate.



24. Why is the data bus bidirectional? The data buses are bidirectional since the data flow is in both directions between

the MPU and memory and peripheral. 25. Why is the address bus unidirectional?

The address bus is unidirectional since the bits flow in one direction – from the MPU to peripheral devices.

26. How many memory location can be addressed by a microprocessor with n address lines?

The 8085 MPU with its n address lines is capable of addressing 2n memory locations. Example: 8 bit microprocessor addresses

27. Specify the four control signals commonly used by the 8085 MPU? The four control signals are generated by combining the signals WRRD, and IO / M . They are i. MEMR (Memory Read) ii. MEMW (Memory write) iii. IOR (I / O Read) iv. IOW (I / O write )

28. How an 8085 microprocessor can qualify as an MPU. i. The low – order address bus of the 8085 microprocessor is multiplexed

with the data bus. The buses need to be demultiplexed ii. Interface memory and I / O with the 8085.

29. List the four categories of 8085 instructions that manipulate data.

i. Data Transfer (copy) Instructions ii. Arithmetic instructions. iii. Logical instructions. iv. Branch Instructions

30. How many instructions are available in 8085 instruction set?

8085 microprocessor has 74 operation codes that result in a 246 instructions. 31. How 8085 microprocessor operations are classified?

The 8085 microprocessor are classified into five major groups. They are data transfer (copy), arithmetic, logic, branch and machine control.

32. Define Opcode and operand? An instruction has two parts

i. Opcode (Operation to be performed) ii. Operand (data to be operated on)



Opcode: Operation code is the task to be performed. Operand: Operand is the data to be operated on Example: MOV C, A Operand [C, A]→ Opcode [MOV] 33. How 8085 instructions are classified according to the work size or

byte size? Instruction set is classified according to the word size as,

i. 1 - byte instructions ii. 2 – byte instructions iii. 3 – byte instructions

34. What is addressing and what are the addressing modes available in

8085 Every instruction of a program has to operate on a data. Te method of

specifying the data to be operated by the instruction is called addressing (i.e the various way of specifying data are called addressing modes)

The 8085 supports five addressing modes and they are, i. Immediate addressing ii. Direct addressing iii. Register addressing iv. Register indirect addressing v. Implied addressing.

35. Explain the immediate addressing with an example

In immediate addressing mode, the data is specified in the instruction itself. The data will be a part of the program instruction.

Example: MVI B, 3 E H Move the data 3 E given in the instruction to B – register. 36. Direct Addressing

In direct addressing mode, the address of the data is specified in the instruction. The data will be in memory. In this addressing mode, the program instructions and data can be stored in different memory locations.

Example: LDA 1050 H – load the data available in memory location 1050 H in accumulator. 37. Explain register addressing with an example?

In register addressing mode, the instruction specifies the name of the register in which the data is available.

Example: MOV A, B -Move the content of B register to A register. 38. What is register indirect addressing? Give an example



In register indirect addressing mode, the instruction specifies the name of the register I which the address of the data is available.. Here the data will be in memory w and the address will be in a register pair

Example: MOV A, M – The memory data addressed by HL pair is moved ot A – register. 39. Explain the implied addressing with an example

In implied addressing mode, the instruction itself specifies the data to be operated. Example: CMA - Complement the content of the accumulator. 40. In which unit arithmetic and logical operations are performed and

where the result is stored? The arithmetic and logical operations are performed in ALU. After the operation

the result will be stored in accumulator. 41. Which group of instruction affects the flag?

The flags are altered after execution of arithmetic and logical instructions 42. What are the arithmetic instructions that do not effect the flag?

The 16 - bit increment and decrement instructions (IN X rp and DCX rp) will not affect any flags.

43. What are the flags affected by 8 – bit increment and decrement

instructions? Except carry, all other flags are affected by 8 – bit increment and decrement

instructions. 44. List the instructions that effect only carry flag.

The instructions that effect only carry flag are the following 1. CMC

2. DAD rP

3. RAL

4. RAR

5. RLC

6. RRC

7. STC

45. List the various instructions that can be used to clear accumulator? The accumulator can be cleared by the following instruction.

1. MVI A, 00H 2. SUB A



3. ANI OOH

4. XRA A

46. Why the program counter and the stack pointer are 16 – Bit registers?

Program counter (Pc) and stack pointer (Sp) are 16 – bit registers used to hold memory addresses. The size of these registers is 16 bits, because the memory addresses are 16 bits.

47. What is machine cycle?

Each instruction of the 8085 microprocessor can be divided into a few basic operations called machine cycle and each machine cycle can be divided into T – states.

48. What are the machine cycles available in 8085 microprocessor?

The various machine cycles of 8085 are 1. Opcode fetch cycle 2. Memory Read cycle 3. Memory Write cycle 4. I / O Read cycle 5. I / O Write cycle 6. Interrupt acknowledge cycle 7. Bus idle cycle

49. What is T - State? The T- state is the time period of the internal clock of the processor. The time

taken by the processor to execute a machine cycle is expressed in T – State. 50.What is flag?

The data conditions, after an arithmetic or logical operation are indicated by setting or resetting the flip-flops called flags.

51.Write the 8085 machine cycle status and control signals. Machine cycle Status Control signals MOI / S, S0

Opcode fetch 0 1 1 0=RD

Memory read 0 1 1 0=RD

Memory Write 0 0 1 0=WR

I / O Read 1 1 0 0=RD

I / O Write 1 0 1 0=WR

Interrupt Acknowledge 1 1 1 0=INTR



Halt Z 0 0

Hold Z X X ZWRRD =, and 1=INTA

Reset Z X X

52. How 8085 can be used as an MPU? 8085 Microprocessor can be used as an MPU but with the following tow

limitations. 1. The low –order address bus of the 8085 multiplexer is multiplexed with

the data bus. Te buses need to be demultiplexed. 2. Appropriate control signals need to be generated to interface memory and

I/O with the 8085. 53. Define mnemonics?

The short hand forms of describing the instructions are called mnemonics. They are given by manufacturer of [company] microprocessors and programmable devices.

Example: Intel Corporation.

54. What is Opcode fetch cycle? The Opcode fetch cycle is a machine cycle executed to fetch the opcode of an

instruction stored in memory. The first machine cycle of every instruction is opcode fetch machine cycle.

16 MARKS

1. Draw and explain the operation of 8085 MPU and its architecture.



Architecture of 8085 Microprocessor

8085 Bus Structure:

Address Bus: • The address bus is a group of 16 lines generally identified as A0 to A15. • The address bus is unidirectional: bits flow in one direction—from the MPU to

peripheral devices. • The MPU uses the address bus to perform the first function: identifying a

peripheral or a memory location.



Data Bus: • The data bus is a group of eight lines used for data flow. • These lines are bi-directional - data flow in both directions between the MPU and

memory and peripheral devices. • The MPU uses the data bus to perform the second function : transferring binary

information . • The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to

FF (28 = 256 numbers). • The largest number that can appear on the data bus is 11111111.

Control Bus: • The control bus carries synchronization signals and providing timing signals. • The MPU generates specific control signals for every operation it performs. These

signals are used to identify a device type with which the MPU wants to communicate.

Registers of 8085:



• The 8085 have six general-purpose registers to store 8-bit data during program execution.

• These registers are identified as B, C, D, E, H, and L. • They can be combined as register pairs—BC, DE, and HL—to perform some 16-

bit operations.

Accumulator (A): • The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU). • This register is used to store 8-bit data and to perform arithmetic and logical

operations. • The result of an operation is stored in the accumulator.

Flags: • The ALU includes five flip-flops that are set or reset according to the result of an

operation. • The microprocessor uses the flags for testing the data conditions. • They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC)

flags. The most commonly used flags are Sign, Zero, and Carry. • The bit position for the flags in flag register is,

D7 D6 D5 D4 D3 D2 D1 D0 S Z AC P CY

(1) Sign Flag (S):

• After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign flag is set. Otherwise it is reset.

• D7 is reserved for indicating the sign; the remaining is the magnitude of number.

• If D7 is 1, the number will be viewed as negative number. If D7 is 0, the number will be viewed as positive number.

(2) Zero Flag (z): If the result of arithmetic and logical operation is zero, then zero

flag is set otherwise it is reset. (3) Auxiliary Carry Flag (AC): If D3 generates any carry when doing

any arithmetic and logical operation, this flag is set. Otherwise it is reset. (4) Parity Flag (P): If the result of arithmetic and logical operation contains even

number of 1’s then this flag will be set and if it is odd number of 1’s it will be reset.

(5) Carry Flag (CY): If any arithmetic and logical operation results any

carry then carry flag is set otherwise it is reset.



Arithmetic and Logic Unit (ALU):

• It is used to perform the arithmetic operations like addition, subtraction, multiplication, division, increment and decrement and logical operations like AND, OR and EX-OR.

• It receives the data from accumulator and registers. • According to the result it set or reset the flags.

Program Counter (PC):

• This 16-bit register sequencing the execution of instructions. • It is a memory pointer. Memory locations have 16-bit addresses, and that is why

this is a 16-bit register. • The function of the program counter is to point to the memory address of the next

instruction to be executed. • When a opcode is being fetched, the program counter is incremented by one to

point to the next memory location. Stack Pointer (Sp):

• The stack pointer is also a 16-bit register used as a memory pointer. • It points to a memory location in R/W memory, called the stack. • The beginning of the stack is defined by loading a 16-bit address in the stack

pointer (register).

Temporary Register: It is used to hold the data during the arithmetic and logical operations.

Instruction Register: When an instruction is fetched from the memory, it is loaded in the instruction register. Instruction Decoder: It gets the instruction from the instruction register and decodes the instruction. It identifies the instruction to be performed. Serial I/O Control: It has two control signals named SID and SOD for serial data transmission. Timing and Control unit:

• It has three control signals ALE, RD (Active low) and WR (Active low) and three status signals IO/M(Active low), S0 and S1.

• ALE is used for provide control signal to synchronize the components of microprocessor and timing for instruction to perform the operation.



• RD (Active low) and WR (Active low) are used to indicate whether the operation is reading the data from memory or writing the data into memory respectively.

• IO/M(Active low) is used to indicate whether the operation is belongs to the memory or peripherals.

• If,

IO/M(Active Low) S1 S2 Data Bus Status(Output)

0 0 0 Halt

0 0 1 Memory WRITE

0 1 0 Memory READ

1 0 1 IO WRITE

1 1 0 IO READ

0 1 1 Opcode fetch

1 1 1 Interrupt acknowledge

Interrupt Control Unit: It receives hardware interrupt signals and sends an acknowledgement for receiving the interrupt signal. (2) DRAW & DISCUSS THE PIN CONFIGURATION OF 8085.

The signals can be grouped as follows 1. Power supply and clock signals 2. Address bus 3. Data bus 4. Control and status signals 5. Interrupts and externally initiated signals 6. Serial I/O ports

1. Power supply and Clock frequency signals: • Vcc + 5 volt power supply • Vss Ground • X1, X2 : Crystal or R/C network or LC network connections to set the

frequency of internal clock generator. • The frequency is internally divided by two. Since the basic operating timing

frequency is 3 MHz, a 6 MHz crystal is connected externally. • CLK (output)-Clock Output is used as the system clock for peripheral and devices

interfaced with the microprocessor.



Pin Diagram of 8085 Logical Schematics of 8085

2. Address Bus: • A8 — A15 (output; 3-state) • It carries the most significant 8 bits of the memory address or the 8 bits of the I/O

address; 3. Multiplexed Address / Data Bus: • AD0 — AD7 (input/output; 3-state) • These multiplexed set of lines used to carry the lower order 8 bit address as well

as data bus. • During the opcode fetch operation, in the first clock cycle, the lines deliver the

lower order address A0 - A7. • In the subsequent IO / memory, read / write clock cycle the lines are used as data

bus. • The CPU may read or write out data through these lines.



4. Control and Status signals: • ALE (output) - Address Latch Enable.

This signal helps to capture the lower order address presented on the multiplexed address / data bus.

• RD (output 3-state, active low) — Read memory or IO device. This indicates that the selected memory location or I/O device is to be read and that the data bus is ready for accepting data from the memory or I/O device.

• WR (output 3-state, active low) - Write memory or IO device. This indicates that the data on the data bus is to be written into the selected memory location or I/O device.

• IO/M (output) - Select memory or an IO device. This status signal indicates that the read / write operation relates to

whether the memory or I/O device. It goes high to indicate an I/O operation. It goes low for memory operations.

5. Status Signals: • It is used to know the type of current operation of the microprocessor.

IO/M(Active Low) S1 S2 Data Bus Status (Output)

0 0 0 Halt

0 0 1 Memory WRITE

0 1 0 Memory READ

1 0 1 IO WRITE

1 1 0 IO READ

0 1 1 Opcode fetch

1 1 1 Interrupt acknowledge

6. Interrupts and Externally initiated operations: • They are the signals initiated by an external device to request the microprocessor

to do a particular task or work. • There are five hardware interrupts called,



• On receipt of an interrupt, the microprocessor acknowledges the interrupt by the

active low INTA (Interrupt Acknowledge) signal. Reset In (input, active low) • This signal is used to reset the microprocessor. • The program counter inside the microprocessor is set to zero. • The buses are tri-stated. Reset Out (Output) • It indicates CPU is being reset. • Used to reset all the connected devices when the microprocessor is reset. 7. Direct Memory Access (DMA):

Tri state devices:

• 3 output states are high & low states and additionally a high impedance state. • When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is

0, Q is 1, otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters into a high impedance state.

E A Q State

1(high) 0 1 High 1 1 0 Low

0(low) 0 0 High impedance

0 1 0 High impedance



• For both high and low states, the output Q draws a current from the input of the

OR gate. • When E is low, Q enters a high impedance state; high impedance means it is

electrically isolated from the OR gate’s input, though it is physically connected. Therefore, it does not draw any current from the OR gate’s input.

• When 2 or more devices are connected to a common bus, to prevent the devices from interfering with each other, the tristate gates are used to disconnect all devices except the one that is communicating at a given instant.

• The CPU controls the data transfer operation between memory and I/O device. Direct Memory Access operation is used for large volume data transfer between memory and an I/O device directly.

• The CPU is disabled by tri-stating its buses and the transfer is effected directly by external control circuits.

• HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the microprocessor acknowledges the request by sending out HLDA signal and leaves out the control of the buses. After the HLDA signal the DMA controller starts the direct transfer of data.

READY (input) • Memory and I/O devices will have slower response compared to microprocessors. • Before completing the present job such a slow peripheral may not be able to

handle further data or control signal from CPU. • The processor sets the READY signal after completing the present job to access

the data. • The microprocessor enters into WAIT state while the READY pin is disabled. 8. Single Bit Serial I/O ports: • SID (input) - Serial input data line • SOD (output) - Serial output data line • These signals are used for serial communication.

(3) DRAW & DISCUSS THE MEMORY INTERFACING. • The memory is made up of semiconductor material used to store the programs

and data. • Three types of memory is,

Process memory



Primary or main memory Secondary memory

TYPICAL EPROM AND STATIC RAM: • A typical semiconductor memory IC will have n address pins, m data pins (or

output pins). • Having two power supply pins (one for connecting required supply voltage (V

and the other for connecting ground). • The control signals needed for static RAM are chip select (chip enable), read

control (output enable) and write control (write enable). • The control signals needed for read operation in EPROM are chip select (chip

enable) and read control (output enable).

Number of Address Pins and Data Pins in Memory ICs



DECODER: • It is used to select the memory chip of processor during the execution of a

program. • No of IC used for decoder is,

2-4 decoder (74LS139) 3-8 decoder (74LS138)

Truth table for 2-4 decoder

2-4

DECODER 74LS139

Y3(active low)

Y2(active low)

Y1(active low)

Y0(active low)

A

B



Truth table for 3-8 decoder

Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface the EPROM with 8085 processor.

• The memory capacity is 64 Kbytes. i.e 2 n = 64 x 1000 bytes where n = address lines. So, n = 16.

• In this system the entire 16 address lines of the processor are connected to address input pins of memory IC in order to address the internal locations of memory.

• The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground).

• Since the processor is connected to EPROM, the active low RD pin is connected to active low output enable pin of EPROM.

• The range of address for EPROM is 0000H to FFFFH.



Interfacing 64Kb EPROM with 8085

Consider a system in which the available 64kb memory space is equally

divided between EPROM and RAM. Interface the EPROM and RAM with 8085 processor.

• Implement 32kb memory capacity of EPROM using single IC 27256. • 32kb RAM capacity is implemented using single IC 62256. • The 32kb memory requires 15 address lines and so the address lines A0 –

A14 of the processor are connected to 15 address pins of both EPROM and RAM.

• The unused address line A15 is used as to chip select. If A15 is 1, it select RAM and If A15 is 0, it select EPROM.

• Inverter is used for selecting the memory. • The memory used is both Ram and EPROM, so the low RD and WR pins

of processor are connected to low WE and OE pins of memory respectively.

• The address range of EPROM will be 0000H to 7FFFH and that of RAM will be 7FFFH to FFFFH.



Interfacing 32Kb EPROM and 32Kb RAM with 8085

Consider a system in which 32kb memory space is implemented using four

numbers of 8kb memory. Interface the EPROM and RAM with 8085 processor.

• The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the remaining two numbers be RAM.

• Each 8kb memory requires 13 address lines and so the address lines A0- A12 of the processor are connected to 13 address pins of all the memory.

• The address lines and A13 – A14 can be decoded using a 2-to-4 decoder to generate four chip select signals.

• These four chip select signals can be used to select one of the four memory IC at any one time.

• The address line A15 is used as enable for decoder. • The simplified schematic memory organization is shown.



Interfacing 16Kb EPROM and 16Kb RAM with 8085

• The address allotted to each memory IC is shown in following table.



Consider a system in which the 64kb memory space is implemented using eight numbers of 8kb memory. Interface the EPROM and RAM with 8085 processor.

• The total memory capacity is 64Kb. So, let 4 numbers of 8Kb EPROM and 4 numbers of 8Kb RAM.

• Each 8kb memory requires 13 address lines. So the address line A0 – A12 of the processor are connected to 13address pins of all the memory lCs.



• The address lines A13, A14 and A]5 are decoded using a 3-to-8 coder to generate eight chip select signals. These eight chip select signals can be used to select one of the eight memories at any one time.

• The memory interfacing is shown in following figure.

Interfacing 4 no. 8Kb EPROM and 4 no. 8Kb RAM with 8085

• The address allocation for Interfacing 4 no. 8Kb EPROM and 4 no. 8Kb RAM with 8085 is,





(3) DRAW & EXPLAIN MEMORY & I/O INTERFACING.

I/O STRUCTURE OF A TYPICAL MICROCOMPUTER: There are three major types of data transfer between the microcomputer and art

I/O device. They are,

• Programmed I/O : In programmed I/O the data transfer is accomplished through an I/O port and controlled by software.

• Interrupt driven I/O : In interrupt driven I/O, the I/O device will interrupt the processor, and initiate data transfer.

• Direct memory access (DMA) : In DMA, the data transfer between memory and I/O can be performed by bypassing the microprocessor.

I/O structure of a typical microcomputer

INTERFACING I/O AND PERIPHERAL DEVICES: For data transfer from input device to processor the following operations are performed.

• The input device will load the data to the port. • When the port receives a data, it sends message to the processor to read the data. • The processor will read the data from the port. • After a data have been read by the processor the input device will load the next

data into the port. For data transfer from processor to output device the following operations are

performed. • The processor will load the data to the port. • The port will send a message to the output device to read the data. • The output device will read the data from the port.



• After the data have been read by the output device the processor can load the next data to the port.

The various INTEL 110 port devices are 8212, 8155/8156, 8255, 8355 and 8755. 8212

• The 8212 is a 24 pin IC. • It consists of eight number of D-type latches. • It has 8-input lines DI1 to DI8 and 8-output lines DO1 to DO8 • The 8212 can be used as an input or output device • It has two selecting device DS1 (low) and DS2. • If,

8155:

• It has two numbers of 8-bit parallel I/O port (port-A and B) • One number of 6-bit parallel I/O port (port-C). • It has 14 bit timer (operating in 4 modes). • It has six internal addresses. • It has one chip select pin CS (low).

Internal address of 8155

8156: • It has two numbers of 8-bit parallel I/O port (port-A and B) • One number of 6-bit parallel 1 port (port-C). • It has 14 bit timer (operating in 4 modes). • It has six internal addresses. • It has one chip select pin CS (low).




8255:

• It has 3 numbers of 8-bit parallel I/O ports (port A, B and C). • Port-A can be programmed in mode-0 mode-1 or mode-2 as input or output port. • Port-B can be programmed in mode-1 and mode-2 as 1/Oport. • When ports A and B are in mode-0, the port-C can be used as I/O port. • One logic low chip select (CS) pin. • It requires four internal addresses


8355:

• It has 2KB ROM. • It has two number of 8 bit port (A,B). • It has one CS(low). • It has four internal addresses.

Internal address of 8355 Internal address of 8755

8755:

• It has 2Kb EPROM. • It has two number of 8 bit port (A,B). • It has one CS(low). • It has four internal addresses.



There are two types for interfacing I/O devices:

1. Memory mapped I/O device. 2. Standard I/O mapped I/O device or isolated I/O mapping.



In a microprocessor system using 8085, the memory requirement is 8kb

EPROM and 8kb RAM. For interfacing I/O devices, three numbers of 8255

are required. Select suitable memories and explain how they are interfaced to

the system. Interface the 8255 by memory mapping.

The IC 2764 is selected for EPROM memory and the IC 6264 is selected for

RAM memory. Both the memory lC have time compatibility with 8085 processor. The 8kb EPROM, 2764 require 13 address tines. The 8kb RAM, 6264 require 13

address lines. The address lines A0 to A12 are connected to both EPROM and RAM memory

ICs.



The 8255 require four internal addresses. Let us connect A1 of 8085 to A0 of 8255 and A2 of 8085 to A1 of 8255. The 8255 is memory mapped in the system. For the memories and 8255’s we require 5 chip-select signals. Hence we can use a

3-to-8 decoder 74LS138 for generating eight chip-select signals by decoding the unused address lines A13, A14 and A15.

The decoder enable pins are permanently tied to appropriate levels. In the eight chips select signals five are used for selecting memory ICs and 8255, and the remaining three can be used for future expansion.

The EPROM is mapped at the starting of memory space. The RAM is mapped at the end of memory space. The EPROM is mapped from 0000H to IFFFH. The RAM is mapped from E000H to FFFFH.

The four internal devices of 8255 are control register, port-A, port-B and port-C. A 16-bit address is allotted to each internal device of 8255.

Memory and I/O Port Interfacing with 8085



The 16 bit address for the memory and 8255 devices are,





A system requires 16kb EPROM and 16kb RAM. Also the system has 2

numbers of 8255, one number of 8279, one number of 8251 and one number of 8254.

(8255 - Programmable peripheral interface; 8279-Keyboard/display controller, 8251

– USART and 8254 - Timer). Draw the Interface diagram. Allocate addresses to all

the devices. The peripheral IC should be I/O mapped.

• The I/O devices in the system should be mapped by standard I/O mapping. Hence

separate decoders can be used to generate chip select signals for memory IC and

peripheral IC’s.

• For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM.

• For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM.

• The 8kb memories require 13 address lines. Hence the address lines A0 – A12 are

used for selecting the memory locations.

• The unused address lines A13, A14 and A15 are used as input to decoder 74LS138 (3-

to-8-deeoder) of memory IC. The logic low enables of this decoder are tied to IO/ M(low)

of 8085, so that this decoder is enabled for memory read/write operation. The other

enable pins of decoder are tied to appropriate logic levels permanently. The 4-outputs of

the decoder are used to select memory lCs and the remaining 4 are kept for future

expansion.

• The EPROM is mapped in the beginning of memory space from 0000H to 3FFF.

• The RAM is mapped at the end of memory space from C000 to FFFFH.

• There are five peripheral IC’s to be interfaced to the system. The chip-select signals

for these IC’s are given through another 3-to-8 decoder 74LS138 (I/O decoder). The

input to this decoder is A11, A12 and A13

• The address lines A13, A14 and A15 are logically ORed and applied to low enable of I/O

decoder.

• The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085, so that this

decoder is enabled for I/O read/write operation.










A system requires 8kb EPROM and 8kb RAM. Also the system has 2

numbers of 8155. Draw the Interface diagram. Allocate addresses to all the devices.

The peripheral IC should be I/O mapped.

• The IC 2764 (8k x 8) is selected for EPROM memory and IC 6264 (8k x 8) is

selected for RAM memory. Both the memory IC has time compatibility with 8085

processor.

• The 8kb memory requires 13 address lines. Hence the address lines A0 – A12 are

used to select memory locations.

• The RAM locations of 8155 are selected by address lines A0 to A7.

• 3-to-8 decoder, 74LS138 is used for generating chip select signals by decoding

the address lines A13, A14 and A15.

• Eight bit addresses are allotted to ports of 8l55 and sixteen bit addresses are

allotted to RAM memory locations of 8155.








(5) DRAW & DISCUSS TIMING DIAGRAM. Instruction Cycle: The time required to execute an instruction is called instruction cycle.

Machine Cycle: The time required to access the memory or input/output devices is called machine cycle.

T-State: • The machine cycle and instruction cycle takes multiple clock periods. • A portion of an operation carried out in one system clock period is called as T-

state.

MACHINE CYCLES OF 8085:

The 8085 microprocessor has 5 (seven) basic machine cycles. They are

1. Opcode fetch cycle (4T) 2. Memory read cycle (3 T) 3. Memory write cycle (3 T) 4. I/O read cycle (3 T) 5. I/O write cycle (3 T)

• Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when the 8085 processor executes an instruction, it will execute some of the machine cycles in a specific order.

• The processor takes a definite time to execute the machine cycles. The time taken by the processor to execute a machine cycle is expressed in T-states.

• One T-state is equal to the time period of the internal clock signal of the processor.

• The T-state starts at the falling edge of a clock.



Opcode fetch machine cycle of 8085 :

Each instruction of the processor has one byte opcode.

The opcodes are stored in memory. So, the processor executes the opcode fetch

machine cycle to fetch the opcode from memory.

Hence, every instruction starts with opcode fetch machine cycle.

The time taken by the processor to execute the opcode fetch cycle is 4T.

In this time, the first, 3 T-states are used for fetching the opcode from memory

and the remaining T-states are used for internal operations by the processor.



Timing Diagram for Opcode Fetch Machine Cycle

Memory Read Machine Cycle of 8085:

The memory read machine cycle is executed by the processor to read a data

byte from memory.

The processor takes 3T states to execute this cycle.

The instructions which have more than one byte word size will use the

machine cycle after the opcode fetch machine cycle.



Timing Diagram for Memory Read Machine Cycle Memory Write Machine Cycle of 8085:

The memory write machine cycle is executed by the processor to write a data byte

in a memory location.

The processor takes, 3T states to execute this machine cycle.



Timing Diagram For Memory Write Machine Cycle

I/O Read Cycle of 8085:

The I/O Read cycle is executed by the processor to read a data byte from I/O port

or from the peripheral, which is I/O, mapped in the system.

The processor takes 3T states to execute this machine cycle.

The IN instruction uses this machine cycle during the execution.



Timing Diagram for I/O Read Machine Cycle

I/O Write Cycle of 8085:

The I/O write machine cycle is executed by the processor to write a data byte in

the I/O port or to a peripheral, which is I/O, mapped in the system.

The processor takes, 3T states to execute this machine cycle.



Timing Diagram for I/O Write Machine Cycle TIMING DIAGRAM OF 8085 INSTRUCTIONS:

• The 8085 instructions consist of one to five machine cycles. • Actually the execution of an instruction is the execution of the machine cycles of

that instruction in the predefined order. • The timing diagram of an instruction ate obtained by drawing the timing diagrams

of the machine cycles of that instruction, one by one in the order of execution.

1. Timing diagram for STA 526AH.

Fetching the Opcode 32H from the memory 41FFH. Read the lower order memory address. Read the higher order memory address. Write the accumulator content into memory location 526AH.



Assume the memory address for the instruction and let the content of accumulator is C7H.

Address Mnemonics Opcode

41FF STA 526AH 32H

4200 6AH

4201 52H

2.Timing diagram for IN C0H.

Fetching the Opcode DBH from the memory 4125H. Read the port address C0H from 4126H. Read the content of port C0H and send it to the accumulator.



Let the content of port is 5EH.


4125 IN C0H DBH

4126 C0H

3. Timing diagram for INR M.

Fetching the Opcode 34H from the memory 4105H. Let the memory address (M) is 4250H. Let the content of that memory is 12H.



Increment the memory content from 12H to 13H.


4105 INR M 34H

4. Timing diagram for MVI B, 43H

.

Fetching the Opcode 06H from the memory 2000H. Read the data 43H from memory 2001H.




2000 MVI B, 43H 06H

2001 43H

(6) DRAW & DISCUSS ABOUT 8085 INTERRUPTS.

• Interrupt is signals send by an external device to the processor, to request the processor to perform a particular task or work.

• Mainly in the microprocessor based system the interrupts are used for data transfer between the peripheral and the microprocessor.

• The processor will check the interrupts always at the 2nd T-state of last machine cycle.

• If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the peripheral.

• The vectored address of particular interrupt is stored in program counter.



• The processor executes an interrupt service routine (ISR) addressed in program counter.

• It returned to main program by RET instruction.

Types of Interrupts: It supports two types of interrupts.

1. Hardware 2. Software Software interrupts:

• The software interrupts are program instructions. These instructions are inserted at desired locations in a program.

• The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for these interrupts can be calculated as follows.

Interrupt number * 8 = vector address For RST 5, 5 * 8 = 40 = 28H

Vector address for interrupt RST 5 is 0028H The Table shows the vector addresses of all interrupts.

• The software interrupts of 8085 are vectored interrupts. • The software interrupts cannot be masked and they cannot be disabled.

Hardware interrupts:

• An external device initiates the hardware interrupts and placing an appropriate signal at the interrupt pin of the processor.

• If the interrupt is accepted then the processor executes an interrupt service routine.

• The 80S5 has five hardware interrupts (1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR



TRAP :

• This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable.

• TRAP bas the highest priority and vectored interrupt. • TRAP interrupt is edge and level triggered. This means hat the TRAP must go

high and remain high until it is acknowledged. • In sudden power failure, it executes a ISR and send the data from main memory to

backup memory. • The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor

receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).

• There are two ways to clear TRAP interrupt. 2) By resetting microprocessor (External signal) 3) By giving a high TRAP ACKNOWLEDGE (Internal signal)

RST 7.5: • The RST 7.5 interrupt is a maskable interrupt. • It has the second highest priority. • It is edge sensitive. ie. Input goes to high and no need to maintain high state until

it recognized. • Maskable interrupt. It is disabled by,

DI instruction System or processor reset. After reorganization of interrupt.

• Enabled by EI instruction.

RST 6.5 and 5.5 : • The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay

high until it recognized. • Maskable interrupt. It is disabled by,

DI, SIM instruction System or processor reset. After reorganization of interrupt.

• Enabled by EI instruction. • The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.



INTR: • INTR is a maskable interrupt. It is disabled by,

DI, SIM instruction System or processor reset. After reorganization of interrupt.

• Enabled by EI instruction. • Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply

the address of ISR. • It has lowest priority. • It is a level sensitive interrupts. ie. Input goes to high and it is necessary to

maintain high state until it recognized. • The following sequence of events occurs when INTR signal goes high.

I) The 8085 checks the status of INTR signal during execution of each instruction. 2) If INTR signal is high, then 8085 completes its current instruction and sends

active low interrupt acknowledge signal, if the interrupt is enabled. 3) In response to the acknowledge signal, external logic places an instruction

OPCODE on the data bus. In the case of multibyte instruction, additional interrupt acknowledge machine cycles are generated by the 8085 to transfer the additional bytes into the microprocessor.

4) On receiving the instruction, the 8085 save the address of next instruction on stack and execute received instruction.

SIM and RIM for interrupts:

• The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using SIM instruction.

• The status of these interrupts can be read by executing RIM instruction. • The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be

performed by moving an 8-bit data to accumulator and then executing SIM instruction.

• The format of the 8-bit data is shown below.



• The status of pending interrupts can be read from accumulator after executing

RIM instruction. • When RIM instruction is executed an 8-bit data is loaded in accumulator, which

can be interpreted as shown in fig.

Interrupt type Trigger Priority Maskable Vector address

TRAP Edge and Level 1st No 0024H

RST 7.5 Edge 2nd Yes 003CH

RST 6.5 Level 3rd Yes 0034H

RST 5.5 Level 4th Yes 002CH

INTR Level 5th Yes -

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Ec 1318 Microprocessor and Applications

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