EC6504 Microprocessor and Microcontroller Lecture Notes All 5 Units

EC6504Microprocessors and

MicrocontrollersDEPARTMENTS: CSE,IT,ECE,ECE,MECH

Regulation : 2013

Presented byC.GOKUL,AP/EEE

DEPARTMENTS: CSE,IT,ECE,ECE,MECHRegulation : 2013

1

Microprocessor• Microprocessor (µP) is the “brain” of a computer

that has been implemented on onesemiconductor chip.

• The word comes from the combination micro andprocessor.

• Processor means a device that processeswhatever(binary numbers, 0’s and 1’s)To process means to manipulate. It describes all

manipulation.Micro - > extremely small

• Microprocessor (µP) is the “brain” of a computerthat has been implemented on onesemiconductor chip.

• The word comes from the combination micro andprocessor.

• Processor means a device that processeswhatever(binary numbers, 0’s and 1’s)To process means to manipulate. It describes all

manipulation.Micro - > extremely small

2

Definition of a Microprocessor.

The microprocessor is aprogrammable device that takes in numbers,performs on them arithmetic or logicaloperations according to the program stored inmemory and then produces other numbers asa result.

The microprocessor is aprogrammable device that takes in numbers,performs on them arithmetic or logicaloperations according to the program stored inmemory and then produces other numbers asa result.

3

Microprocessor ?

A microprocessor is multiprogrammable clock driven

register based semiconductordevice that is used to fetch ,

process & execute a datawithin fraction of seconds.

A microprocessor is multiprogrammable clock driven

register based semiconductordevice that is used to fetch ,

process & execute a datawithin fraction of seconds.

4

Applications

• Calculators• Accounting system• Games machine• Instrumentation• Traffic light Control• Multi user, multi-function environments• Military applications• Communication systems

• Calculators• Accounting system• Games machine• Instrumentation• Traffic light Control• Multi user, multi-function environments• Military applications• Communication systems

5

MICROPROCESSOR HISTORY

6

DIFFERENT PROCESSORS AVAILABLE

SocketPinless

Processor

Processor SlotProcessor

ProcessorSlot

7

Development of Intel Microprocessors

• 8086 - 1979• 286 - 1982• 386 - 1985• 486 - 1989• Pentium - 1993• Pentium Pro - 1995• Pentium MMX -1997• Pentium II - 1997• Pentium II Celeron - 1998• Pentium II Zeon - 1998• Pentium III - 1999• Pentium III Zeon - 1999• Pentium IV - 2000• Pentium IV Zeon - 2001

• 8086 - 1979• 286 - 1982• 386 - 1985• 486 - 1989• Pentium - 1993• Pentium Pro - 1995• Pentium MMX -1997• Pentium II - 1997• Pentium II Celeron - 1998• Pentium II Zeon - 1998• Pentium III - 1999• Pentium III Zeon - 1999• Pentium IV - 2000• Pentium IV Zeon - 2001

8

GENERATION OF PROCESSORS

Processor Bits Speed

8080 8 2 MHz

8086 16 4.5 – 10MHz

4.5 – 10MHz

8088 16 4.5 – 10MHz

80286 16 10 – 20MHz

80386 32 20 – 40MHz

80486 32 40 – 133MHz

9

GENERATION OF PROCESSORS

Processor Bits Speed

Pentium 32 60 – 233MHz

PentiumPro

32 150 – 200MHz

Pentium II,Celeron ,

Xeon

32 233 – 450MHz

Pentium II,Celeron ,

Xeon

32 233 – 450MHz

PentiumIII, Celeron

, Xeon

32 450 MHz –1.4 GHz

Pentium IV,Celeron ,

Xeon

32 1.3 GHz –3.8 GHz

Itanium 64 800 MHz –3.0 GHz

10

Intel 4004 Introduced in 1971.

It was the first microprocessorby Intel.

It was a 4-bit µP.

Its clock speed was 740KHz.

It had 2,300 transistors.

It could execute around60,000 instructions persecond.

Introduced in 1971.

It was the first microprocessorby Intel.

It was a 4-bit µP.

Its clock speed was 740KHz.


It could execute around60,000 instructions persecond.

11

Intel 4040

Introduced in 1971.

It was also 4-bit µP.

12

8-bit Microprocessors

13

Intel 8008

Introduced in 1972.

It was first 8-bit µP.

Its clock speed was500 KHz.

Could execute50,000 instructionsper second.

Introduced in 1972.


Its clock speed was500 KHz.

Could execute50,000 instructionsper second.

14

Intel 8080

Introduced in 1974.


Its clock speed was2 MHz.

It had 6,000transistors.

Introduced in 1974.


Its clock speed was2 MHz.

It had 6,000transistors.

15

Intel 8085 Introduced in 1976.


Its clock speed was 3 MHz.

Its data bus is 8-bit andaddress bus is 16-bit.


Could execute 7,69,230instructions per second.

It could access 64 KB ofmemory.

It had 246 instructions.

Introduced in 1976.


Its clock speed was 3 MHz.

Its data bus is 8-bit andaddress bus is 16-bit.


Could execute 7,69,230instructions per second.

It could access 64 KB ofmemory.

It had 246 instructions.

16

16-bit Microprocessors

17

INTEL 8086 Introduced in 1978.


Its clock speed is 4.77 MHz, 8 MHzand 10 MHz, depending on theversion.

Its data bus is 16-bit and addressbus is 20-bit.


Could execute 2.5 millioninstructions per second.

It could access 1 MB of memory.

It had 22,000 instructions.

It hadMultiply and Divideinstructions.

Introduced in 1978.


Its clock speed is 4.77 MHz, 8 MHzand 10 MHz, depending on theversion.

Its data bus is 16-bit and addressbus is 20-bit.


Could execute 2.5 millioninstructions per second.

It could access 1 MB of memory.

It had 22,000 instructions.

It hadMultiply and Divideinstructions.

18



It was created as acheaper version ofIntel’s 8086.

It was a 16-bit processorwith an 8-bit externalbus.

Introduced in 1979.


It was created as acheaper version ofIntel’s 8086.

It was a 16-bit processorwith an 8-bit externalbus.

19

INTEL 80186 & 80188 Introduced in 1982. They were 16-bit µPs. Clock speed was 6 MHz. 80188 was a cheaper

version of 80186 with an8-bit external data bus.

Introduced in 1982. They were 16-bit µPs. Clock speed was 6 MHz. 80188 was a cheaper

version of 80186 with an8-bit external data bus.

20

INTEL 80286 Introduced in 1982. It was 16-bit µP. Its clock speed was 8

MHz. Its data bus is 16-bit

and address bus is 24-bit.

It could address 16 MBof memory.

It had 1,34,000transistors.

Introduced in 1982. It was 16-bit µP. Its clock speed was 8

MHz. Its data bus is 16-bit


It could address 16 MBof memory.


21

32-BIT MICROPROCESSORS

22

INTEL 80386 Introduced in 1986. It was first 32-bit µP. Its data bus is 32-bit


It could address 4 GB ofmemory.


Its clock speed variedfrom 16 MHz to 33 MHzdepending upon thevarious versions.

Introduced in 1986. It was first 32-bit µP. Its data bus is 32-bit


It could address 4 GB ofmemory.


Its clock speed variedfrom 16 MHz to 33 MHzdepending upon thevarious versions. 23



It had 1.2 milliontransistors.

Its clock speed variedfrom 16 MHz to 100MHz depending uponthe various versions.

8 KB of cache memorywas introduced.

Introduced in 1989.



Its clock speed variedfrom 16 MHz to 100MHz depending uponthe various versions.

8 KB of cache memorywas introduced.

24

INTEL PENTIUM Introduced in 1993.


It was originally named80586.

Its clock speed was 66MHz.

Its data bus is 32-bitand address bus is 32-bit.

Introduced in 1993.


It was originally named80586.

Its clock speed was 66MHz.

Its data bus is 32-bitand address bus is 32-bit.

25

INTEL PENTIUM PRO

Introduced in 1995.


It had 21 milliontransistors.

Cache memory: 8 KB for instructions.

8 KB for data.

Introduced in 1995.



Cache memory: 8 KB for instructions.

8 KB for data.

26

INTEL PENTIUM II Introduced in 1997.


Its clock speed was 233MHz to 500 MHz.

Could execute 333million instructions persecond.

Introduced in 1997.



Could execute 333million instructions persecond.

27

INTEL PENTIUM II XEON

Introduced in 1998.


It was designed forservers.


Introduced in 1998.


It was designed forservers.


28

INTEL PENTIUM III Introduced in 1999.


Its clock speed variedfrom 500 MHz to 1.4GHz.


Introduced in 1999.


Its clock speed variedfrom 500 MHz to 1.4GHz.


29

INTEL PENTIUM IV Introduced in 2000.


Its clock speed was from1.3 GHz to 3.8 GHz.


Introduced in 2000.


Its clock speed was from1.3 GHz to 3.8 GHz.


30

INTEL DUAL CORE Introduced in 2006.

It is 32-bit or 64-bit µP.

31

32

64-BIT MICROPROCESSORS

33

Intel Core 2 Intel Core i3

34

INTEL CORE I5 INTEL CORE I7

35

Basic Terms• Bit: A digit of the binary number { 0 or 1 }• Nibble: 4 bit Byte: 8 bit word: 16 bit• Double word: 32 bit• Data: binary number/code operated by an

instruction• Address: Identification number for memory

locations• Clock: square wave used to synchronize various

devices in µP• Memory Capacity = 2^n ,

n->no. of address lines

• Bit: A digit of the binary number { 0 or 1 }• Nibble: 4 bit Byte: 8 bit word: 16 bit• Double word: 32 bit• Data: binary number/code operated by an

instruction• Address: Identification number for memory

locations• Clock: square wave used to synchronize various

devices in µP• Memory Capacity = 2^n ,

n->no. of address lines

36

BUS CONCEPT• BUS: Group of conducting lines that carries data ,

address & control signals.CLASSIFICATION OF BUSES:1.DATA BUS: group of conducting lines that carries

data.2. ADDRESS BUS: group of conducting lines that

carries address.3.CONTROL BUS: group of conducting lines that

carries control signals {RD, WR etc}CPU BUS: group of conducting lines that directly

connected to µPSYSTEM BUS: group of conducting lines that carries

data , address & control signals in a µP system

• BUS: Group of conducting lines that carries data ,address & control signals.

CLASSIFICATION OF BUSES:1.DATA BUS: group of conducting lines that carries

data.2. ADDRESS BUS: group of conducting lines that

carries address.3.CONTROL BUS: group of conducting lines that

carries control signals {RD, WR etc}CPU BUS: group of conducting lines that directly

connected to µPSYSTEM BUS: group of conducting lines that carries

data , address & control signals in a µP system37

TRISTATE LOGIC3 logic levels are:• High State (logic 1)• Low state (logic 0)• High Impedance state

High Impedance: output is not being driven to any defined logic levelby the output circuit.

3 logic levels are:• High State (logic 1)• Low state (logic 0)• High Impedance state

High Impedance: output is not being driven to any defined logic levelby the output circuit.

38

Basic Microprocessors System

InputDevices

ProcessingData into

Information

OutputDevices

ControlControlUnitUnit

ArithmeticArithmetic--LogicLogicUnitUnit

Central Processing Unit

InputDevices

ProcessingData into

Information

OutputDevices

Secondary Storage Devices

Primary StoragePrimary StorageUnitUnit

Keyboard,Mouseetc

MonitorPrinter

Disks, Tapes, Optical Disks

39

UNITUNIT

11THE 8086 MICROPROCESSOR

UNITUNIT

11

40

8086 Microprocessor-introduction

INTEL launched 8086 in 19788086 is a 16-bit microprocessor with

• 16-bit Data Bus {D0-D15}• 20-bit Address Bus {A0-A19} [can access upto

2^20= 1 MB memory locations] .It has multiplexed address and data bus

AD0-AD15 and A16–A19.It can support upto 64K I/O ports

INTEL launched 8086 in 19788086 is a 16-bit microprocessor with

• 16-bit Data Bus {D0-D15}• 20-bit Address Bus {A0-A19} [can access upto

2^20= 1 MB memory locations] .It has multiplexed address and data bus

AD0-AD15 and A16–A19.It can support upto 64K I/O ports

41

8086 Microprocessor

It provides 14, 16-bit registers.8086 requires one phase clock with a 33%

duty cycle to provide optimized internaltiming.

– Range of clock:• 5 MHz for 8086• 8Mhz for 8086-2• 10Mhz for 8086-1

It provides 14, 16-bit registers.8086 requires one phase clock with a 33%

duty cycle to provide optimized internaltiming.

– Range of clock:• 5 MHz for 8086• 8Mhz for 8086-2• 10Mhz for 8086-1

42

INTEL 8086 - Pin Diagram/Signal Description

43

INTEL 8086 - Pin Details

Ground

Power Supply5V 10%

ResetRegisters, seg

regs, flags

CS: FFFFH, IP:0000H

If high forminimum 4

clksClockDuty cycle: 33%

ResetRegisters, seg

regs, flags

CS: FFFFH, IP:0000H

If high forminimum 4

clks

44


Address/Data Bus:

Contains addressbits A15-A0 when ALEis 1 & data bits D15 –

D0 when ALE is 0.

Address Latch Enable:

When high,multiplexed

address/data buscontains address

information.

Address/Data Bus:

Contains addressbits A15-A0 when ALEis 1 & data bits D15 –

D0 when ALE is 0.

Address Latch Enable:

When high,multiplexed

address/data buscontains address

information.

45


INTERRUPT

Non - maskableinterrupt

Interrupt request

Interruptacknowledge

46


DirectMemoryAccess

Hold

Holdacknowledge

Hold

47


Address/Status Bus

Address bits A19 –A16 & Status bits S6

– S3

48


Bus High Enable/S7

Enables mostsignificant data bitsD15 – D8 during reador write operation.

S7: Always 1.

BHE#, A0:

0,0: Whole word(16-bits)

0,1: High byteto/from odd address

1,0: Low byteto/from even address

1,1: No selection

Bus High Enable/S7

Enables mostsignificant data bitsD15 – D8 during reador write operation.

S7: Always 1.

BHE#, A0:

0,0: Whole word(16-bits)

0,1: High byteto/from odd address

1,0: Low byteto/from even address

1,1: No selection

49


Min/Max modeMinimum Mode: +5V

Maximum Mode: 0V

Minimum Mode Pins

Maximum ModePins

50

Minimum Mode- Pin Details

Read Signal

Write SignalWrite Signal

Memory or I/0

Data Bus Enable

DataTransmit/Receive

51

Maximum Mode - Pin Details

S2 S1 S0

000: INTA001: read I/O port010: write I/O port011: halt100: code access101: read memory110: write memory111: none -passive

Status Signal

Inputs to 8288 togenerate eliminatedsignals due to max

mode.

S2 S1 S0

000: INTA001: read I/O port010: write I/O port011: halt100: code access101: read memory110: write memory111: none -passive

52


DMARequest/Grant

Lock OutputUsed to lock peripheralsoff the system

Activated by using theLOCK: prefix on anyinstruction

DMARequest/Grant

Lock Output

Lock OutputUsed to lock peripheralsoff the system

Activated by using theLOCK: prefix on anyinstruction

53


QS1 QS000: Queue is idle

01: First byte of opcode

10: Queue is empty

11: Subsequent byte ofopcode

Queue StatusUsed by numeric

coprocessor (8087)

QS1 QS000: Queue is idle

01: First byte of opcode

10: Queue is empty

11: Subsequent byte ofopcode

54

8086 Internal Architecture 8086 employs parallel processing 8086 CPU has two parts which operate at the

same time• Bus Interface Unit• Execution Unit

CPU functions1. Fetch

2. Decode3. Execute

8086 CPU

8086 employs parallel processing 8086 CPU has two parts which operate at the

same time• Bus Interface Unit• Execution Unit

CPU functions1. Fetch

2. Decode3. Execute

Bus InterfaceUnit (BIU)

Execution Unit(EU)

55

Bus Interface Unit

Sends out addresses for memory locationsFetches Instructions from memoryReads/Writes data to memorySends out addresses for I/O portsReads/Writes data to Input/Output ports

Sends out addresses for memory locationsFetches Instructions from memoryReads/Writes data to memorySends out addresses for I/O portsReads/Writes data to Input/Output ports

56

Execution Unit

Tells BIU (addresses) where to fetchinstructions or dataDecodes & Executes instructions

Dividing the work between BIU & EUspeeds up processing

Tells BIU (addresses) where to fetchinstructions or dataDecodes & Executes instructions

Dividing the work between BIU & EUspeeds up processing

57

Architecture Diagram of 8086Architecture Diagram of 8086

58

EXTRA SEGMENT (ES)

CODE SEGMENT (CS)

STACK SEGMENT (SS)

DATA SEGMENT (DS)

INSTRUCTION POINTER (IP)

6 5 4 3 2 1

Instruction Queue

∑ MemoryInterface

BIU

AH AL

BH BL

CH CL

DH DL

STACK POINTER (SP)

BASE POINTER (BP)

SOURCE INDEX (SI)

DESTINATION INDEX (DI)

CONTROLSYSTEM

ARITHMETICLOGIC UNIT

FLAGSOPERANDS

EU

InstructionDecoder

59

Execution Unit

Main components are• Instruction Decoder• Control System• Arithmetic Logic Unit• General Purpose Registers• Flag Register• Pointer & Index registers

Main components are• Instruction Decoder• Control System• Arithmetic Logic Unit• General Purpose Registers• Flag Register• Pointer & Index registers

60

Instruction DecoderTranslates instructions fetched from memory

into a series of actions which EU carries out

Control SystemGenerates timing and control signals to

perform the internal operations of themicroprocessor

Generates timing and control signals toperform the internal operations of themicroprocessor

Arithmetic Logic UnitEU has a 16-bit ALU which can ADD,

SUBTRACT, AND, OR, increment, decrement,complement or shift binary numbers

61

General Purpose Registers EU has 8 general

purpose registers Can be individually

used for storing 8-bitdata

AL register is alsocalled Accumulator

Two registers can alsobe combined to form16-bit registers

The valid register pairsare – AX, BX, CX, DX

AH AL

BH BL

CH CL

DH DL

EU has 8 generalpurpose registers

Can be individuallyused for storing 8-bitdata

AL register is alsocalled Accumulator

Two registers can alsobe combined to form16-bit registers

The valid register pairsare – AX, BX, CX, DX

DH DL

AH AL AX

BH BL BX

CH CL CX

DH DL DX62

Flag Register

8086 has a 16-bit flag registerContains 9 active flagsThere are two types of flags in 8086

• Conditional flags – six flags, set or resetby EU on the basis of results of somearithmetic operations

• Control flags – three flags, used to controlcertain operations of the processor

8086 has a 16-bit flag registerContains 9 active flagsThere are two types of flags in 8086

• Conditional flags – six flags, set or resetby EU on the basis of results of somearithmetic operations

• Control flags – three flags, used to controlcertain operations of the processor

63

U U U U OF DF IF TF SF ZF U AF U PF U CF

Flag Register

1. CF CARRY FLAG Conditional Flags(Compatible with 8085,except OF)

2. PF PARITY FLAG

3. AF AUXILIARY CARRY

Conditional Flags(Compatible with 8085,except OF)3. AF AUXILIARY CARRY

4. ZF ZERO FLAG

5. SF SIGN FLAG

6. OF OVERFLOW FLAG

7. TF TRAP FLAG Control Flags8. IF INTERRUPT FLAG

9. DF DIRECTION FLAG64

Flag RegisterCarry Flag

This flag is set, when there isa carry out of MSB in case ofaddition or a borrow in caseof subtraction.

Parity Flag

This flag is set to 1, if the lowerbyte of the result contains evennumber of 1’s ; for odd numberof 1’s set to zero.

Auxiliary Carry Flag

This is set, if there is a carry from thelowest nibble, i.e, bit three duringaddition, or borrow for the lowestnibble, i.e, bit three, duringsubtraction.

Zero Flag

This flag is set, if the result ofthe computation or comparisonperformed by an instruction iszero

Sign Flag

This flag is set, when theresult of any computation

is negative

65

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp FlagIf this flag is set, the processorenters the single step executionmode by generating internalinterrupts after the execution ofeach instruction

Interrupt Flag

Causes the 8086 to recognizeexternal mask interrupts; clearing IF

disables these interrupts.

Direction FlagThis is used by string manipulation instructions. If this flag bitis ‘0’, the string is processed beginning from the lowestaddress to the highest address, i.e., auto incrementing mode.Otherwise, the string is processed from the highest addresstowards the lowest address, i.e., auto incrementing mode.

Over flow FlagThis flag is set, if an overflow occurs, i.e, if the result of a signed

operation is large enough to accommodate in a destinationregister. The result is of more than 7-bits in size in case of 8-bitsigned operation and more than 15-bits in size in case of 16-bit

sign operations, then the overflow will be set.

Registers, Flag

Sl.No. Type Register width Name of register

1 General purposeregister

16 bit AX, BX, CX, DX

8086 registerscategorized

into 4 groups15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

66

1 General purposeregister

16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logicoperations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logicoperations

BX Base register Used to hold base value in base addressing modeto access memory data

CX Count Register Used to hold the count value in SHIFT, ROTATEand LOOP instructions

Registers and Special Functions

67

Used to hold the count value in SHIFT, ROTATEand LOOP instructions

DX Data Register Used to hold data for multiplication and divisionoperations

SP Stack Pointer Used to hold the offset address of top stackmemory

BP Base Pointer Used to hold the base value in base addressingusing SS register to access data from stackmemory

SI Source Index Used to hold index value of source operand (data)for string instructions

DI Data Index Used to hold the index value of destinationoperand (data) for string operations

Bus Interface Unit

Main Components are• Instruction Queue• Segment Registers• Instruction Pointer

Main Components are• Instruction Queue• Segment Registers• Instruction Pointer

68

EXTRA SEGMENT (ES)

CODE SEGMENT (CS)

STACK SEGMENT (SS)

DATA SEGMENT (DS)

INSTRUCTION POINTER (IP)

6 5 4 3 2 1

Instruction Queue

∑ MemoryInterface

BIU

AH AL

BH BL

CH CL

DH DL

STACK POINTER (SP)

BASE POINTER (BP)

SOURCE INDEX (SI)

DESTINATION INDEX (DI)

CONTROLSYSTEM

ARITHMETICLOGIC UNIT

FLAGSOPERANDS

EU

InstructionDecoder

69

Instruction Queue 8086 employs parallel processingWhen EU is busy decoding or executing

current instruction, the buses of 8086 maynot be in use.At that time, BIU can use buses to fetch upto

six instruction bytes for the followinginstructionsBIU stores these pre-fetched bytes in a FIFO

register called Instruction QueueWhen EU is ready for its next instruction, it

simply reads the instruction from the queuein BIU

8086 employs parallel processingWhen EU is busy decoding or executing

current instruction, the buses of 8086 maynot be in use.At that time, BIU can use buses to fetch upto

six instruction bytes for the followinginstructionsBIU stores these pre-fetched bytes in a FIFO

register called Instruction QueueWhen EU is ready for its next instruction, it

simply reads the instruction from the queuein BIU

70

Pipelining

EU of 8086 does not have to wait inbetween for BIU to fetch nextinstruction byte from memorySo the presence of a queue in 8086

speeds up the processingFetching the next instruction while the

current instruction executes is calledpipelining

EU of 8086 does not have to wait inbetween for BIU to fetch nextinstruction byte from memorySo the presence of a queue in 8086

speeds up the processingFetching the next instruction while the

current instruction executes is calledpipelining

71

Memory Segmentation 8086 has a 20-bit address busSo it can address a maximum of 1MB of

memory 8086 can work with only four 64KB segments

at a time within this 1MB rangeThese four memory segments are called

• Code segment• Stack segment• Data segment• Extra segment

8086 has a 20-bit address busSo it can address a maximum of 1MB of

memory 8086 can work with only four 64KB segments

at a time within this 1MB rangeThese four memory segments are called

• Code segment• Stack segment• Data segment• Extra segment

72

1

2

3

4

5

6

7

8

Memory

00000H

1MBAddressRange

64KB MemorySegment

Only 4 such segments can beaddressed at a time

4

5

6

7

8

9

10

11

12

13

14

15

16 FFFFFH

1MBAddressRange

73

Code SegmentThat part of memory from where BIU is

currently fetching instruction code bytes

Stack SegmentA section of memory set aside to store

addresses and data while a subprogramexecutes

A section of memory set aside to storeaddresses and data while a subprogramexecutes

Data & Extra SegmentsUsed for storing data values to be used in

the program

74

1

2

3

4

5

6

7

8

Memory

00000H

1MBAddressRange

Code Segment

Data & ExtraSegments

8

9

10

11

12

13

14

15

16 FFFFFH

1MBAddressRange

Stack Segment75

Segment Registers

hold the upper 16-bits of the startingaddress for each of the segmentsThe four segment registers are

• CS (Code Segment register)• DS (Data Segment register)• SS (Stack Segment register)• ES (Extra Segment register)

hold the upper 16-bits of the startingaddress for each of the segmentsThe four segment registers are

• CS (Code Segment register)• DS (Data Segment register)• SS (Stack Segment register)• ES (Extra Segment register)

76

1

Code Segment3

4

Data SegmentExtra Segment

7

8

Memory00000H

1MBAddressRange

Star

ting

Add

ress

esof

Seg

men

ts

1000 0H

4000 0H5000 0H

CS

DSES

9

10

11

12

13

14

15

Stack Segment FFFFFH

1MBAddressRange

Star

ting

Add

ress

esof

Seg

men

ts

F000 0HSS77

Address of a segment is of 20-bitsA segment register stores only upper 16-

bitsBIU always inserts zeros for the lowest 4-

bits of the 20-bit starting address.E.g. if CS = 348AH, then the code

segment will start at 348A0HA 64-KB segment can be located

anywhere in the memory, but will start atan address with zeros in the lowest 4-bits

Address of a segment is of 20-bitsA segment register stores only upper 16-

bitsBIU always inserts zeros for the lowest 4-

bits of the 20-bit starting address.E.g. if CS = 348AH, then the code

segment will start at 348A0HA 64-KB segment can be located

anywhere in the memory, but will start atan address with zeros in the lowest 4-bits

78

Instruction Pointer (IP) Register

a 16-bit registerHolds 16-bit offset, of the next instruction

byte in the code segmentBIU uses IP and CS registers to generate

the 20-bit address of the instruction to befetched from memory

a 16-bit registerHolds 16-bit offset, of the next instruction

byte in the code segmentBIU uses IP and CS registers to generate

the 20-bit address of the instruction to befetched from memory

79

1Data

Segment3

4

CodeSegment

ExtraSegment

7

Memory

00000H

1MBAddressRange

Start of Code Segment

348A0H

Code Byte MOV AL, BL38AB4H

IP = 4214H

Physical Address Calculation

7

8

9

10

11

12

13

14

15

StackSegment FFFFFH

1MBAddressRange

348A H

4214 H

38AB4 H

CS

IPPhysical Address

+

0

80

Stack Segment (SS) RegisterStack Pointer (SP) Register

Upper 16-bits of the starting address ofstack segment is stored in SS registerIt is located in BIUSP register holds a 16-bit offset from the

start of stack segment to the top of thestackIt is located in EU

Upper 16-bits of the starting address ofstack segment is stored in SS registerIt is located in BIUSP register holds a 16-bit offset from the

start of stack segment to the top of thestackIt is located in EU

81

Other Pointer & Index Registers

Base Pointer (BP) registerSource Index (SI) registerDestination Index (DI) registerCan be used for temporary storage of dataMain use is to hold a 16-bit offset of a data

word in one of the segments

Base Pointer (BP) registerSource Index (SI) registerDestination Index (DI) registerCan be used for temporary storage of dataMain use is to hold a 16-bit offset of a data

word in one of the segments

82

ADDRESSINGMODES OF

8086

ADDRESSINGMODES OF

808683

Various Addressing Modes1. Immediate Addressing Mode2. Register Addressing Mode3. Direct Addressing Mode4. Register Indirect Addressing Mode5. Index Addressing Mode6. Based Addressing Mode7. Based & Indexed Addressing Mode8. Based & Indexed with displacement Addressing

Mode9. Strings Addressing Mode

1. Immediate Addressing Mode2. Register Addressing Mode3. Direct Addressing Mode4. Register Indirect Addressing Mode5. Index Addressing Mode6. Based Addressing Mode7. Based & Indexed Addressing Mode8. Based & Indexed with displacement Addressing

Mode9. Strings Addressing Mode

84Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode

1. IMMEDIATE ADDRESSING MODE• The instruction will specify the name

of the register which holds the datato be operated by the instruction.

• Source data is within theinstruction

• Ex: MOV AX,10ABH

AL=ABH, AH=10H

• The instruction will specify the nameof the register which holds the datato be operated by the instruction.

• Source data is within theinstruction

• Ex: MOV AX,10ABH

AL=ABH, AH=10H

85

2.REGISTER ADDRESSING MODE

• In immediate addressing mode, an8-bit or 16-bit data is specified aspart of the instruction

• Ex: MOV AX,BLH

MOV AX,BLH

• In immediate addressing mode, an8-bit or 16-bit data is specified aspart of the instruction

• Ex: MOV AX,BLH

MOV AX,BLH

86

3. DIRECT ADDRESSING MODE

• Memory address is supplied with inthe instruction

• Mnemonic: MOV AH,[MEMBDS]AH [1000H]

• But the memory address is notindex or pointer register

• Memory address is supplied with inthe instruction

• Mnemonic: MOV AH,[MEMBDS]AH [1000H]

• But the memory address is notindex or pointer register

87

4. REGISTER INDIRECT ADDRESSING MODE

• Memory address is supplied in an index orpointer register

• EX:

MOV AX,[SI] ; AL [SI] ; AH [SI+1]JMP [DI] ; IP [DI+1: DI]INC BYTE PTR [BP] ; [BP] [BP]+1DEC WORD PTR [BX] ;

[BX+1:BX] [BX+1:BX]-1

• Memory address is supplied in an index orpointer register

• EX:

MOV AX,[SI] ; AL [SI] ; AH [SI+1]JMP [DI] ; IP [DI+1: DI]INC BYTE PTR [BP] ; [BP] [BP]+1DEC WORD PTR [BX] ;

[BX+1:BX] [BX+1:BX]-1

88

5.Indexed Addressing Mode

• Memory address is the sum of indexregister plus displacement

MOV AX,[SI+2] AL [SI+2]; AH [SI+3]JMP [DI+2] IP [BX+3:BX+2]

• Memory address is the sum of indexregister plus displacement

MOV AX,[SI+2] AL [SI+2]; AH [SI+3]JMP [DI+2] IP [BX+3:BX+2]

89

6. Based Addressing Mode

• Memory address is the sum of the BX or BPbase register plus a displacement withininstruction

• Ex:MOV AX,[BP+2] AL [BP+2]; AH [BP+3]JMP [BX+2] IP [BX+3:BX+2]

• Memory address is the sum of the BX or BPbase register plus a displacement withininstruction

• Ex:MOV AX,[BP+2] AL [BP+2]; AH [BP+3]JMP [BX+2] IP [BX+3:BX+2]

90

7.BASED & INDEX ADDRESSING MODES

• Memory address is the sum of the index register& base register

Ex:MOV AX,[BX+SI] ; AL [BX+SI] ; AH [BX+SI+1]

JMP [BX+DI] ; IP [BX+DI+1 : BX+DI]INC BYTE PTR [BP+SI] ; [BP] [BP]+1DEC WORD PTR [BP+DI] ;

[BX+1:BX] [BX+1:BX]-1

• Memory address is the sum of the index register& base register

Ex:MOV AX,[BX+SI] ; AL [BX+SI] ; AH [BX+SI+1]

JMP [BX+DI] ; IP [BX+DI+1 : BX+DI]INC BYTE PTR [BP+SI] ; [BP] [BP]+1DEC WORD PTR [BP+DI] ;

[BX+1:BX] [BX+1:BX]-1

91

8. BASED & INDEXED WITH DISPLACEMENT ADDRESSING MODE

• Memory address is the sum of an index register ,base register and displacement within instruction

MOV AX,[BX+SI+6] ; AL [BX+SI+6] ; AH [BX+SI+7]JMP [BX+DI+6] ; IP [BX+DI+7 : BX+DI+6]

INC BYTE PTR [BP+SI+5] ;DEC WORD PTR [BP+DI+5] ;

• Memory address is the sum of an index register ,base register and displacement within instruction

MOV AX,[BX+SI+6] ; AL [BX+SI+6] ; AH [BX+SI+7]JMP [BX+DI+6] ; IP [BX+DI+7 : BX+DI+6]

INC BYTE PTR [BP+SI+5] ;DEC WORD PTR [BP+DI+5] ;


9. Strings Addressing Mode

• The memory source address is a register SI in thedata segment, and the memory destinationaddress is register DI in the extra segment

• Ex: MOVSB [ES:DI] [DS:SI]

• If DF=0 SI SI+1 , DI DI+1DF=1 SI SI-1 , DI DI-1

• The memory source address is a register SI in thedata segment, and the memory destinationaddress is register DI in the extra segment

• Ex: MOVSB [ES:DI] [DS:SI]

• If DF=0 SI SI+1 , DI DI+1DF=1 SI SI-1 , DI DI-1

93

INSTRUCTIONSET of 8086

INSTRUCTIONSET of 8086

94

• Instruction:- An instruction is a binary pattern designedinside a microprocessor to perform a specific function.

• Opcode:- It stands for operational code. It specifies the typeof operation to be performed by CPU. It is the first field inthe machine language instruction format.

• E.g. 08 is the opcode for instruction “MOV X,Y”.

• Operand:- We can also say it as data on which operationshould act. operands may be register values or memoryvalues. The CPU executes the instructions using informationpresent in this field. It may be 8-bit data or 16-bit data.

Instruction set basics

• Instruction:- An instruction is a binary pattern designedinside a microprocessor to perform a specific function.

• Opcode:- It stands for operational code. It specifies the typeof operation to be performed by CPU. It is the first field inthe machine language instruction format.

• E.g. 08 is the opcode for instruction “MOV X,Y”.

• Operand:- We can also say it as data on which operationshould act. operands may be register values or memoryvalues. The CPU executes the instructions using informationpresent in this field. It may be 8-bit data or 16-bit data.

95

• Assembler:- it converts the instruction into sequence ofbinary bits, so that this bits can be read by the processor.

• Mnemonics:- these are the symbolic codes for eitherinstructions or commands to perform a particularfunction.

• E.g. MOV, ADD, SUB etc.

Instruction set basics

• Assembler:- it converts the instruction into sequence ofbinary bits, so that this bits can be read by the processor.

• Mnemonics:- these are the symbolic codes for eitherinstructions or commands to perform a particularfunction.

• E.g. MOV, ADD, SUB etc.

96

Types of instruction set of 8086Types of instruction set of 8086microprocessormicroprocessor

(1). Data Copy/Transfer instructions.

(2). Arithmetic & Logical instructions.

(3). Branch instructions.

(4). Loop instructions.

(5). Machine Control instructions.

(6). Flag Manipulation instructions.

(7). Shift & Rotate instructions.

(8). String instructions.

(1). Data Copy/Transfer instructions.

(2). Arithmetic & Logical instructions.

(3). Branch instructions.

(4). Loop instructions.

(5). Machine Control instructions.

(6). Flag Manipulation instructions.

(7). Shift & Rotate instructions.

(8). String instructions.97

(1). Data copy/transfer instructions.(1). Data copy/transfer instructions.(1). MOV Destination, Source

There will be transfer of data from source to destination. Source can be register, memory location or immediate

data. Destination can be register or memory operand. Both Source and Destination cannot be memory location

or segment registers at the same time. E.g. (1). MOV CX, 037A H; (2). MOV AL, BL; (3). MOV BX, [0301 H];

(1). MOV Destination, Source

There will be transfer of data from source to destination. Source can be register, memory location or immediate

data. Destination can be register or memory operand. Both Source and Destination cannot be memory location

or segment registers at the same time. E.g. (1). MOV CX, 037A H; (2). MOV AL, BL; (3). MOV BX, [0301 H];

98

BX 2000HAX 2000H

BEFOREEXECUTION

AFTEREXECUTION

MOV BX,AX

BEFOREEXECUTION

AFTEREXECUTION

AH

AL

BH

BL

CH

CL

DH

DL

AH

AL

BH

BL

CH

CL 40

DH

DL

MOV CL,M

40 40

BEFOREEXECUTION

AFTEREXECUTION

99

Stack PointerStack Pointer It is a 16-bit register, contains the address of the data

item currently on top of the stack.

Stack operation includes pushing (providing) data onto the stack and popping (taking)data from the stack.

Pushing operation decrements stack pointer andPopping operation increments stack pointer. i.e.there is a last in first out (LIFO) operation.

It is a 16-bit register, contains the address of the dataitem currently on top of the stack.

Stack operation includes pushing (providing) data onto the stack and popping (taking)data from the stack.

Pushing operation decrements stack pointer andPopping operation increments stack pointer. i.e.there is a last in first out (LIFO) operation.

100

(2). Push Source(2). Push Source Source can be register, segment register or

memory. This instruction pushes the contents of specified

source on to the stack. In this stack pointer is decremented by 2. The higher byte data is pushed first (SP-1). Then lower byte data is pushed (SP-2).

E.g.: (1). PUSH AX; (2). PUSH DS; (3). PUSH [5000H];

Source can be register, segment register ormemory. This instruction pushes the contents of specified

source on to the stack. In this stack pointer is decremented by 2. The higher byte data is pushed first (SP-1). Then lower byte data is pushed (SP-2).

E.g.: (1). PUSH AX; (2). PUSH DS; (3). PUSH [5000H];

101

INITIAL POSITION

DECREMENTS SP & STORES HIGHERBYTE

(1) STACKPOINTER

(2) STACK POINTERHIGHER BYTE

DECREMENTS SP & STORES LOWERBYTE

LOWER BYTE

HIGHER BYTE

(2) STACK POINTER

(3) STACKPOINTER

102

BH BL

CH 10 CL 50

DH DL

SP 2002H

BEFORE EXECUTION

2000H

2001H

2002H

PUSH CX

BH BL

CH 10 CL 50

DH DL

50

10

SP 2000H

AFTER EXECUTION2000H

2001H

2002H

PUSH CX

103

(3) POP Destination(3) POP Destination Destination can be register, segment register or

memory. This instruction pops (takes) the contents of

specified destination. In this stack pointer is incremented by 2. The lower byte data is popped first (SP+1). Then higher byte data is popped (SP+2).

E.g. (1). POP AX; (2). POP DS; (3). POP [5000H];

Destination can be register, segment register ormemory. This instruction pops (takes) the contents of

specified destination. In this stack pointer is incremented by 2. The lower byte data is popped first (SP+1). Then higher byte data is popped (SP+2).

E.g. (1). POP AX; (2). POP DS; (3). POP [5000H];

104

INITIAL POSITION AND READS LOWERBYTE

LOWER BYTE

INCREMENTS SP & READS HIGHERBYTE

LOWER BYTE

(1) STACKPOINTER

(2) STACK POINTER LOWER BYTE

HIGHER BYTE

INCREMENTS SP

LOWER BYTE

HIGHER BYTE

(2) STACK POINTER

(3) STACKPOINTER

105

BH BL

SP 2000H3050

BEFORE EXECUTION

POP BX

2000H

2001H

2002H

BH 50

BL 30SP 2002H

3050

AFTER EXECUTION

POP BX

2000H2001H

2002H

106

(4). XCHG Destination, source;(4). XCHG Destination, source;

• This instruction exchanges contents of Source withdestination.

• It cannot exchange two memory locations directly.

•The contents of AL are exchanged with BL.

•The contents of AH are exchanged with BH.

•E.g.(1). XCHG BX, AX;(2). XCHG [5000H],AX;

• This instruction exchanges contents of Source withdestination.

• It cannot exchange two memory locations directly.

•The contents of AL are exchanged with BL.

•The contents of AH are exchanged with BH.

•E.g.(1). XCHG BX, AX;(2). XCHG [5000H],AX;

107

AH 20 AL 40 AH 70 AL 80

BEFORE EXECUTION AFTER EXECUTION

BH 70 BL 80 BH 20 BL 40

XCHG AX,BX108

(5)IN AL/AX, 8(5)IN AL/AX, 8--bit/16bit/16--bit port addressbit port address

It reads from the specified port address. It copies data to accumulator from a port with 8-

bit or 16-bit address. DX is the only register is allowed to carry port

address. E.g.(1). IN AL, 80H;(2). IN AX,DX; //DX contains address of 16-bit

port.

It reads from the specified port address. It copies data to accumulator from a port with 8-

bit or 16-bit address. DX is the only register is allowed to carry port

address. E.g.(1). IN AL, 80H;(2). IN AX,DX; //DX contains address of 16-bit

port.109

10 AL

BEFORE EXECUTION

IN AL,80H

PORT80H

10 AL 10

AFTER EXECUTION

IN AL,80H

PORT80H

110

OUT 8OUT 8--bit/16bit/16--bit port address, AL/AXbit port address, AL/AX

It writes to the specified port address. It copies contents of accumulator to the port

with 8-bit or 16-bit address. DX is the only register is allowed to carry port

address. E.g.(1). OUT 80H,AL;(2). OUT DX,AX; //DX contains address of 16-bit

port.

It writes to the specified port address. It copies contents of accumulator to the port

with 8-bit or 16-bit address. DX is the only register is allowed to carry port

address. E.g.(1). OUT 80H,AL;(2). OUT DX,AX; //DX contains address of 16-bit

port.111

10 AL 40

BEFORE EXECUTION

OUT 50H,AL

PORT50H

40 AL 40

AFTER EXECUTION

OUT 50H,AL

PORT50H

112

(7) XLAT(7) XLAT

Also known as translate instruction. It is used to find out codes in case of code conversion. i.e. it translates code of the key pressed to the

corresponding 7-segment code. After execution this instruction contents of AL register

always gets replaced. E.g. XLAT;

Also known as translate instruction. It is used to find out codes in case of code conversion. i.e. it translates code of the key pressed to the

corresponding 7-segment code. After execution this instruction contents of AL register

always gets replaced. E.g. XLAT;

113

8.8.LEA 16LEA 16--bit register (source), address (dest.)bit register (source), address (dest.)

LEA Also known as Load Effective Address(LEA). It loads effective address formed by the

destination into the source register.

E.g.(1). LEA BX,Address;(2). LEA SI,Address[BX];

LEA Also known as Load Effective Address(LEA). It loads effective address formed by the

destination into the source register.

E.g.(1). LEA BX,Address;(2). LEA SI,Address[BX];

114

(9). LDS 16-bit register (source), address (dest.);(10). LES 16-bit register (source), address (dest.);

LDS Also known as Load Data Segment (LDS). LES Also known as Load Extra Segment (LES). It loads the contents of DS (Data Segment) or ES

(Extra Segment) & contents of the destination tothe contents of source register.

E.g.(1). LDS BX,5000H;(2). LES BX,5000H;

LDS Also known as Load Data Segment (LDS). LES Also known as Load Extra Segment (LES). It loads the contents of DS (Data Segment) or ES

(Extra Segment) & contents of the destination tothe contents of source register.

E.g.(1). LDS BX,5000H;(2). LES BX,5000H;

115

10

20

5000H

5001H

20 10

(1). LDS BX,5000H;(2). LES BX,5000H;

BX07015

30

40

5001H

5002H

5003H

40 30DS/ES

116

(11). LAHF:- This instruction loads the AH registerfrom the contents of lower byte of the flag register. This command is used to observe the status of the

all conditional flags of flag register.E.g. LAHF;

(12). SAHF:- This instruction sets or resets allconditional flags of flag register with respect to thecorresponding bit positions. If bit position in AH is 1 then related flag is set

otherwise flag will be reset.E.g. SAHF;

(11). LAHF:- This instruction loads the AH registerfrom the contents of lower byte of the flag register. This command is used to observe the status of the

all conditional flags of flag register.E.g. LAHF;

(12). SAHF:- This instruction sets or resets allconditional flags of flag register with respect to thecorresponding bit positions. If bit position in AH is 1 then related flag is set

otherwise flag will be reset.E.g. SAHF;

117

PUSH & POPPUSH & POP

(13). PUSH F:- This instruction decrements thestack pointer by 2. It copies contents of flag register to the memory

location pointed by stack pointer. E.g. PUSH F;

(14). POP F:- This instruction increments the stackpointer by 2. It copies contents of memory location pointed by

stack pointer to the flag register. E.g. POP F;

(13). PUSH F:- This instruction decrements thestack pointer by 2. It copies contents of flag register to the memory

location pointed by stack pointer. E.g. PUSH F;

(14). POP F:- This instruction increments the stackpointer by 2. It copies contents of memory location pointed by

stack pointer to the flag register. E.g. POP F;

118

(2). Arithmetic Instructions(2). Arithmetic Instructions

These instructions perform theoperations like:

Addition, Subtraction, Increment, Decrement.

These instructions perform theoperations like:

Addition, Subtraction, Increment, Decrement.

119

(2). Arithmetic Instructions(2). Arithmetic Instructions(1). ADD destination, source;

This instruction adds the contents of source operand withthe contents of destination operand.

The source may be immediate data, memory location orregister.

The destination may be memory location or register. The result is stored in destination operand. AX is the default destination register.

E.g. (1). ADD AX,2020H;(2). ADD AX,BX;

(1). ADD destination, source;

This instruction adds the contents of source operand withthe contents of destination operand.

The source may be immediate data, memory location orregister.

The destination may be memory location or register. The result is stored in destination operand. AX is the default destination register.

E.g. (1). ADD AX,2020H;(2). ADD AX,BX;

120

AH 10 AL 10

AFTER EXECUTIONBEFORE EXECUTION

ADD AX,2020HAH 30 AL 30

1010+20203030

AH 10 AL 10

BH 20 BL 20


ADD AX,BX

1010+20203030

AH 30 AL 30

BH 20 BL 20

121

ADC destination, sourceADC destination, source This instruction adds the contents of source

operand with the contents of destination operandwith carry flag bit.

The source may be immediate data, memorylocation or register.

The destination may be memory location orregister.

The result is stored in destination operand. AX is the default destination register.

E.g. (1). ADC AX,2020H;(2). ADC AX,BX;

This instruction adds the contents of sourceoperand with the contents of destination operandwith carry flag bit.



The result is stored in destination operand. AX is the default destination register.

E.g. (1). ADC AX,2020H;(2). ADC AX,BX;

122

(3) INC source(3) INC source This instruction increases the contents of source

operand by 1. The source may be memory location or register. The source can not be immediate data. The result is stored in the same place.

E.g. (1). INC AX;(2). INC [5000H];

This instruction increases the contents of sourceoperand by 1. The source may be memory location or register. The source can not be immediate data. The result is stored in the same place.

E.g. (1). INC AX;(2). INC [5000H];

123


INC AXAH 10 AL 10 AH 10 AL 11

5000H


INC [5000H]1010 5000H 1011

124

4. DEC source4. DEC source This instruction decreases the contents of

source operand by 1. The source may be memory location or register. The source can not be immediate data. The result is stored in the same place.

E.g. (1). DEC AX;(2). DEC [5000H];

This instruction decreases the contents ofsource operand by 1. The source may be memory location or register. The source can not be immediate data. The result is stored in the same place.

E.g. (1). DEC AX;(2). DEC [5000H];

125


DEC AXAH 10 AL 10 AH 10 AL 09

5000H


DEC [5000H]1010 5000H 1009

126

(5) SUB destination, source;(5) SUB destination, source; This instruction subtracts the contents of source

operand from contents of destination. The source may be immediate data, memory

location or register. The destination may be memory location or

register. The result is stored in the destination place.

E.g. (1). SUB AX,1000H;(2). SUB AX,BX;

This instruction subtracts the contents of sourceoperand from contents of destination. The source may be immediate data, memory


register. The result is stored in the destination place.

E.g. (1). SUB AX,1000H;(2). SUB AX,BX;

127


SUB AX,1000HAH 20 AL 00 AH 10 AL 00

2000-1000=1000


SUB AX,BX

2000-1000=1000

AH 20 AL 00BH 10 BL 00

AH 10 AL 00

BH 10 BL 00

128

(6). SBB destination, source;(6). SBB destination, source; Also known as Subtract with Borrow. This instruction subtracts the contents of source

operand & borrow from contents of destinationoperand.



The result is stored in the destination place.

E.g. (1). SBB AX,1000H;(2). SBB AX,BX;

Also known as Subtract with Borrow. This instruction subtracts the contents of source

operand & borrow from contents of destinationoperand.



The result is stored in the destination place.

E.g. (1). SBB AX,1000H;(2). SBB AX,BX;

129

AH 20 AL 20


SBB AX,1000H

AH 10 AL 192020

- 10001020-

1=1019

B 1

AH 20 AL 20

BH 10 BL 10


SBB AX,BX

2050

2020- 10001020-

1=1019

AH 10 AL 19

BH 10 BL 10

B 1

130

(7). CMP destination, source(7). CMP destination, source Also known as Compare. This instruction compares the contents of source

operand with the contents of destination operands. The source may be immediate data, memory


register. Then resulting carry & zero flag will be set or reset.

E.g. (1). CMP AX,1000H;(2). CMP AX,BX;

Also known as Compare. This instruction compares the contents of source

operand with the contents of destination operands. The source may be immediate data, memory


register. Then resulting carry & zero flag will be set or reset.

E.g. (1). CMP AX,1000H;(2). CMP AX,BX;

131

AFTER EXECUTION

CMP AX,BX

BEFORE EXECUTION

CY 0 Z 1


D=S: CY=0,Z=1D>S: CY=0,Z=0D<S: CY=1,Z=0

AH 10 AL 00BH 10 BL 00

CMP AX,BX CY 0 Z 0AH 10 AL 00

CMP AX,BX CY 0 Z 0AH 10 AL 00BH 00 BL 10


CMP AX,BX CY 1 Z 0AH 10 AL 00BH 20 BL 00

132

AAA (ASCII Adjust after Addition): The data entered from the terminal is in ASCII format.

In ASCII, 0 – 9 are represented by 30H – 39H.

This instruction allows us to add the ASCII codes.

This instruction does not have any operand.

Other ASCII Instructions: AAS (ASCII Adjust after Subtraction)

AAM (ASCII Adjust after Multiplication)

AAD (ASCII Adjust Before Division)

AAA (ASCII Adjust after Addition): The data entered from the terminal is in ASCII format.

In ASCII, 0 – 9 are represented by 30H – 39H.

This instruction allows us to add the ASCII codes.

This instruction does not have any operand.

Other ASCII Instructions: AAS (ASCII Adjust after Subtraction)

AAM (ASCII Adjust after Multiplication)

AAD (ASCII Adjust Before Division)133

DAA (Decimal Adjust after Addition)

It is used to make sure that the result of adding two BCD numbers isadjusted to be a correct BCD number.

It only works on AL register.

DAS (Decimal Adjust after Subtraction)

It is used to make sure that the result of subtracting two BCDnumbers is adjusted to be a correct BCD number.


DAA (Decimal Adjust after Addition)

It is used to make sure that the result of adding two BCD numbers isadjusted to be a correct BCD number.


DAS (Decimal Adjust after Subtraction)

It is used to make sure that the result of subtracting two BCDnumbers is adjusted to be a correct BCD number.


134

MUL operandMUL operand Unsigned Multiplication. Operand contents are positively signed. Operand may be general purpose register or memory

location. If operand is of 8-bit then multiply it with contents of AL. If operand is of 16-bit then multiply it with contents of AX. Result is stored in accumulator (AX).

E.g. (1). MUL BH // AX= AL*BH; // (+3) * (+4) = +12.

(2). MUL CX // AX=AX*CX;

Unsigned Multiplication. Operand contents are positively signed. Operand may be general purpose register or memory

location. If operand is of 8-bit then multiply it with contents of AL. If operand is of 16-bit then multiply it with contents of AX. Result is stored in accumulator (AX).

E.g. (1). MUL BH // AX= AL*BH; // (+3) * (+4) = +12.

(2). MUL CX // AX=AX*CX;

135

IMUL operandIMUL operand Signed Multiplication. Operand contents are negatively signed. Operand may be general purpose register, memory location

or index register. If operand is of 8-bit then multiply it with contents of AL. If operand is of 16-bit then multiply it with contents of AX. Result is stored in accumulator (AX).

E.g. (1). IMUL BH // AX= AL*BH; // (-3) * (-4) = 12.

(2). IMUL CX // AX=AX*CX;

Signed Multiplication. Operand contents are negatively signed. Operand may be general purpose register, memory location

or index register. If operand is of 8-bit then multiply it with contents of AL. If operand is of 16-bit then multiply it with contents of AX. Result is stored in accumulator (AX).

E.g. (1). IMUL BH // AX= AL*BH; // (-3) * (-4) = 12.

(2). IMUL CX // AX=AX*CX;

136

DIV operandDIV operand Unsigned Division. Operand may be register or memory. Operand contents are positively signed. Operand may be general purpose register or

memory location. AL=AX/Operand (8-bit/16-bit) & AH=Remainder.

E.g. MOV AX, 0203 // AX=0203 MOV BL, 04 // BL=04 IDIV BL // AL=0203/04=50 (i.e. AL=50 & AH=03)

Unsigned Division. Operand may be register or memory. Operand contents are positively signed. Operand may be general purpose register or


E.g. MOV AX, 0203 // AX=0203 MOV BL, 04 // BL=04 IDIV BL // AL=0203/04=50 (i.e. AL=50 & AH=03)

137

IDIV operandIDIV operand Signed Division. Operand may be register or memory. Operand contents are negatively signed. Operand may be general purpose register or


E.g. MOV AX, -0203 // AX=-0203 MOV BL, 04 // BL=04 DIV BL // AL=-0203/04=-50 (i.e. AL=-50 &

AH=03)

Signed Division. Operand may be register or memory. Operand contents are negatively signed. Operand may be general purpose register or


E.g. MOV AX, -0203 // AX=-0203 MOV BL, 04 // BL=04 DIV BL // AL=-0203/04=-50 (i.e. AL=-50 &

AH=03)

138

Multiplication and Division ExamplesMultiplication and Division Examples

139

140

141

142

LOGICAL (or) Bit ManipulationInstructions

These instructions are used at the bit level.

These instructions can be used for:

Testing a zero bit

Set or reset a bit

Shift bits across registers

These instructions are used at the bit level.

These instructions can be used for:

Testing a zero bit

Set or reset a bit

Shift bits across registers

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Bit Manipulation Instructions(LOGICAL Instructions)

• AND– Especially used in clearing certain bits (masking)

xxxx xxxx AND 0000 1111 = 0000 xxxx(clear the first four bits)

– Examples: AND BL, 0FH

• OR– Used in setting certain bits

xxxx xxxx OR 0000 1111 = xxxx 1111(Set the upper four bits)

• AND– Especially used in clearing certain bits (masking)

xxxx xxxx AND 0000 1111 = 0000 xxxx(clear the first four bits)

– Examples: AND BL, 0FH

• OR– Used in setting certain bits

xxxx xxxx OR 0000 1111 = xxxx 1111(Set the upper four bits)

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XOR– Used in Inverting bits

xxxx xxxx XOR 0000 1111 = xxxxx’x’x’x’

-Example: Clear bits 0 and 1, set bits 6 and 7, invertbit 5 of register CL:

AND CL, FCH ; 1111 1100B

OR CL, C0H ; 1100 0000B

XOR CL, 20H ; 0010 0000B

XOR– Used in Inverting bits

xxxx xxxx XOR 0000 1111 = xxxxx’x’x’x’

-Example: Clear bits 0 and 1, set bits 6 and 7, invertbit 5 of register CL:

AND CL, FCH ; 1111 1100B

OR CL, C0H ; 1100 0000B

XOR CL, 20H ; 0010 0000B

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SHL Instruction

The SHL (shift left) instruction performs a logical left shifton the destination operand, filling the lowest bit with 0.

CF

0

CF

0

mov dl,5d

shl dl,1

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SHR Instruction

The SHR (shift right) instruction performs a logical right shifton the destination operand. The highest bit position is filledwith a zero.

CF

0

CF

0

MOV DL,80dSHR DL,1 ; DL = 40SHR DL,2 ; DL = 10

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SAR Instruction

SAR (shift arithmetic right) performs a rightarithmetic shift on the destination operand.

CFCF

An arithmetic shift preserves the number's sign.

MOV DL,-80SAR DL,1 ; DL = -40SAR DL,2 ; DL = -10

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Shifting left n bits multiplies the operand by 2n

For example, 5 * 22 = 20

Shifting right n bits divides the operand by 2n

For example, 80 / 23 = 10

mov dl,5

shl dl,1

Shifting left n bits multiplies the operand by 2n

For example, 5 * 22 = 20

Shifting right n bits divides the operand by 2n

For example, 80 / 23 = 10

0 0 0 0 1 0 1 0

0 0 0 0 0 1 0 1 = 5

= 10

Before:

After:

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ROL Instruction

ROL (rotate) shifts each bit to the left The highest bit is copied into both the Carry flag

and into the lowest bit No bits are lost

CFCF

MOV Al,11110000bROL Al,1 ; AL = 11100001b

MOV Dl,3FhROL Dl,4 ; DL = F3h

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ROR Instruction ROR (rotate right) shifts each bit to the right The lowest bit is copied into both the Carry flag and

into the highest bit No bits are lost

CFCF

MOV AL,11110000bROR AL,1 ; AL = 01111000b

MOV DL,3FhROR DL,4 ; DL = F3h

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RCL Instruction RCL (rotate carry left) shifts each bit to the left Copies the Carry flag to the least significant bit Copies the most significant bit to the Carry flag

CFCF

CLC ; CF = 0

MOV BL,88H ; CF,BL = 0 10001000b

RCL BL,1 ; CF,BL = 1 00010000b

RCL BL,1 ; CF,BL = 0 00100001b152

RCR Instruction RCR (rotate carry right) shifts each bit to the right Copies the Carry flag to the most significant bit Copies the least significant bit to the Carry flag

CF

STC ; CF = 1

MOV AH,10H ; CF,AH = 00010000 1

RCR AH,1 ; CF,AH = 10001000 0

CF

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Branching Instructions (or)Program Execution Transfer

Instructions

These instructions cause change in the sequence of the executionof instruction.

This change can be through a condition or sometimesunconditional.

The conditions are represented by flags.

These instructions cause change in the sequence of the executionof instruction.

This change can be through a condition or sometimesunconditional.

The conditions are represented by flags.

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CALL Des:

This instruction is used to call a subroutine or function orprocedure.

The address of next instruction after CALL is saved onto stack.

RET:

It returns the control from procedure to calling program.

Every CALL instruction should have a RET.

CALL Des:

This instruction is used to call a subroutine or function orprocedure.

The address of next instruction after CALL is saved onto stack.

RET:

It returns the control from procedure to calling program.

Every CALL instruction should have a RET.

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SUBROUTINE & SUBROUTINE HANDILING INSTRUCTIONS

Call subroutine A

Next instruction

Main program

Subroutine A

First Instruction

Call subroutine A

Next instruction

Return

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JMP Des:

This instruction is used for unconditional jump from one place toanother.

Jxx Des (Conditional Jump):

All the conditional jumps follow some conditional statements or anyinstruction that affects the flag.

JMP Des:

This instruction is used for unconditional jump from one place toanother.

Jxx Des (Conditional Jump):

All the conditional jumps follow some conditional statements or anyinstruction that affects the flag.

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Conditional Jump TableMnemonic Meaning

JA Jump if Above

JAE Jump if Above or Equal

JB Jump if Below

JBE Jump if Below or EqualJBE Jump if Below or Equal

JC Jump if Carry

JE Jump if Equal

JNC Jump if Not Carry

JNE Jump if Not Equal

JNZ Jump if Not Zero

JPE Jump if Parity Even

JPO Jump if Parity Odd

JZ Jump if Zero158

Loop Des:

This is a looping instruction.

The number of times looping is required is placed in the CXregister.

With each iteration, the contents of CX are decremented.

ZF is checked whether to loop again or not.

Loop Des:

This is a looping instruction.

The number of times looping is required is placed in the CXregister.

With each iteration, the contents of CX are decremented.

ZF is checked whether to loop again or not.

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String Instructions String in assembly language is just a sequentially stored bytes or

words.

There are very strong set of string instructions in 8086.

By using these string instructions, the size of the program isconsiderably reduced.

String in assembly language is just a sequentially stored bytes orwords.

There are very strong set of string instructions in 8086.

By using these string instructions, the size of the program isconsiderably reduced.

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CMPS Des, Src:

It compares the string bytes or words.

SCAS String:

It scans a string.

It compares the String with byte in AL or with word inAX.

CMPS Des, Src:

It compares the string bytes or words.

SCAS String:

It scans a string.

It compares the String with byte in AL or with word inAX.

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MOVS / MOVSB / MOVSW:

It causes moving of byte or word from one string to another.

In this instruction, the source string is in Data Segment anddestination string is in Extra Segment.

SI and DI store the offset values for source and destination index.

MOVS / MOVSB / MOVSW:

It causes moving of byte or word from one string to another.

In this instruction, the source string is in Data Segment anddestination string is in Extra Segment.

SI and DI store the offset values for source and destination index.

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REP (Repeat):

This is an instruction prefix.

It causes the repetition of the instruction until CX becomes zero.

E.g.: REP MOVSB STR1, STR2

It copies byte by byte contents.

REP repeats the operation MOVSB until CX becomes zero.

REP (Repeat):

This is an instruction prefix.

It causes the repetition of the instruction until CX becomes zero.

E.g.: REP MOVSB STR1, STR2

It copies byte by byte contents.

REP repeats the operation MOVSB until CX becomes zero.

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Processor Control Instructions These instructions control the processor itself.

8086 allows to control certain control flags that:

causes the processing in a certain direction

processor synchronization if more than one microprocessorattached.

These instructions control the processor itself.

8086 allows to control certain control flags that:

causes the processing in a certain direction

processor synchronization if more than one microprocessorattached.

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STC

It sets the carry flag to 1.

CLC

It clears the carry flag to 0.

CMC

It complements the carry flag.

STC

It sets the carry flag to 1.

CLC

It clears the carry flag to 0.

CMC

It complements the carry flag.

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STD: It sets the direction flag to 1.

If it is set, string bytes are accessed from higher memory address tolower memory address.

CLD: It clears the direction flag to 0.

If it is reset, the string bytes are accessed from lower memoryaddress to higher memory address.

STD: It sets the direction flag to 1.

If it is set, string bytes are accessed from higher memory address tolower memory address.

CLD: It clears the direction flag to 0.

If it is reset, the string bytes are accessed from lower memoryaddress to higher memory address.

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HLT instruction – HALT processing

The HLT instruction will cause the 8086 to stop fetching andexecuting instructions.

NOP instructionthis instruction simply takes up three clock cycles and does no

processing.

LOCK instructionthis is a prefix to an instruction. This prefix makes sure that during

execution of the instruction, control of system bus is not taken by othermicroprocessor.

WAIT instructionthis instruction takes 8086 to an idle condition. The CPU

will not do any processing during this.

HLT instruction – HALT processing

The HLT instruction will cause the 8086 to stop fetching andexecuting instructions.

NOP instructionthis instruction simply takes up three clock cycles and does no

processing.

LOCK instructionthis is a prefix to an instruction. This prefix makes sure that during

execution of the instruction, control of system bus is not taken by othermicroprocessor.

WAIT instructionthis instruction takes 8086 to an idle condition. The CPU

will not do any processing during this.167

INSTRUCTION SET-summary1.DATA TRANSFER INSTRUCTIONS

Mnemonic Meaning Format Operation

MOV Move Mov D,S (S) (D)

XCHG Exchange XCHG D,S (S) (D)

LEA Load Effective Address LEA Reg16,EA EA (Reg16)

PUSH pushes the operand into top ofstack.

PUSH BXPUSH pushes the operand into top ofstack.

PUSH BX

POP pops the operand from top ofstack to Des.

POP BX

IN transfers the operand fromspecified port to accumulatorregister.

IN AX,0028

OUT transfers the operand fromaccumulator to specifiedport.

OUT 0028,BX

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2. ARITHMETIC INSTRUCTIONSMnemonic Meaning Format Operation

SUB Subtract SUB D,S (D) - (S) (D)

Borrow (CF)

SBB Subtract withborrow

SBB D,S (D) - (S) - (CF) (D)

DEC Decrement by one DEC D (D) - 1 (D)

NEG Negate NEG D

DAS Decimal adjust forsubtraction

DAS Convert the result in AL to packeddecimal format

DAS Decimal adjust forsubtraction

DAS Convert the result in AL to packeddecimal format

AAS ASCII adjust forsubtraction

AAS (AL) difference (AH) dec by 1 ifborrow

ADD Addition ADD D,S (S)+(D) (D) carry (CF)

ADC Add with carry ADC D,S (S)+(D)+(CF) (D) carry (CF)

INC Increment by one INC D (D)+1 (D)

AAA ASCII adjust foraddition

AAA If the sum is >9, AH

is incremented by 1DAA Decimal adjust for

additionDAA Adjust AL for decimal Packed BCD169

Mnemonic Meaning Format Operation

AND

OR

XOR

NOT

Logical AND

Logical Inclusive OR

Logical Exclusive OR

LOGICAL NOT

AND D,S

OR D,S

XOR D,S

NOT D

(S) · (D) → (D)

(S)+(D) → (D)

(S) (D)→(D)

(D) → (D)

+

3. Bit Manipulation Instructions(Logical Instructions)

AND

OR

XOR

NOT

Logical AND

Logical Inclusive OR

Logical Exclusive OR

LOGICAL NOT

AND D,S

OR D,S

XOR D,S

NOT D

(S) · (D) → (D)

(S)+(D) → (D)

(S) (D)→(D)

(D) → (D)


Shift & Rotate InstructionsMnemonic Meaning Format

SAL/SHL

SHR

SAR

Shift arithmetic Left/Shift Logical left

Shift logical right

Shift arithmeticright

SAL/SHL D, Count

SHR D, Count

SAR D, Count

Mnemonic Meaning Format

ROL Rotate Left ROL D,Count

ROR Rotate Right ROR D,Count

RCL Rotate Left through Carry RCL D,Count

RCR Rotate right through Carry RCR D,Count

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4. Branching or PROGRAMEXECUTION TRANSFER INSTRUCTIONS• CALL - call a subroutine• RET - returns the control from procedure to calling

program

• JMP Des – Unconditional Jump• Jxx Des – conditional Jump (ex: JC 8000)• Loop Des

• CALL - call a subroutine• RET - returns the control from procedure to calling

program

• JMP Des – Unconditional Jump• Jxx Des – conditional Jump (ex: JC 8000)• Loop Des

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5. STRING INSTRUCTIONS

• CMPS Des, Src - compares the string bytes• SCAS String - scans a string• MOVS / MOVSB / MOVSW - moving of byte or

word• REP (Repeat) - repetition of the instruction

• CMPS Des, Src - compares the string bytes• SCAS String - scans a string• MOVS / MOVSB / MOVSW - moving of byte or

word• REP (Repeat) - repetition of the instruction

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6. PROCESSOR CONTROL INSTRUCTIONS• STC – set the carry flag (CF=1)• CLC – clear the carry flag (CF=0)• STD – set the direction flag (DF=1)• CLD – clear the direction flag (DF=0)• HLT – stop fetching & execution• NOP – no operation(no processing)• LOCK - control of system bus is not taken by other µP

• WAIT - CPU will not do any processing• ESC - µP does NOP or access a data from memory for coprocessor

• STC – set the carry flag (CF=1)• CLC – clear the carry flag (CF=0)• STD – set the direction flag (DF=1)• CLD – clear the direction flag (DF=0)• HLT – stop fetching & execution• NOP – no operation(no processing)• LOCK - control of system bus is not taken by other µP

• WAIT - CPU will not do any processing• ESC - µP does NOP or access a data from memory for coprocessor

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AssemblerDirectivesAssemblerDirectives

175

Directives Expansion

176

• ASSUME Directive - The ASSUME directive isused to tell the assembler that the name ofthe logical segment should be used for aspecified segment.

• DB(define byte) - DB directive is used todeclare a byte type variable or to store a bytein memory location.

• DW(define word) - The DW directive is usedto define a variable of type word or to reservestorage location of type word in memory.

• ASSUME Directive - The ASSUME directive isused to tell the assembler that the name ofthe logical segment should be used for aspecified segment.

• DB(define byte) - DB directive is used todeclare a byte type variable or to store a bytein memory location.

• DW(define word) - The DW directive is usedto define a variable of type word or to reservestorage location of type word in memory.


• DD(define double word) :This directive is usedto declare a variable of type double word orrestore memory locations which can beaccessed as type double word.

• DQ (define quadword) :This directive is usedto tell the assembler to declare a variable 4words in length or to reserve 4 words ofstorage in memory .

• DT (define ten bytes):It is used to inform theassembler to define a variable which is 10bytes in length or to reserve 10 bytes ofstorage in memory.

• DD(define double word) :This directive is usedto declare a variable of type double word orrestore memory locations which can beaccessed as type double word.

• DQ (define quadword) :This directive is usedto tell the assembler to declare a variable 4words in length or to reserve 4 words ofstorage in memory .

• DT (define ten bytes):It is used to inform theassembler to define a variable which is 10bytes in length or to reserve 10 bytes ofstorage in memory.

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• END- End program .This directive indicates theassembler that this is the end of the programmodule. The assembler ignores anystatements after an END directive.

• ENDP- End procedure: It indicates the end ofthe procedure (subroutine) to the assembler.

• ENDS-End Segment: This directive is used withthe name of the segment to indicate the endof that logical segment.

• EQU - This EQU directive is used to give aname to some value or to a symbol.

• END- End program .This directive indicates theassembler that this is the end of the programmodule. The assembler ignores anystatements after an END directive.

• ENDP- End procedure: It indicates the end ofthe procedure (subroutine) to the assembler.

• ENDS-End Segment: This directive is used withthe name of the segment to indicate the endof that logical segment.

• EQU - This EQU directive is used to give aname to some value or to a symbol.

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• PROC - The PROC directive is used to identifythe start of a procedure.

• PTR -This PTR operator is used to assign aspecific type of a variable or to a label.

• ORG -Originate : The ORG statementchanges the starting offset address of thedata.

• PROC - The PROC directive is used to identifythe start of a procedure.

• PTR -This PTR operator is used to assign aspecific type of a variable or to a label.

• ORG -Originate : The ORG statementchanges the starting offset address of thedata.

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Directives examples

• ASSUME CS:CODE cs=> code segment• ORG 3000• NAME DB ‘THOMAS’• POINTER DD 12341234H

• FACTOR EQU 03H

• ASSUME CS:CODE cs=> code segment• ORG 3000• NAME DB ‘THOMAS’• POINTER DD 12341234H

• FACTOR EQU 03H

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Assembly LanguageProgramming(ALP)

8086

Assembly LanguageProgramming(ALP)

8086

182

Program 1: Increment an 8-bit number

• MOV AL, 05H Move 8-bit data to AL.• INC AL Increment AL.

Program 2: Increment an 16-bit numberProgram 2: Increment an 16-bit number

• MOV AX, 0005H Move 16-bit data to AX.• INC AX Increment AX.


Program 3: Decrement an 8-bit number

• MOV AL, 05H Move 8-bit data to AL.• DEC AL Decrement AL.

Program 4: Decrement an 16-bit numberProgram 4: Decrement an 16-bit number

• MOV AX, 0005H Move 16-bit data to AX.• DEC AX Decrement AX.

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Program 5: 1’s complement of an 8-bit number.

• MOV AL, 05H Move 8-bit data to AL.• NOT AL Complement AL.

Program 6: 1’s complement of a 16-bitnumber.


• MOV AX, 0005H Move 16-bit data to AX.• NOT AX Complement AX.

185

Program 7: 2’s complement of an 8-bit number.• MOV AL, 05H Move 8-bit data to AL.• NOT AL Complement AL.• INC AL Increment AL



• MOV AX, 0005H Move 16-bit data to AX.• NOT AX Complement AX.• INC AX Increment AX

186

Program 7: 2’s complement of an 8-bit number.• MOV AL, 05H Move 8-bit data to AL.• NOT AL Complement AL.• INC AL Increment AL



• MOV AX, 0005H Move 16-bit data to AX.• NOT AX Complement AX.• INC AX Increment AX

187

Program 9: Add two 8-bit numbers

MOV AL, 05H Move 1st 8-bit number to AL.MOV BL, 03H Move 2nd 8-bit number to BL.ADD AL, BL Add BL with AL.

Program 10: Add two 16-bit numbersProgram 10: Add two 16-bit numbers

MOV AX, 0005H Move 1st 16-bit number to AX.MOV BX, 0003H Move 2nd 16-bit number to BX.ADD AX, BX Add BX with AX.

188

Program 11: subtract two 8-bit numbers

MOV AL, 05H Move 1st 8-bit number to AL.MOV BL, 03H Move 2nd 8-bit number to BL.SUB AL, BL subtract BL from AL.

Program 12: subtract two 16-bit numbersProgram 12: subtract two 16-bit numbers

MOV AX, 0005H Move 1st 16-bit number to AX.MOV BX, 0003H Move 2nd 16-bit number to BX.SUB AX, BX subtract BX from AX.

189

Program 13: Multiply two 8-bit unsignednumbers.

MOV AL, 04H Move 1st 8-bit number to AL.MOV BL, 02H Move 2nd 8-bit number to BL.MUL BL Multiply BL with AL and the result will

be in AX.

Program 14: Multiply two 8-bit signednumbers.

Program 14: Multiply two 8-bit signednumbers.

MOV AL, 04H Move 1st 8-bit number to AL.MOV BL, 02H Move 2nd 8-bit number to BL.IMUL BL Multiply BL with AL and the result will

be in AX.

190

Program 15: Multiply two 16-bit unsignednumbers.

MOV AX, 0004H Move 1st 16-bit number to AL.MOV BX, 0002H Move 2nd 16-bit number to BL.MUL BX Multiply BX with AX and the result will

be in DX:AX {4*2=0008=> 08=> AX , 00=> DX}

Program 16: Divide two 16-bit unsignednumbers.

Program 16: Divide two 16-bit unsignednumbers.

MOV AX, 0004H Move 1st 16-bit number to AL.MOV BX, 0002H Move 2nd 16-bit number to BL.DIV BX Divide BX from AX and the result will be in AX & DX

{4/2=0002=> 02=> AX ,00=>DX}(ie: Quotient => AX , Reminder => DX )


Detailed coding16 BIT ADDITION

192

Detailed coding16 BIT SUBTRACTION

193

16 BIT MULTIPLICATION

194

16 BIT DIVISION

195

SUM of N numbersMOV AX,0000MOV SI,1100MOV DI,1200MOV CX,0005 5 NUMBERS TO BE TAKEN SUMMOV DX,0000

L1: ADD AX,[SI]INC SIINC DXCMP CX,DXJNZ L1MOV [1200],AXHLT

MOV AX,0000MOV SI,1100MOV DI,1200MOV CX,0005 5 NUMBERS TO BE TAKEN SUMMOV DX,0000

L1: ADD AX,[SI]INC SIINC DXCMP CX,DXJNZ L1MOV [1200],AXHLT 196

Average of N numbersMOV AX,0000MOV SI,1100MOV DI,1200MOV CX,0005 5 NUMBERS TO BE TAKEN AVERAGEMOV DX,0000

L1: ADD AX,[SI]INC SIINC DXCMP CX,DXJNZ L1DIV CX AX=AX/5(AVERAGE OF 5 NUMBERS)MOV [1200],AXHLT

MOV AX,0000MOV SI,1100MOV DI,1200MOV CX,0005 5 NUMBERS TO BE TAKEN AVERAGEMOV DX,0000

L1: ADD AX,[SI]INC SIINC DXCMP CX,DXJNZ L1DIV CX AX=AX/5(AVERAGE OF 5 NUMBERS)MOV [1200],AXHLT 197Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode

FACTORIAL of NMOV CX,0005 5 Factorial=5*4*3*2*1=120MOV DX,0000MOV AX,0001

L1: MUL CXDEC DXCMP CX,DXJNZ L1MOV [1200],AXHLT

MOV CX,0005 5 Factorial=5*4*3*2*1=120MOV DX,0000MOV AX,0001

L1: MUL CXDEC DXCMP CX,DXJNZ L1MOV [1200],AXHLT

198

ASCENDING ORDER

199

200

DECENDING ORDER

Note: change the coding JNB L1 into JB L1 in the LINE 10201

LARGEST, smallest NUMBER IN ANARRAY

202

LARGEST NUMBER

203

SMALLEST NUMBER

204

ModularProgramming

ModularProgramming

205

• Generally , industry-programming projects consistof thousands of lines of instructions or operationcode.

• The size of the modules are reduced to a humanlycomprehensible and manageable level.

• Program is composed from several smallermodules. Modules could be developed byseparate teams concurrently.OBJ modules(Object modules).

• The .OBJ modules so produced are combinedusing a LINK program.

• Modular programming techniques simplify thesoftware development process

• Generally , industry-programming projects consistof thousands of lines of instructions or operationcode.

• The size of the modules are reduced to a humanlycomprehensible and manageable level.

• Program is composed from several smallermodules. Modules could be developed byseparate teams concurrently.OBJ modules(Object modules).

• The .OBJ modules so produced are combinedusing a LINK program.

• Modular programming techniques simplify thesoftware development process

206

CHARACTERISTICS of module:1. Each module is independent of other modules.2. Each module has one input and one output.3. A module is small in size.4. Programming a single function per module is a goalAdvantages of Modular Programming:• It is easy to write, test and debug a module.• Code can be reused.• The programmer can divide tasks.• Re-usable Modules can be re-used within a programDRAWBACKS:Modular programming requires extra time and memory

CHARACTERISTICS of module:1. Each module is independent of other modules.2. Each module has one input and one output.3. A module is small in size.4. Programming a single function per module is a goalAdvantages of Modular Programming:• It is easy to write, test and debug a module.• Code can be reused.• The programmer can divide tasks.• Re-usable Modules can be re-used within a programDRAWBACKS:Modular programming requires extra time and memory

207

MODULAR PROGRAMMING:1.LINKING & RELOCATION2.STACKS3.Procedures4.Interrupts & Interrupt Routines5.Macros

MODULAR PROGRAMMING:1.LINKING & RELOCATION2.STACKS3.Procedures4.Interrupts & Interrupt Routines5.Macros

208

LINKING &RELOCATIONLINKING &

RELOCATION209

LINKER• A linker is a program used to join together several

object files into one large object file.• The linker produces a link file which contains the

binary codes for all the combined modules.

The linker program is invoked using the followingoptions.C> LINK

orC>LINK MS.OBJ

• A linker is a program used to join together severalobject files into one large object file.

• The linker produces a link file which contains thebinary codes for all the combined modules.

The linker program is invoked using the followingoptions.C> LINK

orC>LINK MS.OBJ

210

• The loader is a part of the operating systemand places codes into the memory afterreading the ‘.exe’ file

• A program called locator reallocates thelinked file and creates a file for permanentlocation of codes in a standard format.

211

Creation and execution of a program

212

Loader->Loader is a utility program which takes object code as

input prepares it for execution and loads theexecutable code into the memory .

->Loader is actually responsible for initializing theprocess of execution.

Functions of loaders:1.It allocates the space for program in the memory(Allocation)2.It resolves the code between the object modules(Linking)3. some address dependent locations in the program, address constants

must be adjusted according to allocated space(Relocation)4. It also places all the machine instructions and data of corresponding

programs and subroutines into the memory .(Loading)

Loader->Loader is a utility program which takes object code as

input prepares it for execution and loads theexecutable code into the memory .

->Loader is actually responsible for initializing theprocess of execution.

Functions of loaders:1.It allocates the space for program in the memory(Allocation)2.It resolves the code between the object modules(Linking)3. some address dependent locations in the program, address constants

must be adjusted according to allocated space(Relocation)4. It also places all the machine instructions and data of corresponding

programs and subroutines into the memory .(Loading)

213

Relocating loader (BSS Loader)• When a single subroutine is changed then all

the subroutine needs to be reassembled.• The binary symbolic subroutine (BSS) loader

used in IBM 7094 machine is relocating loader.• In BSS loader there are many procedure

segments• The assembler reads one sourced program

and assembles each procedure segmentindependently

• When a single subroutine is changed then allthe subroutine needs to be reassembled.

• The binary symbolic subroutine (BSS) loaderused in IBM 7094 machine is relocating loader.

• In BSS loader there are many proceduresegments

• The assembler reads one sourced programand assembles each procedure segmentindependently

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• The output of the relocating loader is the object program• The assembler takes the source program as input; this source

program may call some external routines.SEGMENT COMBINATION:

ASM-86 assembler regulating the way segments with thesame name are concatenated & sometimes they are overlaid.

Form of segment directive:Segment name SEGEMENT Combine-type

Possible combine-type are:• PUBLIC• COMMON• STACK• AT• MEMORY

• The output of the relocating loader is the object program• The assembler takes the source program as input; this source

program may call some external routines.SEGMENT COMBINATION:

ASM-86 assembler regulating the way segments with thesame name are concatenated & sometimes they are overlaid.

Form of segment directive:Segment name SEGEMENT Combine-type

Possible combine-type are:• PUBLIC• COMMON• STACK• AT• MEMORY

215

ProceduresProcedures216

• Procedure is a part of code that can be called fromyour program in order to make some specific task.Procedures make program more structural andeasier to understand.

• syntax for procedure declaration:name PROC

…………. ; here goes the code…………. ; of the procedure ...

RET

name ENDP

here PROC is the procedure name.(used in top & bottom)RET - used to return from OS. CALL-call a procedurePROC & ENDP – complier directivesCALL & RET - instructions

• Procedure is a part of code that can be called fromyour program in order to make some specific task.Procedures make program more structural andeasier to understand.

• syntax for procedure declaration:name PROC

…………. ; here goes the code…………. ; of the procedure ...

RET

name ENDP

here PROC is the procedure name.(used in top & bottom)RET - used to return from OS. CALL-call a procedurePROC & ENDP – complier directivesCALL & RET - instructions 217

EXAMPLE 1 (call a procedure)ORG 100hCALL m1MOV AX, 2RET ; return to operating system.

m1 PROCMOV BX, 5RET ; return to caller.m1 ENDPEND

• The above example calls procedure m1, does MOV BX, 5 &returns to the next instruction after CALL: MOV AX, 2.

ORG 100hCALL m1MOV AX, 2RET ; return to operating system.

m1 PROCMOV BX, 5RET ; return to caller.m1 ENDPEND

• The above example calls procedure m1, does MOV BX, 5 &returns to the next instruction after CALL: MOV AX, 2.


Example 2 : several ways to passparameters to procedure

ORG 100hMOV AL, 1MOV BL, 2CALL m2CALL m2CALL m2CALL m2

RET ; return to operating system.

m2 PROCMUL BL ; AX = AL * BL.RET ; return to caller.m2 ENDPEND

ORG 100hMOV AL, 1MOV BL, 2CALL m2CALL m2CALL m2CALL m2

RET ; return to operating system.

m2 PROCMUL BL ; AX = AL * BL.RET ; return to caller.m2 ENDPEND

value of AL register is update every time theprocedure is called.final result in AX register is 16 (or 10h) 219

220

• Stack is an area of memory for keepingtemporary data.

• STACK is used by CALL & RET instructions.PUSH -stores 16 bit value in the stack.POP -gets 16 bit value from the stack.

• PUSH and POP instruction are especially usefulbecause we don't have too much registers to operate

1. Store original value of the register in stack (usingPUSH).

2. Use the register for any purpose.3. Restore the original value of the register from stack

(using POP).

• Stack is an area of memory for keepingtemporary data.

• STACK is used by CALL & RET instructions.PUSH -stores 16 bit value in the stack.POP -gets 16 bit value from the stack.

• PUSH and POP instruction are especially usefulbecause we don't have too much registers to operate

1. Store original value of the register in stack (usingPUSH).

2. Use the register for any purpose.3. Restore the original value of the register from stack

(using POP).

221

Example-1 (store value in STACK usingPUSH & POP)

ORG 100hMOV AX, 1234hPUSH AX ; store value of AX in stack.MOV AX, 5678h ; modify the AX value.POP AX ; restore the original value of AX.RETEND

ORG 100hMOV AX, 1234hPUSH AX ; store value of AX in stack.MOV AX, 5678h ; modify the AX value.POP AX ; restore the original value of AX.RETEND

222

Example 2: use of the stack is forexchanging the values

ORG 100hMOV AX, 1212h ; store 1212h in AX.MOV BX, 3434h ; store 3434h in BXPUSH AX ; store value of AX in stack.PUSH BX ; store value of BX in stack.POP AX ; set AX to original value of BX.POP BX ; set BX to original value of AX.RETEND

ORG 100hMOV AX, 1212h ; store 1212h in AX.MOV BX, 3434h ; store 3434h in BXPUSH AX ; store value of AX in stack.PUSH BX ; store value of BX in stack.POP AX ; set AX to original value of BX.POP BX ; set BX to original value of AX.RETEND

push 1212h and then 3434h, on pop we willfirst get 3434h and only after it 1212h 223

MACROSMACROS224

• Macros are just like procedures, but not really.• Macros exist only until your code is compiled• After compilation all macros are replaced with

real instructions• several macros to make coding easier(Reduce

large & complex programs)Example (Macro definition)

name MACRO [parameters,...]<instructions>ENDM

• Macros are just like procedures, but not really.• Macros exist only until your code is compiled• After compilation all macros are replaced with

real instructions• several macros to make coding easier(Reduce

large & complex programs)Example (Macro definition)

name MACRO [parameters,...]<instructions>ENDM

225

Example1 : Macro DefinitionsSAVE MACRO definition of MACRO name SAVE

PUSH AXPUSH BXPUSH CXENDM

RETREIVE MACRO Another definition of MACRO name RETREIVE

POP CXPOP BXPOP AXENDM

SAVE MACRO definition of MACRO name SAVEPUSH AXPUSH BXPUSH CXENDM

RETREIVE MACRO Another definition of MACRO name RETREIVE

POP CXPOP BXPOP AXENDM

226

227

MACROS with Parameters

Example:COPY MACRO x, y ; macro named COPY with

2 parameters{x, y}

PUSH AXMOV AX, xMOV y, AXPOP AXENDM

Example:COPY MACRO x, y ; macro named COPY with

2 parameters{x, y}

PUSH AXMOV AX, xMOV y, AXPOP AXENDM

228

INTERRUPTS&

INTERRUPT SERVICEROUTINE(ISR)

INTERRUPTS&

INTERRUPT SERVICEROUTINE(ISR)

229

INTERRUPT & ISR ?

• ‘Interrupts’ is to break the sequence ofoperation.

• While the CPU is executing a program, on‘interrupt’ breaks the normal sequence ofexecution of instructions, diverts its executionto some other program called InterruptService Routine (ISR)

• ‘Interrupts’ is to break the sequence ofoperation.

• While the CPU is executing a program, on‘interrupt’ breaks the normal sequence ofexecution of instructions, diverts its executionto some other program called InterruptService Routine (ISR)

230

231

232

233

• Maskable Interrupt: An Interrupt that can bedisabled or ignored by the instructions of CPUare called as Maskable Interrupt.

• Non- Maskable Interrupt: An interrupt thatcannot be disabled or ignored by the instructionsof CPU are called as Non- Maskable Interrupt.

• Software interrupts are machine instructionsthat amount to a call to the designated interruptsubroutine, usually identified by interruptnumber. Ex: INT0 - INT255

• Maskable Interrupt: An Interrupt that can bedisabled or ignored by the instructions of CPUare called as Maskable Interrupt.

• Non- Maskable Interrupt: An interrupt thatcannot be disabled or ignored by the instructionsof CPU are called as Non- Maskable Interrupt.

• Software interrupts are machine instructionsthat amount to a call to the designated interruptsubroutine, usually identified by interruptnumber. Ex: INT0 - INT255

234

235

236

237

238

239

INTERRUPT VECTOR TABLE256 INTERRUPTS OF 8086 ARE DIVIDED IN TO 3 GROUPS

1. TYPE 0 TO TYPE 4 INTERRUPTS-These Are Used For Fixed Operations And Hence Are CalledDedicated Interrupts2. TYPE 5 TO TYPE 31 INTERRUPTSNot Used By 8086,reserved For Higher Processors Like 8028680386 Etc3. TYPE 32 TO 255 INTERRUPTSAvailable For User, called User Defined Interrupts These CanBe H/W Interrupts And Activated Through Intr Line Or Can BeS/W Interrupts.

1. TYPE 0 TO TYPE 4 INTERRUPTS-These Are Used For Fixed Operations And Hence Are CalledDedicated Interrupts2. TYPE 5 TO TYPE 31 INTERRUPTSNot Used By 8086,reserved For Higher Processors Like 8028680386 Etc3. TYPE 32 TO 255 INTERRUPTSAvailable For User, called User Defined Interrupts These CanBe H/W Interrupts And Activated Through Intr Line Or Can BeS/W Interrupts. 240

Type – 0 Divide Error Interrupt

Quotient is too large cant be fit in AL/AX or Divide By Zero {AX/0=∞}

Type –1 Single Step Interruptused for executing the program in single step mode by setting Trap Flag

To Set Trap Flag PUSHFMOV BP,SPOR [BP+0],0100H;SET BIT8POPF

Type – 2 Non Maskable InterruptThis Interrupt is used for executing ISR of NMI Pin (Positive Egde Signal). NMIcant be masked by S/W

Type – 3 Break Point Interrupt

used for providing BREAK POINTS in the program

Type – 4 Over Flow Interrupt

used to handle any Overflow Error after signed arithmetic

Type – 0 Divide Error Interrupt

Quotient is too large cant be fit in AL/AX or Divide By Zero {AX/0=∞}

Type –1 Single Step Interruptused for executing the program in single step mode by setting Trap Flag

To Set Trap Flag PUSHFMOV BP,SPOR [BP+0],0100H;SET BIT8POPF

Type – 2 Non Maskable InterruptThis Interrupt is used for executing ISR of NMI Pin (Positive Egde Signal). NMIcant be masked by S/W

Type – 3 Break Point Interrupt

used for providing BREAK POINTS in the program

Type – 4 Over Flow Interrupt

used to handle any Overflow Error after signed arithmetic241

PRIORITY OF INTERRUPTSInterrupt Type PriorityINT0, INT3-INT 255, HighestNMI(INT2)NMI(INT2)INTRSINGLE STEP Lowest242

Byte &String

Manipulation

Byte &String

Manipulation243

Move, compare, store, load, scan

Refer String Instructions in Instruction SetSlide No: 160-163

244

Byte ManipulationExample 1:

MOV AX,[1000]MOV BX,[1002]AND AX,BXMOV [2000],AXHLT

Example 2:MOV AX,[1000]MOV BX,[1002]OR AX,BXMOV [2000],AXHLT

Example 3:MOV AX,[1000]MOV BX,[1002]XOR AX,BXMOV [2000],AXHLT

Example 4:MOV AX,[1000]NOT AXMOV [2000],AXHLT

Example 1:MOV AX,[1000]MOV BX,[1002]AND AX,BXMOV [2000],AXHLT

Example 2:MOV AX,[1000]MOV BX,[1002]OR AX,BXMOV [2000],AXHLT

Example 3:MOV AX,[1000]MOV BX,[1002]XOR AX,BXMOV [2000],AXHLT

Example 4:MOV AX,[1000]NOT AXMOV [2000],AXHLT


STRING MANIPULATION1. Copying a string (MOV SB)

MOV CX,0003 copy 3 memory locationsMOV SI,1000MOV DI,2000

L1 CLDMOV SBDEC CX decrement CXJNZ L1HLT

MOV CX,0003 copy 3 memory locationsMOV SI,1000MOV DI,2000

L1 CLDMOV SBDEC CX decrement CXJNZ L1HLT

246

2. Find & Replace

247

UNIT-28086 SYSTEM

BUS STRUCTURE

DEPARTMENTS: CSE,IT,ECE,ECE,MECHRegulation : 2013

UNIT-28086 SYSTEM

BUS STRUCTURE248

8086 signals or Pin Diagram

Refer UNIT-1 Slide No: 43-54Refer UNIT-1 Slide No: 43-54

249

GNDAD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0NMI

INTRCLKGND

VccAD15A16/S3A17/S4A18/S5A19/S6___BHE/S7 (HIGH)___MN/MX___RD ___ ____HOLD (RQ/GT0)___ ____HLDA (RQ/GT1)___ ______WR (LOCK)__ __IO/M (S2)__ __DT/R (S1)____ __DEN (S0)ALE (QS0)_____INTA (QS1)_____TESTREADYRESET

1 40

INTEL8086

20 21

Minmode operationsignals (MN/MX=1)

Maxmode operationsignals (MN/MX=0)

Time-multiplexedAddress / Data Bus

(bidirectional)

0V=“0”,reference

for allvoltages

5V±10%

Time-multiplexedAddress Bus

/Status signals(outputs)

Operation Mode,(input):

1 = minmode(8088 generates allthe needed controlsignals for a small

system),

0 = maxmode(8288 Bus

Controller expandsthe status signals to

generate morecontrol signals)

ControlBus

(in,out)

GNDAD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0NMI

INTRCLKGND

VccAD15A16/S3A17/S4A18/S5A19/S6___BHE/S7 (HIGH)___MN/MX___RD ___ ____HOLD (RQ/GT0)___ ____HLDA (RQ/GT1)___ ______WR (LOCK)__ __IO/M (S2)__ __DT/R (S1)____ __DEN (S0)ALE (QS0)_____INTA (QS1)_____TESTREADYRESET

1 40

INTEL8086

20 21

Time-multiplexedAddress / Data Bus

(bidirectional)

Hardwareinterrupt requests

(inputs)

2...5MHz,1/3 duty cycle

(input)

Statussignals

(outputs)

Operation Mode,(input):

1 = minmode(8088 generates allthe needed controlsignals for a small

system),

0 = maxmode(8288 Bus

Controller expandsthe status signals to

generate morecontrol signals)

Interruptacknowledge

(output)

ControlBus

(in,out)

250

MINIMUM MODE SIGNALS

251

MAXIMUM MODE SIGNALS

252

SYSTEM BUSTIMING

SYSTEM BUSTIMING

253

System Timing Diagrams

T-State:— One clock period is referred to as a T-State

T-State

— An operation takes an integer number of T-States— An operation takes an integer number of T-States

CPU Bus Cycle:— A bus cycle consists of 4 or more T-States

T1 T2 T3 T4

254

Memory Read Timing Diagrams

• Dump address on address bus.• Issue a read ( RD ) and set M/ IO to 1.• Wait for memory access cycle.

255

• Dump address on address bus.• Dump data on data bus.• Issue a write ( WR ) and set M/ IO to 1.

Memory Write Timing Diagrams

256

Bus TimingDuring T 1 :• The address is placed on the Address/Data bus.• Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the address

onto the address bus and set the direction of data transfer on data bus.During T 2 :• 8086 issues the RD or WR signal, DEN , and, for a write, the data.

• DEN enables the memory or I/O device to receive the data for writes and the 8086 toreceive the data for reads.

During T 3 :• This cycle is provided to allow memory to access data.• READY is sampled at the end of T 2 .

• If low, T 3 becomes a wait state.• Otherwise, the data bus is sampled at the end of T 3 .

During T 4 :• All bus signals are deactivated, in preparation for next bus cycle.• Data is sampled for reads, writes occur for writes.

During T 1 :• The address is placed on the Address/Data bus.• Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the address

onto the address bus and set the direction of data transfer on data bus.During T 2 :• 8086 issues the RD or WR signal, DEN , and, for a write, the data.

• DEN enables the memory or I/O device to receive the data for writes and the 8086 toreceive the data for reads.

During T 3 :• This cycle is provided to allow memory to access data.• READY is sampled at the end of T 2 .

• If low, T 3 becomes a wait state.• Otherwise, the data bus is sampled at the end of T 3 .

During T 4 :• All bus signals are deactivated, in preparation for next bus cycle.• Data is sampled for reads, writes occur for writes.

257

Setup & Hold Time

Setup time – The time before the rising edge of the clock, while the datamust be valid and constantHold time – The time after the rising edge of the clock during which the datamust remain valid and constant

258

WAIT State

• A wait state (Tw) is an extra clocking period, insertedbetween T2 and T3, to lengthen the bus cycle, allowingslower memory and I/O components to respond.

• The READY input is sampled at the end of T2, and again,if necessary in the middle of Tw. If READY is ‘0’ then aTw is inserted.

• A wait state (Tw) is an extra clocking period, insertedbetween T2 and T3, to lengthen the bus cycle, allowingslower memory and I/O components to respond.

• The READY input is sampled at the end of T2, and again,if necessary in the middle of Tw. If READY is ‘0’ then aTw is inserted.

259

Basicconfigurations

Basicconfigurations

260

BASIC CONFIGURATIONS-1.Minimum Mode 2.Maximum Mode– Minimum mode(MN/MX=Vcc)

• Pin #33 (MN/MX) connect to +5V• Pin 24-31 are used as memory and I/O control signal• The control signals are generated internally by the 8086/88• More cost-efficient

– Maximum mode(MN/MX=GND)• Pin #33 (MN/MX) connect to Ground• Some control signals are generated externally by the 8288

bus controller chip• Max mode is used when math processor is used.

– Minimum mode(MN/MX=Vcc)• Pin #33 (MN/MX) connect to +5V• Pin 24-31 are used as memory and I/O control signal• The control signals are generated internally by the 8086/88• More cost-efficient

– Maximum mode(MN/MX=GND)• Pin #33 (MN/MX) connect to Ground• Some control signals are generated externally by the 8288

bus controller chip• Max mode is used when math processor is used.

261

Minimum Mode 8086 System• 8086 is operated in minimum mode by

MN/MX pin to logic 1 ( Vcc ).• In this mode, all the control signals are given

out by the microprocessor chip itself.

• 8086 is operated in minimum mode byMN/MX pin to logic 1 ( Vcc ).

• In this mode, all the control signals are givenout by the microprocessor chip itself.

262

263

Explain Minimum mode Signals also: Refer Slide No 47-54

264

265

266

MAXIMUM MODE

267

8288 – BUS CONTROLLERExplain Maximum mode Signals also: Refer Slide No 47-54

268

269

270

MULTIPROCESSORCONFIGURATIONSMULTIPROCESSORCONFIGURATIONS

271

Multiprocessorconfiguration

Coprocessor 8087

Multiprocessorconfiguration

272

Multiprocessor configuration

• Multiprocessor Systems refer to the use of multipleprocessors that executes instructions simultaneouslyand communicate with each other using mail boxes andSemaphores.

• Maximum mode of 8086 is designed to implement 3basic multiprocessor configurations:

1. Coprocessor (8087)2. Closely coupled (8089)3. Loosely coupled (Multibus)

• Multiprocessor Systems refer to the use of multipleprocessors that executes instructions simultaneouslyand communicate with each other using mail boxes andSemaphores.

• Maximum mode of 8086 is designed to implement 3basic multiprocessor configurations:

1. Coprocessor (8087)2. Closely coupled (8089)3. Loosely coupled (Multibus)

273

• Coprocessors and Closely coupled configurations aresimilar in that both the 8086 and the external processorshares the:

- Memory- I/O system- Bus & bus control logic- Clock generator

• Coprocessors and Closely coupled configurations aresimilar in that both the 8086 and the external processorshares the:

- Memory- I/O system- Bus & bus control logic- Clock generator

274

Co-processor – Intel 8087

8087instructionsare insertedin the 8086program

8086 and 8087 readsinstruction bytes andputs them in therespective queues

NOP

8087 instructions have11011 as the MSB oftheir first code byte

275

Coprocessor / Closely CoupledConfiguration

276

TEST pin of 8086

• Used in conjunction with the WAIT instruction inmultiprocessing environments.

• This is input from the 8087 coprocessor.

• During execution of a wait instruction, the CPU checks thissignal.

• If it is low, execution of the signal will continue; if not, itwill stop executing.

• Used in conjunction with the WAIT instruction inmultiprocessing environments.

• This is input from the 8087 coprocessor.

• During execution of a wait instruction, the CPU checks thissignal.

• If it is low, execution of the signal will continue; if not, itwill stop executing.

277

1.Coprocessor Execution ExampleCoprocessor cannot take control of the bus, it does everything through the CPU

278

2.Closely Coupled Execution Example

• Closely Coupledprocessor may takecontrol of the busindependently.

• Two 8086’s cannotbe closely coupled.

• Closely Coupledprocessor may takecontrol of the busindependently.

• Two 8086’s cannotbe closely coupled.

279

3.Loosely Coupled Configuration• has shared system bus, system memory, and system

I/O.

• each processor has its own clock as well as its ownmemory (in addition to access to the system resources).

• Used for medium to large multiprocessor systems.

• Each module is capable of being the bus master.

• Any module could be a processor capable of being a busmaster, a coprocessor configuration or a closely coupledconfiguration.

• has shared system bus, system memory, and systemI/O.

• each processor has its own clock as well as its ownmemory (in addition to access to the system resources).

• Used for medium to large multiprocessor systems.

• Each module is capable of being the bus master.

• Any module could be a processor capable of being a busmaster, a coprocessor configuration or a closely coupledconfiguration.

280

281

Loosely Coupled Configuration• No direct connections between the modules.

• Each share the system bus and communicate throughshared resources.

• Processor in their separate modules can simultaneouslyaccess their private subsystems through their localbusses, and perform their local data references andinstruction fetches independently. This results inimproved degree of concurrent processing.

• Excellent for real time applications, as separate modulescan be assigned specialized tasks

• No direct connections between the modules.

• Each share the system bus and communicate throughshared resources.

• Processor in their separate modules can simultaneouslyaccess their private subsystems through their localbusses, and perform their local data references andinstruction fetches independently. This results inimproved degree of concurrent processing.

• Excellent for real time applications, as separate modulescan be assigned specialized tasks

282

Advantages of MultiprocessorConfiguration

1. High system throughput can be achieved by having more thanone CPU.

2. The system can be expanded in modular form.Each bus master module is an independent unit and normally resides ona separate PC board. One can be added or removed without affecting theothers in the system.

3. A failure in one module normally does not affect the breakdownof the entire system and the faulty module can be easilydetected and replaced

4. Each bus master has its own local bus to access dedicatedmemory or IO devices. So a greater degree of parallel processingcan be achieved.

1. High system throughput can be achieved by having more thanone CPU.

2. The system can be expanded in modular form.Each bus master module is an independent unit and normally resides ona separate PC board. One can be added or removed without affecting theothers in the system.

3. A failure in one module normally does not affect the breakdownof the entire system and the faulty module can be easilydetected and replaced

4. Each bus master has its own local bus to access dedicatedmemory or IO devices. So a greater degree of parallel processingcan be achieved.

283

INTRODUCTIONTO ADVANCEDPROCESSORS

INTRODUCTIONTO ADVANCEDPROCESSORS

284

Intel family of microprocessor, bus and memory sizes

Microprocessor

Data buswidth

Address buswidth

Memory size

80186 16 20 1M

80286 16 24 16M80286 16 24 16M

80386 DX 32 32 4G80486 32 32 4G

Pentium 4 &core 2

64 40 1T


80186

286

80286

287

80386

288

TEXT BOOK ReferencesMain Book:1. Microprocessors and Interfacing, Programming and Hardware by Doughlas

V.HallOther Authors:

2. Microcomputer Systems: The 8086 / 8088 Family -Architecture,Programming and Design by Yu-Cheng Liu, Glenn A.Gibson

3. INTEL Microprocessors 8086/8088, 80186/80188, 80286, 80386, 80486,Pentium, Prentium ProProcessor, Pentium II, III, 4 by Barry B. Bery

4. Advanced microprocessor and peripherals by A K RAY5. 8085 Microprocessor - Ramesh Gaonkar (MP history, Basics)

LOCAL AUTHOR:

6.8086 Microprocessor by Nagoor Kani

Main Book:1. Microprocessors and Interfacing, Programming and Hardware by Doughlas




4. Advanced microprocessor and peripherals by A K RAY5. 8085 Microprocessor - Ramesh Gaonkar (MP history, Basics)

LOCAL AUTHOR:


289

Documents References• 8086 SYSTEM BUS STRUCTURE by Prof.L.PETER STANLEY BEBINGTON

( PROFESSOR AND DEAN(ACADEMIC),VCET,Erode)• I/O Interfacing by Prof.P.JAYACHANDAR , ASSOCIATE PROFESSOR and

DEAN(SA),VCET,Erode• 8086 Microprocessor by Dr. M. Gopikrishna ,Assistant Professor of

Physics,Maharajas College ,Ernakulam• 8086 architecture By Er. Swapnil Kaware• 8086 presentations by Gursharan Singh Tatla (Eazynotes.com)• Microprocessor - Ramesh Gaonkar• 8086 micro processor prasadpawaskar• 8086 class notes-Y.N.M by MURTHY Y.N• Introduction to 8086 Microprocessor by Rajvir Singh• 8086 micro processor by Poojith Chowdhary• 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar & Cutajar• Intel microprocessor history by Ramzi_Alqrainy

• 8086 SYSTEM BUS STRUCTURE by Prof.L.PETER STANLEY BEBINGTON( PROFESSOR AND DEAN(ACADEMIC),VCET,Erode)

• I/O Interfacing by Prof.P.JAYACHANDAR , ASSOCIATE PROFESSOR andDEAN(SA),VCET,Erode

• 8086 Microprocessor by Dr. M. Gopikrishna ,Assistant Professor ofPhysics,Maharajas College ,Ernakulam

• 8086 architecture By Er. Swapnil Kaware• 8086 presentations by Gursharan Singh Tatla (Eazynotes.com)• Microprocessor - Ramesh Gaonkar• 8086 micro processor prasadpawaskar• 8086 class notes-Y.N.M by MURTHY Y.N• Introduction to 8086 Microprocessor by Rajvir Singh• 8086 micro processor by Poojith Chowdhary• 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar & Cutajar• Intel microprocessor history by Ramzi_Alqrainy

290

Website References• http://80864beginner.com/• www.eazynotes.com• www.slideshare.net• www.scribd.com• www.docstoc.com• www.slideworld.com• www.nptel.ac.in• http://opencourses.emu.edu.tr/• http://engineeringppt.blogspot.in/• http://www.pptsearchengine.net/• www.4shared.com• http://8085projects.info/

• http://80864beginner.com/• www.eazynotes.com• www.slideshare.net• www.scribd.com• www.docstoc.com• www.slideworld.com• www.nptel.ac.in• http://opencourses.emu.edu.tr/• http://engineeringppt.blogspot.in/• http://www.pptsearchengine.net/• www.4shared.com• http://8085projects.info/

291

NPTEL Lecture Materials References

• Microprocessor and Peripheral Devices by Dr.Pramod Agarwal , IIT Roorkee

Link: http://nptel.ac.in/courses/108107029/

• Microprocessors and Microcontrollers by Prof.Krishna Kumar IISc Bangalore

link: http://nptel.ac.in/courses/106108100/





292

UNITUNIT--33I/OI/O

INTERFACINGINTERFACING

EC6504 Microprocessors and MicrocontrollersDept: CSE,IT,ECE,MECH Regulation : 2013

293

UNITUNIT--33I/OI/O

INTERFACINGINTERFACINGPresented by

C.GOKUL,AP/EEE

Data TransfersData Transfers Synchronous ----- Usually occur when

peripherals are located within the samecomputer as the CPU. Close proximityallows all state bits change at sametime on a common clock.

Asynchronous ----- Do not require thatthe source and destination use thesame system clock.

294

Synchronous ----- Usually occur whenperipherals are located within the samecomputer as the CPU. Close proximityallows all state bits change at sametime on a common clock.

Asynchronous ----- Do not require thatthe source and destination use thesame system clock.

295

MEMORY DEVICES I/O DEVICESPresented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode

interface memory (RAM, ROM, EPROM'...)or I/O devices to 8086 microprocessor.Several memory chips or I/O devices canconnected to a microprocessor. An addressdecoding circuit is used to select therequired I/O device or a memory chip.

296

interface memory (RAM, ROM, EPROM'...)or I/O devices to 8086 microprocessor.Several memory chips or I/O devices canconnected to a microprocessor. An addressdecoding circuit is used to select therequired I/O device or a memory chip.

IO mapped IO V/s Memory MappedIO mapped IO V/s Memory MappedIOIO

Memory Mapped IO

IO is treated as memory. 16-bit addressing. More Decoder Hardware. Can address 216=64k

locations. Less memory is available.

IO Mapped IO

IO is treated IO. 8- bit addressing. Less Decoder

Hardware. Can address 28=256

locations. Whole memory address

space is available.

297

IO is treated as memory. 16-bit addressing. More Decoder Hardware. Can address 216=64k

locations. Less memory is available.

IO is treated IO. 8- bit addressing. Less Decoder

Hardware. Can address 28=256

locations. Whole memory address

space is available.

Memory Mapped IO

• Memory Instructions areused.

• Memory control signalsare used.

• Arithmetic and logicoperations can beperformed on data.

• Data transfer b/w registerand IO.

IO Mapped IO

• Special Instructions areused like IN, OUT.

• Special control signalsare used.

• Arithmetic and logicoperations can not beperformed on data.

• Data transfer b/waccumulator and IO.

298

• Memory Instructions areused.

• Memory control signalsare used.

• Arithmetic and logicoperations can beperformed on data.

• Data transfer b/w registerand IO.

• Special Instructions areused like IN, OUT.

• Special control signalsare used.

• Arithmetic and logicoperations can not beperformed on data.

• Data transfer b/waccumulator and IO.

Parallel communicationinterface

INTEL 8255INTEL 8255

299

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode

8255 PPI8255 PPI

• The 8255 chip is also called as ProgrammablePeripheral Interface.

• The Intel’s 8255 is designed for use with Intel’s8-bit, 16-bit and higher capabilitymicroprocessors

• The 8255 is a 40 pin integrated circuit (IC),designed to perform a variety of interfacefunctions in a computer environment.

• It is flexible and economical.

300

• The 8255 chip is also called as ProgrammablePeripheral Interface.

• The Intel’s 8255 is designed for use with Intel’s8-bit, 16-bit and higher capabilitymicroprocessors

• The 8255 is a 40 pin integrated circuit (IC),designed to perform a variety of interfacefunctions in a computer environment.

• It is flexible and economical.

PIN DIAGRAM OF 8255PIN DIAGRAM OF 8255301

Signals of 8085Signals of 8085302

8255 PIO/PPI8255 PIO/PPI It has 24 input/output lines which may be

individually programmed. 2 groups of I/O pins are named as

Group A (Port-A & Port C Upper)Group B (Port-B & Port C Lower)

3 ports(each port has 8 bit)Port A lines are identified by symbols PA0-PA7

Port B lines are identified by symbols PB0-PB7

Port C lines are identified by PC0-PC7 , PC3-PC0ie: PORT C UPPER(PC7-PC4) , PORT C LOWER(PC3-PC0)

303

It has 24 input/output lines which may beindividually programmed.

2 groups of I/O pins are named asGroup A (Port-A & Port C Upper)Group B (Port-B & Port C Lower)

3 ports(each port has 8 bit)Port A lines are identified by symbols PA0-PA7

Port B lines are identified by symbols PB0-PB7

Port C lines are identified by PC0-PC7 , PC3-PC0ie: PORT C UPPER(PC7-PC4) , PORT C LOWER(PC3-PC0)

D0 - D7: data input/output lines for thedevice. All information read from andwritten to the 8255 occurs via these 8 datalines.

CS (Chip Select). If this line is a logical 0, themicroprocessor can read and write to the8255.

RESET : The 8255 is placed into its resetstate if this input line is a logical 1

304D0 - D7: data input/output lines for thedevice. All information read from andwritten to the 8255 occurs via these 8 datalines.

CS (Chip Select). If this line is a logical 0, themicroprocessor can read and write to the8255.

RESET : The 8255 is placed into its resetstate if this input line is a logical 1

• RD : This is the input line driven by themicroprocessor and should be low toindicate read operation to 8255.

• WR : This is an input line driven by themicroprocessor. A low on this lineindicates write operation.

• A1-A0 : These are the address input linesand are driven by the microprocessor.

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• RD : This is the input line driven by themicroprocessor and should be low toindicate read operation to 8255.

• WR : This is an input line driven by themicroprocessor. A low on this lineindicates write operation.

• A1-A0 : These are the address input linesand are driven by the microprocessor.

Control LogicControl Logic CS signal is the master Chip Select A0 and A1 specify one of the two I/O Ports

CS A1 A0 Selected0 0 0 Port A

306

0 0 0 Port A0 0 1 Port B0 1 0 Port C0 1 1 Control

Register1 X X 8255 is not

selected

Block Diagram of 8255ABlock Diagram of 8255A 307

Block Diagram of 8255Block Diagram of 8255(Architecture)(Architecture)

It has a 40 pins of 4 parts.1. Data bus buffer2. Read/Write control logic3. Group A and Group B controls4. Port A, B and C

308

It has a 40 pins of 4 parts.1. Data bus buffer2. Read/Write control logic3. Group A and Group B controls4. Port A, B and C

1. Data bus buffer1. Data bus buffer

This is a tristate bidirectional buffer usedto interface the 8255 to system data bus.Data is transmitted or received by thebuffer on execution of input or outputinstruction by the CPU.

309

This is a tristate bidirectional buffer usedto interface the 8255 to system data bus.Data is transmitted or received by thebuffer on execution of input or outputinstruction by the CPU.

2. Read/Write control logic2. Read/Write control logic

This unit accepts control signals ( RD, WR ) andalso inputs from address bus and issuescommands to individual group of control blocks( Group A, Group B).

It has the following pins.

CS , RD , WR , RESET , A1 , A0

310

This unit accepts control signals ( RD, WR ) andalso inputs from address bus and issuescommands to individual group of control blocks( Group A, Group B).

It has the following pins.

CS , RD , WR , RESET , A1 , A0

3. Group A and Group B controls3. Group A and Group B controls• These block receive control from the CPU

and issues commands to their respectiveports.Group A - PA and PCU ( PC7 –PC4)Group B – PB and PCL ( PC3 –PC0)

a) Port A: This has an 8 bit latched/bufferedO/P and 8 bit input latch. It can beprogrammed in 3 modes – mode 0, mode 1,mode 2.

311

• These block receive control from the CPUand issues commands to their respectiveports.Group A - PA and PCU ( PC7 –PC4)Group B – PB and PCL ( PC3 –PC0)

a) Port A: This has an 8 bit latched/bufferedO/P and 8 bit input latch. It can beprogrammed in 3 modes – mode 0, mode 1,mode 2.

b) Port B: It can be programmed in mode 0,mode1

c) Port C : It can be programmed in mode 0

312

313

Modes of Operation of 8255Modes of Operation of 8255

Bit Set/Reset(BSR) Mode Set/Reset bits in Port C

I/O Mode Mode 0 (Simple input/output) Mode 1 (Handshake mode) Mode 2 (Bidirectional Data Transfer)

314

Bit Set/Reset(BSR) Mode Set/Reset bits in Port C

I/O Mode Mode 0 (Simple input/output) Mode 1 (Handshake mode) Mode 2 (Bidirectional Data Transfer)

1. BSR Mode1. BSR Mode315

B3 B2 B1 Bit/pin of port Cselected

0 0 0 PC0

0 0 1 PC1

0 1 0 PC2

0 1 1 PC3

1 0 0 PC4

316

1 0 0 PC4

1 0 1 PC5

1 1 0 PC6

1 1 1 PC7

Concerned only with the 8-bits of Port C.Set or Reset by control wordPorts A and B are not affected

a) Mode 0 (Simple Input or Output):a) Mode 0 (Simple Input or Output):

• Ports A and B are used as Simple I/OPorts

• Port C as two 4-bit ports

• Features– Outputs are latched– Inputs are not latched– Ports do not have handshake or

interrupt capability

2. I/O MODE2. I/O MODE317

• Ports A and B are used as Simple I/OPorts

• Port C as two 4-bit ports

• Features– Outputs are latched– Inputs are not latched– Ports do not have handshake or

interrupt capability

318

b)b) Mode 1: (Mode 1: (Input or Output withInput or Output withHandshakeHandshake))

• Handshake signals are exchangedbetween MPU & Peripherals

• Features– Ports A and B are used as Simple I/O Ports– Each port uses 3 lines from Port C as

handshake signals– Input & Output data are latched– interrupt logic supported

319

• Handshake signals are exchangedbetween MPU & Peripherals

• Features– Ports A and B are used as Simple I/O Ports– Each port uses 3 lines from Port C as

handshake signals– Input & Output data are latched– interrupt logic supported

c) Mode 2: Bidirectional Data Transfer

• Used primarily in applications such as datatransfer between two computers

• Features– Ports A can be configured as the bidirectional

Port– Port B in Mode 0 or Mode 1.– Port A uses 5 Signals from Port C as handshake

signals for data transfer– Remaining 3 Signals from Port C Used as –

Simple I/O or handshake for Port B

320

• Used primarily in applications such as datatransfer between two computers

• Features– Ports A can be configured as the bidirectional

Port– Port B in Mode 0 or Mode 1.– Port A uses 5 Signals from Port C as handshake

signals for data transfer– Remaining 3 Signals from Port C Used as –

Simple I/O or handshake for Port B

Write a program to initialize 8255 in the configurationbelow.(assume address of the CW register as 23H).(1) Port A: output with handshake(2) Port B: input with handshake(3) Port CL: output (4)Port CU: input

Solution:

1 0 1 0 1 1 1 0 = AEH

321

1 0 1 0 1 1 1 0 = AEH

MVI A,AEH ; LOAD CONTROL WORD

OUT 23H ; SEND CONTROL WORD

Program:

Port A: Output, Port B: Output, Port CU: Output, Port CL: Output

Solution:

322

Solution:

1 0 0 0 0 0 0 0 = 80H

The control word register for the above ports of Intel8255 is 80H.

Port A: Input, Port B: Input, Port CU: Input, Port CL: Input

Solution:

323

Solution:

1 0 0 1 1 0 1 1 = 9BH

The control word register for the above ports of intel8255 is 9BH.

Basics of serial communicationBasics of serial communication1. Transmitter:- A parallel-in, serial-outshift register

2. Receiver:- A serial-in, parallel-outshift register.

-

1. Transmitter:- A parallel-in, serial-outshift register

2. Receiver:- A serial-in, parallel-outshift register.

-324

Parallel Transfer

TRANSMITTER

Receiver

325

Receiver

Serial communicationinterface

INTEL 8251 USARTINTEL 8251 USART

326

UUNIVERSALNIVERSAL SSYNCHRONOUSYNCHRONOUSAASYNCHRONOUSSYNCHRONOUS RRECEIVERECEIVER

TTRANSMITTER (USARTRANSMITTER (USART)) Programmable chip designed for

synchronous and asynchronous serial datatransmission

28 pin DIP Coverts the parallel data into a serial stream

of bits suitable for serial transmission. Receives a serial stream of bits and convert

it into parallel data bytes to be read by amicroprocessor.

327

Programmable chip designed forsynchronous and asynchronous serial datatransmission

28 pin DIP Coverts the parallel data into a serial stream

of bits suitable for serial transmission. Receives a serial stream of bits and convert

it into parallel data bytes to be read by amicroprocessor.

328

BLOCK DIAGRAMBLOCK DIAGRAM 329

Five SectionsFive Sections– Read/Write Control Logic

• Interfaces the chip with MPU• Determine the functions according to the control word• Monitors data flow

– Transmitter• Converts parallel word received from MPU into serial bits• Transmits serial bits over TXD line to a peripheral.

– Receiver• Receives serial bits from peripheral• Converts serial bits into parallel word• Transfers the parallel word to the MPU

– Data Bus Buffer- 8 bit Bidirectional bus.– Modem Controller

• Used to establish data communication modems overtelephone line

330

– Read/Write Control Logic• Interfaces the chip with MPU• Determine the functions according to the control word• Monitors data flow

– Transmitter• Converts parallel word received from MPU into serial bits• Transmits serial bits over TXD line to a peripheral.

– Receiver• Receives serial bits from peripheral• Converts serial bits into parallel word• Transfers the parallel word to the MPU

– Data Bus Buffer- 8 bit Bidirectional bus.– Modem Controller

• Used to establish data communication modems overtelephone line

Input SignalsInput Signals

CS – Chip Select When this signal goes low, 8251 is selected by

MPU for communication C/D – Control/Data

When this signal is high, the control registeror status register is addressed

When it is low, the data buffer is addressed Control and Status register is differentiated by

WR and RD signals, respectively

331

CS – Chip Select When this signal goes low, 8251 is selected by

MPU for communication C/D – Control/Data

When this signal is high, the control registeror status register is addressed

When it is low, the data buffer is addressed Control and Status register is differentiated by

WR and RD signals, respectively

• WR – Write– writes in the control register or sends outputs to the

data buffer.– This connected to IOW or MEMW

• RD – Read– Either reads a status from status register or accepts

data from the data buffer– This is connected to either IOR or MEMR

• RESET - Reset• CLK - Clock

– Connected to system clock– Necessary for communication with microprocessor.

332

• WR – Write– writes in the control register or sends outputs to the

data buffer.– This connected to IOW or MEMW

• RD – Read– Either reads a status from status register or accepts

data from the data buffer– This is connected to either IOR or MEMR

• RESET - Reset• CLK - Clock

– Connected to system clock– Necessary for communication with microprocessor.

CS C/D RD WR Function0 1 1 0 MPU writes instruction in the

control register0 1 0 1 MPU reads status from the status

registerMPU outputs the data to the DataBuffer

333

MPU reads status from the statusregister

0 0 1 0 MPU outputs the data to the DataBuffer

0 0 0 1 MPU accepts data from the DataBuffer

1 X X X USART is not Selected

• Control Register– 16-bit register– This register can be accessed an output port

when the C/D pin is high

• Status Register– Checks ready status of a peripheral

• Data Buffer

334

• Control Register– 16-bit register– This register can be accessed an output port

when the C/D pin is high

• Status Register– Checks ready status of a peripheral

• Data Buffer

Transmitter SectionTransmitter Section

Accepts parallel data and converts it intoserial data

Two registers Buffer Register

To hold eight bits

Output Register Converts eight bits into a stream of serial bits

Transmits data on TxD pin with appropriateframing bits(Start and Stop)

335

Accepts parallel data and converts it intoserial data

Two registers Buffer Register

To hold eight bits

Output Register Converts eight bits into a stream of serial bits

Transmits data on TxD pin with appropriateframing bits(Start and Stop)

Signals Associated with TransmitterSignals Associated with TransmitterSectionSection

• TxD – Transmit Data– Serial bits are transmitted on this line

• TxC – Transmitter Clock– Controls the rate at which bits are transmitted

• TxRDY – Transmitter Ready– Can be used either to interrupt the MPU or

indicate the status• TxE – Transmitter Empty

– Logic 1 on this line indicate that the outputregister is empty

336

• TxD – Transmit Data– Serial bits are transmitted on this line

• TxC – Transmitter Clock– Controls the rate at which bits are transmitted

• TxRDY – Transmitter Ready– Can be used either to interrupt the MPU or

indicate the status• TxE – Transmitter Empty

– Logic 1 on this line indicate that the outputregister is empty

Receiver SectionReceiver Section

Accepts serial data from peripheral andconverts it into parallel data

The section has two registers Input Register Buffer Register

337

Accepts serial data from peripheral andconverts it into parallel data

The section has two registers Input Register Buffer Register

Signals Associated with ReceiverSignals Associated with ReceiverSectionSection

RxD – Receive Data Bits are received serially on this line and

converted into parallel byte in the receiver input

RxC – Receiver Clock RxRDY – Receiver Ready

It goes high when the USART has a character inthe buffer register and is ready to transfer it tothe MPU

338

RxD – Receive Data Bits are received serially on this line and

converted into parallel byte in the receiver input

RxC – Receiver Clock RxRDY – Receiver Ready

It goes high when the USART has a character inthe buffer register and is ready to transfer it tothe MPU

Signals Associated with ModemSignals Associated with ModemControlControl

• DSR- Data Set Ready– Normally used to check if the Data Set is ready when

communicating with a modem

• DTR – Data Terminal Ready– device is ready to accept data when the 8251 is

communicating with a modem.

• RTS – Request to send Data– the receiver is ready to receive a data byte from

modem

• CTS – Clear to Send

339

• DSR- Data Set Ready– Normally used to check if the Data Set is ready when

communicating with a modem

• DTR – Data Terminal Ready– device is ready to accept data when the 8251 is

communicating with a modem.

• RTS – Request to send Data– the receiver is ready to receive a data byte from

modem

• CTS – Clear to Send

Control wordsControl words340

341

342

343

344

Interfacing of 8255(PPI) with 8085 processor: 345

346

11-347

Programming 8251 8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number ofStop bits Parity enable

0: disable1: enable

Baud RateNumber ofStop bits

00: invalid01: 1 bit10: 1.5 bits11: 2 bits

Parity0: odd1: even

Parity enable0: disable1: enable

Character length00: 5 bits01: 6 bits10: 7 bits11: 8 bits

Baud Rate00: Syn. Mode01: x1 clock10: x16 clock11: x64 clock

11-348

8251 command register

EH IR RTS ER SBRK RxE DTR TxE command register

TxE: transmit enableDTR: data terminal ready, DTR pin will be lowRxE: receiver enableSBPRK: send break character, TxD pin will be lowER: error resetRTS: request to send, CTS pin will be lowIR: internal resetEH: enter hunt mode (1=enable search for SYN character)

TxE: transmit enableDTR: data terminal ready, DTR pin will be lowRxE: receiver enableSBPRK: send break character, TxD pin will be lowER: error resetRTS: request to send, CTS pin will be lowIR: internal resetEH: enter hunt mode (1=enable search for SYN character)

11-349

8251 status register

DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY statusregister

TxRDY: transmit readyRxRDY: receiver readyTxEMPTY: transmitter emptyPE: parity errorOE: overrun errorFE: framing errorSYNDET: sync. character detectedDSR: data set ready

TxRDY: transmit readyRxRDY: receiver readyTxEMPTY: transmitter emptyPE: parity errorOE: overrun errorFE: framing errorSYNDET: sync. character detectedDSR: data set ready

350

The analog to digital converter chips 0808and 0809 are 8-bit CMOS,successiveapproximation converters.

Successive approximation technique is oneof the fast techniques for analog to digitalconversion. The conversion delay is 100 µsat a clock frequency of 640 kHz.

351

The analog to digital converter chips 0808and 0809 are 8-bit CMOS,successiveapproximation converters.

Successive approximation technique is oneof the fast techniques for analog to digitalconversion. The conversion delay is 100 µsat a clock frequency of 640 kHz.

352

353

354

355

356

The digital to analog converters convertbinary numbers into their analog equivalentvoltages or currents.Techniques are employed for digital to analogconversion.

i. Weighted resistor network ii. R-2R ladder network iii. Current output D/A converter

357

The digital to analog converters convertbinary numbers into their analog equivalentvoltages or currents.Techniques are employed for digital to analogconversion.

i. Weighted resistor network ii. R-2R ladder network iii. Current output D/A converter

The DAC find applications in areas like digitally controlledgains, motor speed control, programmable gain amplifiers,digital voltmeters, panel meters, etc.

In a compact disk audio player for example a 14 or16-bitD/A converter is used to convert the binary data read offthe disk by a laser to an analog audio signal.

Characteristics :1. Resolution: It is a change in analog output for one LSBchange in digital input.It is given by(1/2^n )*Vref. If n=8 (i.e.8-bit DAC)

1/256*5V=39.06mV2. Settling time: It is the time required for the DAC to settlefor a full scale code change.

358

The DAC find applications in areas like digitally controlledgains, motor speed control, programmable gain amplifiers,digital voltmeters, panel meters, etc.

In a compact disk audio player for example a 14 or16-bitD/A converter is used to convert the binary data read offthe disk by a laser to an analog audio signal.

Characteristics :1. Resolution: It is a change in analog output for one LSBchange in digital input.It is given by(1/2^n )*Vref. If n=8 (i.e.8-bit DAC)

1/256*5V=39.06mV2. Settling time: It is the time required for the DAC to settlefor a full scale code change.

DAC 0800 8-bit Digital to Analog converter

Features:i. DAC0800 is a monolithic 8-bit DAC manufactured by

National semiconductor.ii. It has settling time around 100msiii. It can operate on a range of power supply voltage i.e.

from 4.5V to +18V. Usually the supply V+ is 5V or +12V.The V- pin can be kept at a minimum of -12V.

iv. Resolution of the DAC is 39.06mV

359

DAC 0800 8-bit Digital to Analog converter

Features:i. DAC0800 is a monolithic 8-bit DAC manufactured by

National semiconductor.ii. It has settling time around 100msiii. It can operate on a range of power supply voltage i.e.

from 4.5V to +18V. Usually the supply V+ is 5V or +12V.The V- pin can be kept at a minimum of -12V.

iv. Resolution of the DAC is 39.06mV

360

361

TIMER/COUNTERTIMER/COUNTER

362

363

RD: read signal WR: write signal CS: chip select signal A0, A1: address lines Clock :This is the clock input for the counter.

The counter is 16 bits. Out :This single output line is the signal that

is the final programmed output of the device. Gate :This input can act as a gate for the

clock input line, or it can act as a start pulse,

364 RD: read signal WR: write signal CS: chip select signal A0, A1: address lines Clock :This is the clock input for the counter.

The counter is 16 bits. Out :This single output line is the signal that

is the final programmed output of the device. Gate :This input can act as a gate for the

clock input line, or it can act as a start pulse,

365

366

8254 Programming

11-367

8254 ModesGate is low thecount will bepaused

Gate is highWill continuecounting

Mode 0: An events counter enabled with G.

Gate is highWill continuecounting

Mode 1: One-shot mode. s

Gate isHigh outputwill be high

Counter will be reloadedAfter gate high.

368

Mode 2: Counter generates a series of pulses 1 clockpulse wide

cycle is repeated untilreprogrammed or G pinset to 0

Mode 3: Generates a continuous square-wave with G set to 1

cycle is repeated untilreprogrammed or G pinset to 0

If count is even, 50% duty cycleotherwise OUT is high 1 cyclelonger

369

Mode 4: Software triggered one-shot.

In the last countingWill be stop(not repeated)

Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.In the last countOut will be low

370

Keyboard/DisplayController

INTEL 8279

371

Keyboard/DisplayController

INTEL 8279

The INTEL 8279 is specially developedfor interfacing keyboard and display devicesto 8085/8086 microprocessor basedsystem

372

The INTEL 8279 is specially developedfor interfacing keyboard and display devicesto 8085/8086 microprocessor basedsystem

Simultaneous keyboard and displayoperations

Scanned keyboard mode Scanned sensor mode 8-character keyboard FIFO 1 6-character display

373

Simultaneous keyboard and displayoperations

Scanned keyboard mode Scanned sensor mode 8-character keyboard FIFO 1 6-character display

374

Keyboard section Display section Scan section CPU interface section

375

Keyboard section Display section Scan section CPU interface section

376

377

The keyboard section consists of 8 returnlines RL0 - RL7 that can be used to form thecolumns of a keyboard matrix.

It has two additional input : shift andcontrol/strobe. The keys are automaticallydebounced.

The two operating modes of keyboardsection are 2-key lockout and N-key rollover.

378

The keyboard section consists of 8 returnlines RL0 - RL7 that can be used to form thecolumns of a keyboard matrix.

It has two additional input : shift andcontrol/strobe. The keys are automaticallydebounced.

The two operating modes of keyboardsection are 2-key lockout and N-key rollover.

In the 2-key lockout mode, if two keys arepressed simultaneously, only the first key isrecognized.

In the N-key rollover mode simultaneouskeys are recognized and their codes arestored in FIFO.

The keyboard section also have an 8 x 8FIFO (First In First Out) RAM.

The FIFO can store eight key codes in the scankeyboard mode. The status of the shift key andcontrol key are also stored along with key code. The8279 generate an interrupt signal (IRQ)when thereis an entry in FIFO.

379 In the 2-key lockout mode, if two keys arepressed simultaneously, only the first key isrecognized.

In the N-key rollover mode simultaneouskeys are recognized and their codes arestored in FIFO.

The keyboard section also have an 8 x 8FIFO (First In First Out) RAM.

The FIFO can store eight key codes in the scankeyboard mode. The status of the shift key andcontrol key are also stored along with key code. The8279 generate an interrupt signal (IRQ)when thereis an entry in FIFO.

The display section has eight output linesdivided into two groups A0-A3 and B0-B3.

The output lines can be used either as asingle group of eight lines or as two groupsof four lines, in conjunction with the scanlines for a multiplexed display.

The output lines are connected to theanodes through driver transistor in case ofcommon cathode 7-segment LEDs.

380

The display section has eight output linesdivided into two groups A0-A3 and B0-B3.

The output lines can be used either as asingle group of eight lines or as two groupsof four lines, in conjunction with the scanlines for a multiplexed display.

The output lines are connected to theanodes through driver transistor in case ofcommon cathode 7-segment LEDs.

The cathodes are connected to scan linesthrough driver transistors.

The display can be blanked by BD (low) line.

The display section consists of 16 x 8 displayRAM. The CPU can read from or write intoany location of the display RAM.

381

The cathodes are connected to scan linesthrough driver transistors.

The display can be blanked by BD (low) line.

The display section consists of 16 x 8 displayRAM. The CPU can read from or write intoany location of the display RAM.

The scan section has a scan counter and four scanlines, SL0 to SL3.

In decoded scan mode, the output of scan lines willbe similar to a 2-to-4 decoder.

In encoded scan mode, the output of scan lineswill be binary count, and so an external decodershould be used to convert the binary count todecoded output.

The scan lines are common for keyboard anddisplay.

382

The scan section has a scan counter and four scanlines, SL0 to SL3.

In decoded scan mode, the output of scan lines willbe similar to a 2-to-4 decoder.

In encoded scan mode, the output of scan lineswill be binary count, and so an external decodershould be used to convert the binary count todecoded output.

The scan lines are common for keyboard anddisplay.

The CPU interface section takes care of datatransfer between 8279 and the processor.

This section has eight bidirectional datalines DB0 to DB7 for data transfer between8279 and CPU.

It requires two internal address A =0 forselecting data buffer and A = 1 for selectingcontrol register of8279.

383

The CPU interface section takes care of datatransfer between 8279 and the processor.

This section has eight bidirectional datalines DB0 to DB7 for data transfer between8279 and CPU.

It requires two internal address A =0 forselecting data buffer and A = 1 for selectingcontrol register of8279.

The control signals WR (low), RD (low), CS(low) and A0 are used for read/write to8279.

It has an interrupt request line IRQ, forinterrupt driven data transfer with processor.

The 8279 require an internal clockfrequency of 100 kHz. This can be obtainedby dividing the input clock by an internalprescaler.

384

The control signals WR (low), RD (low), CS(low) and A0 are used for read/write to8279.

It has an interrupt request line IRQ, forinterrupt driven data transfer with processor.

The 8279 require an internal clockfrequency of 100 kHz. This can be obtainedby dividing the input clock by an internalprescaler.

All the command words or status words are written orread with A0 = 1 and CS = 0 to or from 8279.

a) Keyboard Display Mode Set : The format of the command word to select differentmodes of operation of 8279 is given below with its bit definitions.

D7 D6 D5 D4 D3 D2 D1 D0

385

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 D D K K K

386

SENSOR MATRIX

SENSOR MATRIX

B) Programmable clock :

The clock for operation of 8279 is obtained bydividing the external clock input signal by aprogrammable constant called prescaler. PPPPP is a 5-bit binary constant.The input frequency is divided by a decimal constantranging from 2 to 31, decided by the bits of an internalprescaler, PPPPP.

387

B) Programmable clock :

The clock for operation of 8279 is obtained bydividing the external clock input signal by aprogrammable constant called prescaler. PPPPP is a 5-bit binary constant.The input frequency is divided by a decimal constantranging from 2 to 31, decided by the bits of an internalprescaler, PPPPP.

D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 P P P P P

c) Read FIFO / Sensor RAM : The format of this command is givenbelow.

AI – Auto Increment FlagAAA – Address pointer to 8 bit FIFO RAM

X- Don’t careThis word is written to set up 8279 for reading FIFO/ sensor RAM.In scanned keyboard mode, AI and AAA bits are of no use. The8279 will automatically drive data bus for each subsequent read, inthe same sequence, in which the data was entered.In sensor matrix mode, the bits AAA select one of the 8 rows ofRAM.If AI flag is set, each successive read will be from the subsequentRAM location.

D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 AI X A A A

388c) Read FIFO / Sensor RAM : The format of this command is givenbelow.

AI – Auto Increment FlagAAA – Address pointer to 8 bit FIFO RAM

X- Don’t careThis word is written to set up 8279 for reading FIFO/ sensor RAM.In scanned keyboard mode, AI and AAA bits are of no use. The8279 will automatically drive data bus for each subsequent read, inthe same sequence, in which the data was entered.In sensor matrix mode, the bits AAA select one of the 8 rows ofRAM.If AI flag is set, each successive read will be from the subsequentRAM location.

d) Read Display RAM :This command enables a programmer to read the display RAM data.

The CPU writes this command word to 8279 to prepare it fordisplay RAM read operation.AI is auto increment flag and AAAA, the 4-bit address points tothe 16-byte display RAM that is to be read.If AI=1, the address will be automatically, incremented aftereach read or write to the Display RAM.The same address counter is used for reading and writing.

D7 D6 D5 D4 D3 D2 D1 D0

0 1 1 AI A A A A

389

d) Read Display RAM :This command enables a programmer to read the display RAM data.

The CPU writes this command word to 8279 to prepare it fordisplay RAM read operation.AI is auto increment flag and AAAA, the 4-bit address points tothe 16-byte display RAM that is to be read.If AI=1, the address will be automatically, incremented aftereach read or write to the Display RAM.The same address counter is used for reading and writing.

d) Write Display RAM :This command enables a programmer to write the display RAM data.

AI – Auto increment Flag.AAAA – 4 bit address for 16-bit display RAM to be

written.e) Display Write Inhibit/Blanking :

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 AI A A A A

390

d) Write Display RAM :This command enables a programmer to write the display RAM data.

AI – Auto increment Flag.AAAA – 4 bit address for 16-bit display RAM to be

written.e) Display Write Inhibit/Blanking :

D7 D6 D5 D4 D3 D2 D1 D0

1 0 1 X IW IW BL BL

IW - inhibit write flagBL - blank display bit flags

g) Clear Display RAM :

ENABLES CLEAR DISPLAYWHEN CD2=1

• CD2 must be 1 for enabling the clear display command.• If CD2 = 0, the clear display command is invoked by settingCA(CLEAR ALL) =1 and maintaining CD1, CD0 bits exactly sameas above.• If CF(CLEAR FIFO RAM STATUS) =1, FIFO status is cleared andIRQ line is pulled down and the sensor RAM pointer is set to row0.•If CA=1, this combines the effect of CD and CF bits.

D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 CD2 CD1 CD0 CF CA

CD2 CD1 CD0

0X - All zeros ( x don’t care ) AB=0010 - A3-A0 =2 (0010) and B3-B0=00 (0000)11 - All ones (AB =FF), i.e. clear RAM

391

g) Clear Display RAM :

ENABLES CLEAR DISPLAYWHEN CD2=1

• CD2 must be 1 for enabling the clear display command.• If CD2 = 0, the clear display command is invoked by settingCA(CLEAR ALL) =1 and maintaining CD1, CD0 bits exactly sameas above.• If CF(CLEAR FIFO RAM STATUS) =1, FIFO status is cleared andIRQ line is pulled down and the sensor RAM pointer is set to row0.•If CA=1, this combines the effect of CD and CF bits.

0X - All zeros ( x don’t care ) AB=0010 - A3-A0 =2 (0010) and B3-B0=00 (0000)11 - All ones (AB =FF), i.e. clear RAM

h) End Interrupt / Error mode Set :

E- Error modeX- don’t care

For the sensor matrix mode, this command lowers theIRQ line and enables further writing into the RAM.Otherwise, if a change in sensor value is detected, IRQgoes high that inhibits writing in the sensor RAM. For N-Key roll over mode, if the E bit is programmed tobe ‘1’, the 8279 operates in special Error mode

D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 E X X X 1

392

h) End Interrupt / Error mode Set :

E- Error modeX- don’t care

For the sensor matrix mode, this command lowers theIRQ line and enables further writing into the RAM.Otherwise, if a change in sensor value is detected, IRQgoes high that inhibits writing in the sensor RAM. For N-Key roll over mode, if the E bit is programmed tobe ‘1’, the 8279 operates in special Error mode

INTERRUPTINTERRUPTCONTROLLERCONTROLLER

393

INTERRUPTINTERRUPTCONTROLLERCONTROLLER

If we are working with an 8086, we have aproblem here because the 8086 has onlytwo interrupt inputs, NMI and INTR.

If we save NMI for a power failure interrupt,this leaves only one interrupt for all the otherapplications. For applications where we haveinterrupts from multiple source, we use anexternal device called a priority interruptcontroller ( PIC ) to the interrupt signals intoa single interrupt input on the processor.

394

If we are working with an 8086, we have aproblem here because the 8086 has onlytwo interrupt inputs, NMI and INTR.

If we save NMI for a power failure interrupt,this leaves only one interrupt for all the otherapplications. For applications where we haveinterrupts from multiple source, we use anexternal device called a priority interruptcontroller ( PIC ) to the interrupt signals intoa single interrupt input on the processor.

395

Interrupt Request Register (RR): Theinterrupts at IRQ input lines are handled byInterrupt Request internally. IRR stores allthe interrupt request in it in order to servethem one by one on the priority basis.

In-Service Register (ISR): This stores all theinterrupt requests those are being served,i.e. ISR keeps a track of the requests beingserved.

396

Interrupt Request Register (RR): Theinterrupts at IRQ input lines are handled byInterrupt Request internally. IRR stores allthe interrupt request in it in order to servethem one by one on the priority basis.

In-Service Register (ISR): This stores all theinterrupt requests those are being served,i.e. ISR keeps a track of the requests beingserved.

Priority Resolver : This unit determines thepriorities of the interrupt requests appearingsimultaneously. The highest priority is selected andstored into the corresponding bit of ISR during INTApulse. The IR0 has the highest priority while theIR7 has the lowest one, normally in fixed prioritymode. The priorities however may be altered byprogramming the 8259A in rotating priority mode.

Interrupt Mask Register (IMR) : This registerstores the bits required to mask the interruptinputs. IMR operates on IRR at the directionof the Priority Resolver.

397 Priority Resolver : This unit determines thepriorities of the interrupt requests appearingsimultaneously. The highest priority is selected andstored into the corresponding bit of ISR during INTApulse. The IR0 has the highest priority while theIR7 has the lowest one, normally in fixed prioritymode. The priorities however may be altered byprogramming the 8259A in rotating priority mode.

Interrupt Mask Register (IMR) : This registerstores the bits required to mask the interruptinputs. IMR operates on IRR at the directionof the Priority Resolver.

Interrupt Control Logic: This block managesthe interrupt and interrupt acknowledgesignals to be sent to the CPU for serving oneof the eight interrupt requests. This alsoaccepts the interrupt acknowledge (INTA)signal from CPU that causes the 8259A torelease vector address on to the data bus.

Data Bus Buffer : This tristate bidirectionalbuffer interfaces internal 8259A bus to themicroprocessor system data bus. Controlwords, status and vector information passthrough data buffer during read or writeoperations.

398 Interrupt Control Logic: This block managesthe interrupt and interrupt acknowledgesignals to be sent to the CPU for serving oneof the eight interrupt requests. This alsoaccepts the interrupt acknowledge (INTA)signal from CPU that causes the 8259A torelease vector address on to the data bus.

Data Bus Buffer : This tristate bidirectionalbuffer interfaces internal 8259A bus to themicroprocessor system data bus. Controlwords, status and vector information passthrough data buffer during read or writeoperations.

Read/Write Control Logic: This circuit acceptsand decodes commands from the CPU. Thisblock also allows the status of the 8259A tobe transferred on to the data bus.

Cascade Buffer/Comparator: This block storesand compares the ID’s all the 8259A used in system.The three I/O pins CASO-2 are outputs when the8259A is used as a master. The same pins act asinputs when the 8259A is in slave mode. The 8259Ain master mode sends the ID of the interruptingslave device on these lines. The slave thus selected,will send its preprogrammed vector address onthe data bus during the next INTA pulse.

399

Read/Write Control Logic: This circuit acceptsand decodes commands from the CPU. Thisblock also allows the status of the 8259A tobe transferred on to the data bus.

Cascade Buffer/Comparator: This block storesand compares the ID’s all the 8259A used in system.The three I/O pins CASO-2 are outputs when the8259A is used as a master. The same pins act asinputs when the 8259A is in slave mode. The 8259Ain master mode sends the ID of the interruptingslave device on these lines. The slave thus selected,will send its preprogrammed vector address onthe data bus during the next INTA pulse.

8237DMA CONTROLLER

400

Introduction: Direct Memory Access (DMA) is a method of allowing data

to be moved from one location to another in a computerwithout intervention from the central processor (CPU). It is also a fast way of transferring data within (and

sometimes between) computer. The DMA I/O technique provides direct access to the

memory while the microprocessor is temporarily disabled. The DMA controller temporarily borrows the address bus,

data bus and control bus from the microprocessor andtransfers the data directly from the external devices to aseries of memory locations (and vice versa).

Direct Memory Access (DMA) is a method of allowing datato be moved from one location to another in a computerwithout intervention from the central processor (CPU). It is also a fast way of transferring data within (and

sometimes between) computer. The DMA I/O technique provides direct access to the

memory while the microprocessor is temporarily disabled. The DMA controller temporarily borrows the address bus,

data bus and control bus from the microprocessor andtransfers the data directly from the external devices to aseries of memory locations (and vice versa).

401

The 8237 DMA controller

• Supplies memory and I/O with control signals and addresses during DMAtransfer

• 4-channels (expandable)– 0: DRAM refresh

– 1: Free

– 2: Floppy disk controller

– 3: Free

• 1.6MByte/sec transfer rate

• 64 KByte section of memory address capability with single programming

• “fly-by” controller (data does not pass through the DMA-only memory to I/Otransfer capability)

• Initialization involves writing into each channel:• i) The address of the first byte of the block of data that must be transferred (called

the base address).

• ii) The number of bytes to be transferred (called the word count).

• Supplies memory and I/O with control signals and addresses during DMAtransfer

• 4-channels (expandable)– 0: DRAM refresh

– 1: Free

– 2: Floppy disk controller

– 3: Free

• 1.6MByte/sec transfer rate

• 64 KByte section of memory address capability with single programming

• “fly-by” controller (data does not pass through the DMA-only memory to I/Otransfer capability)

• Initialization involves writing into each channel:• i) The address of the first byte of the block of data that must be transferred (called

the base address).

• ii) The number of bytes to be transferred (called the word count).

402

8237 pins• CLK: System clock• CS΄: Chip select (decoder output)• RESET: Clears registers, sets mask register• READY: 0 for inserting wait states• HLDA: Signals that the μp has relinquished buses• DREQ3 – DREQ0: DMA request input for each channel• DB7-DB0: Data bus pins• IOR΄: Bidirectional pin used during programmingand during a DMA write cycle• IOW΄: Bidirectional pin used during programmingand during a DMA read cycle• EOP΄: End of process is a bidirectional signal used as input to terminate a DMA process or

as output to signal the end of the DMA transfer• A3-A0: Address pins for selecting internal registers• A7-A4: Outputs that provide part of the DMA transfer address• HRQ: DMA request output• DACK3-DACK0: DMA acknowledge for each channel.• AEN: Address enable signal• ADSTB: Address strobe• MEMR΄: Memory read output used in DMA read cycle• MEMW΄: Memory write output used in DMA write cycle

• CLK: System clock• CS΄: Chip select (decoder output)• RESET: Clears registers, sets mask register• READY: 0 for inserting wait states• HLDA: Signals that the μp has relinquished buses• DREQ3 – DREQ0: DMA request input for each channel• DB7-DB0: Data bus pins• IOR΄: Bidirectional pin used during programmingand during a DMA write cycle• IOW΄: Bidirectional pin used during programmingand during a DMA read cycle• EOP΄: End of process is a bidirectional signal used as input to terminate a DMA process or

as output to signal the end of the DMA transfer• A3-A0: Address pins for selecting internal registers• A7-A4: Outputs that provide part of the DMA transfer address• HRQ: DMA request output• DACK3-DACK0: DMA acknowledge for each channel.• AEN: Address enable signal• ADSTB: Address strobe• MEMR΄: Memory read output used in DMA read cycle• MEMW΄: Memory write output used in DMA write cycle

403

8237 block diagram

404

Block Diagram Description

It containing Five main Blocks.1. Data bus buffer2. Read/Control logic3. Control logic block4. Priority resolver5. DMA channels.

It containing Five main Blocks.1. Data bus buffer2. Read/Control logic3. Control logic block4. Priority resolver5. DMA channels.

405

DATA BUS BUFFER: It contain tristate ,8 bit bi-directional buffer. Slave mode ,it transfer data between

microprocessor and internal data bus. Master mode ,the outputs A8-A15 bits of

memory address on data lines(Unidirectional).

READ/CONTROL LOGIC: It control all internal Read/Write operation. Slave mode ,it accepts address bits and control

signal from microprocessor. Master mode ,it generate address bits and control

signal.

DATA BUS BUFFER: It contain tristate ,8 bit bi-directional buffer. Slave mode ,it transfer data between

microprocessor and internal data bus. Master mode ,the outputs A8-A15 bits of

memory address on data lines(Unidirectional).

READ/CONTROL LOGIC: It control all internal Read/Write operation. Slave mode ,it accepts address bits and control

signal from microprocessor. Master mode ,it generate address bits and control

signal.406

Control logic block It contains ,1. Control logic2. Mode set register and3. Status Register.

CONTROL LOGIC: Master mode ,It control the sequence of DMA

operation during all DMA cycles. It generates address and control signals. It increments 16 bit address and decrement 14 bit

counter registers. It activate a HRQ signal on DMA channel Request. Slave ,mode it is disabled.

Control logic block It contains ,1. Control logic2. Mode set register and3. Status Register.

CONTROL LOGIC: Master mode ,It control the sequence of DMA

operation during all DMA cycles. It generates address and control signals. It increments 16 bit address and decrement 14 bit

counter registers. It activate a HRQ signal on DMA channel Request. Slave ,mode it is disabled.

407

DMA controller details

408

Programming andapplications Case

studies1.Traffic Light control

2.LED display3.LCD display

4.Keyboard display interface5.Alarm Controller

Programming andapplications Case

studies1.Traffic Light control

2.LED display3.LCD display

4.Keyboard display interface5.Alarm Controller409

1. TRAFFICLIGHT

CONTROL

1. TRAFFICLIGHT

CONTROL410

Traffic lights, which may also be known as stoplights, trafficlamps, traffic signals, signal lights, robots or semaphore, aresignaling devices positioned at road intersections, pedestriancrossings and other locations to control competing flows oftraffic. INTERFACING TRAFFIC LIGHT WITH 8086

The Traffic light controller section consists of 12 Nos.point led’s arranged by 4Lanes in Traffic light interface card.Each lane has Go(Green), Listen(Yellow) and Stop(Red) LEDis being placed.

Traffic lights, which may also be known as stoplights, trafficlamps, traffic signals, signal lights, robots or semaphore, aresignaling devices positioned at road intersections, pedestriancrossings and other locations to control competing flows oftraffic. INTERFACING TRAFFIC LIGHT WITH 8086

The Traffic light controller section consists of 12 Nos.point led’s arranged by 4Lanes in Traffic light interface card.Each lane has Go(Green), Listen(Yellow) and Stop(Red) LEDis being placed.

411

LAN Direction 8086 LINES MODULES

412

CIRCUIT DIAGRAM TO INTERFACE TRAFFIC LIGHT WITH 8086

413

8086 ALP:1100: START: MOV BX, 1200H

MOV CX, 0008H

MOV AL,[BX]MOV DX, CONTROL PORTOUT DX, ALINC BX

NEXT: MOV AL,[BX]MOV DX, PORT AOUT DX,ALCALL DELAYINC BXLOOP NEXTJMP START

DELAY: PUSH CXMOV CX,0005H

REPEAT: MOV DX,0FFFFH

LOOP2: DEC DXJNZ LOOP2LOOP REPEATPOP CXRET

1100: START: MOV BX, 1200H

MOV CX, 0008H

MOV AL,[BX]MOV DX, CONTROL PORTOUT DX, ALINC BX

NEXT: MOV AL,[BX]MOV DX, PORT AOUT DX,ALCALL DELAYINC BXLOOP NEXTJMP START

DELAY: PUSH CXMOV CX,0005H

REPEAT: MOV DX,0FFFFH

LOOP2: DEC DXJNZ LOOP2LOOP REPEATPOP CXRET

414

Lookup Table 1200 80H

1201 21H,09H,10H,00H (SOUTH WAY)

1205 0CH,09H,80H,00H (EAST WAY)

1209 64H,08H,00H,04H (NOURTH WAY)

120D 24H,03H,02H,00H (WEST WAY)

1211 END

1200 80H

1201 21H,09H,10H,00H (SOUTH WAY)

1205 0CH,09H,80H,00H (EAST WAY)

1209 64H,08H,00H,04H (NOURTH WAY)

120D 24H,03H,02H,00H (WEST WAY)

1211 END

415

2. LED DISPLAY

416

Light Emitting Diodes (LED) is the most commonlyused components, usually for displaying pins digital states.Typical uses of LEDs include alarm devices, timers andconfirmation of user input such as a mouse click or keystroke.

INTERFACING LEDAnode is connected through a resistor to GND & the

Cathode is connected to the Microprocessor pin. So whenthe Port Pin is HIGH the LED is OFF & when the Port Pin isLOW the LED is turned ON.

Light Emitting Diodes (LED) is the most commonlyused components, usually for displaying pins digital states.Typical uses of LEDs include alarm devices, timers andconfirmation of user input such as a mouse click or keystroke.

INTERFACING LEDAnode is connected through a resistor to GND & the

Cathode is connected to the Microprocessor pin. So whenthe Port Pin is HIGH the LED is OFF & when the Port Pin isLOW the LED is turned ON.

417

PIN ASSIGNMENT WITH 8086

418

INTERFACE LED WITH 8255

419

8086 ALP LED interface1100: START: MOV AL, 80

MOV DX, FF36OUT DX, AL

BEGIN: MOV AL, 00MOV DX, FF30OUT DX, ALCALL DELAYMOV AL, FFOUT DX, ALCALL DELAYJMP BEGIN

DELAY: MOV CX, FFFFPO: DEC CX

JNE PORET

1100: START: MOV AL, 80MOV DX, FF36OUT DX, AL

BEGIN: MOV AL, 00MOV DX, FF30OUT DX, ALCALL DELAYMOV AL, FFOUT DX, ALCALL DELAYJMP BEGIN

DELAY: MOV CX, FFFFPO: DEC CX

JNE PORET

420

3. LCD DISPLAY

421

422

HARDWARE CONFIGURATION OF LCDWITH 8051/8086/8085

423

LCD INTERFACING WITH 8086TRAINER KIT

GPIO- I (8255) J1 ConnectorPORTS ADDRESS

Control port FF26PORT A FF20PORT B FF22PORT C FF24





424

425

LCD INTERFACING WITH 8051 TRAINER KIT GPIO- I (8255) J1 Connector

PORTS ADDRESSControl port 4003PORT A 4000PORT B 4001PORT C 4002

Used in UNIT 5 also


Control port 4003PORT A 4000PORT B 4001PORT C 4002

426

427

4. Keyboard display interface

428

HARDWARE DESCRIPTION OF 8279 INTERFACE CARDKeyboard and display is configured in the encoded mode.

In the encoded mode, a binary count sequence is put on the scanlines SL0-SL3.These lines must be externally decoded to providethe scan lines for keyboard and display. A 3 to 8 decoder74LS138 is provided for this purpose. The S0-S1 output lines ofthis decoder are connected to the two rows of the keyboard.And QA0 to QA7 is connected to 7 Segment Display

429

PIN DIAGRAM OF 8279 PIN DIAGRAMOF 74LS138

430


431

432

MVI A, 00H Initialize keyboard/display in encodedOUT 81H scan keyboard 2 key lockout modeMVI A, 34H

OUT 81H Initialize prescaler countMVI A, 0BH Load mask pattern to enable RST 7.5SIM mask other interruptsEI Enable Interrupt

HERE: JMP HERE Wait for the interruptInterrupt service routine

MVI A, 40H Initialize 8279 in read FIFO RAM modeOUT 81H

IN 80H Get keycodeMVI H, 62H Initialize memory pointer to pointMOV L, A 7-Segment codeMVI A, 80H : Initialize 8279 in write display RAM modeOUT 81H

MOV A, M : Get the 7 segment codeOUT 80H : Write 7-segment code in display RAMEI : Enable interruptRET : Return to main program

433

MVI A, 00H Initialize keyboard/display in encodedOUT 81H scan keyboard 2 key lockout modeMVI A, 34H

OUT 81H Initialize prescaler countMVI A, 0BH Load mask pattern to enable RST 7.5SIM mask other interruptsEI Enable Interrupt

HERE: JMP HERE Wait for the interruptInterrupt service routine

MVI A, 40H Initialize 8279 in read FIFO RAM modeOUT 81H

IN 80H Get keycodeMVI H, 62H Initialize memory pointer to pointMOV L, A 7-Segment codeMVI A, 80H : Initialize 8279 in write display RAM modeOUT 81H

MOV A, M : Get the 7 segment codeOUT 80H : Write 7-segment code in display RAMEI : Enable interruptRET : Return to main program

5. ALARM5. ALARMCONTROLLERCONTROLLER

RelevantMaterialNot exact

434

RelevantMaterialNot exact

435

GPIO- I J1 ConnecterPORTS ADDRESS


436

GPIO- I J1 ConnecterPORTS ADDRESS


GPIO- II J1 ConnecterPORTS ADDRESS


TEXT BOOK ReferencesMain Book:1. Microprocessors and Interfacing, Programming and Hardware by Doughlas




4. Advanced microprocessor and peripherals by A K RAYLOCAL AUTHOR:


ONLINE MATERILALS:

www.vtulearning.com

Main Book:1. Microprocessors and Interfacing, Programming and Hardware by Doughlas




4. Advanced microprocessor and peripherals by A K RAYLOCAL AUTHOR:


ONLINE MATERILALS:

www.vtulearning.com

437

Documents References• 8086 SYSTEM BUS STRUCTURE by Prof.L.PETER STANLEY BEBINGTON ( PROFESSOR

AND DEAN(ACADEMIC),VCET,Erode)• I/O Interfacing by Prof.P.JAYACHANDAR , ASSOCIATE PROFESSOR and

DEAN(SA),VCET,Erode• 8086 Microprocessor by Dr. M. Gopikrishna ,Assistant Professor of

Physics,Maharajas College ,Ernakulam• 8086 architecture By Er. Swapnil Kaware• 8086 presentations by Gursharan Singh Tatla (Eazynotes.com)• Interfacing 8255 by Anuja Bhakuni in Technology• Microprocessor and-interfacing by Akshay Makadiya• Interfacing is for microprocessor by R-THANDAIAH PRABU M.E., Lecturer – ECE• Microprocessor - Ramesh Gaonkar• 8086 micro processor prasadpawaskar• 8086 class notes-Y.N.M by MURTHY Y.N• Introduction to 8086 Microprocessor by Rajvir Singh• 8086 micro processor by Poojith Chowdhary• 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar & Cutajar• Intel microprocessor history by Ramzi_Alqrainy

• 8086 SYSTEM BUS STRUCTURE by Prof.L.PETER STANLEY BEBINGTON ( PROFESSORAND DEAN(ACADEMIC),VCET,Erode)

• I/O Interfacing by Prof.P.JAYACHANDAR , ASSOCIATE PROFESSOR andDEAN(SA),VCET,Erode

• 8086 Microprocessor by Dr. M. Gopikrishna ,Assistant Professor ofPhysics,Maharajas College ,Ernakulam

• 8086 architecture By Er. Swapnil Kaware• 8086 presentations by Gursharan Singh Tatla (Eazynotes.com)• Interfacing 8255 by Anuja Bhakuni in Technology• Microprocessor and-interfacing by Akshay Makadiya• Interfacing is for microprocessor by R-THANDAIAH PRABU M.E., Lecturer – ECE• Microprocessor - Ramesh Gaonkar• 8086 micro processor prasadpawaskar• 8086 class notes-Y.N.M by MURTHY Y.N• Introduction to 8086 Microprocessor by Rajvir Singh• 8086 micro processor by Poojith Chowdhary• 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar & Cutajar• Intel microprocessor history by Ramzi_Alqrainy

438

Website References• http://80864beginner.com/• www.eazynotes.com• www.slideshare.net• www.scribd.com• www.docstoc.com• www.slideworld.com• www.nptel.ac.in• http://opencourses.emu.edu.tr/• http://engineeringppt.blogspot.in/• http://www.pptsearchengine.net/• www.4shared.com• http://8085projects.info/

• http://80864beginner.com/• www.eazynotes.com• www.slideshare.net• www.scribd.com• www.docstoc.com• www.slideworld.com• www.nptel.ac.in• http://opencourses.emu.edu.tr/• http://engineeringppt.blogspot.in/• http://www.pptsearchengine.net/• www.4shared.com• http://8085projects.info/

439










440

MicrocontrollersIntroduction

EC6504 Microprocessors and MicrocontrollersDept: CSE,IT,ECE,MECH

Regulation : R2013

441

MicrocontrollersIntroduction


CPU for Computers No RAM, ROM, I/O on CPU chip itself Example: Intel's x86, Motorola’s 680x0

442

A smaller computer On-chip RAM, ROM, I/O ports... Example: Motorola’s 6811, Intel’s 8051, Zilog’s

Z8 and PIC

443

A smaller computer On-chip RAM, ROM, I/O ports... Example: Motorola’s 6811, Intel’s 8051, Zilog’s

Z8 and PIC

Microprocessor

CPU is stand-alone, RAM,ROM, I/O, timer areseparate

Designer can decide on theamount of ROM, RAM andI/O ports.

Expansive

General-purpose

Microcontroller

CPU, RAM, ROM, I/O and timerare all on a single chip

Fix amount of on-chip ROM, RAM,I/O ports

For applications in which cost,power and space are critical

Not Expansive

Single-purpose

444

Microprocessor

CPU is stand-alone, RAM,ROM, I/O, timer areseparate

Designer can decide on theamount of ROM, RAM andI/O ports.

Expansive

General-purpose

Microcontroller

CPU, RAM, ROM, I/O and timerare all on a single chip

Fix amount of on-chip ROM, RAM,I/O ports

For applications in which cost,power and space are critical

Not Expansive

Single-purpose

Home Appliances, intercom, telephones, security systems, garage door

openers, answering machines, fax machines, home computers,TVs, cable TV tuner, VCR, camcorder, remote controls, videogames, cellular phones, musical instruments, sewing machines,lighting control, paging, camera, pinball machines, toys, exerciseequipment etc.

Office Telephones, computers, security systems, fax machines,

microwave, copier, laser printer, color printer, paging etc.

Auto Trip computer, engine control, air bag, ABS, instrumentation,

security system, transmission control, entertainment, climatecontrol, cellular phone, keyless entry

445

Home Appliances, intercom, telephones, security systems, garage door

openers, answering machines, fax machines, home computers,TVs, cable TV tuner, VCR, camcorder, remote controls, videogames, cellular phones, musical instruments, sewing machines,lighting control, paging, camera, pinball machines, toys, exerciseequipment etc.

Office Telephones, computers, security systems, fax machines,

microwave, copier, laser printer, color printer, paging etc.

Auto Trip computer, engine control, air bag, ABS, instrumentation,

security system, transmission control, entertainment, climatecontrol, cellular phone, keyless entry

446


447

8051 CPU Operation1. Features

2. Pin Diagram

3. Block Diagram

1. Features

2. Pin Diagram

3. Block Diagram

448

8051 Microcontroller

• Intel introduced 8051, developed in the year 1981.

• The 8051 is an 8-bit processor– The CPU can work on only 8 bits of data at a time

• The 8051 became widely popular after allowingother manufactures to make and market anyflavor of the 8051.

• Intel introduced 8051, developed in the year 1981.

• The 8051 is an 8-bit processor– The CPU can work on only 8 bits of data at a time

• The 8051 became widely popular after allowingother manufactures to make and market anyflavor of the 8051.

449

8051 Family

• The 8051 is a subset of the 8052• The 8031 is a ROM-less 8051

– Add external ROM to it– You lose two ports, and leave only 2 ports for I/O operations

450

8051 Features

• 64KB Program Memory address space• 64KB Data Memory address space• 4K bytes of on-chip Program Memory• 128 bytes of on-chip Data RAM• 32 bidirectional and individually addressable I/0 lines• Two 16-bit timer/counters• 6-source/5-vector interrupt structure with two priority

levels• On-chip clock oscillator

• 64KB Program Memory address space• 64KB Data Memory address space• 4K bytes of on-chip Program Memory• 128 bytes of on-chip Data RAM• 32 bidirectional and individually addressable I/0 lines• Two 16-bit timer/counters• 6-source/5-vector interrupt structure with two priority

levels• On-chip clock oscillator

451

Pin Description of the 8051

• 8051 family members (e.g., 8751, 89C51, 89C52,DS89C4x0)– Have 40 pins dedicated for various functions such as I/O, RD,

WR, address, data, and interrupts.

• DIP(dual in-line package),

• Some companies provide a 20-pin version of the 8051with a reduced number of I/O ports for less demandingapplications

• 8051 family members (e.g., 8751, 89C51, 89C52,DS89C4x0)– Have 40 pins dedicated for various functions such as I/O, RD,

WR, address, data, and interrupts.

• DIP(dual in-line package),

• Some companies provide a 20-pin version of the 8051with a reduced number of I/O ports for less demandingapplications

452

Pin Diagram of the 8051

453

XTAL1 and XTAL2

• The 8051 has an on-chip oscillator but requires anexternal clock to run it– A quartz crystal oscillator is connected to inputs XTAL1 (pin19)

and XTAL2 (pin18)– The quartz crystal oscillator also needs two capacitors of 30 pF

value

• The 8051 has an on-chip oscillator but requires anexternal clock to run it– A quartz crystal oscillator is connected to inputs XTAL1 (pin19)

and XTAL2 (pin18)– The quartz crystal oscillator also needs two capacitors of 30 pF

value

454

XTAL1 and XTAL2 …..

• If you use a frequency source other than a crystaloscillator, such as a TTL oscillator:– It will be connected to XTAL1– XTAL2 is left unconnected

455

XTAL1 and XTAL2 …..

• The speed of 8051 refers to the maximum oscillatorfrequency connected to XTAL.

• We can observe the frequency on the XTAL2 pin usingthe oscilloscope.

• The speed of 8051 refers to the maximum oscillatorfrequency connected to XTAL.

• We can observe the frequency on the XTAL2 pin usingthe oscilloscope.

456

RST• RESET pin is an input and is active high (normally low)• Upon applying a high pulse to this pin, the microcontroller will

reset and terminate all activities

457

EA’

• EA’, “external access’’, is an input pin andmust be connected to Vcc or GND

• Normally EA pin is connected to Vcc

• EA pin must be connected to GND toindicate that the code or data is storedexternally.

• EA’, “external access’’, is an input pin andmust be connected to Vcc or GND

• Normally EA pin is connected to Vcc

• EA pin must be connected to GND toindicate that the code or data is storedexternally.

458

PSEN’ and ALE

• PSEN, “program store enable’’, is anoutput pin

• This pin is connected to the OE pin of theexternal memory.

• For External Code Memory, PSEN’ = 0

• For External Data Memory, PSEN’ = 1

• ALE pin is used for demultiplexing theaddress and data.

• PSEN, “program store enable’’, is anoutput pin

• This pin is connected to the OE pin of theexternal memory.

• For External Code Memory, PSEN’ = 0

• For External Data Memory, PSEN’ = 1

• ALE pin is used for demultiplexing theaddress and data.

459

I/O Port Pins

• The four 8-bit I/O ports P0, P1, P2and P3 each uses 8 pins.

460

Port 0

• Port 0 is also designated as AD0-AD7.

• When connecting an 8051 to an externalmemory, port 0 provides both addressand data.

• The 8051 multiplexes address and datathrough port 0 to save pins.

• ALE indicates if P0 has address or data.– When ALE=0, it provides data D0-D7– When ALE=1, it has address A0-A7

• Port 0 is also designated as AD0-AD7.

• When connecting an 8051 to an externalmemory, port 0 provides both addressand data.

• The 8051 multiplexes address and datathrough port 0 to save pins.

• ALE indicates if P0 has address or data.– When ALE=0, it provides data D0-D7– When ALE=1, it has address A0-A7

461

Port 1 and Port 2

• In 8051-based systems with no externalmemory connection:– Both P1 and P2 are used as simple I/O.

• In 8051-based systems with externalmemory connections:– Port 2 must be used along with P0 to provide

the 16-bit address for the external memory.– P0 provides the lower 8 bits via A0 – A7.– P2 is used for the upper 8 bits of the 16-bit

address, designated as A8 – A15, and it cannotbe used for I/O.

• In 8051-based systems with no externalmemory connection:– Both P1 and P2 are used as simple I/O.

• In 8051-based systems with externalmemory connections:– Port 2 must be used along with P0 to provide

the 16-bit address for the external memory.– P0 provides the lower 8 bits via A0 – A7.– P2 is used for the upper 8 bits of the 16-bit

address, designated as A8 – A15, and it cannotbe used for I/O.

462

Port 3

• Port 3 can be used as input or output.

• Port 3 has the additional function ofproviding some extremely importantsignals

• Port 3 can be used as input or output.

• Port 3 has the additional function ofproviding some extremely importantsignals

463

Pin Description SummaryPIN TYPE NAME AND FUNCTION

Vss I Ground: 0 V reference.Vcc I Power Supply: This is the power supply voltage for normal,

idle, and power-down operation.P0.0 - P0.7 I/O Port 0: Port 0 is an open-drain, bi-directional I/O port. Port

0 is also the multiplexed low-order address and databus during accesses to external program and datamemory.

Port 0: Port 0 is an open-drain, bi-directional I/O port. Port0 is also the multiplexed low-order address and databus during accesses to external program and datamemory.

P1.0 - P1.7 I/O Port 1: Port I is an 8-bit bi-directional I/O port.

P2.0 - P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits thehigh order address byte during fetches from externalprogram memory and during accesses to external datamemory that use 16 bit addresses.

P3.0 - P3.7 I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 alsoserves special features as explained.

464

Pin Description SummaryPIN TYPE NAME AND FUNCTION

RST I Reset: A high on this pin for two machine cycles while theoscillator is running, resets the device.

ALE O Address Latch Enable: Output pulse for latching the low byteof the address during an access to external memory.

PSEN* O Program Store Enable: The read strobe to external programmemory. When executing code from the external programmemory, PSEN* is activated twice each machine cycle,except that two PSEN* activations are skipped duringeach access to external data memory.

Program Store Enable: The read strobe to external programmemory. When executing code from the external programmemory, PSEN* is activated twice each machine cycle,except that two PSEN* activations are skipped duringeach access to external data memory.

EA*/VPP I External Access Enable/Programming Supply Voltage: Vpppin also receives the programming supply voltage Vppduring Flash programming. (applies for 89c5x MCU's)

465

InterruptControl

CPU

4KROM

128 BRAM Timer 1

Timer 0

General Block Diagram of 8051

CPU

OSC BusControl 4 I/O Ports Serial

Port

TXD RXDP0 P1 P2 P3 466

Detailed Block Diagram

467

8051Memory Space

8051Memory Space

468

8051 Memory Structure

Exte

rnal

Exte

rnal

64K 64K

60K

Exte

rnal

EXT INT 128

SFR

Exte

rnal

Program Memory Data Memory

64K 64K

EA = 0 EA = 1

4K

469

Internal RAM Structure

DirectAddressing

OnlySFR [ Special FunctionRegisters]Direct &

IndirectAddressing

SFR [ Special FunctionRegisters]

128 Byte Internal RAM

470

SpecialFunction

Register [SFR]

SpecialFunction

Register [SFR]471

Special Function Registers [SFR]

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode472

SFR Registers & their AddressesMOVMOV 0E0H,#55H0E0H,#55H ;is the same as;is the same asMOVMOV A,#55HA,#55H ;which means load 55H into A (A=55H);which means load 55H into A (A=55H)

MOVMOV 0F0H,#25H0F0H,#25H ;is the same as;is the same asMOV B,#25HMOV B,#25H ;which means load 25H into B (B=25H);which means load 25H into B (B=25H)

MOVMOV 0E0H,R20E0H,R2 ;is the same as;is the same asMOVMOV A,R2A,R2 ;which means copy R2 into A;which means copy R2 into A

MOVMOV 0F0H,R00F0H,R0 ;is the same as;is the same asMOVMOV B,R0B,R0 ;which means copy R0 into B;which means copy R0 into B

MOVMOV 0E0H,#55H0E0H,#55H ;is the same as;is the same asMOVMOV A,#55HA,#55H ;which means load 55H into A (A=55H);which means load 55H into A (A=55H)

MOVMOV 0F0H,#25H0F0H,#25H ;is the same as;is the same asMOV B,#25HMOV B,#25H ;which means load 25H into B (B=25H);which means load 25H into B (B=25H)

MOVMOV 0E0H,R20E0H,R2 ;is the same as;is the same asMOVMOV A,R2A,R2 ;which means copy R2 into A;which means copy R2 into A

MOVMOV 0F0H,R00F0H,R0 ;is the same as;is the same asMOVMOV B,R0B,R0 ;which means copy R0 into B;which means copy R0 into B

473

SFR Addresses ( 1 of 2 )

474

SFR Addresses ( 2 of 2 )

475

Example

476

Program Status Word [PSW]

C AC F0 RS1 RS0 OV F1 PCarry Parity

Register Bank Select

Carry

Auxiliary Carry

User Flag 0

Parity

User Flag 1

Overflow

477

8051 instructions that affects flag

478

128 Byte RAM• There are 128 bytes of RAM in the 8051.

– Assigned addresses 00 to 7FH

• The 128 bytes are divided into 3 differentgroups as follows:1. A total of 32 bytes from locations 00 to 1F

hex are set aside for register banks and thestack.

2. A total of 16 bytes from locations 20H to 2FHare set aside for bit-addressable read/writememory.

3. A total of 80 bytes from locations 30H to 7FHare used for read and write storage, calledscratch pad.

BIT AddressableArea

General PurposeArea

• There are 128 bytes of RAM in the 8051.– Assigned addresses 00 to 7FH

• The 128 bytes are divided into 3 differentgroups as follows:1. A total of 32 bytes from locations 00 to 1F

hex are set aside for register banks and thestack.

2. A total of 16 bytes from locations 20H to 2FHare set aside for bit-addressable read/writememory.

3. A total of 80 bytes from locations 30H to 7FHare used for read and write storage, calledscratch pad.

128 BYTEINTERNAL RAM

Register Banks

Reg Bank 0

Reg Bank 1

Reg Bank 2

Reg Bank 3

BIT AddressableArea

479

8051 RAM with addresses

480

8051 Register Bank Structure

R0 R1 R2 R3 R4 R5 R6 R7Bank 3


Bank 0



R0 R1 R2 R3 R4 R5 R6 R7

481

8051 Register Banks with address

482

8051 Programming Model

483

8051 Stack

• The stack is a section of RAM used by the CPU to storeinformation temporarily.– This information could be data or an address

• The register used to access the stack is called the SP(stack pointer) register– The stack pointer in the 8051 is only 8 bit wide, which means

that it can take value of 00 to FFH

• The stack is a section of RAM used by the CPU to storeinformation temporarily.– This information could be data or an address

• The register used to access the stack is called the SP(stack pointer) register– The stack pointer in the 8051 is only 8 bit wide, which means

that it can take value of 00 to FFH

484

8051 Stack

• The storing of a CPU register in the stack is called a PUSH– SP is pointing to the last used location of the stack– As we push data onto the stack, the SP is incremented by one– This is different from many microprocessors

• Loading the contents of the stack back into a CPUregister is called a POP– With every pop, the top byte of the stack is copied to the

register specified by the instruction and the stack pointer isdecremented once

• The storing of a CPU register in the stack is called a PUSH– SP is pointing to the last used location of the stack– As we push data onto the stack, the SP is incremented by one– This is different from many microprocessors

• Loading the contents of the stack back into a CPUregister is called a POP– With every pop, the top byte of the stack is copied to the

register specified by the instruction and the stack pointer isdecremented once

485

INSTRUCTIONSET OF8051

INSTRUCTIONSET OF8051

486

8051 Instruction Set• The instructions are grouped into 5 groups

– Arithmetic– Logic– Data Transfer– Boolean– Branching

• The instructions are grouped into 5 groups– Arithmetic– Logic– Data Transfer– Boolean– Branching

487

1. Arithmetic Instructions• ADD

– 8-bit addition between the accumulator (A) and asecond operand.

• The result is always in the accumulator.• The CY flag is set/reset appropriately.

• ADDC– 8-bit addition between the accumulator, a second

operand and the previous value of the CY flag.

• ADD– 8-bit addition between the accumulator (A) and a

second operand.• The result is always in the accumulator.• The CY flag is set/reset appropriately.

• ADDC– 8-bit addition between the accumulator, a second

operand and the previous value of the CY flag.

488

ADD Instruction

• ADD A, source ;ADD the source operand tothe accumulator

• MOV A, #03H ;load 03H into A

MOV B,#02H ;load 02H into B

ADD A,B ;add B register to accumulator

;(A = A + B)= 05

• ADD A, source ;ADD the source operand tothe accumulator



ADD A,B ;add B register to accumulator

;(A = A + B)= 05

489

SUBB–Subtract with Borrow.

–A A - <operand> - CY.–The result is always saved in the

accumulator.–The CY flag is set/reset appropriately.

SUBB–Subtract with Borrow.

–A A - <operand> - CY.–The result is always saved in the

accumulator.–The CY flag is set/reset appropriately.

490

SUBB Instruction

• SUBB A, source ;ADD the source operand tothe accumulator



SUBB A,B ;add B register to accumulator

;(A = A - B)= 01

• SUBB A, source ;ADD the source operand tothe accumulator



SUBB A,B ;add B register to accumulator

;(A = A - B)= 01

491

• INC– Increment the operand by one. Ex: INC DPTR

• The operand can be a register, a direct address, anindirect address, the data pointer.

• DEC– Decrement the operand by one. Ex: DEC B

• The operand can be a register, a direct address, anindirect address.

• MUL AB / DIV AB– Multiply A by B and place result in A:B.– Divide A by B and place result in A:B.

• INC– Increment the operand by one. Ex: INC DPTR

• The operand can be a register, a direct address, anindirect address, the data pointer.

• DEC– Decrement the operand by one. Ex: DEC B

• The operand can be a register, a direct address, anindirect address.

• MUL AB / DIV AB– Multiply A by B and place result in A:B.– Divide A by B and place result in A:B.

492

Multiplication of Numbers

MUL AB ; A B, place 16-bit result in B and A

MOV A,#05MOV A,#05 ;load 05H to reg. A;load 05H to reg. AMOV B,#03MOV B,#03 ;load 03H in reg. B;load 03H in reg. BMUL ABMUL AB ;05 * 03 = 000F where;05 * 03 = 000F where B = 00B = 00 andand A = 0FA = 0F

Table 6-1:Unsigned Multiplication Summary (MUL AB)

Multiplication Operand 1 Operand 2 Result

byte byte A B A=low byte,

B=high byte

493

Division of NumbersMOV AMOV A,#05,#05 ;load;load 05H05H to reg. Ato reg. AMOV BMOV B,#03,#03 ;load;load 03H03H in reg. Bin reg. BDIV AB ;05/03 =>Quotient =DIV AB ;05/03 =>Quotient = 0101,Reminder =,Reminder = 0202

wherewhere B =B = 0202 andand A =A = 0101

Table 6-2:Unsigned Division Summary (DIV AB)

Division Numerator Denominator Quotient Remainder

byte / byte A B A B

MOV AMOV A,#05,#05 ;load;load 05H05H to reg. Ato reg. AMOV BMOV B,#03,#03 ;load;load 03H03H in reg. Bin reg. BDIV AB ;05/03 =>Quotient =DIV AB ;05/03 =>Quotient = 0101,Reminder =,Reminder = 0202

wherewhere B =B = 0202 andand A =A = 0101

494

•ADD A,@Rn A = A+ memory pointed to Rn

•DA A Decimal Adjust A {BCD addition}

•ADDC A,@Rn•SUBB A,@Rn•INC @Ri

•ADD A,@Rn A = A+ memory pointed to Rn

•DA A Decimal Adjust A {BCD addition}

•ADDC A,@Rn•SUBB A,@Rn•INC @Ri

495

2. Logicalinstructions

2. Logicalinstructions

496

• ANL D,S-Performs logical AND of destination & source-Destination : A/memory;-Source : data/register/memory

- Eg: ANL A,#0FH ANL A,R5• ORL D,S

-Performs logical OR of destination & source-Destination : A/memory;-Source : data/register/memory

- Eg: ORL A,#28H ORL A,@R0

497

• ANL D,S-Performs logical AND of destination & source-Destination : A/memory;-Source : data/register/memory

- Eg: ANL A,#0FH ANL A,R5• ORL D,S

-Performs logical OR of destination & source-Destination : A/memory;-Source : data/register/memory

- Eg: ORL A,#28H ORL A,@R0

•XRL D,S-Performs logical XOR of destination & source-Destination : A/memory;-Source : data/register/memory

- Eg: XRL A,#28H XRL A,@R0

• CPL A-Compliment accumulator-gives 1’s compliment of accumulator data

• SWAP A-Exchange the upper & lower nibbles of accumulator

498

•XRL D,S-Performs logical XOR of destination & source-Destination : A/memory;-Source : data/register/memory

- Eg: XRL A,#28H XRL A,@R0

• CPL A-Compliment accumulator-gives 1’s compliment of accumulator data

• SWAP A-Exchange the upper & lower nibbles of accumulator

• RL A-Rotate data of accumulator towards left withoutcarry

• RLC A- Rotate data of accumulator towards left with carry

• RR A-Rotate data of accumulator towards right withoutcarry

• RRC A- Rotate data of accumulator towards right withcarry

• RL A-Rotate data of accumulator towards left withoutcarry

• RLC A- Rotate data of accumulator towards left with carry

• RR A-Rotate data of accumulator towards right withoutcarry

• RRC A- Rotate data of accumulator towards right withcarry

499

3. Data TransferInstructions

3. Data TransferInstructions

500

MOV Instruction• MOV destination, source ; copy source to destination.

• MOV A,#55H ;load value 55H into reg. AMOV R0,A ;copy contents of A into R0

;(now A=R0=55H)MOV R1,A ;copy contents of A into R1

;(now A=R0=R1=55H)MOV R2,A ;copy contents of A into R2

;(now A=R0=R1=R2=55H)MOV R3,#95H ;load value 95H into R3

;(now R3=95H)MOV A,R3 ;copy contents of R3 into A

;now A=R3=95H

• MOV destination, source ; copy source to destination.

• MOV A,#55H ;load value 55H into reg. AMOV R0,A ;copy contents of A into R0

;(now A=R0=55H)MOV R1,A ;copy contents of A into R1

;(now A=R0=R1=55H)MOV R2,A ;copy contents of A into R2

;(now A=R0=R1=R2=55H)MOV R3,#95H ;load value 95H into R3

;(now R3=95H)MOV A,R3 ;copy contents of R3 into A

;now A=R3=95H

501

• MOVX– Data transfer between the accumulator and

a byte from external data memory.•MOVX A, @Ri•MOVX A, @DPTR•MOVX @Ri, A•MOVX @DPTR, A

• MOVX– Data transfer between the accumulator and

a byte from external data memory.•MOVX A, @Ri•MOVX A, @DPTR•MOVX @Ri, A•MOVX @DPTR, A

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode 502

• PUSH / POP– Push and Pop a data byte onto the stack.– The data byte is identified by a direct

address from the internal RAM locations.

•PUSH DPL•POP 40H

• PUSH / POP– Push and Pop a data byte onto the stack.– The data byte is identified by a direct

address from the internal RAM locations.

•PUSH DPL•POP 40H

503

• XCH– Exchange accumulator and a byte variable

•XCH A, Rn•XCH A, direct•XCH A, @Ri

• XCH– Exchange accumulator and a byte variable

•XCH A, Rn•XCH A, direct•XCH A, @Ri

504

4.Boolean variableinstructions

4.Boolean variableinstructions

505

CLR:• The operation clears the specified bit indicated in

the instruction• Ex: CLR C clear the carry

SETB:• The operation sets the specified bit to 1.

CPL:• The operation complements the specified bit

indicated in the instruction

CLR:• The operation clears the specified bit indicated in

the instruction• Ex: CLR C clear the carry

SETB:• The operation sets the specified bit to 1.

CPL:• The operation complements the specified bit

indicated in the instruction

506

• ANL C,<Source-bit>

-Performs AND bit addressed with the carry bit.- Eg: ANL C,P2.7 AND carry flag with bit 7 of P2

• ORL C,<Source-bit>

-Performs OR bit addressed with the carry bit.- Eg: ORL C,P2.1 OR carry flag with bit 1 of P2

507

• ANL C,<Source-bit>

-Performs AND bit addressed with the carry bit.- Eg: ANL C,P2.7 AND carry flag with bit 7 of P2

• ORL C,<Source-bit>

-Performs OR bit addressed with the carry bit.- Eg: ORL C,P2.1 OR carry flag with bit 1 of P2

• XORL C,<Source-bit>

-Performs XOR bit addressed with the carry bit.- Eg: XOL C,P2.1 OR carry flag with bit 1 of P2

•MOV P2.3,C•MOV C,P3.3•MOV P2.0,C

• XORL C,<Source-bit>

-Performs XOR bit addressed with the carry bit.- Eg: XOL C,P2.1 OR carry flag with bit 1 of P2

•MOV P2.3,C•MOV C,P3.3•MOV P2.0,C

508

5. Branchinginstructions5. Branchinginstructions

509

• Program branching instructions areused to control the flow of actions ina program

• Some instructions provide decisionmaking capabilities and transfercontrol to other parts of the program.– e.g. conditional and unconditional

branches

• Program branching instructions areused to control the flow of actions ina program

• Some instructions provide decisionmaking capabilities and transfercontrol to other parts of the program.– e.g. conditional and unconditional

branches

510

Jump Instructions• All conditional jumps are short jumps

– Target address within -128 to +127 of PC

• LJMP (long jump): 3-byte instruction– 2-byte target address: 0000 to FFFFH

– Original 8051 has only 4KB on-chip ROM

• SJMP (short jump): 2-byte instruction– 1-byte relative address: -128 to +127

• All conditional jumps are short jumps– Target address within -128 to +127 of PC

• LJMP (long jump): 3-byte instruction– 2-byte target address: 0000 to FFFFH

– Original 8051 has only 4KB on-chip ROM

• SJMP (short jump): 2-byte instruction– 1-byte relative address: -128 to +127

511

Call Instructions• LCALL (long call): 3-byte instruction

– 2-byte address– Target address within 64K-byte range

• ACALL (absolute call): 2-byte instruction– 11-bit address– Target address within 2K-byte range

• LCALL (long call): 3-byte instruction– 2-byte address– Target address within 64K-byte range

• ACALL (absolute call): 2-byte instruction– 11-bit address– Target address within 2K-byte range

512

• The 8051 provides 2 forms for the returninstruction:– Return from subroutine – RET– Return from ISR – RETI

513

514

8051Addressing

Modes

8051Addressing

Modes515

8051 Addressing Modes

• The CPU can access data in various ways, which arecalled addressing modes

1. Immediate2. Register3. Direct4. Register indirect5. External Direct

• The CPU can access data in various ways, which arecalled addressing modes

1. Immediate2. Register3. Direct4. Register indirect5. External Direct

516

1. Immediate Addressing Mode• The source operand is a constant.• The immediate data must be preceded by the pound sign, “#”• Can load information into any registers, including 16-bit DPTR

register– DPTR can also be accessed as two 8-bit registers, the high byte DPH and

low byte DPL

• The source operand is a constant.• The immediate data must be preceded by the pound sign, “#”• Can load information into any registers, including 16-bit DPTR

register– DPTR can also be accessed as two 8-bit registers, the high byte DPH and

low byte DPL

517

2. Register Addressing Mode• Use registers to hold the data to be manipulated.

• The source and destination registers must match in size.MOV DPTR,A will give an error

• The source and destination registers must match in size.MOV DPTR,A will give an error

• The movement of data between Rn registers is not allowedMOV R4,R7 is invalid

518

3. Direct Addressing Mode

• It is most often used the direct addressing mode toaccess RAM locations 30 – 7FH.

• The entire 128 bytes of RAM can be accessed.

• Contrast this with immediate addressing mode, there isno “#” sign in the operand.

• It is most often used the direct addressing mode toaccess RAM locations 30 – 7FH.

• The entire 128 bytes of RAM can be accessed.

• Contrast this with immediate addressing mode, there isno “#” sign in the operand.

519

Stack and Direct Addressing Mode

• Only direct addressing mode is allowed for pushing orpopping the stack.

• PUSH A is invalid.

• Pushing the accumulator onto the stack must be codedas PUSH 0E0H.

• Only direct addressing mode is allowed for pushing orpopping the stack.

• PUSH A is invalid.

• Pushing the accumulator onto the stack must be codedas PUSH 0E0H.

520

4. Register Indirect Addressing Mode

• A register is used as a pointer to the data.• Only register R0 and R1 are used for this purpose.• R2 – R7 cannot be used to hold the address of an

operand located in RAM.• When R0 and R1 hold the addresses of RAM locations,

they must be preceded by the “@” sign.

• A register is used as a pointer to the data.• Only register R0 and R1 are used for this purpose.• R2 – R7 cannot be used to hold the address of an

operand located in RAM.• When R0 and R1 hold the addresses of RAM locations,

they must be preceded by the “@” sign.

521

Register Indirect Addressing Mode• Write a program to copy the value 55H into RAM memory locations 40H

to 41H using (a) direct addressing mode, (b) register indirect addressingmode without a loop, and (c) with a loop.

522

Register Indirect Addressing Mode• The advantage is that it makes accessing data dynamic

rather than static as in direct addressing mode.

• Looping is not possible in direct addressing mode.

• Write a program to clear 16 RAM locations starting atRAM address 60H.

• The advantage is that it makes accessing data dynamicrather than static as in direct addressing mode.

• Looping is not possible in direct addressing mode.

• Write a program to clear 16 RAM locations starting atRAM address 60H.

523

5. External Direct

• External Memory is accessed.

• There are only two commands that use External Directaddressing mode:– MOVX A, @DPTR

MOVX @DPTR, A

• DPTR must first be loaded with the address of externalmemory.

• External Memory is accessed.

• There are only two commands that use External Directaddressing mode:– MOVX A, @DPTR

MOVX @DPTR, A

• DPTR must first be loaded with the address of externalmemory.

524

8051AssemblyLanguage

Programming(ALP)

8051AssemblyLanguage

Programming(ALP)

525

ADDITION OF TWO 8 bit NumbersADDRESS LABEL MNEMONICS

9100 START CLR C

MOV R0, #00

MOV A,#05

MOV B,#03

ADD A,BADD A,B

MOV DPTR,#9200

JNC AHEAD

INC R0

AHEAD MOV X @DPTR,A

INC DPTR

MOV A,R0

MOV X @DPTR,A

HERE SJMP HERE 526

SUBTRACTION OF TWO 8 bit NumbersADDRESS LABEL MNEMONICS

9100 START CLR C

MOV R0, #00

MOV A,#05

MOV B,#03

SUBB A,BSUBB A,B

MOV DPTR,#9200

JNC AHEAD

INC R0

AHEAD MOV X @DPTR,A

INC DPTR

MOV A,R0

MOV X @DPTR,A

HERE SJMP HERE 527

Multiplication Concept

MUL AB ; A B, place 16-bit result in B and A

MOV A,#25HMOV A,#25H ;load 25H to reg. A;load 25H to reg. AMOV B,#65HMOV B,#65H ;load 65H in reg. B;load 65H in reg. BMUL ABMUL AB ;25H * 65H = E99 where B = 0EH and A = 99H;25H * 65H = E99 where B = 0EH and A = 99H

Table 6-1:Unsigned Multiplication Summary (MUL AB)

Multiplication Operand 1 Operand 2 Result

byte byte A B A=low byte,

B=high byte

528

Division Concept

DIV AB ; divide A by B

• MOV A,#95H ;load 95 into A• MOV B,#10H ;load 10 into B• DIV AB ;now A = 09 (quotient) and B = 05 (remainder)

DIV AB ; divide A by B

• MOV A,#95H ;load 95 into A• MOV B,#10H ;load 10 into B• DIV AB ;now A = 09 (quotient) and B = 05 (remainder)

Table 6-2:Unsigned Division Summary (DIV AB)

Division Numerator Denominator Quotient Remainder

byte / byte A B A B

529

MULTIPLICATION OF TWO8 bit Numbers

Address Label Mnemonics

9000 START MOV A,#05

MOV F0,#03

MUL AB

MOV DPTR,#9200

Address Label Mnemonics

9000 START MOV A,#05

MOV F0,#03

DIV AB

MOV DPTR,#9200

DIVISION OF TWO 8 bitNumbers

MOV DPTR,#9200

MOVX @ DPTR,A

INC DPTR

MOV A,F0

MOVX @DPTR,A

HERE SJMP HERE

MOV DPTR,#9200

MOVX @ DPTR,A

INC DPTR

MOV A,F0

MOVX @DPTR,A

HERE SJMP HERE

530

MOV 40H, #05H store I st number in location 40H

MOV 41H, #04H

MOV 42H, #03H

MOV 43H, #02H

MOV 44H, #01H

MOV R0, #40H store I st number address 40H in R0

MOV R5, #05H store the number 05H in R5

MOV B,R5 store the number 05H in B

CLR A Clear AccLOOP: ADD A,@R0

INC R0DJNZ R5,LOOPDIV ABMOV 55H,A Save the quotient in location 55HEND

Average of Five(or N) 8 bit NumbersMOV 40H, #05H store I st number in location 40H

MOV 41H, #04H

MOV 42H, #03H

MOV 43H, #02H

MOV 44H, #01H

MOV R0, #40H store I st number address 40H in R0

MOV R5, #05H store the number 05H in R5

MOV B,R5 store the number 05H in B

CLR A Clear AccLOOP: ADD A,@R0

INC R0DJNZ R5,LOOPDIV ABMOV 55H,A Save the quotient in location 55HEND

531

Checking an input bitJNB (jump if no bit) ; JB (jump if bit = 1)

532

Switch Register Banks

533

Pushing onto Stack

534

Popping from Stack

535

Looping

536

Loop inside a Loop (Nested Loop)

537

Conditional Jump Example

538

Conditional Jump Example

539


540


8051TIMERS

8051TIMERS

541

8051 Timer/Counter

OSC ÷12

TLx(8 Bit)

/ 0C T

/ 1C T

T PIN

THx(8 Bit)

TFx(1 Bit)

INT PIN

Gate

TR

T PININTERRUPT

542

TMOD Register

GATE:When set, timer/counter x is enabled, if INTx pin is highand TRx is set.When cleared, timer/counter x is enabled, if TRx bit set.

C/T*:When set, counter operation (input from Tx input pin).When cleared, timer operation (input from internal clock).

GATE:When set, timer/counter x is enabled, if INTx pin is highand TRx is set.When cleared, timer/counter x is enabled, if TRx bit set.

C/T*:When set, counter operation (input from Tx input pin).When cleared, timer operation (input from internal clock).

543

TMOD Register

The TMOD byte is not bit addressable.

544

TCON Register

545

8051 Timer Modes

Timer 0

Mode 0 Mode 0

Timer 1

8051 TIMERS

Mode 3

Mode 2

Mode 1

Mode 0

Mode 2

Mode 1

Mode 0

546

OSC ÷12

TL0/ 0C T

/ 1C T

0T PIN

TH0

TIMER 0

TF0

0INT PIN

Gate

0TR

0T PININTERRUPT

547

TL0(5 Bit)

INTERRUPT

TIMER 0 – Mode 0

OSC ÷12/ 0C T

/ 1C T

0T PIN

TH0(8 Bit) TF0

13 Bit Timer / Counter

0INT PIN

Gate

0TR

0T PIN

Maximum Count = 1FFFh (0001111111111111)

548

TL0(8 Bit)

INTERRUPT

TIMER 0 – Mode 1

OSC ÷12/ 0C T

/ 1C T

0T PIN

TH0(8 Bit) TF0


0INT PIN

Gate

0TR

0T PIN

Maximum Count = FFFFh (1111111111111111)

549

TIMER 0 – Mode 2

8 Bit Timer / Counter with AUTORELOAD

TL0(8 Bit)

OSC ÷12/ 0C T

/ 1C T

0T PIN

TH0(8 Bit) TF0 INTERRUPT

TH0(8 Bit)

Reload

0INT PIN

Gate

0TR

0T PIN

Maximum Count = FFh (11111111)550

TL0(8 Bit)

INTERRUPT

TIMER 0 – Mode 3

OSC ÷12/ 0C T

/ 1C T

0TR

0T PIN

TF0

Two - 8 Bit Timer / Counter

0INT PIN

Gate

OSC ÷12

1TR

TH0(8 Bit)

INTERRUPTTF1

551

OSC ÷12

TL1/ 0C T

/ 1C T TH1

INTERRUPT

TIMER 1

TF1

1T PIN

Gate

INTERRUPT

1INT PIN

1TR

1T PIN

552

TL1(5 Bit)

INTERRUPT

TIMER 1 – Mode 0

OSC ÷12/ 0C T

/ 1C T

TH1(8 Bit) TF1


1T PIN

Gate

Maximum Count = 1FFFh (0001111111111111)

1INT PIN

1TR

1T PIN

553

TL1(8 Bit)

INTERRUPT

TIMER 1 – Mode 1

OSC ÷12/ 0C T

/ 1C T

TH1(8 Bit) TF1


1T PIN

Gate

Maximum Count = FFFFh (1111111111111111)

1INT PIN

1TR

1T PIN

554

TIMER 1 – Mode 2

8 Bit Timer / Counter with AUTORELOAD

TL1(8 Bit)

OSC ÷12/ 0C T

/ 1C T

TH1(8 Bit) TF1 INTERRUPT

1T PIN

TH1(8 Bit)

ReloadGate

Maximum Count = FFh (11111111)

1INT PIN

1TR

1T PIN

555

Programming Timers

• Example: Indicate which mode and which timer areselected for each of the following.(a) MOV TMOD, #01H (b) MOV TMOD, #20H (c) MOVTMOD, #12H

• Solution: We convert the value from hex to binary.(a) TMOD = 00000001, mode 1 of timer 0 is selected.(b) TMOD = 00100000, mode 2 of timer 1 is selected.(c) TMOD = 00010010, mode 2 of timer 0, and mode 1 of timer 1

are selected.

• Example: Indicate which mode and which timer areselected for each of the following.(a) MOV TMOD, #01H (b) MOV TMOD, #20H (c) MOVTMOD, #12H

• Solution: We convert the value from hex to binary.(a) TMOD = 00000001, mode 1 of timer 0 is selected.(b) TMOD = 00100000, mode 2 of timer 1 is selected.(c) TMOD = 00010010, mode 2 of timer 0, and mode 1 of timer 1

are selected.

556

Programming Timers

• Find the timer’s clock frequency and its period forvarious 8051-based system, with the crystal frequency11.0592 MHz when C/T bit of TMOD is 0.

• Solution:

• Find the timer’s clock frequency and its period forvarious 8051-based system, with the crystal frequency11.0592 MHz when C/T bit of TMOD is 0.

• Solution:

1/12 × 11.0529 MHz = 921.6 MHz;

T = 1/921.6 kHz = 1.085 us

557

558


8051SerialPort

8051SerialPort

559

Basics of Serial Communication

• Computers transfer data in two ways:– Parallel: Often 8 or more lines (wire conductors) are used to

transfer data to a device that is only a few feet away.

– Serial: To transfer to a device located many meters away, theserial method is used. The data is sent one bit at a time.

• Computers transfer data in two ways:– Parallel: Often 8 or more lines (wire conductors) are used to

transfer data to a device that is only a few feet away.

– Serial: To transfer to a device located many meters away, theserial method is used. The data is sent one bit at a time.

560

Basics of Serial Communication

• Serial data communication uses two methods– Synchronous method transfers a block of data at a time

– Asynchronous method transfers a single byte at a time

• There are special IC’s made by many manufacturers forserial communications.– UART (universal asynchronous Receiver transmitter)

– USART (universal synchronous-asynchronous Receiver-transmitter)

• Serial data communication uses two methods– Synchronous method transfers a block of data at a time

– Asynchronous method transfers a single byte at a time

• There are special IC’s made by many manufacturers forserial communications.– UART (universal asynchronous Receiver transmitter)

– USART (universal synchronous-asynchronous Receiver-transmitter)

561

Asynchronous – Start & Stop Bit

• Asynchronous serial data communication is widely usedfor character-oriented transmissions– Each character is placed in between start and stop bits, this is

called framing.– Block-oriented data transfers use the synchronous method.

• The start bit is always one bit, but the stop bit can beone or two bits

• The start bit is always a 0 (low) and the stop bit(s) is 1(high)

• Asynchronous serial data communication is widely usedfor character-oriented transmissions– Each character is placed in between start and stop bits, this is

called framing.– Block-oriented data transfers use the synchronous method.

• The start bit is always one bit, but the stop bit can beone or two bits

• The start bit is always a 0 (low) and the stop bit(s) is 1(high)

562

Asynchronous – Start & Stop Bit

563

Data Transfer Rate• The rate of data transfer in serial data communication is

stated in bps (bits per second).

• Another widely used terminology for bps is baud rate.– It is modem terminology and is defined as the number of

signal changes per second– In modems, there are occasions when a single change of signal

transfers several bits of data

• As far as the conductor wire is concerned, the baud rateand bps are the same.

• The rate of data transfer in serial data communication isstated in bps (bits per second).

• Another widely used terminology for bps is baud rate.– It is modem terminology and is defined as the number of

signal changes per second– In modems, there are occasions when a single change of signal

transfers several bits of data

• As far as the conductor wire is concerned, the baud rateand bps are the same.

564

8051 Serial Port

• Synchronous and Asynchronous• SCON Register is used to Control• Data Transfer through TXd & RXd pins• Some time - Clock through TXd Pin• Four Modes of Operation:

• Synchronous and Asynchronous• SCON Register is used to Control• Data Transfer through TXd & RXd pins• Some time - Clock through TXd Pin• Four Modes of Operation:

Mode 0 :Synchronous Serial CommunicationMode 1 :8-Bit UART with Timer Data RateMode 2 :9-Bit UART with Set Data RateMode 3 :9-Bit UART with Timer Data Rate

565

Registers related to SerialCommunication

1. SBUF Register

2. SCON Register

3. PCON Register

1. SBUF Register

2. SCON Register

3. PCON Register

566

SBUF Register

• SBUF is an 8-bit register used solely for serial communication.

• For a byte data to be transferred via the TxD line, it must beplaced in the SBUF register.

• The moment a byte is written into SBUF, it is framed with thestart and stop bits and transferred serially via the TxD line.

• SBUF holds the byte of data when it is received by 8051 RxDline.

• When the bits are received serially via RxD, the 8051 deframesit by eliminating the stop and start bits, making a byte out ofthe data received, and then placing it in SBUF.

• SBUF is an 8-bit register used solely for serial communication.

• For a byte data to be transferred via the TxD line, it must beplaced in the SBUF register.

• The moment a byte is written into SBUF, it is framed with thestart and stop bits and transferred serially via the TxD line.

• SBUF holds the byte of data when it is received by 8051 RxDline.

• When the bits are received serially via RxD, the 8051 deframesit by eliminating the stop and start bits, making a byte out ofthe data received, and then placing it in SBUF.

567

SBUF Register

• Sample Program:

568

SCON Register

SM0 SM1 SM2 REN TB8 RB8 TI RI

Set when a Cha-ractor received

Enable MultiprocessorCommunication Mode

Set to EnableSerial Datareception

9th Data BitSent in Mode 2,3

9th Data BitReceived in Mode 2,3

Set when Stop bit Txed

Set when a Cha-ractor received

569

8051 Serial Port – Mode 0

The Serial Port in Mode-0 has the following features:

1. Serial data enters and exits through RXD

2. TXD outputs the clock

3. 8 bits are transmitted / received

4. The baud rate is fixed at (1/12) of the oscillator frequency


1. Serial data enters and exits through RXD

2. TXD outputs the clock

3. 8 bits are transmitted / received

4. The baud rate is fixed at (1/12) of the oscillator frequency

570



1. Serial data enters through RXD

2. Serial data exits through TXD

3. On receive, the stop bit goes into RB8 in SCON

4. 10 bits are transmitted / received1. Start bit (0)

2. Data bits (8)

3. Stop Bit (1)

5. Baud rate is determined by the Timer 1 over flow rate.


1. Serial data enters through RXD

2. Serial data exits through TXD

3. On receive, the stop bit goes into RB8 in SCON

4. 10 bits are transmitted / received1. Start bit (0)

2. Data bits (8)

3. Stop Bit (1)

5. Baud rate is determined by the Timer 1 over flow rate.

571



1. Serial data enters through RXD2. Serial data exits through TXD3. 9th data bit (TB8) can be assign value 0 or 14. On receive, the 9th data bit goes into RB8 in SCON5. 11 bits are transmitted / received

1.Start bit (0)2.Data bits (9)3.Stop Bit (1)

6. Baud rate is programmable




6. Baud rate is programmable

572





6. Baud rate is determined by Timer 1 overflow rate.




6. Baud rate is determined by Timer 1 overflow rate.

573

Programming Serial Data Transmission1. TMOD register is loaded with the value 20H, indicating the use of timer

1 in mode 2 (8-bit auto-reload) to set baud rate.

2. The TH1 is loaded with one of the values to set baud rate for serial datatransfer.

3. The SCON register is loaded with the value 50H, indicating serial mode1, where an 8- bit data is framed with start and stop bits.

4. TR1 is set to 1 to start timer 1

5. TI is cleared by CLR TI instruction

6. The character byte to be transferred serially is written into SBUFregister.

7. The TI flag bit is monitored with the use of instruction JNB TI, xx to seeif the character has been transferred completely.

8. To transfer the next byte, go to step 5

1. TMOD register is loaded with the value 20H, indicating the use of timer1 in mode 2 (8-bit auto-reload) to set baud rate.

2. The TH1 is loaded with one of the values to set baud rate for serial datatransfer.

3. The SCON register is loaded with the value 50H, indicating serial mode1, where an 8- bit data is framed with start and stop bits.


5. TI is cleared by CLR TI instruction

6. The character byte to be transferred serially is written into SBUFregister.

7. The TI flag bit is monitored with the use of instruction JNB TI, xx to seeif the character has been transferred completely.

8. To transfer the next byte, go to step 5574

Programming Serial Data Reception1. TMOD register is loaded with the value 20H, indicating the use of timer 1

in mode 2 (8-bit auto-reload) to set baud rate.

2. TH1 is loaded to set baud rate

3. The SCON register is loaded with the value 50H, indicating serial mode 1,where an 8- bit data is framed with start and stop bits.


5. RI is cleared by CLR RI instruction

6. The RI flag bit is monitored with the use of instruction JNB RI, xx to see ifan entire character has been received yet

7. When RI is raised, SBUF has the byte, its contents are moved into a safeplace.

8. To receive the next character, go to step 5.

1. TMOD register is loaded with the value 20H, indicating the use of timer 1in mode 2 (8-bit auto-reload) to set baud rate.

2. TH1 is loaded to set baud rate

3. The SCON register is loaded with the value 50H, indicating serial mode 1,where an 8- bit data is framed with start and stop bits.


5. RI is cleared by CLR RI instruction

6. The RI flag bit is monitored with the use of instruction JNB RI, xx to see ifan entire character has been received yet

7. When RI is raised, SBUF has the byte, its contents are moved into a safeplace.

8. To receive the next character, go to step 5.

575

Doubling Baud Rate

• There are two ways to increase the baud rate of datatransfer1. By using a higher frequency crystal2. By changing a bit in the PCON register

• PCON register is an 8-bit register.

• There are two ways to increase the baud rate of datatransfer1. By using a higher frequency crystal2. By changing a bit in the PCON register

• PCON register is an 8-bit register.

•When 8051 is powered up, SMOD is zero

•We can set it to high by software and thereby double the baud rate.

576

Doubling Baud Rate (cont…)

577

8051Interrupts

8051Interrupts

578

INTERRUPTS

• An interrupt is an external or internal event thatinterrupts the microcontroller to inform it that a deviceneeds its service

• A single microcontroller can serve several devices by twoways:

1. Interrupt2. Polling

• An interrupt is an external or internal event thatinterrupts the microcontroller to inform it that a deviceneeds its service

• A single microcontroller can serve several devices by twoways:

1. Interrupt2. Polling

579

Interrupt Vs Polling1. Interrupts

– Whenever any device needs its service, the device notifies themicrocontroller by sending it an interrupt signal.

– Upon receiving an interrupt signal, the microcontrollerinterrupts whatever it is doing and serves the device.

– The program which is associated with the interrupt is called theinterrupt service routine (ISR) or interrupt handler.

2. Polling– The microcontroller continuously monitors the status of a

given device.– When the conditions met, it performs the service.– After that, it moves on to monitor the next device until every

one is serviced.

1. Interrupts– Whenever any device needs its service, the device notifies the

microcontroller by sending it an interrupt signal.– Upon receiving an interrupt signal, the microcontroller

interrupts whatever it is doing and serves the device.– The program which is associated with the interrupt is called the

interrupt service routine (ISR) or interrupt handler.

2. Polling– The microcontroller continuously monitors the status of a

given device.– When the conditions met, it performs the service.– After that, it moves on to monitor the next device until every

one is serviced.580

Interrupt Vs Polling• The polling method is not efficient, since it wastes much of

the microcontroller’s time by polling devices that do notneed service.

• The advantage of interrupts is that the microcontroller canserve many devices (not all at the same time).

• Each devices can get the attention of the microcontrollerbased on the assigned priority.

• For the polling method, it is not possible to assign prioritysince it checks all devices in a round-robin fashion.

• The microcontroller can also ignore (mask) a device requestfor service in Interrupt.

• The polling method is not efficient, since it wastes much ofthe microcontroller’s time by polling devices that do notneed service.

• The advantage of interrupts is that the microcontroller canserve many devices (not all at the same time).

• Each devices can get the attention of the microcontrollerbased on the assigned priority.

• For the polling method, it is not possible to assign prioritysince it checks all devices in a round-robin fashion.

• The microcontroller can also ignore (mask) a device requestfor service in Interrupt.

581

Steps in Executing an Interrupt1. It finishes the instruction it is executing and saves the address of

the next instruction (PC) on the stack.

2. It also saves the current status of all the interrupts internally (i.e:not on the stack).

3. It jumps to a fixed location in memory, called the interruptvector table, that holds the address of the ISR.

4. The microcontroller gets the address of the ISR from theinterrupt vector table and jumps to it.

5. It starts to execute the interrupt service subroutine until itreaches the last instruction of the subroutine which is RETI(return from interrupt).

6. Upon executing the RETI instruction, the microcontroller returnsto the place where it was interrupted.

1. It finishes the instruction it is executing and saves the address ofthe next instruction (PC) on the stack.

2. It also saves the current status of all the interrupts internally (i.e:not on the stack).

3. It jumps to a fixed location in memory, called the interruptvector table, that holds the address of the ISR.

4. The microcontroller gets the address of the ISR from theinterrupt vector table and jumps to it.

5. It starts to execute the interrupt service subroutine until itreaches the last instruction of the subroutine which is RETI(return from interrupt).

6. Upon executing the RETI instruction, the microcontroller returnsto the place where it was interrupted.

582

Six Interrupts in 8051

Six interrupts are allocated as follows:

1. Reset – power-up reset.

2. Two interrupts are set aside for the timers.– one for timer 0 and one for timer 1

3. Two interrupts are set aside for hardware externalinterrupts.– P3.2 and P3.3 are for the external hardware interrupts INT0

(or EX1), and INT1 (or EX2)

4. Serial communication has a single interrupt thatbelongs to both receive and transfer.

Six interrupts are allocated as follows:

1. Reset – power-up reset.

2. Two interrupts are set aside for the timers.– one for timer 0 and one for timer 1

3. Two interrupts are set aside for hardware externalinterrupts.– P3.2 and P3.3 are for the external hardware interrupts INT0

(or EX1), and INT1 (or EX2)

4. Serial communication has a single interrupt thatbelongs to both receive and transfer.

583

What events can trigger Interrupts?

• We can configure the 8051 so that any of the followingevents will cause an interrupt:

– Timer 0 Overflow.– Timer 1 Overflow.– Reception/Transmission of Serial Character.– External Event 0.– External Event 1.

• We can configure the 8051 so that when Timer 0Overflows or when a character is sent/received, theappropriate interrupt handler routines are called.

• We can configure the 8051 so that any of the followingevents will cause an interrupt:

– Timer 0 Overflow.– Timer 1 Overflow.– Reception/Transmission of Serial Character.– External Event 0.– External Event 1.

• We can configure the 8051 so that when Timer 0Overflows or when a character is sent/received, theappropriate interrupt handler routines are called.

584

8051 Interrupt Vectors

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode 585

8051 Interrupt related Registers

• The various registers associated with the use ofinterrupts are:

– TCON - Edge and Type bits for External Interrupts 0/1

– SCON - RI and TI interrupt flags for RS232

– IE - Enable interrupt sources

– IP - Specify priority of interrupts

• The various registers associated with the use ofinterrupts are:

– TCON - Edge and Type bits for External Interrupts 0/1

– SCON - RI and TI interrupt flags for RS232

– IE - Enable interrupt sources

– IP - Specify priority of interrupts

586

Enabling and Disabling an Interrupt

• Upon reset, all interrupts are disabled (masked),meaning that none will be responded to by themicrocontroller if they are activated.

• The interrupts must be enabled by software in order forthe microcontroller to respond to them.

• There is a register called IE (interrupt enable) that isresponsible for enabling (unmasking) and disabling(masking) the interrupts.

• Upon reset, all interrupts are disabled (masked),meaning that none will be responded to by themicrocontroller if they are activated.

• The interrupts must be enabled by software in order forthe microcontroller to respond to them.

• There is a register called IE (interrupt enable) that isresponsible for enabling (unmasking) and disabling(masking) the interrupts.

587

Interrupt Enable (IE) Register

• EA : Global enable/disable.

• --- : Reserved for additional interrupt hardware.

• ES : Enable Serial port interrupt.

• ET1 : Enable Timer 1 control bit.

• EX1 : Enable External 1 interrupt.



--

• EA : Global enable/disable.

• --- : Reserved for additional interrupt hardware.

• ES : Enable Serial port interrupt.





MOV IE,#08hor

SETB ET1

588

Enabling and Disabling an Interrupt• Example: Show the instructions to (a) enable the serial interrupt,

timer 0 interrupt, and external hardware interrupt 1 and (b)disable (mask) the timer 0 interrupt, then (c) show how to disableall the interrupts with a single instruction.

• Solution:

– (a) MOV IE,#10010110B ;enable serial, timer 0, EX1• Another way to perform the same manipulation is:

– SETB IE.7 ;EA=1, global enable– SETB IE.4 ;enable serial interrupt– SETB IE.1 ;enable Timer 0 interrupt– SETB IE.2 ;enable EX1

– (b) CLR IE.1 ;mask (disable) timer 0 interrupt only

– (c) CLR IE.7 ;disable all interrupts

• Example: Show the instructions to (a) enable the serial interrupt,timer 0 interrupt, and external hardware interrupt 1 and (b)disable (mask) the timer 0 interrupt, then (c) show how to disableall the interrupts with a single instruction.

• Solution:

– (a) MOV IE,#10010110B ;enable serial, timer 0, EX1• Another way to perform the same manipulation is:

– SETB IE.7 ;EA=1, global enable– SETB IE.4 ;enable serial interrupt– SETB IE.1 ;enable Timer 0 interrupt– SETB IE.2 ;enable EX1

– (b) CLR IE.1 ;mask (disable) timer 0 interrupt only

– (c) CLR IE.7 ;disable all interrupts589

Interrupt Priority• When the 8051 is powered up, the priorities are assigned according

to the following.

• In reality, the priority scheme is nothing but an internal pollingsequence in which the 8051 polls the interrupts in the sequencelisted and responds accordingly.

• When the 8051 is powered up, the priorities are assigned accordingto the following.

• In reality, the priority scheme is nothing but an internal pollingsequence in which the 8051 polls the interrupts in the sequencelisted and responds accordingly.

590

Interrupt Priority• We can alter the sequence of interrupt priority by assigning a

higher priority to any one of the interrupts by programming aregister called IP (interrupt priority).

• To give a higher priority to any of the interrupts, we make thecorresponding bit in the IP register high.

591

Interrupt Priority (IP) Register

PS PT1 PX1 PT0 PX0Reserved

Serial Port

Timer 1 Pin

INT 1 Pin Timer 0 Pin

INT 0 Pin

Priority bit=1 assigns high priorityPriority bit=0 assigns low priority

592

KEYBOARDKEYBOARDINTERFACINGINTERFACING

593

KEYBOARDKEYBOARDINTERFACINGINTERFACING

KEYBOARD INTERFACING• Keyboards are organized in a matrix of rows

and columnsThe CPU accesses both rows and columns

through ports .• Therefore, with two 8-bit ports, an 8 x 8

matrix of keys can be connected to amicroprocessor

When a key is pressed, a row and acolumn make a contact

• Keyboards are organized in a matrix of rowsand columnsThe CPU accesses both rows and columns

through ports .• Therefore, with two 8-bit ports, an 8 x 8

matrix of keys can be connected to amicroprocessor

When a key is pressed, a row and acolumn make a contact

594

• Otherwise, there is no connectionbetween rows and columns

• In IBM PC keyboards, a singlemicrocontroller takes care of hardwareand software interfacing

• A 4x4 matrix connected to two portsThe rows are connected to an

output port and the columns areconnected to an input port

• Otherwise, there is no connectionbetween rows and columns

• In IBM PC keyboards, a singlemicrocontroller takes care of hardwareand software interfacing

• A 4x4 matrix connected to two portsThe rows are connected to an

output port and the columns areconnected to an input port

595

4x4 matrix

596

597

598

• Identify the row and column of the pressed keyfor each of the following.

(a) D3 – D0 = 1110 for the row, D3 – D0 = 1011for the column

(b) D3 – D0 = 1101 for the row, D3 – D0 = 0111for the column

Solution:(a) The row belongs to D0 and the column

belongs to D2; therefore, key number 2 waspressed.

(b) The row belongs to D1 and the columnbelongs to D3; therefore, key number 7 waspressed.

• Identify the row and column of the pressed keyfor each of the following.

(a) D3 – D0 = 1110 for the row, D3 – D0 = 1011for the column

(b) D3 – D0 = 1101 for the row, D3 – D0 = 0111for the column

Solution:(a) The row belongs to D0 and the column

belongs to D2; therefore, key number 2 waspressed.

(b) The row belongs to D1 and the columnbelongs to D3; therefore, key number 7 waspressed.

599

600

601

Stepper MotorInterfacing

Stepper MotorInterfacing

602

Stepper Motor Interfacing

• Stepper motor is a widely used device thattranslates electrical pulses into mechanical movement.

• Stepper motor is used in applications such as; diskdrives, dot matrix printer, robotics etc

• It has a permanent magnet rotor called the shaft whichis surrounded by a stator. Commonly used steppermotors have four stator windings

• Such motors are called as four-phase or unipolar steppermotor.

• Stepper motor is a widely used device thattranslates electrical pulses into mechanical movement.

• Stepper motor is used in applications such as; diskdrives, dot matrix printer, robotics etc

• It has a permanent magnet rotor called the shaft whichis surrounded by a stator. Commonly used steppermotors have four stator windings

• Such motors are called as four-phase or unipolar steppermotor.

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Step angle:

• Step angle is defined as the minimum degree of rotationwith a single step.

• No of steps per revolution = 360° / step angle• Steps per second = (rpm x steps per revolution) / 60• Example: step angle = 2°• No of steps per revolution = 180

• Step angle is defined as the minimum degree of rotationwith a single step.

• No of steps per revolution = 360° / step angle• Steps per second = (rpm x steps per revolution) / 60• Example: step angle = 2°• No of steps per revolution = 180

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A switch is connected to pin P2.7. Write an ALP to monitor the status ofthe SW. If SW = 0, motor moves clockwise and if SW = 1, motormoves anticlockwise

SETB P2.7 MOV A, #66H MOV P1,A TURN: JNB P2.7, CW RL A ACALL DELAY MOV P1,A SJMP TURN CW: RR A ACALL DELAY MOV P1,A SJMP TURN

SETB P2.7 MOV A, #66H MOV P1,A TURN: JNB P2.7, CW RL A ACALL DELAY MOV P1,A SJMP TURN CW: RR A ACALL DELAY MOV P1,A SJMP TURN607

Full step

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LCD Interfacing{before discussed in Unit 3 LCD

interfacing using 8086}

LCD Interfacing{before discussed in Unit 3 LCD


Slide number 127,128 inUnit 3

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Already discussed in UNIT 3 also

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HARDWARE CONFIGURATION OF LCDWITH 8051/8086/8085

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LCD INTERFACING WITH 8051 TRAINER KIT GPIO- I (8255) J1 Connector

PORTS ADDRESSControl port 4003PORT A 4000PORT B 4001PORT C 4002


Control port 4003PORT A 4000PORT B 4001PORT C 4002

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A/D Interfacing{before discussed in Unit 3 A/D


A/D Interfacing{before discussed in Unit 3 A/D


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Interfacing ADC to 8051ADC0804 is an 8 bit successive approximation analogue to digital

converter from National semiconductors. The features of ADC0804are differential analogue voltage inputs, 0-5V input voltage range, no zeroadjustment, built in clock generator, reference voltage can be externallyadjusted to convert smaller analogue voltage span to 8 bit resolution etc.

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Steps for converting the analogue input and reading theoutput from ADC0804

• Make CS=0 and send a low to high pulse to WR pin tostart the conversion.

• Now keep checking the INTR pin. INTR will be 1 ifconversion is not finished and INTR will be 0 ifconversion is finished.

• If conversion is not finished (INTR=1) , poll until it isfinished.

• If conversion is finished (INTR=0), go to the next step.• Make CS=0 and send a high to low pulse to RD pin to

read the data from the ADC.

• Make CS=0 and send a low to high pulse to WR pin tostart the conversion.

• Now keep checking the INTR pin. INTR will be 1 ifconversion is not finished and INTR will be 0 ifconversion is finished.

• If conversion is not finished (INTR=1) , poll until it isfinished.

• If conversion is finished (INTR=0), go to the next step.• Make CS=0 and send a high to low pulse to RD pin to

read the data from the ADC.616

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The circuit initiates the ADC to convert a given analogue input ,then accepts the corresponding digital data and displays it on theLED array connected at P0. For example, if the analogue inputvoltage Vin is 5V then all LEDs will glow indicating 11111111 inbinary which is the equivalent of 255 in decimal. AT89s51 is themicrocontroller used here. Data out pins (D0 to D7) of theADC0804 are connected to the port pins P1.0 to P1.7 respectively.LEDs D1 to D8 are connected to the port pins P0.0 to P0.7respectively. Resistors R1 to R8 are current limiting resistors. Insimple words P1 of the microcontroller is the input port and P0 isthe output port. Control signals for the ADC (INTR, WR, RD and CS)are available at port pins P3.4 to P3.7 respectively. Resistor R9 andcapacitor C1 are associated with the internal clock circuitry of theADC. Preset resistor R10 forms a voltage divider which can be usedto apply a particular input analogue voltage to the ADC. Pushbutton S1, resistor R11 and capacitor C4 forms a debouncing resetmechanism. Crystal X1 and capacitors C2,C3 are associated with theclock circuitry of the microcontroller.

The circuit initiates the ADC to convert a given analogue input ,then accepts the corresponding digital data and displays it on theLED array connected at P0. For example, if the analogue inputvoltage Vin is 5V then all LEDs will glow indicating 11111111 inbinary which is the equivalent of 255 in decimal. AT89s51 is themicrocontroller used here. Data out pins (D0 to D7) of theADC0804 are connected to the port pins P1.0 to P1.7 respectively.LEDs D1 to D8 are connected to the port pins P0.0 to P0.7respectively. Resistors R1 to R8 are current limiting resistors. Insimple words P1 of the microcontroller is the input port and P0 isthe output port. Control signals for the ADC (INTR, WR, RD and CS)are available at port pins P3.4 to P3.7 respectively. Resistor R9 andcapacitor C1 are associated with the internal clock circuitry of theADC. Preset resistor R10 forms a voltage divider which can be usedto apply a particular input analogue voltage to the ADC. Pushbutton S1, resistor R11 and capacitor C4 forms a debouncing resetmechanism. Crystal X1 and capacitors C2,C3 are associated with theclock circuitry of the microcontroller.

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Program:MOV P1,#11111111B // initiates P1 as the input port

MAIN: CLR P3.7 // makes CS=0SETB P3.6 // makes RD highCLR P3.5 // makes WR lowSETB P3.5 // low to high pulse to WR for starting

conversionWAIT: JB P3.4,WAIT // polls until INTR=0

CLR P3.7 // ensures CS=0CLR P3.6 // high to low pulse to RD for reading the

data from ADCMOV A,P1 // moves the digital data to accumulatorCPL A // complements the digital dataMOV P0,A // outputs the data to P0 for the LEDsSJMP MAIN // jumps back to the MAIN program END

Program:MOV P1,#11111111B // initiates P1 as the input port

MAIN: CLR P3.7 // makes CS=0SETB P3.6 // makes RD highCLR P3.5 // makes WR lowSETB P3.5 // low to high pulse to WR for starting

conversionWAIT: JB P3.4,WAIT // polls until INTR=0

CLR P3.7 // ensures CS=0CLR P3.6 // high to low pulse to RD for reading the

data from ADCMOV A,P1 // moves the digital data to accumulatorCPL A // complements the digital dataMOV P0,A // outputs the data to P0 for the LEDsSJMP MAIN // jumps back to the MAIN program END


D/A Interfacing{before discussed in Unit 3 D/A


D/A Interfacing{before discussed in Unit 3 D/A


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Digital-to-analog (DAC) converter

• The digital-to-analog converter (DAC) is a device widely used to convertdigital pulses to analog signals.Two methods of creating a DAC:

Binary weighted and R/2R ladder.The vast majority of integrated circuit DACs, including the MC1408

(DAC0808) used in this section, use the R/2R method since it can achieve amuch higher degree of precision. The first criterion for judging a DAC is itsresolution, which is a function of the number of binary inputs. Thecommon ones are 8, 10, and 12 bits. The number of data bit inputsdecides the resolution of the DAC since the number of analog outputlevels is equal to 2″, where n is the number of data bit inputs. Therefore,an 8-input DAC such as the DAC0808 provides 256 discrete voltage (orcurrent) levels of output.

Similarly, the 12-bit DAC provides 4096 discrete voltage levels. Thereare also 16-bit DACs, but they are more expensive.

• The digital-to-analog converter (DAC) is a device widely used to convertdigital pulses to analog signals.Two methods of creating a DAC:

Binary weighted and R/2R ladder.The vast majority of integrated circuit DACs, including the MC1408

(DAC0808) used in this section, use the R/2R method since it can achieve amuch higher degree of precision. The first criterion for judging a DAC is itsresolution, which is a function of the number of binary inputs. Thecommon ones are 8, 10, and 12 bits. The number of data bit inputsdecides the resolution of the DAC since the number of analog outputlevels is equal to 2″, where n is the number of data bit inputs. Therefore,an 8-input DAC such as the DAC0808 provides 256 discrete voltage (orcurrent) levels of output.

Similarly, the 12-bit DAC provides 4096 discrete voltage levels. Thereare also 16-bit DACs, but they are more expensive.

621

8051 Connection to DAC808

622

program to send data to the DAC togenerate a stair-step ramp

623

SENSORINTERFACING

SENSORINTERFACING

take temperature sensor for example

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625

626

EXTERNALMEMORY

INTERFACING

EXTERNALMEMORY

INTERFACING627

Access to External Memory• Port 0 acts as a multiplexed address/data bus. Sending

the low byte of the program counter (PCL) as anaddress.

• Port 2 sends the program counter high byte (PCH)directly to the external memory.

• The signal ALE operates as in the 8051 to allow anexternal latch to store the PCL byte while the multiplexedbus is made ready to receive the code byte from theexternal memory.

• Port 0 then switches function and becomes the data busreceiving the byte from memory.

• Port 0 acts as a multiplexed address/data bus. Sendingthe low byte of the program counter (PCL) as anaddress.

• Port 2 sends the program counter high byte (PCH)directly to the external memory.

• The signal ALE operates as in the 8051 to allow anexternal latch to store the PCL byte while the multiplexedbus is made ready to receive the code byte from theexternal memory.

• Port 0 then switches function and becomes the data busreceiving the byte from memory.

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Books References Mohamed Ali Mazidi, Janice Gillispie Mazidi, Rolin McKinlay,

“The 8051 Microcontroller and Embedded Systems: UsingAssembly and C” Programming and Interfacing the 8051 Microcontroller by

SencerYeralan ,Ashutosh Ahluwalia The 8051 Microcontroller by by I. Scott MacKenzie Programming & Customizing the 8051 Microcontroller by

Michael Predko Microcontrollers by RajKamal

Mohamed Ali Mazidi, Janice Gillispie Mazidi, Rolin McKinlay,“The 8051 Microcontroller and Embedded Systems: UsingAssembly and C” Programming and Interfacing the 8051 Microcontroller by

SencerYeralan ,Ashutosh Ahluwalia The 8051 Microcontroller by by I. Scott MacKenzie Programming & Customizing the 8051 Microcontroller by

Michael Predko Microcontrollers by RajKamal

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Documents References• 8051 microcontroller by Suresh P. Nair[ME, (PhD)] MIEEE Professor&Head Department of Electronics and

Communication Engineering Royal College of Engineering and Technology• 8051 Microcontroller by Dr. M. Gopikrishna ,Assistant Professor of Physics,Maharajas College ,Ernakulam• 8051 Microcontroller By Er. Swapnil Kaware• 8051 MICROCONTROLLER by Prathyusha Institute of Technology & Management in Education• 8051 MICROCONTROLLER by Prathyusha Institute of Technology & Management in Education• www.pantechsolutions.net/• Embedded systems, 8051 microcontroller by Amandeep Alag in Education• 8051 microcontroller features by Tech_MX in Technology• 8051 microcontroller by Gaurav Verma in Engineering• 8051 (microcontroller)class1 by Nitin Ahire in Education• 8051 microcontroller by Bibek Kattel in Education• 8051 microcontroller by Jhemi22 in Education• 8051 microcontrollers by Chih-Hsiang Tang in Technology• Embedded systems, 8051 microcontroller by Amandeep Alag• Embedded C programming based on 8051 microcontroller by Gaurav Verma• Microcontroller 8051 features & application• MICROCONTROLLER-8051 Features & Applications Dr. Y .Narasimha Murthy Ph.D., Sri Saibaba National

College• 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar & Cutajar• Intel microprocessor history by Ramzi_Alqrainy

• 8051 microcontroller by Suresh P. Nair[ME, (PhD)] MIEEE Professor&Head Department of Electronics andCommunication Engineering Royal College of Engineering and Technology

• 8051 Microcontroller by Dr. M. Gopikrishna ,Assistant Professor of Physics,Maharajas College ,Ernakulam• 8051 Microcontroller By Er. Swapnil Kaware• 8051 MICROCONTROLLER by Prathyusha Institute of Technology & Management in Education• 8051 MICROCONTROLLER by Prathyusha Institute of Technology & Management in Education• www.pantechsolutions.net/• Embedded systems, 8051 microcontroller by Amandeep Alag in Education• 8051 microcontroller features by Tech_MX in Technology• 8051 microcontroller by Gaurav Verma in Engineering• 8051 (microcontroller)class1 by Nitin Ahire in Education• 8051 microcontroller by Bibek Kattel in Education• 8051 microcontroller by Jhemi22 in Education• 8051 microcontrollers by Chih-Hsiang Tang in Technology• Embedded systems, 8051 microcontroller by Amandeep Alag• Embedded C programming based on 8051 microcontroller by Gaurav Verma• Microcontroller 8051 features & application• MICROCONTROLLER-8051 Features & Applications Dr. Y .Narasimha Murthy Ph.D., Sri Saibaba National

College• 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar & Cutajar• Intel microprocessor history by Ramzi_Alqrainy 631

Website Referenceshttp://amcmp.blogspot.in/2012/06/8051-micro-controller.htmlhttp://www.mikroe.com/chapters/view/65/chapter-2-8051-microcontroller-architecture/https://www.pantechsolutions.net/project-kits/user-guide-for-lcd-interface-card LCD DIsplay

http://www.slideshare.net/pantechsolutions/interfacing-stepper-motor-with-8051 stepper motor

https://www.pantechsolutions.net/microcontroller-boards/adc-0809-interfacing-with-8086-ps2-lab-kit ADC interface

https://www.pantechsolutions.net/microcontroller-boards/dac-0800-interfacing-with-8086-ps2-lab-kit DAC interface

https://www.pantechsolutions.net/microcontroller-boards/led-interfacing-with-8086-ps2-lab-kit LED Interface• www.vtulearning.com• www.eazynotes.com• www.slideshare.net• www.scribd.com• www.docstoc.com• www.slideworld.com• www.nptel.ac.in• http://opencourses.emu.edu.tr/• http://engineeringppt.blogspot.in/• http://www.pptsearchengine.net/• www.4shared.com• http://8085projects.info/

http://amcmp.blogspot.in/2012/06/8051-micro-controller.htmlhttp://www.mikroe.com/chapters/view/65/chapter-2-8051-microcontroller-architecture/https://www.pantechsolutions.net/project-kits/user-guide-for-lcd-interface-card LCD DIsplay

http://www.slideshare.net/pantechsolutions/interfacing-stepper-motor-with-8051 stepper motor

https://www.pantechsolutions.net/microcontroller-boards/adc-0809-interfacing-with-8086-ps2-lab-kit ADC interface

https://www.pantechsolutions.net/microcontroller-boards/dac-0800-interfacing-with-8086-ps2-lab-kit DAC interface

https://www.pantechsolutions.net/microcontroller-boards/led-interfacing-with-8086-ps2-lab-kit LED Interface• www.vtulearning.com• www.eazynotes.com• www.slideshare.net• www.scribd.com• www.docstoc.com• www.slideworld.com• www.nptel.ac.in• http://opencourses.emu.edu.tr/• http://engineeringppt.blogspot.in/• http://www.pptsearchengine.net/• www.4shared.com• http://8085projects.info/

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