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LABORATORY MANUAL EC792-VLSI Design Lab DEPERTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING FACULTY OF ENGINEERING & TECHNOLOGY IEM, KOLKATA-700091
LABORATORY MANUAL
EC792-VLSI Design Lab
DEPERTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING FACULTY OF ENGINEERING & TECHNOLOGY
IEM, KOLKATA-700091
LIST OF EXPERIMENTS
Sl.No. Name of Experiments Page.No. Introduction of VHDL 1 Steps to implement the design(Peak VHDL)
2 ASSIGNMENT-1
3 1) Design and simulate 2input OR gate by dataflow architecture style
using PECK-VHDL environment.
4 2) Design and simulate 2 Input AND gate by dataflow architecture style
using VHDL environment.
5 3) Design and simulate 2 input XOR gate by dataflow architecture style
using VHDL environment.
6 4) Design and simulate a NOT gate by dataflow architecture style using VHDL environment.
7 5)Design and simulate a 2 input NAND gate by dataflow architecture
style using VHDL environment.
8 6) Design and simulate a 2 input NOR gate by dataflow architecture style
using VHDL environment
9 7) Design and simulate y=a’+cd by dataflow architecture style using
VHDL environment.
10 ASSIGNMENT 2
11 1)Design and simulate 3 INPUT OR GATE by Structural architecture style using VHDL environment.
12 2) Design and simulate 2 INPUT XOR GATE GATE by Structural architecture style using VHDL environment.
13 3) Design and simulate f=ab+cd GATE by Structural architecture style using VHDL environment.
14 4) Design and simulate y=acd+b BY by Structural architecture style using VHDL environment.
15 5) Design and simulate HALF ADDER by Structural architecture
style using VHDL environment.
16 Steps to implement the design
17 Write VHDL code for basic gates: AND, OR, NOT (USING XILINX SOFTWARE)
18 Write VHDL code for universal logic gates: NAND, NOR and XOR, XNOR gates using basic gates
19 Write VHDL code for Multiplexer.
20 Write VHDL code for Full adder, Half Adder, Full Substractor, Half Substractor,
Introduction to VHDL
It is a hardware description language that can be used to model a digital system at many levels
of abstraction ranging from the algorithmic level to the gate level. The system may be a single
gate to a complete digital electronic system.
VHDL is a hardware description language used in electronic design automation to describe
digital and mixed-signal system such as field-programmable gate arrays and integrated circuits.
VHDL can also be used as a general purpose parallel programming language.
It can be considered a combination of following languages as:
a) Sequential language
b) Concurrent language
c) Net list language
d) Timing language
e) Waveform Generation language
Need of VHDL
The requirement for it was generated in 1981 under VHSIC program. In this program a number
of US companies were involved in designing VHSIC chips for DoD (defense department).
Most of the companies were using different hardware description to describe and develop their
IC, as a result different vendors could not efficiently exchange designing with one another.
Also they were provided DoD, descriptions of their chips in different hardware description
language. Reuse was also an issue, thus a need for a standard language for design and
documentation of the digital system was generated.
Capabilities of VHDL
1. It is used as an exchange medium between different chip vendors and CAD tool users.
2. It can be used for communication medium between different CAD and CAE tools.
3. Digital system can be modeled a set of interconnected components. Each component in turn
van be modeled a s set of interconnected components further.
4. It supports flexible design methodologies: Top-down Bottom-up mixed
5. It is not technology specific but it is capable of supported technology specific features.
6. It supports both synchronous and asynchronous timing modules.
7. It is an IEEE and ANSI standard.
8. It supports three basic different description styles.
9. It supports a wide range of abstraction levels ranging from abstract behavioral.
10. It has element that make large scale design modeling easier such as components, functions
and procedure and package.
11. It is publically available, human readable and above all, it is not proprietary.
Package:
It provides convenient mechanism to store and share declarations that are common across
many design units standard package used-IEEE std_logic_1164. It is decided by IEEE and
ANSI.
Hardware abstraction:
VHDL is used to describe a model for digital hardware device. This model specifies the
external view of device and one or more internal views. The internal views of the device
specify the functionality or the structure while the external vies specifies the interface of
device through which it communicate with other modes in environment. Figure 1.1 shows
hardware device and corresponding software of the device.
In VHDL each device model is treated as a distinct representation of unique device, called an
entity. Figure 1.2, shows VHDL view of hardware device that has multiple device models,
with each device model representing an entity. Each entity is described using one model,
which contains one external view and one or more internal view.
VHDL provides 5 different primary constructs called the design units. They are-
1. Entity Declaration
2. Architecture Body
3. Configuration Declaration
4. Package Declaration
5. Package Body
1. Entity Declaration:
It describes the external view of entity.
Ex.-Input-output signal names
2. Architecture Body:
It contains internal description of entity.
Ex.- A set of inter connected components that represents the structure of entity or set of
concurrent or sequential statements that represent the behavior of entity.
3. Configuration Declaration:
It is used to create an entity; it specifies the binding of one architecture body from many
architecture bodies that may be associated with the entity. It may also specify the binding of
components used in selected architecture body to other entities. An entity may have number of
different configuration.
4. Package Declaration:
A package declaration is used to store a set of common declarations like components, types,
procedures, and functions. These declarations can then be imported into other design units
using a context clause.
5. Package Body:
A package body is primarily used to store the definitions of functions and procedures that were
declared in the corresponding package declaration, and also the complete constant declarations
for any deferred constants that appear in the package declaration. Therefore, a package body is
always associated with a package declaration.
Steps to implement the design (Peak VHDL)
Step 1: Start the Peak VHDL project navigator by double click on Peak VHDL icon
displayed over desktop.
Project Navigator window will open.
Step 2: In the project navigator window click on new Project Navigator->file->New
Project.
Within Project Navigator window a new window will open.
Step3: Now again go to File-> Select Project As
Step 4: Then Save As the Project in .acc extension.
Then Project will be saving in Project_name.acc extension.
Step 5: Again go to File-> New Module
Step 6: New Module-> Create Blank Module.
Step 7: File->Save As->Save the file in .vhd extension(File name should be same as your
entity name).
Step 8: Write the VHDL code for any gate or circuit.
Step 9: Repeat Step5,6,7 to create another blank module.
Step 9: Write VHDL code for Test Program.
Step 10: Click on “Rebuild Hierarchy”
Step 11: Select each file and compile accordingly To check wheather there is any error or
not present in the code.
Step 12: Link the Test Module for Simulation.
Step 14: Then click on Add All.
Step 15: Then click on Close.
Step 16: Click On “GO” Key.
Step 17: Analyze the waveform.
ASSIGNMENT-1
Q1: Design and simulate 2input OR gate by dataflow architecture style using
PECK-VHDL environment. BLOCK DIAGRAM:
PROGRAM CODE:
• Main Program:
entity ritu is port(a,b: in bit; y: out bit);
end entity; architecture dataflow of ritu is
begin y<=a or b; end architecture;
Test Program:
entity ritu1 is end entity; architecture mined of ritu1 is signal a1, b1, y1: bit; component ritu is port(a,b : in bit; y: out bit); end component; begin ritu port map(a1, b1, y1);
process begin a1<= ‘0’; b1<= ‘0’; wait for 30 ns; a1<= ‘1’;
b1<= ‘0’; wait for 30ns; a1<= ‘0’; b1<= ‘1’; wait for 30ns; a1<= ‘1’; b1<= ‘1’; wait for 30ns; end process; end architecture;
• OUTPUT:
TRUTH TABLE:
a b y
0 0 0
1 0 1
0 1 1
1 1 1
• DISCUSSION: A 2 input OR gate is designed and simulated in VHDL environment. It is
observed that the output graph exactly satisfies the theoretical truth table of OR gate.
Q2: Design and simulate 2 Input AND gate by dataflow architecture
style using VHDL environment.
• BLOCK DIAGRAM:
• PROGRAM CODE:
Main Program:
entity ritu_2 is port(a,b: in bit; y: out bit);
end entity; architecture dataflow of ritu_2
is begin y<=a and b; end
architecture;
Test Program:
entity ritu_3 is
end entity; architecture mixed of ritu_3
is signal a1, b1, y1: bit;
complement ritu_2 is
port(a,b: in bit; y: out bit);
end component; begin ritu_2 port map(a1, b1,
y1); process begin
a1<= ‘0’;
b1<= ‘0’; wait for 30 ns; a1<= ‘0’; b1<= ‘1’; wait for 30ns; a1<= ‘1’; b1<= ‘0’; wait for 30ns; a1<= ‘1’; b1<= ‘1’; wait for 30ns; end process; end architecture;
• OUTPUT:
• TRUTH TABLE:
a b y
0 0 0
0 1 0
1 0 0
1 1 1
• DISCUSSION: A 2 input AND gate is designed and simulated in VHDL environment. It is
observed that the output graph exactly satisfies the theoretical truth table of AND gate.
Q3: Design and simulate 2 input XOR gate by dataflow architecture
style using VHDL environment.
• BLOCK DIAGRAM:
• PROGRAM CODE:
Main Program:
entity ritu_4 is port(a,b: in bit; y: out bit);
end entity; architecture dataflow of ritu_4 is
begin y<=a xor b; end architecture;
Test Program:
entity ritu_5 is
end entity; architecture mixed of ritu_5 is
signal a1, b1, y1: bit;
complement ritu_4 is port(a,b:
in bit; y: out bit); end
component; begin ritu_4 port map(a1, b1, y1);
process
begin
a1<= ‘0’;
b1<= ‘0’; wait for 30 ns; a1<= ‘0’; b1<= ‘1’; wait
for 30ns; a1<= ‘1’; b1<= ‘0’; wait for 30ns; a1<= ‘1’; b1<= ‘1’; wait for 30ns; end process; end architecture;
• OUTPUT:
• TRUTH TABLE:
a b y
0 0 0
0 1 1
1 0 1
1 1 0
• DISCUSSION: A 2 input XOR gate is designed and simulated in VHDL environment.
It is observed that the output graph exactly satisfies the theoretical truth table of XOR
gate.
Q4: Design and simulate a NOT gate by dataflow architecture style using VHDL environment.
• BLOCK DIAGRAM:
a1 y1
• PROGRAM CODE: Main
Program:
entity ritu_6 is port(a,b: in bit; y: out bit); end
entity; architecture dataflow of ritu_6 is
begin y<=a not b; end architecture;
Test Program:
entity ritu_7 is end
entity; architecture mixed of ritu_7 is
signal a1, b1, y1: bit; complement
ritu_6 is port(a,b: in bit; y: out bit);
end component; begin ritu_6 port map(a1, b1, y1);
process begin a1<=
‘0’;
wait for 30 ns; a1<= ‘1’; wait for 30ns; end process; end architecture;
• Output
• TRUTH TABLE:
a y 0 1
1 0
• DISCUSSION: A NOT gate is designed and simulated in VHDL environment. It is
observed that the output graph exactly satisfies the theoretical truth table of NOT gate.
Q5: Design and simulate a 2 i/p NAND gate by dataflow architecture style
using VHDL environment.
• BLOCK DIAGRAM:
• PROGRAM CODE: Main Program:
entity ritu_8 is port(a,b: in bit; y: out bit);
end entity; architecture dataflow of ritu_8 is begin y<=a nand b; end architecture;
Test Program:
entity ritu_9 is
end entity; architecture mixed of ritu_9 is
signal a1, b1, y1: bit; complement ritu_8 is
port(a,b: in bit; y: out bit);
end component; begin ritu_8 port map(a1, b1, y1);
process begin
a1<= ‘0’;
b1<= ‘0’; wait for 30 ns; a1<= ‘0’; b1<= ‘1’; wait for 30ns; a1<= ‘1’; b1<= ‘0’; wait for 30ns; a1<= ‘1’; b1<= ‘1’; wait for 30ns; end process; end architecture;
• OUTPUT:
• TRUTH TABLE:
A b y 0 0 1
0 1 1
1 0 1
1 1 0
• DISCUSSION: A NAND gate is designed and simulated in VHDL environment. It is
observed that the output graph exactly satisfies the theoretical truth table of NAND gate.
Q6: Design and simulate a 2 input NOR gate by dataflow architecture style
using VHDL environment
• BLOCK DIAGRAM:
• PROGRAM CODE:
• Main Program:
entity ritu_10 is port(a,b: in bit; y: out bit); end entity; architecture dataflow of ritu_8 is begin y<=a nor b; end architecture;
Test Program: entity ritu_11 is
end entity; architecture mixed of ritu_11 is signal a1, b1, y1: bit; complement ritu_10 is port(a,b: in bit; y: out bit); end component; begin ritu_10 port map(a1, b1, y1); process begin a1<= ‘0’; b1<= ‘0’; wait for 30 ns; a1<= ‘0’; b1<= ‘1’; wait for 30ns; a1<= ‘1’; b1<= ‘0’; wait for 30ns; a1<= ‘1’; b1<= ‘1’; wait for 30ns; end process; end architecture;
• OUTPUT:
• TRUTH TABLE:
a b Y 0 0 1
1 0 0
0 1 0
1 1 0
• DISCUSSION: A NOR gate is designed and simulated in VHDL environment. It is
observed that the output graph exactly satisfies the theoretical truth table of NOR gate.
Q7: Design and simulate y=a’+cd by dataflow architecture style using
VHDL environment.
• BLOCK DIAGRAM: • PROGRAM CODE: Main Program: entity ritu_12 is port(a,c,d: in bit; y: out bit); end entity; architecture dataflow of ritu_12 is begin y<=((not a) or (c and d)); end architecture; Test Program: entity ritu_13 is end entity; architecture mixed of ritu_13 is signal a1, b1, y1: bit; complement ritu_12 is port(a,c,d: in bit; y: out bit); end component; begin ritu_12 port map(a1, c1, d1, y1); process begin a1<= ‘0’; c1<= ‘0’; d1<= ‘0’; wait for 30 ns; a1<= ‘0’; c1<= ‘0’; d1<= ‘1’; wait for 30ns; a1<= ‘0’; c1<= ‘1’; d1<= ‘0’;
wait for 30ns; a1<= ‘0’; c1<= ‘1’; d1<= ‘1’; wait for 30ns; a1<= ‘1’; c1<= ‘0’; d1<= ‘0’; wait for 30ns; a1<= ‘1’; c1<= ‘0’; d1<= ‘1’; wait for 30ns; a1<= ‘1’; c1<= ‘1’; d1<= ‘0’; wait for 30ns; a1<= ‘1’; c1<= ‘1’; d1<= ‘1’; wait for 30ns; end process; end architecture;
OUTPUT:
• TRUTH TABLE:
a c d y 0 0 0 1
0 0 1 1
0 1 0 1 0 1 1 1
1 0 0 0
1 0 1 0 1 1 0 0
1 1 1 1
• DISCUSSION: y=a’+cd is designed and simulated in VHDL environment. It is observed that the output graph of the given equation exactly satisfies the theoretical truth table.
ASSIGNMENT 2
Q1: DESIGN AND STIMULATE 3 INPUT OR GATE BY STRUCTURAL ARCHITECTURE
STYLE USING VHDL ENVIROMENT. BLOCK DIAGRAM: PROGRAM CODE: SUB MODULE entity sweet is pout(a,b:in bit;
f:out bit); end entity; architecture dataflow of sweet is begin y<=(a or b);
end architecture;
MAIN MODULE entity main_sweet is port(p,q,r:in
bit; f:out bit); end entity;
architecture structural of main_sweet is component sweet is port(a,b:in bit; f:out bit); end component; signal s:bit; begin sweet port map(p,q,s); sweet port map(s,r,f); end architecture; TEST MODULE entity test_sweet is end entity;
architecture mixed of test_sweet is signal p1,q1,r1,f1:bit; component main_sweet is port(p,q,r:in bit; f:out bit); end component; begin main_sweet port map(p1.q1,r1,f1); process begin p1<='0'; q1<='0'; r1<='0'; wait for 30ns; p1<='0'; q1<='0'; r1<='1'; wait for 30 ns; p1<='0'; q1<='1'; r1<='0'; wait for 30ns; p1<='0'; q1<='1'; r1<='1'; wait for 30 ns; p1<='1'; q1<='0'; r1<= '0'; wait for 30ns; p1<='1'; q1<='0'; r1<='1'; wait for 30 ns; p1<='1'; q1<='1'; r1<='0'; wait for 30ns; p1<='1'; q1<='1'; r1<='1'; wait for 30 ns; end process;
end architecture;
Output TRUTH TABLE:
p q r f
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
DISCUSSION: 3 input OR is designed and simulated by structural architecture style in VHDL. The output is taken and
it is observed that the output satisfies the theoretical truth table of the gate.
Q2: DESIGN AND SIMULATE 2 INPUT XOR GATE BY STRUCTURAL
ARCITECTURE STYLE. BLOCK DIAGRAM: PROGRAM CODE; SUBMODULE1 entity sweet_1 is pout(i,j:in bit; y:out bit); end entity; architecture dataflow of sweet_1 is begin y<=(i and j); end architecture;
SUBMODULE2 entity orsweet_1 is pout( p,q:in bit;
z:out bit);
end entity; architecture dataflow of orsweet_1 is begin z<=(p or q); end architecture;
MAIN MODULE entity main_sweet_1 is
port(a,b:in bit; f:out bit);
end entity; architecture structural of main_sweet_1 is
signal y1,y2:bit; component sweet_1 is
port(i,j:in bit; y:out bit);
end component;
component orsweet_1 is
port(p,q:in bit; y:out bit);
end component; begin sweet_1 port map((not a),b,y1);
sweet_1 port map(a,(not b),y2);
orsweet_1 port map(y1,y2,f);
end architecture;
TEST MODULE entity test_sweet_1 is
end entity: architecture mixed of test_sweet_1 is
signal a1,b1,f1:bit; component main_sweet_1 is
port(a,b:in bit : f:out bit);
end component:
begin main_sweet_1 port map(a1,b1,f1);
process begin
a1<=’0’;
b1<=’0’;
wait for 30ns;
a1<=’0’;
b1<=’1’;
wait for 30ns;
a1<=’1’;
b1<=’0’;
wait for 30ns;
a1<=’1’;
b1<=’1’;
wait for 30ns;
end process; end architecture;
OUTPUT: TRUTH TABLE;
A b f 0 0 0 0 1 1 1 0 1 1 1 0
DISCUSSION:
The output graph and the theoretical truth table of the 2 i/p XOR gate is equal and satisfies each
other.
Q3: DESIGN AND SIMULATE f=ab+cd BY STRUCTURAL ARCITECTURE STYLE. BLOCK DIAGRAM; PROGRAM CODE:
SUBMODULE1 entity sweet_2 is
pout(a,b:in bit; m:out
bit); end entity; architecture dataflow of sweet_2 is
begin m<=(a and b);
end architecture;
SUBMODULE2 entity orsweet_2 is
pout(i,j:in bit; k:outbit);
end entity;
architecture dataflow of orsweet_2 is
begin k<=(i or j); end architecture;
MAIN MODULE entity main_sweet_2 is
port(p,q,r,s:in bit; y:out bit);
end entity;
architecture structural of main_sweet_2 is
component sweet_2 is port(a,b:in bit; m:out bit);
end component;
component orsweet_2 is
port(i,j:in bit; k:out bit);
end component;
signal g,h:bit; begin sweet_2 port map(p,q,g);
sweet_2 port map(r,s,h);
orsweet_2 port map(g,h,y);
end architecture;
TEST MODULE
entity test_sweet_2 is
end entity;
architecture mixed of test_sweet_2 is
signal p1,q1,r1,s1,y1:bit;
component main_sweet_2 is
port(p,q,r,s:in bit; y:out bit);
end component;
begin
main_sweet_2 port map(p1,q1,r1,s1,y1);
process
begin
p1<='0';
q1<='0';
r1<='0';
s1<=’0’;
wait for 30ns;
p1<='0';
q1<='0';
r1<='0';
s1<=’1’;
wait for 30ns;
p1<='0';
q1<='0';
r1<='1';
s1<=’0’;
wait for 30 ns;
p1<='1';
q1<='1';
r1<='1';
s1<=’0’;
wait for 30ns;
p1<='1';
q1<='1';
r1<='1';
s1<=’1’;
wait for 30ns;
end process;
end architecture;
OUTPUT:
TRUTH TABLE:
a b c d f
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
DISCUSSION: The output graph and the theoretical truth table of the values are equal and satisfies the result.
Q4: DESIGN AND SIMULATE y=acd+b BY STRUCTURAL ARCITECTURE STYLE.
PROGRAM CODE:
SUBMODULE1 entity sweet_3 is pout(i,j:in bit; y:out bit); end entity; architecture dataflow of sweet_3 is begin y<=(i and j); end architecture; SUBMODULE2 entity orsweet_3 is pout(p,q:in bit; z:out bit);
end entity; architecture dataflow of orsweet_3 is begin z<=(p or q); end architecture;
MAIN MODULE entity main_sweet_3 is
port(a,b,c,d:in bit; f:out bit);
end entity;
architecture structural of main_sweet_3 is
signal y1,y2:bit; component sweet_3 is
port(i,j:in bit; z:out bit);
end component;
begin sweet_3 pout map(a,c,y1);
sweet_3 pout map(d,y1,y2);
orsweet_3 pout map(b,y2,f); end architecture;
TEST MODULE entity test_sweet_3 is end entity; architecture mixed of test_sweet_3 is signal a1,b1,c1,d1,f1:bit; component main_sweet_3 is pout(a,b,c,d:in bit; f:out bit); end component; begin main_sweet_3 port map(a1,b1,c1,d1,f1);
process begin a1<='0'; b1<='0'; c1<='0'; d1<=’0’;
wait for 30ns;
a1<='0';
b1<='0';
c1<='0';
d1<=’1’;
wait for 30ns;
a1<='0';
q1<='0';
c1<='1';
d1<=’0’;
wait for 30 ns; a1<='1'; b1<='1'; c1<='1'; d1<=’0’; wait for 30ns; a1<='1'; b1<='1'; c1<='1'; d1<=’1’; wait for 30ns; end process; end architecture; Output
TRUTH TABLE:
a b c d f
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
.Q5: DESIGN AND SIMULATE HALF ADDER BY STRUCTURAL
ARCITECTURE STYLE USING VHDL ENVIRONMENT. BLOCK DIAGRAM;
PROGRAM CODE: SUBMODULE1 entity sweet_4 is
port(a,b:in bit; s:out bit);
end entity; architecture dataflow of sweet_4 is begin
s<=(a xor b);
end architecture;
SUBMODULE2 entity asweet_4 is
port(p,q:in bit; c:out bit);
end entity;
architecture dataflow of asweet_4 is
begin
c<=(p orq);
end architecture;
MAIN MODULE entity main_sweet_4 is
port( x,y:in bit;
j,k:out bit);
end entity; architecture structural of main_sweet_4
is
component sweet_4 is
port(a,b:in bit; s:out bit);
end component;
component asweet_4 is
port(p,q:in bit;
c:out bit);
end component; begin sweet_4 port map(x,y,j);
asweet_4 pout map(x,y,j);
end architecture;
TEST MODULE entity test_sweet_4 is end entity; architecture mixed of test_sweet_4 is signal x1,y1,j1,k1:bit;
component main_sweet_4 is pout(x,y:in bit; j,k:out bit);
end component; begin main_sweet_4 port map(x1,y1,j1,k1); process begin x1<='0'; y1<='0'; wait for 30ns;
x1<='0';
y1<=’1’;
wait for 30ns;
x1<='1';
y1<=’0’;
wait for 30ns;
x1<='1';
y1<='1'; wait for 30ns;
end process;
end architecture;
Output:
TRUTH TABLE:
x y j k
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
DISCUSSION: A half adder is designed and simulated using structural architecture. The output generated
exactly satisfies the theoretical truth table of the adder given.
BLOCK DIAGRAM:
PROGRAM CODE: SUBMODULE1 entity sweet_5 is
pout(a,b:in bit; s,t:out bit);
end entity; architecture dataflow of sweet_5 is
begin s<=(a xor b);
t<=(a and b); end architecture;
SUBMODULE2 entity or_sweet_5 is
port(p,q:in bit; c:out
bit);
end entity;
architecture dataflow of or_sweet_5
is
begin c<=(p or q);
end
architecture;
MAIN MODULE entity main_sweet_5 is
port(x,y,z:in bit; j,k:out
bit);
end entity;
architecture structural of main_sweet_5
is
component sweet_5 is pout(a,b:in bit; s,t:out
bit);
end component;
component or_sweet_5 is
pout(p,q:in bit; c:out bit);
end component;
signal
m,n,o:bit;
begin
sweet_5 port map(y,z,m,n);
sweet_5 port map(x,m,j,o);
or_sweet_5 pout
map(o,n,k);
end architecture;
TEST MODULE entity test_sweet_5 is end entity; architecture mixed of test_sweet_5 is signal x1,y1,z1,j1,k1:bit; component main_sweet_5 is pout(x,y,z:in bit; j,k:out bit); end component; begin main_sweet_5 port map(x1,y1,z1,j1,k1); process
begin
x1<='0';
y1<='0';
z1<='0'; wait for 30ns;
x1<='0';
y1<='0';
z1<='1'; wait for 30ns;
x1<='0';
y1<='1';
z1<='0'; wait for 30ns;
x1<='0';
y1<='1';
z1<='1'; wait for 30ns;
x1<='1';
y1<='0';
z1<='0'; wait for 30ns;
x1<='1';
y1<='0';
z1<='1'; wait for 30ns;
x1<='1';
y1<='1';
z1<='0'; wait for 30ns;
x1<='1';
y1<='1';
z1<='1'; wait for 30ns;
end process;
end architecture;
Output
TRUTH TABLE:
x y Z j k
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
DISCUSSION: A full adder is designed and simulated using the structural architecture using half adder.
The output generated exactly satisfies the theoretical truth table of the adder given.
Steps to implement the design Step 1: Start the Xilinx project navigator by Stat->programs->Xilinx ISE->Project Navigator Step 2: In the project navigator window click on new project->give file name->next.
Step 3: In the projector window right click on project name-> new source->VHDL
module->give file name->define ports->finish.
Step 4: Write the VHDL code for any gate or circuit.
Step 5: Check Syntax and remove error if present.
Step 6: Simulate design using Modelsim.
Step 7: In the project navigator window click on simulation->click on simulate
behavioral model.
Step 8: Give inputs by right click on any input->force constant
Step 9: Run simulation
Step 10: Analyze the waveform.
ASSIGNMENT-3
Q1.Write VHDL code for basic gates: AND, OR, NOT (USING
XILINX SOFTWARE)
Q2. Write VHDL code for universal logic gates: NAND, NOR and
XOR, XNOR gates using basic gates (USING XILINX
SOFTWARE)
.
NOR GATE
Q3. Write VHDL code for 2:1 mux using other basic gates(USING
XILINX SOFTWARE)
2:1 mux: A digital multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it to a single output line.
Z= (A.S/ ) + B.S
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_2 to 1 is
port (a : in STD_LOGIC; b : in STD_LOGIC; s : in STD_LOGIC z : out STD_LOGIC) ;
end mux_2 to 1 is;
architecture behavioral of mux_2 to 1 is
begin
process (a, b, s)
begin
if (s=‟0‟)then z<=a;
else z<=b;
end if;
end process;
end behavioral;
2:1 mux using gates: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_2 to 1 is port (a : in STD_LOGIC; b : in STD_LOGIC;
s : in STD_LOGIC z : out STD_LOGIC) ; end mux_2 to 1 ; architecture behavioral of mux_2 to 1 is begin process (a, b, s) variable (s1, s2, s3:STD_LOGIC) begin s1:=NOT s; s2:=s1 AND a; s3:=s AND b; z<=s2 OR s3; end process; end behavioral
Q4. Write VHDL code for Half-adder, full-adder, half-substractor and full-subsractor Half-adder:
A B s c 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity half_adder is port (a : in STD_LOGIC;
b : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC);
end half_adder; architecture behavioral of half_adder is begin process (a,b) begin if (a=‟0‟ and b=‟0‟) then s<=‟0‟; c<=‟0‟; elsif (a=‟1‟ and b=‟1‟) s<=‟0‟; c<=‟1‟; else s<=‟1‟; c<=‟0‟; end if; end process; end behavioral; Full-Adder: A B C S cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1
1 1 1 1
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity full_adder is port (a : in STD_LOGIC_VECTOR (0 to 2); s : out STD_LOGIC_VECTOR (0 to 1)); end full_adder; architecture behavioral of full_adder is begin process (a) begin case a is when “000”=> s<=“00”; when “001”=> s<=“10”; when “010”=> s<=“10”; when“011”=> s<=“01”; when “100”=> s<=“10”; when “101”=> s<=“01”; when “110”=> s<=“01”; when others =>s<=“11”; end case; end process; end behavioral; Half-substractor:
A B S c 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity half_subs is port ( a : in STD_LOGIC;
b : in STD_LOGIC; d : out STD_LOGIC; b1 : out STD_LOGIC);
end half_subs;
architecture behavioral of half_subs is
begin
process (a,b)
begin
if (a=b)
then d<=‟0‟;
else d<=‟1‟;
end if;
if (a=‟0‟ and b=‟1‟)
then b1<=‟1‟ ;
else b1<=‟0‟;
end if;
end process;
end behavioral;
Full-Substractor:
A B C S cout 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1
1 1 1 1
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_subs is
port (a : in STD_LOGIC_VECTOR (0 to 2);
s : out STD_LOGIC_VECTOR (0 to 1)); end full_subs; architecture behavioral of full_subs is begin process (a) begin case a is when “000”=> s<=“00”; when “001”=> s<=“11”; when “010”=> s<=“11”; when “011”=> s<=“01”; when “100”=> s<=“10”; when “101”=> s<=“00”;
when “110”=> s<=“00”; when others =>s<=“11”; end case; end process; end behavioral;
