ECE 1312 IIUM L16 FET DC Analysis

7/23/2019 ECE 1312 IIUM L16 FET DC Analysis

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Electronics Electronics ECE 1231ECE 1231

Recall Last Lecture

The MOSFET has only one current, ID

Operation of MOSFET NMOS and PMOS

For NMOS,

VS! VTN

VDS sat" VS# VTN

For PMOS

VS! $VTP$

VSD sat" VS% VTP


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ID&ersus VDS 'NMOS( or ID&ersus VSD'PMOS(


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NMOSo VTN is POSITIVE

o VS! VTN toturn on

oTriode)non*saturation re+ion

o Saturation re+ion

o VDSsat " VS * VTN

PMOSo VTP is NETIVE

o VS! $VTP$ to turnon

oTriode)non*saturation re+ion

o Saturation re+ion

o VSDsat" VS% VTP


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D- analysis of FET


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MOSFET DC Circuit AnalysisMOSFET DC Circuit Analysis- NMOS The source terminal is

at ground and common

to both input and output

portions of the circuit.

The CCacts as an open

circuit to dc but it allows

the signal voltage to the

gate of the MOSFET.

In the ! e"uivalent circuit# the gate current into the transistor is

$ero# the voltage at the gate is given b% a voltage divider principle&

'( ) 'T*) +, '

+- +,

.se /VL at S loop0

VS#VT1% 2 " 2VS" VT1


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MOSFET DC Circuit AnalysisMOSFET DC Circuit Analysis

- NMOS- NMOS

/ssume the transistor is biased in the

saturation region# the drain current&

0se 1'2 at S loop

I+ 'S ') 3

If VDS

4 VDS

5sat6 ) VGS

VTN

# then the transistor is biased in the

saturation region.

If VDS

7 VDS

5sat6#then the transistor is biased in the nonsaturation

region.


7/20 Electronics Electronics ECE 1231ECE 1231

!alculate the drain current and drain to source voltage of a common source

circuit with an n8channel enhancement mode MOSFET. /ssume that +-) 93:# +,) ,3 :# +) ,3 :# ') ;'# 'T VDSsat, our assumption

that the transistor is in saturation region is correct

'T*) ,3 ; ) ,' hence '(S ) 'T*) ,'

93 ,3

EXAMPLE:



E3MPLE

The transistor haspara4eters VTN" 5V and

/n" 26574)V56

Find IDand VDS

VDD"

82V

RD"

829

R8"

5:29

R5"

8;29



Solution

56 ssu4e in saturation 4ode0

ID " /n'VS * VTN(5

So, ID " 26;;< 4

=6 KVL at DS loop: VDS" VDD# IDRD" 82 # 26;;< '82( " =6=8 V

>6 VDS sat" VS# VTN " =6;=; # 5 " 86;=; V

So, VDS! VDSsat, therefore, assu4ption is correct?

86 VT1" 8;2 82 "

=6;=; V->3 ,?3

ns@er0 ID" 26;;< 4 and VDS" =6=8 V

KVL at GS loop:VS# VT1% 2 " 2 VS"

VT1



MOSFET DC Circuit AnalysisMOSFET DC Circuit Analysis-PMOSifferent notation&

'S(and 'SThreshold 'oltage ) 'T@

s! KVL at GS loop:VS% 2 % VT1# VDD" 2

VS" VDD* VT1

'( ) 'T*) +, '

+- +,



MOSFET DC Circuit AnalysisMOSFET DC Circuit Analysis- PMOS

/ssume the transistor is biased in the saturation

region# the drain current&

!alculate 'S&

Use KVL at DS loop&

'S I+8 ') 3

If VSD

4VSD

5sat6 ) VSG

VTP

# then the transistor is biased in the

saturation region.

If VSD

7 VSD

5sat6# then the transistor is biased in the non8saturation

region.

VSD " VDD* IDRD

ID " /p'VS % VTP(5



72 9

72 9A67 9

!alculate the drain current and source to drain voltage of a common

source circuit with an p8channel enhancement mode MOSFET.

/lso find the power dissipation.

/ssume that# 'T@) 8-.-' and 1p) 3.9 m/=',

s! KVL at SG loop:VS% 2 %567 # 7 " 2

VS " 7 # 567 " 567 V

ssu4e Biased in saturation 4ode0

1ence, ID " 26= ' 567 # 868(5 " 267:::4

Calculat! VSD

s! KVL at SD loop:VSD% IDRD# 7 " 2

VSD" 7 * IDRDVSD " 7 # 267::: ' A67( " "#$%& V

7V

VS! $VTP $


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VSD sat" VS% VTP" 567 # 868 " '#&V

1ence, VSD ( VSD sat6 T)!r!*or! assu+ption is

incorr!ct#The transistor is in non*saturation 4ode?

ID" 26= 5 ' 567 # 868( '7 # IDRD( # '7 # IDRD(5

ID" 26= 56: '7 # A67ID( # '7*A67ID(

5

ID" 26= 8> # 58ID# '57 # A7ID% 7;657ID

5(

ID" 26= 8> # 58ID*57 %A7ID# 7;657ID5

7;657 I 5# 726;A I % 88 " 2

ID" 267=; 4

ID" 26=;7

4


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ID" 267=; 4 ID" 26=;7

4

VSD" 7 # IDRD" 26


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LOD LINE

-o44on source con+uration i6esource is +rounded6

It is the linear euation of ID&ersus VDS

.se /VL

VDS" VDD# IDRD

ID" *VDS% VDD

RD RD


16/20


ID'4(

VDS'V(

VS

VDS

IDG*POINTS

y*intercept

H*intercept


17/20


D- nalysis @here source is NOT RO.NDED

86 For the NMOS transistor in the circuit Belo@, the para4eters are VTN

" 8V and /n " 267 4)V56


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a( Jhat is the &alue of VK

B( Jrite do@n the Branch current

euation for the source ter4inal6

c( et an eHpression for VS in ter4s of ID

ID

ID

V" *8V

Or us! no1!6olta7!s: VS "

V* VSVS " *8 # ' ID# 7(

VS " > * ID

use /VL0

2 % VS% 8'ID( *7 %8

" 2VS" > * ID


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d( The transistor is Biased in saturation 4ode,

calculate ID6 ou @ill 9no@ @hich &alue of IDthat

you need to choose By calculatin+ VS6 ustify

your ans@er6

ID

ID


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e( Jrite do@n the Branch current euation

for the drain ter4inal

f( -alculate VDSand conr4 that the

transistor is Biased in saturation 4ode6

.se /VL0

IDRD % VDS % IDRS# 7 # 7 " 2

86=7> '5( % VDS% 86=7> # 82" 2VDS " 82 # 86=7> # 56A2: "

$#2/% V

ID

ID

Or us! no1! 6olta7!s:VDS " VD* VS

@here VD " 7 * 5' 86=7>( "565; V

So, VDS" 565

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ECE 1312 IIUM L16 FET DC Analysis

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