ECE 331 – Digital System Design

ECE 331 – Digital System Design

Power Dissipationand

Propagation Delay

ECE 331 - Digital System Design 2

Power Dissipation


Power Consumption

• Each integrated circuit (IC) consumes power

• PT = P

S + P

D

– PT = total power consumed by IC

– PS = static or quiescent power consumption

– PD = dynamic power consumption


Power Dissipation

Static Power Consumption



• PS = V

CC * I

CC

– VCC

= supply voltage

– ICC

= quiescent supply current

– PS = static power consumption

• ICC

and VCC

are specified in the datasheet for

integrated circuit (IC).

• PS for CMOS devices is very small



Example:

Calculate the static power dissipation for a 74LS00 2-input NAND gate.


Example: 74LS00 (TTL)


Example: 74LS00 (TTL) Supply Voltage

4.75 V <= VCC

<= 5.25 V

Supply Current High Output: I

CCmax = 1.6 mA

Low Output: ICCmax

= 4.4 mA

Maximum static power consumption High Output: P

S = 8.4 mW

Low Output: PS = 23.1 mW


Example: 74LS00 (TTL)• Example: (continued)

– Duty Cycle

• Clock signal typically has 50% duty cycle

– PS = P

S_high * t

high + P

S_low * t

low

• PS_high

= 8.4 mW

• PS_low

= 23.1 mW

• Assume 50% duty cycle (high / low half the time)

• PS = 8.4 mW * 0.5 + 23.1 mW * 0.5 = 15.8 mW

• Assume 60% duty cycle (high 60% of the time)

• PS = 8.4 mW * 0.6 + 23.1 mW * 0.4 = 14.28 mW



Example:

Compare the static power dissipation of the 74LS00 NAND gate with that of

the 74HC00 NAND gate.


Example: 74HC00 (CMOS)



PS = V

CC * I

CC

Supply Voltage V

CC = 6.0 V

Supply Current I

CC = 20 A

Maximum static power consumption P

S = 6.0 V * 20 A = 120 W


Power Dissipation

Dynamic Power Consumption



• TTL

– PD ~= 0 W

• CMOS

– PD != 0 W

– Movement of charge into and out of device capacitances is used to determine dynamic power consumption.



• CMOS

– Charge is stored in the internal (CPD

) and

load (CL) capacitances

• CPD

= power dissipation capacitance (internal)

• CL = capacitance of load and wires (external)

– Capacitances are in parallel

• CT = total capacitance = C

PD + C

L

– Stored charge (Q)

• QT = C

T * V

DD = (C

PD + C

L) * V

DD



• CMOS (continued)

– Charge is moved on each output transition

• Output transition from high to low and low to high

– Movement of charge = current

• IAVG

= (CPD

+ CL) * V

DD * f

T

• fT = output frequency (i.e. # of transitions per

second)

– PD = I

AVG * V

DD = (C

PD + C

L) * V2

DD * f

T



Example:

Calculate the dynamic power consumption for a 74HC00 2-input NAND gate.






Dynamic Power Consumption• Example: 74HC00 (Quad 2-input NAND)

VDD

= 5 V, CPD

= 22 pF, CL = 50 pF

PD = (22 pF + 50 pF) * (5 V)2 * fT

FT

(Hz) PD

1K 1.8 W

1M 1.8 mW

100M 180 mW

IDDmax

= 20 A

PS = V

DD * I

DDmax = 5 V * 20 A = 100 W


Power Dissipation

Total Power Consumption


Total Power Consumption• P

T = P

S + P

D

• Compare PT for Quad 2-input NAND (74xx00)

0 Hz 1 MHz 100 MHz

TTL 15.8 mW 15.8 mW 15.8 mW

CMOS 100 W 1.805 mW 180 mW

• Compare TTL and CMOS

TTL CMOS

PS

VCC

* ICC

VDD

* IDD

PD

~ 0 W (CPD

+ CL) * V2

DD *

fT


Propagation Delay


Definitions Propagation Delay: The time from a change in

one input to the final change in the output Maximum Delay: Worst-case delay Typical Delay: Mean delay Minimum Delay: Fastest possible

The specifications for maximum, typical, and minimum delay are those measured by the manufacturer for the given conditions


Propagation Delay

The time delay between a change in the input and the corresponding change in the output

tPHL

= time for output to transition from high to low

tPLH

= time for output to transition from low to high

Ideal Propagation Delay

input

output

tPHL

tPLH


Propagation delay

V DD

V DD

Gnd

Gnd

50% 50%

90%

Propagation delay

10%

t r

50%

90%

50%

10%

t f

input

output

Propagation Delay


Propagation Delay

Propagation delay is used to determine When outputs are valid The maximum speed of a combinational circuit The maximum frequency of a sequential

circuit


Simple Analysis

Given: A logic circuit with multiple inputs and a single output.

Given: A single transition on one of the inputs. Determine: The time delay to propagate the

transition on the input to the output. Use the propagation delay specified for each

gate in the path between the input on which the transition occurred and the output.

The gate propagation delays are specified in the associate datasheets.


More Complex Analysis

Problem: Some circuits have more than one path from an input to an output.

Solution: Analyze every possible delay path

or Use the Worst Case Analysis

Provides a conservative specification Often sufficient


More Complex Analysis

Problem: What if multiple inputs change at the same time?

Solution: Analyze all combinations of input changes

for all delay paths (to the output).

or Use the Worst Case Analysis


Sum of Worst Cases (SWC) Analysis

Write worst case delay next to each logic gate

Select maximum of tPLH

and tPHL

Identify all input-output paths (i.e. all delay paths) Calculate worst case delay for each path

Summarize in table

Select worst case (i.e. maximum propagation delay)


Example:

Determine the worst-case propagation delay using the SWC Analysis for the XOR Logic Circuit.


Example

f

x1

x2

74LS04

74F04

74F08

74LS08

74F32

TPLH TPHL

min typ max min typ max

74LS04 0 9 15 0 10 14

74F04 2.4 3.7 6.0 1.5 3.2 5.4

74LS08 0 8 18 0 10 20

74F08 2.4 3.7 6.2 2.0 3.2 5.3

74F32 2.4 3.7 6.1 1.8 3.2 5.5


Example

f

x1

x2

74LS04

74F04

74F08

74LS08

74F32

TPLH TPHL


74LS04 0 9 15 0 10 14

74F04 2.4 3.7 6.0 1.5 3.2 5.4

74LS08 0 8 18 0 10 20

74F08 2.4 3.7 6.2 2.0 3.2 5.3

74F32 2.4 3.7 6.1 1.8 3.2 5.5

TP = 32.1


Example

f

x1

x2

74LS04

74F04

74F08

74LS08

74F32

TPLH TPHL


74LS04 0 9 15 0 10 14

74F04 2.4 3.7 6.0 1.5 3.2 5.4

74LS08 0 8 18 0 10 20

74F08 2.4 3.7 6.2 2.0 3.2 5.3

74F32 2.4 3.7 6.1 1.8 3.2 5.5

TP = 12.3


Example

f

x1

x2

74LS04

74F04

74F08

74LS08

74F32

TPLH TPHL


74LS04 0 9 15 0 10 14

74F04 2.4 3.7 6.0 1.5 3.2 5.4

74LS08 0 8 18 0 10 20

74F08 2.4 3.7 6.2 2.0 3.2 5.3

74F32 2.4 3.7 6.1 1.8 3.2 5.5

TP = 26.1


Example

f

x1

x2

74LS04

74F04

74F08

74LS08

74F32

TPLH TPHL


74LS04 0 9 15 0 10 14

74F04 2.4 3.7 6.0 1.5 3.2 5.4

74LS08 0 8 18 0 10 20

74F08 2.4 3.7 6.2 2.0 3.2 5.3

74F32 2.4 3.7 6.1 1.8 3.2 5.5

TP = 27.3


Example

Input Output Delay

X1 F 32.1

X1 F 12.3

X2 F 26.1

X2 F 27.3

Worst Case Propagation Delay = 32.1


SWC Analysis - Summary

Permits Worst Case assessment of delay Simple / Robust Conservative

If it does not satisfy the design requirements it may be necessary to implement a more detailed analysis.

In particular, with the case-limiting paths

Date post:	31-Dec-2015
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ECE 331 – Digital System Design

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