1MOS Digital CircuitsChapter 16

In the late 70s as the era of LSI and VLSI began, NMOS became the fabrication technology choice.

Later the design flexibility and other advantages of the CMOS were realized, CMOS technology then replaced NMOS at all level of integration.

The small transistor size and low power dissipation of CMOS circuits, demonstration principal advantages of CMOS over NMOS circuits.

NMOS Inverter

For any IC technology used in digital circuit design, the basic circuit element is the logic inverter.

Once the operation and characterization of an inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits.

NMOS Inverter If VI VNT, the transistor is on and initially is biased in saturation region, since

VDS >VGS-VTN. As the input voltage increases

(VGS) , the drain to source voltage (VDS) decreases and the transistor inter into the non saturation region.

+

+

VGS=V

RD

=VDD=VDS

NMOS Inverter Transfer Characteristics with load resister (Saturation Region)

+

+

VGS=V

RD

=VDD=VDS

VGS=V

RD

=VDD=VDS

As the input is increased slightly above the VTN, the transistor turns on and is in the saturation region. The output voltage is then

vo = VDD iDRD (16.6 )

where the drain current is given by

iD = Kn(VGS - VTN)2 = Kn(Vi - VTN)2 ( 16.7)

By substituting the value of ID from Eq. 16.7 we get ,

VO = VDD - KnRD(VI - VTN)2 (16.8)

which relates the output and input voltages as long as the transistor is biased in the saturation region.

NMOS Inverter Transfer Characteristics with load resister (transition Region)

As the input voltage is further increases and voltage drop across the RD become sufficient to reduce the drain to source voltage such that

VDSVGS-VTN.

the Q-point of the transistor moves up the load line. At the transition point, we have

vot = VIt - VTN 16.9

where Vo, and VI, are the drain-to-source and gate-to-source voltages, respectively, at the transition point. By substituting Equation (16.9) into (16.8), the input voltage at the transition point can be determined as,

KnRD(VIt - VTN)2+ (VIt - VTN) - VDD = 0

+

+

VGS=V

RD

=VDD=VDS

VGS=V

RD

=VDD=VDS

NMOS Inverter Transfer Characteristics with load resister (Nonsaturation Region)

As the input voltage becomes greater than VIt, the Q-point continues to move up the load line, and the transistor becomes biased in the nonsaturation region. The drain current is theniD = Kn[2(VGS - VTN)VDS VDS2]

= Kn[2(vI - VTN)VO Vo2] (16.11)The output voltage is then

determined by vo = VDD iDRDSubstitute the value of ID from above equation we get the output voltage relation when the transistor is biased in nonsaturation region.

VO = VDD KnRD [2(vl - VTN)vo -vo2]

+

+

VGS=V

RD

=VDD=VDS

VGS=V

RD

=VDD=VDS

2+

+

VGS=V

RD

=VDD=VDS

VGS=V

RD

=VDD=VDS

It should be be noted that the minimum output voltage, or the logic 0 level, for a high input decreases with increasing load resistance, and the sharpness of the transition region between a low input and a high input increases with increasing load resistance.

Summary of NMOS inverter C-V relationship with the resister load

Saturation region

Transition region

iD = Kn(VGS - VTN)2 = Kn(Vi - VTN)2VO = VDD - KnRD(VI - VTN)2

vot = VIt - VTNKnRD(VIt - VTN)2+ (VIt - VTN) - VDD

Nonsaturation region

= Kn[2(vI - VTN)VO Vo2] iD

VO = VDD KnRD [2(vl - VTN)vo - vo2]

+

+

VGS=V

RD

=VDD=VDS

VGS=V

RD

=VDD=VDS

NMOS Inverter with Enhancement Load

This basic inverter consist of two enhancement-only NMOS transistors and is much more practical than the resister loaded inverter, which is thousand of times larger than a MOSFET.

n-Channel MOSFET connected as saturated load device

An n-channel enhancement-mode MOSFET with the gate connected to the drain can be used as load device in an NMOS inverter.

Since the gate and drain of the transistor are connected, we have

VGS=VDSWhen VGS=VDS>VTN, a non zero drain

current is induced in the transistor and thus the transistor operates in saturation only. And following condition is satisfied.

VDS>(VGS-VTN)

VDS (sat)= (VDS-VTN) because VGS=VDS or VDS (sat)= (VGS-VTN)

In the saturation region the drain current is iD=Kn(VGS-VTN)2 = Kn(VDS-VTN)2

The iD versus vDS characteristics are shown in Figure 16.7(b), which indicates that this device acts as a nonlinear resistor.

NMOS Inverter with Enhancement Load/Saturated

In the saturation region the loaddrain current is

iDL=KL(VGSL-VTNL)2 = KL(VDSL-VTNL)2

For VGSDVTND A non zero drain current is induced in

the transistor and thus the drive transistor operates in saturation only. As shown in the figure the following condition is satisfiediDD=iDL or

KD(VGSD-VTND)2 = KL(VGSL-VTNL)2Substituting VGSD=VI and VGSL=VDD-VO

yieldsKD(VI - VTND)2 = KL(VDD - VO - VTNL)2Solving for VO givesVO= VDD-VTNL- KD/KL(VI-VTND)

3NMOS inverter with Enhancement Load/Saturated (driver at the transition point)

As the input voltage (VGS) further increases, the drive Q-point moves up and switch into the transition region., we have

VDSD(sat)= VGSD-VTNDIn terms of input/output transition

voltagesor VOt=VIt-VTND

Substituting above Equation into following equation

VO= VDD-VTNL- KD/KL(VI-VTND)we find the input voltage at the

transition point, which is

VIt= [VDDVTNL+VTND(1+ KD/KL)]/(1+ KD/KL)

NMOS Inverter with Enhancement Load/Saturated (driver at the non saturation region))

As the input voltage becomes greater than VIt the driver transistor Q- point continues to move up the load curve and the driver becomes biased in the nonsaturation region. Since the driver and load drain currents are still equal, or iDD = iDL, we now have

KD[2(VGSD - VTND)VDSD - VDSD2] = KL(VDSL -VTNL)2

Substituting VGSD=VI and VDSD=VO and VDSL= VDD-VO we get

KD[2(vl -VTND) Vo- VO2 ] = KL(VDD - VO - VTNL)2

The ratio KDIKL is the aspect ratio and is related to the width-to-length parameters of the driver and load transistors.

The slope of the VTC curves in the saturation region is known as inverter gain and is given by

dVo/dVI= - KD/KL

If the inverter gain is greater then unity, the inverter logic gate is belonged to restoring logic family.

Limitation of NMOS inverterExample 16.3

Limitation of Enhancement Load inverter

VO,max= VOH =VDD-VTNL

the output high voltage VOis degraded by the thresholdvoltage.

NMOS Inverter with Depletion Load This is an alternate form of

the NMOS inverter that uses an enhancement-depletion MOSFET load device with gate and source terminal connected.

This inverter has the advantage of VO= VDD, as well as more abrupt VTC transition region even though the W/L ratio for the output MOSFET is small.

The term depletion modemeans that a channel exists even with zero gate voltage.

4N-Channel Depletion-Mode MOSFET

In n- channel depletion mode MOSFET, an n-channel region or inversion layer exists under the gate oxide layer even at zero gate voltage and hence term depletion mode.

A negative voltage must be applied to the gate to turn thedevice off.

The threshold voltage is alwaysnegative for this kind of device.

NMOS Inverter with Depletion Load (saturation condition)

With the gate and sourceare connected, VGSL=0.

Since the threshold voltageof load transistor is

negative, we have

VGSL=0>VTNL= -(VTNL)

This implies that load MOSFET is always active.

For an active device we canwrite

VDSLVGSL VTNL= -VTNL=VTNL

becauseVGSL=0.

NMOS Inverter with Depletion Load (cont.)

Case I: when VIVTND (driver turns on)and is biased in the saturation

region; however, the load is biased in the nonsaturationregion.

Under the condition we can write iDD=IDDL

KD(VGSD-VTND)2 =KL[2(VGSL - VTNL)VDSL- VDSL2]

Substituting VGSD=VI, VGSL=0, and VDSL=VDD-VOYields KD(VI-VTND)2 =KL[2(-VTNL)(VDD -VO)-VDD VO)2]

Which relates the input and output voltage as long as the driver is biased in saturation region and

Two transition points for NMOS depletion load inverter

In the Figure the point B and C are corresponding the two transition points: one for the load and one for the driver.

The transition point for the load is given by,VDSL=VDD-VOtAlso VDSL=VGSL-VTNLBy equating the relations we getVDD-VOt=VGSL-VTNLSince VGSL=0

V0t=VDD+VTNLAs we know VTNL is negative. This implies that Vot

5VT Characteristics of NMOS Inverter with Depletion Load

The Figure demonstrate in present configuration more abrupt VTC transition region can be achieved even though the W/L ratio for the output MOSFET is small.

Transient Analysis of NMOS inverters

The source of capacitance CT2 and CT3are the transistor input capacitances and parasitic capacitancesdue to interconnect lines between the inverter stages.

The constant current over a wide range of VDS provided by the depletion load implies that this type of inverter switch a capacitive load more rapidly than the other two types inverter configurations.The rate at

Transient Analysis of NMOS inverters (cont.)

The fall time relatively short, because the load capacitor discharges through the large driver transistor.

The raise time is longer because the load capacitor is charged by the current through the smaller load transistor.

(W/L)L=1(W/L)D=4F-0.5pF

6depletion loadenhancement load

1160W 825W 200W

716.2: NMOS Logic Circuit

NMOS logic circuits are constructed by connecting driver transistor in parallel, series or series-parallel combinations

to produce required output logic function

NMOS NOR gate NMOS NOR gate can be constructed by

connecting an additional driver transistor in parallel with a depletion load inverter.

The output of a NOR gate is only high when both inputs are at logic 0(low)i.e.

If A=B=logic 0,Then both driver transistors MDA and MDB

are in cut off mode and V0=VDD (logic 1)

For all other possible inputs V0= 0 (logic 0).For example,If A=high (logic1) and B=low (logic0)Then MDB is in cut off mode and remaining

circuit behave as depletion load inverter. However, when both driver transistors are in active mode the value of the output voltage logic 0) is changed.

NMOS NOR gate: Special case when all inputs are at logic 1

When A=B=logic 1Both driver transistors are switched into nonsaturation regionand load transistor is biased in saturation region. We have

iDL=iDA+iDBBy substituting the values of current equation we can write as,

KL(VGSL-VTNL)2 = KDA[2(VGSA - VTNA)VDSA - VDSA2] + KDB[2(VGSB-VTNB)VDSB - VDSB2]

Suppose two driver transister are identical, which implies that,KDA=KDB=KDVTNA=VTNB=VTNDAs we know VGSL=0Also from figure VGSA=VGSB=VDDVDSA=VDSB=V0By substituting all these parameters we can write above equation as,

(-VTNL)2 = 2(KD/KL)[2(VDD-VTND)V0-VO2)Conclusion: The above equation suggested that when the both the

driver are in conducting mode, the effective aspect ratio of the NOR gate is double. This further suggested that output voltage becomes slightly smaller when both inputs are high. Because higher the aspect ratio lower the output.

Concept of effective width to length ratios

For the NOR gate the effective width of the drivers transistors doubles. That means the effective aspect ratio is increased.

For the NAND gate the effective length of the driver transistors doubles. That means the effective aspect ratio is decreased..

Parallel combination Series combination

8 At present, complementary MOS or CMOS has replaced NMOS at all level of integration, in both analog and digital applications.

The basic reason of this replacement is that the power dissipation in CMOS logic circuits is much less than in NMOS circuits, which makes CMOS very attractive.

Although the processing is more complicated for CMOS circuits than for NMOS circuits.

However, the advantages of CMOS digital circuits over NMOS circuits justify their use.

CMOS: the most abundant devices on earth

Full rail-to-rail swing high noise marginsz Logic levels not dependent upon the relative device sizes

transistors can be minimum size ratio less Always a path to Vdd or GND in steady state low

output impedance (output resistance in k range) large fan-out.

Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current

No direct path steady-state between power and ground no static power dissipation

Propagation delay function of load capacitance and resistance of transistors

CMOS properties

16.3.1:p-Channel MOSFET Revisited

In p-channel enhancement device. A negative gate-to-source voltage must be applied to create the inversion layer, or channel region, of holes that, connect the source and drain regions.

The threshold voltage VTPfor p-channel enhancement load device is always negative and positive for depletion-mode PMOS.

Cross-section of p-channel enhancement mode MOSFET

The operation of the p-channel is same as the n-channel device , except that the hole is the charge carrier, rather than the electron, and the conventional current direction and voltage polarities are reversed.

Simplified cross section of a CMOS inverter

In the fabrication process, a separate p-well region is formed within the starting n-substrate.

The n-channel MOSFET is fabricated in the p-well region and p-channel MOSFET is fabricated in the n-substrate.

9CMOS Inverter: Steady State Response

VDD

Rn

Vout = 0

Vin = V DD

VDD

Rp

Vout = 1

Vin = 0

VOL = 0VOH = VDD

Voltage Transfer CurveCMOS Inverter Load Lines

0

0.5

1

1.5

2

2.5

0 0.5 1 1.5 2 2.5

I Dn

( A)

Vout (V)

X 10-4

Vin = 1.0V

Vin = 1.5V

Vin = 2.0V

Vin = 2.5V

0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V

Vin = 0V

Vin = 0.5V

Vin = 1.0V

Vin = 1.5VVin = 0.5VVin = 2.0V

Vin = 2.5VVin = 2.5V

Vin = 2VVin = 2VVin = 1.5VVin = 1.5V

Vin = 1VVin = 1VVin = 0.5VVin = 0.5V

Vin = 0VVin = 0V

PMOS NMOS

NMOS offPMOS in non sat

NMOS in satPMOS in non

sat

NMOS in satPMOS in sat

NMOS in non sat

PMOS in sat

NMOS in nonsat

PMOS off

DC analysis of the CMOS inverter The figure shows series

combination of a CMOS inverter.

To form the input, gate of the two MOSFET are connected.

To form the output, the drains are connected together.

VI Vo 1 0 0 1

The transistor KN is also known as pull downDevice, it is pulling the output voltage down towards ground.The transistor KP is known as the pull up device because it is pulling the output voltage up towards VDD. This property speed up the operation considerably.

It is to be noted that the static power dissipation during both extreme cases(logic 1 or 0) is almost zero because iDp=iDn=0.

7

CMOS inverter in either high or low state (ideal case)

Ideally, the power dissipation of the CMOS inverter is zero.

However, real CMOS inverter exhibits a very small power dissipation in the nanowatt range rather than in the milliwatt rang of NMOS inverter.

1

10

Different biasing conditions for a CMOS inverter.

Case I: when NMOS is biased in saturation region and PMOS is biased in nonsaturationregion.

The above condition can be achieved when NMOS just start to conduct (VI=VTN). Under this condition we can write,

iDN=iDP

KN[VGSN-VTN]2=KP[2(VGSP+VTP)VSDP-VSDP2)]In terms of input output voltage we can write,KN[VI-VTN]2=KP[2(VDD-VI+VTP)VDD-VO)-(VDD-VO)2]

Transition points for PMOS and NMOS

As we know transition point for the PMOS can be define as,

VSDP(sat)=VSGP+VTPOr VOPt=VIPt-VTPOr VOPt=VIPt+|VTP|

Similarly, the transition point for NMOS can be written as

VDSN(sat)=VGSN-VTNorVoNt=VINT-VTN

Biasing conditions for the CMOS inverter (cont.)

Case II:When both transistors are biased

in the saturation region.iDN=iDPKN[VGSN-VTN]2=KP(VGSP+VTP)2In terms of input output voltage we

can write,KN[VI-VTN]2=KP(VDD-VI+VTP)2The input voltage can be determine

by simplifying above equation as,

The above eq. can also be used to determine input voltage at the transition points.

P

N

TNP

NTPDD

ItI

KK

VKKVV

VV+

++==

1

Both are in Saturationregion

Symmetrical properties of the CMOS inverter

CMOS inverter design consideration

The CMOS inverter usually design to have, (i)VTN =|VTP|

(ii) Kn(W/L)=Kp (W/L)

But Kn> Kp (because n>p)

How equation (ii) can be satisfied?

This can achieved if width of the PMOS is made two or three times than that of the NMOS device. This is very important in order to provide a symmetrical VTC, results in wide noise margin.

8

11

CMOS inverter VTC

VCC

VCCVin

Vout

kp=kn

kp=5knkp=0.2kn

Increase W of PMOSkp increasesVTC moves to right

Increase W of NMOSkn increasesVTC moves to left

For VTH = Vcc/2kn = kpWn 2Wp

Effects of VIt adjustment

Result from changing kp/kn ratio: Inverter threshold VIt Vcc/2 Rise and fall delays unequal Noise margins not equal

Reasons for changing inverter threshold Want a faster delay for one type of transition

(rise/fall) Remove noise from input signal: increase one

noise margin at expense of the other

12

CMOS inverter currents When the output of a

CMOS inverter is either at a logic 1 or 0, the current in the circuit is zero.

When the input voltage is in the range

VTN

13

NMOS Transistor Capacitances: Triode Region

Cox = Gate-channel capacitance per unit area(F/m2).

CGC = Total gate channel capacitance.

CGS = Gate-source capacitance.

CGD = Gate-drain capacitance.

CGSO and CGDO = overlap capacitances (F/m).

NMOS Transistor Capacitances: Saturation Region

Drain no longer connected to channel

NMOS Transistor Capacitances: Cutoff Region

Conducting channel region completely gone.

CGB = Gate-bulk capacitance

CGBO = gate-bulk capacitance per unit width.

CMOS Inverter: Switch Model of Dynamic Behavior

VDD

Rn

VoutCL

Vin = V DD

VDD

Rp

VoutCL

Vin = 0

z Gate response time is determined by the time to charge CLthrough Rp (discharge CL through Rn)

CMOS inverter power

Power has three components Static power: when input isnt switching

Dynamic capacitive power: due to charging and discharging of load capacitance

Dynamic short-circuit power: direct current from VDD to Gnd when both transistors are on

CMOS inverter static power

Static power consumption: Static current: in CMOS there is no static current

as long as Vin < VTN or Vin > VDD+VTP Leakage current: determined by off transistor Influenced by transistor width, supply voltage,

transistor threshold voltagesVDD

VI

14

Dynamic Capacitive Power and energy stored in the PMOS device

Case I: When the input is at logic 0: Under this condition the PMOS is conducting and NMOS is in cutoff mode and the load capacitor must be charged through the PMOS device.

Power dissipation in the PMOS transistor is given by,PP=iLVSDp= iL(VDD-VO)The current and output voltages are related by,iL=CLdvO/dtSimilarly the energy dissipation in the PMOS device can

be written as the output switches from low to high ,

Above equation showed the energy stored in the capacitor CL when the output is high.

2

2

0

2

0

0000

21

)02

()0(,2

,)(

DDLP

DDLDDDDLP

V

OL

VODDLP

O

V

OL

V

ODDLPO

ODDLPP

VCE

VCVVCECVCE

dCdVCEdtdt

dVCPE

DD

DD

DDDD

=

==

===

Power Dissipation and Total Energy Stored in the CMOS Device

Case II: when the input is high and out put is low:During switching all the energy stored in the load

capacitor is dissipated in the NMOS device because NMOS is conducting and PMOS is in cutoff mode. The energy dissipated in the NMOS inverter can be written as,

The total energy dissipated during one switching cycle is,

The power dissipated in terms pf frquency can be written as

2

21

DDLN VCE =

222

21

21

DDLDDLDDLNPT VCVCVCEEE =+=+=

2DDLT

TT VfCfEPt

EPtPE ===This implied that the power dissipation in the CMOS inverter is directly proportional to switching frequency and VDD2

Dynamic capacitive power

Formula for dynamic power:

Observations Does not (directly) depend on device sizes Does not depend on switching delay Applies to general CMOS gate in which:

Switched capacitances are lumped into CL Output swings from Gnd to VDD Input signal approximated as step function Gate switches with frequency f

fVCP DDLdyn2=

Dynamic short-circuit power Short-circuit current flows from VDD to Gnd

when both transistors are on saturation mode Plot on VTC curve:

VCC

VCCVin

Vout ID

Imax

Imax: depends on saturation current of devices

Inverter power consumption

Total power consumption

fVCPtot

IVftt

IVfVCP

PPPP

CCL

leakCCfr

CCCCLtot

statscdyntot

2

max2

~

2+

++=

++=

Power reduction

Reducing dynamic capacitive power: Lower the voltage!

Quadratic effect on dynamic power

Reduce capacitance Short interconnect lengths Drive small gate load (small gates, small fan-out)

Reduce frequency Lower clock frequency - Lower signal activity

fVCP DDLdyn2=

15

Power reduction

Reducing short-circuit current: Fast rise/fall times on input signal Reduce input capacitance Insert small buffers to clean up slow input

signals before sending to large gate Reducing leakage current:

Small transistors (leakage proportional to width)

Lower voltage

Concept of Noise Margins

NML=VIL-VOL (noise margin for low input)NMH=VOH-VIH (noise margin for high input)

NML=VIL-VOLU (noise margin for low input)NMH=VOHU - VIH (noise margin for high input)

VI

At point VIL the NMOS is biased in the saturation region and PMOS is biased in the nonsaturation region

Taking derivative with respect to VI yields

At VIL

Assume CMOS is symmetrical i. e. KN=KP

(1)

(2)

(3)

(4)

(5)

Substituting (5) into (1) (6)

Noise Margins equations

At point VIH the NMOS is biased in the nonsaturation region and PMOS is biased in the saturation region

Taking derivative with respect to VI yields

(6)

(9)

(8)

(7)

Assume CMOS is symmetrical i. e. KN=KP

(10)

Substituting (10) into (6)

Noise Margins equations

(cont.)Summary of the noise margin of a symmetrical

CMOS inverter

NML = VIL - VOLU (noise margin for low input)

NMH = VOHU - VIH (noise margin for high input)

16

Summary of the noise margin of asymmetrical CMOS inverter

NML = VIL - VOLU (noise margin for low input)

NMH = VOHU - VIH (noise margin for high input)

4

CMOS Logic Circuits

Large scale integrated CMOS logic circuits such as watched, calculators, and microprocessors are constructed by using basic CMOS NOR and NAND gates. Therefore, understanding of these basic gates is very important for the designing of very large scale integrated (VLSI) logic circuits.

7

CMOS NOR gateCMOS NOR gate can be

constructed by using two parallel NMOS devices and two series PMOS transistors as shown in the figure. In the CMOS NOR gate the output is at logic 1 when all inputs are low. For all other possible inputs, output is low or at logic 0.

8

17

CMOS NAND gate

In CMOS NAND gate the output is at logic 0 when all inputs are high.

For all other possible inputs, output is high or at logic 1.

How can we design CMOS NOR symmetrical gate?

In order to obtained symmetrical switching times for the high-to-low and low-to-high output transitions, the effective conduction (design) parameters of the compositePMOS and composite NMOSdevice must be equal. For the CMOS NOR gate we can write as,

KCN=KCP

By recalling effective channel width and effective channel length concept, the effective conduction parameter for NMOS and PMOS for a CMOS NOR can be written as,

Since Kn~2Kpp

p

N

n

LWK

LWK

=

222

2

pN LW

LW

=

222

NP LW

LW

=

8or

This implies that in order to get the symmetrical switching properties , the width to length ratio of PMOS transistor must be approximately eight times that of the NMOS device.

For asymmetrical case switching time is longer

Concept of effective width to length ratiosParallel combination Series combination

Fan-In and Fan-Out

The Fan-in of a gate is the number of its inputs. Thus a four input NOR gate has a fan-In of 4.

Similarly, Fan-Out is the maximum number of similar gates that a gate can drive while remaining within guaranteed specifications.

18

t

Vout

Vin

inputwaveform

outputwaveform

tp = (tpHL + tpLH)/2Propagation delay

t

50%

tpHL

50%

tpLH

tf

90%

10%tr

signal slopes

Vin VoutThe propagation delay tp of a gate defines how quicklyit responds to a change at its input(s).

Propagation Delay Definitions Switching Time and Propagation Delay Time

The dynamic performance of a logic circuit family is characterized by propagation delay of its basic inverter. The propagation delay time is define as the average of low-to-high propagation delay time and the high-to-low propagation delay time.

The propagation delay time is directly proportional to the switching time and increases as the Fan-out increases. Therefore, the maximum Fan-out is limited by the maximum acceptable propagation delay time.

Each additional load gate increases the load capacitance their must be charge and discharge as the driver gate changes state. This place a practical limit on the maximum allowable number of load gates.

Inverter Transient Response (input step pulse)

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

Vin

V out

(V)

t (sec) x 10-10

VDD=2.5V0.25mW/Ln = 1.5W/Lp = 4.5Reqn= 13 k ( 1.5)Reqp= 31 k ( 4.5)

tpHL = 36 psec

tpLH = 29 psec

so

tp = 32.5 psec

tf trtpHL tpLH

From simulation: tpHL = 39.9 psec and tpLH = 31.7 psec

Propagation Delay Estimate

The two modes of capacitive charging/discharging that contribute to propagation delay

Switch-level model

Delay estimation using switch-level model (for general RC

circuit):Rn CL

[ ]

==

==

==

==

0

101

01

ln)ln()ln(

1

0

VVRCVVRCt

dVVRCttt

dVVRCdt

RVI

dVICdt

dtdVCI

p

V

Vp

Switch-level model

For fall delay tphl, V0=Vcc, V1=Vcc/2

Lpplh

Lnphl

p

CC

CCp

CRtCRt

RCtVVRC

VVRCt

69.0

69.0)5.0ln(

lnln 21

0

1

===

=

=

Standard RC-delay equations

19

Transmission Gates

Use of transistors as switches are called transmission gates because switches can transmit information from one circuit to another.

NMOS transmission gate as an open switch.

The figure shows NMOS transmission gate. The transistor in the gate can conduct current in either direction. The bias applied to the transistor determineswhich terminal acts as the drain and which terminal acts as the source.

When gate voltage =0The n-channel transistor is

cut off and the transistor acts as an open switch

Characteristics of NMOS transmission gate (at high input)

If =VDD, VI=VDD, and initially, the output V0 is 0 and

capacitance CL is fully discharged.

Under these conditions, the terminal a acts as the drain because its bias is VDD, and terminal b acts as the source because its bias is 0.

The gate to source voltage can be written asVGS=-VO or

VGS= VDD-VOAs CL charges up and Vo increases, the gate to

source voltage decreases. When the gate to source voltage VGS become equal to threshold voltage VTN, the capacitance stop charging and current goes to zero.

This implies that theVO=VO(max) when VGS=VTN

OrVO(max) = VDD-VTN

d S

G

This implies that output voltage never will be equal to VDD. ; rather it will be lower by VTN.This is one of the disadvantage of an NMOS transmission gate when VI=high

Characteristics of NMOS transmission gate (at low input)

When VI=0 and =VDDand VO=VDD-VTN at t=o (initially).It is to be noted that in the present case

terminal b acts as the drain and terminal a acts as the source.

Under these conditions the gate to source voltage is,

VGS=-VIVGS=VDD-ovGS=vDD

This implies that value of VGS is constant.In this case the capacitor is fully

discharge to zero as the drain current goes to zero.

VO=0

This implies that the NMOS transistor provide a good logic 0 when VI=low

VDD-Vt

G

S D

source draingate

Why NMOS transmission gate does not remain in a static condition?

The reverse leakage current due to reverse bias between terminal b and ground begins to discharge the capacitor, and the circuit does not remain in a static condition.

VDD-Vt

source draingate

20

VO(max) = VDD-VTN