ECE 423

DESIGN PROJECT

CMOS INVERTER DESIGNDaud Ali, Deniz Comez, Mehari Ghebreyohannes,

Vishal Rathore, Riya Sharma, Bharat Verma

5 May, 2015

TABLE OF CONTENTS

1. INTRODUCTION

2. ASSIGNMENT QUESTION

3. SCHEMATIC DESIGN OF CMOS INVERTER

4. TRANSIENT RESPONSE OF CMOS INVERTER

5. CALCULATING THE DELAY : “tp” ( WITHOUT CAPACITOR)

6. CALCULATING THE DELAY : “tp” ( WITH CAPACITOR)

7. CALCULATING THE POWER

8. CALCULATING THE ENERGY

9. DRC/LVS LAYOUT

10. SUMMARY

INTRODUCTION TO CMOS INVERTER

CMOS inverters (Complementary MOSFET Inverters) are some of the most widely used and adaptable MOSFET inverters used in chip design. They operate with very little power loss and at a relatively high speed. Furthermore, the CMOS inverter has good logic buffer characteristics, in that, its noise margins in both low and high states are large. This short description of CMOS inverters gives a basic understanding of the how a CMOS inverter works. It will cover input or output characteristics, MOSFET states at different input voltages, and power losses due to electrical current. A CMOS inverter is the combination of a PMOS and a NMOS transistor connected at the drain and gate terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS source terminal.

The input source, Vin is connected to the gate terminals, while the output, Vout is connected to the drain terminals. It is important to notice that the CMOS does not contain any resistors, which makes the CMOS use power more efficiently than a regular resistor-MOSFET inverter.

ASSIGNMENT – QUESTION

Design Problem:

“Using the IBM 0.18um CMOS (cmrf7sf) process, design a CMOS inverter that meets the following requirements:

a) Matched pull-up and pull-down times (i.e., tpHL ≈ tpLH).

b) tp = 25 pS (± 1 pS).

Determine the appropriate load capacitance CL that can be connected at the output of this inverter while meeting the design specifications in (a) and in (b). Determine the W and L of the transistors. Verify and optimize the design, using Cadence simulator showing all the basic inverter performances learnt in chapter 5 of the text. Compute also the average power and energy consumed per transition (over one time period). Using Cadence Virtuoso layout tool, generate the basic layout of the inverter designed, run DRC/LVS and attach DRC/LVS output log. ECE623 Students: Please complete the inverter layout connecting signalinput, signal-output and supply lines up to the input/output pads and insert chip-edge (from the cmrf7sf library). Run DRC/LVS on this whole layout and attach the DRC/LVS log.”

SCHEMATIC DESIGN OF CMOS INVERTER

(Fig. 1: Shows the schematic of the CMOS Inverter)

The schematic design shown in Fig. 1 is a CMOS inverter circuit which consists of two different type of transistor which are NMOS and PMOS transistor with their gates connected together at the input. The applied voltage is denoted by “V1” and the output voltage, “Output” is taken out from the common drain terminals. The transistors are connected in a manner that ensures that only one of the MOSFETs conducts when the input is stable at a low or high voltage. This happened due to the use of the complementary arrangement.

TRANSIENT RESPONSE OF CMOS INVERTER

(Fig. 2: Transient Analysis, with input and output voltages separately)

For the transient analysis, the previous schematic design of CMOS inverter was modified and the schematic is shown in Fig.2. The master interface of the input voltage, is set to PULSE. The purpose of this transient analysis is to study the characteristics of the CMOS inverter for a given with respect to time such as the delay.

(Fig. 3: Transient Analysis, with input and output voltages together)

From this, we can conclude the performance of the inverter. As the transient response of the inverter is printed out, there are delays between the Vin and Vout the. Each inverter has its own delay, depending on the design. To study the delay, we connected a capacitor in parallel with the NMOS transistor. Keeping the load capacitance relatively small is the most effective means of implementing high-performance circuits.

DELAY WITHOUT ADDING THE CAPACITOR

Calculation for calculating tpHL Calculation for calculating tpLH

Input : 50.15 ns Input : 60.05 nsOutput : 50.1874 ns Output: 60.0646 nstpHL : (50.1874 - 50.15) ns tpLH : (60.0646 - 60.05) ns : 0.0374 ns : 0.0146 ns : 37.4 ps : 14.6 ps

(Fig. 4: Magnified in image of Transient Analysis to calculate the tpHL and tpLH)

tp= tphl+tplh2

¿37.4+14.6

2

¿26 ps

We get approximate delay of 25 (+/- 1)ps after matching the tpLH with tpLH.

DELAY AFTER ADDING THE CAPACITOR

The value of the Capacitor: 150 fF

Calculation for calculating tpHL Calculation for calculating tpLH

Input : 30.1783 ns Input : 40.0715 nsOutput : 30.1500 ns Output: 40.0500 nstpHL : (30.1783 - 30.1500) ns tpLH : (40.0715 - 40.050) ns : 0.0283 ns : 0.0215 ns : 28.30 ps : 21.50 ps

(Fig. 5: Magnified in image of Transient Analysis to calculate the tpHL and tpLH)

tp= tphl+tplh2

¿28.3+21.5

2

¿24.90 ps

We get approximate delay of 25 (+/- 1)ps after matching the tpLH with tpHL.

CALCULATING THE POWER Power: 209.4 nW (We have a negative sign upfront because of the direction of the current/voltage). Hence we have taken the absolute value to obtain the value of 209.4 nW, on average, consumed per one time period.

(Fig. 6: Calculating the power of the schematic of inverter in Fig 1)

CALCULATING THE ENERGYEnergy: Power * Time Period (20 ns) : 209.4E-9 * 20E-9 = 4.188 fJ

(Fig. 7: Calculating the energy of the schematic of inverter in Fig 1)

DRC/LVS LAYOUT

We successfully ran the DRC with only 7 errors. Hence, we achieved the minimum error count that it possible. Step-by-step the major parts of the procedure that we used is as follows:

1) Environmental Variable Setup

These are the settings that we used to configure our Environmental Variable setup, as shown on Fig. 8.

(Fig. 8)

2) Schematic Editor XL

The following schematic as shown in Fig. 9 was utilized to run the DRC.

(Fig. 9)

3) Troubleshooting

Within the following Fig.10, on the left, the initial errors that we encountered were shown. The tilt and pin spacing being incompatible were found to be some of the main challenges that we faced.

(Fig. 10)

4) LVS with various components and their respective layers

We adjusted the pin spacing appropriately and made measurements to implement an improved tilt. See Figure 11.

(Fig. 11)

5) Corrections verified with only seven errors

The following figures 12 through 15 show our results in obtaining the minimum number of errors possible from our knowledge.

(Fig. 12)

(Fig. 13)

(Fig. 14)

(Fig. 15)

SUMMARY

Interesting relationships between the theoretical values and actual values obtained from the simulation, were observed. It was necessary to state that the pull-up and pull-down times were approximately equal rather than exactly equal. By relating the load capacitance, propagation delay, pull-up time, and pull-down time from the equations given in chapter five of our textbook, we successfully approximated our pull-down and pull-up times so that our propagation delay was the value of 25ps, as required. We found that using a 2pF load capacitor was necessary to get the correct propagation delay. Through the specific load capacitance value that we used to get our 25ps propagation delay, we generated the general layout of our inverter design and ran the DRC/LVS. The width, W, of our pfet that got us the correct propagation delay was 3µm. Likewise, we needed a width of 1.5µm for our nfet. After computing the average power, the relationship among power, time, and energy was applied to solve for the energy consumed per one time period. Any errors that occurred, may have resulted from the approximations that were taken because it was necessary to approximate our values at times.