ECE 485/585Microprocessor System Design
Lecture 14: Virtual Memory and Paging (cont’d)
Zeshan Chishti
Electrical and Computer Engineering Dept.
Maseeh College of Engineering and Computer Science
Source: Lecture based on materials provided by Mark F.
ECE 485/585
Paging
Segments too large to provide sufficient granularity
entire segment had to be in memory
variable size segments made allocation of physical memory difficult
So… paging was created. The basic idea is:
Virtual addresses mapped to physical addresses through an MMU
Data corresponding to a virtual address may be
in physical memory
on disk
unallocated
…But managing individual addresses is too cumbersome and uses too much memory
Use fixed-length pages – an entire page is mapped and is resident in memory or it is on the disk
Paging worked so well that over time (the “good”) features of segments were incorporated into paging strategies
protection
sharing
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Paging (cont’d)
Virtual Address
01
201
2
Physical memory
disk
Page Table
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Benefits of Paging
Provides every process with large (linear) virtual address space (may be larger than physical memory)
Facilitates code sharing (different virtual addresses can map to same physical address, eliminating need to have multiple copies of shared libraries)
Facilitates position independent code (data/code can be relocated anywhere in physical memory)
Facilitates debugging by providing mechanisms for checking references (e.g. attempts to access unallocated memory, null pointers)
Provides protection from intentional or accidental attempts to access or write memory belonging to another user process (or the OS)
No need to have entire process memory image loaded to begin execution (“demand paging”)
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Benefits of Paging (cont.)
• Programs have illusion of entire potential address space– All programs can start at address (e.g. 0) without being remapped
by loader
• Don’t need contiguous physical memory– Programs can co-exist, be swapped in/out with small granularity
(no holes)
• Facilitates dynamic storage allocation (e.g. malloc)– Simply request more memory, pages allocated as needed
– Physical memory required when used (“demand paged”)
– No need to copy/relocate code or data
• Protection– Hardware assisted range checking via page fault mechanism
– Permissions on per page basis for sharing
– Can detect referencing null pointer
– Prevents accidental or malicious attempts to access memory not owned by process
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Address Translation
A virtual address needs to be translated to a physical address, before the memory is accessed
Each virtual address generated by the processor is interpreted as a virtual page number (high-order bits) plus a offset (low-order bits) that specifies the location of a particular byte within that page
For example, if the processor uses 40 address bits and the page size is 4 kBytes, then the address bits are interpreted as follows:
The first step in address translation is to break down a virtual address into the above two fields
Virtual Page Number Offset
28 bits 12 bits
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Address Translation (cont.)
Information about each virtual page is kept in the page table Conceptually the page table has one entry for each virtual page
Is the virtual page currently mapped into the main memory? If yes, what is the main memory address where the page is mapped
to? Current status of the page (dirty, LRU etc.)
Starting address of the page table is kept in page table base register
Virtual page number generated by the processor is added to the contents of the page table base register
This provides the address of the corresponding entry in the page table
The contents of this page table entry provide the starting address of the page if the page is currently in the main memory
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Paging
Physical memory
disk
Page frame
Virtual page number offset
Virtual address
031
031 1112
12 bitsPage size 212 = 4K
20 bitsNumber of Pages
220 = 1M
01
4095
Page Table
0
1
1M - 1
01
4095
+
Page fault if page not in memory when referenced• Interrupt/trap occurs• OS handles by
suspending processscheduling disk I/O (“page in”)
• may require “page out” of another page
Page table contains PTEs (page table entries)• (Base) address of page frame if in memory• Disk address if not• Valid bit
PTE Page frame address
unallocated
1
0
1
0
1
V
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Paging (cont’d)
Physical memory
disk
01
4095
Page Table (Process A)
01
4095
Page frame addressPOSGWDUC
Page frame addressPOSGWDUC
Sharedpage
• Cacheable• Used Recently• Dirty (written)• Writeable• Global• OS/User code• Present in
memory
Page Table (Process B)
Page table base register Loaded by OS on process switch
Page Tables
Page Table Entry
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Similarities to Caching
“Present” bit “Valid” bit
VM: Indicates whether page is present in memory
Cache: Indicates whether line in cache is valid
Page Fault Cache Miss
VM: Page not resident in memory, page in from disk
Cache: Line not in cache, cache line fill from next level memory
Insufficient memory for new page Cache collision
VM: Insufficient physical memory for page from disk
Cache: All “ways” in cache occupied for this index
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Similarities to Caching (cont’d)
Need to identify page to be over-written Victim
VM: Page replacement algorithms
Cache: Cache line replacement algorithms (LRU)
Need to save information to make room for new information
VM: Write modified pages to memory or disk
Cache: Write Back line
“Dirty” bit to indicate page has been written to Modified bit
No need to write out “clean” pages
No need to write back unmodified lines
Need to avoid “thrashing”
VM: Avoid repeatedly swapping pages to/from disk
Cache: Avoid repeatedly replacing cache lines
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Types of Page Tables: Flat
Flat
Large!
Proportional to VA space
May be too big for physicalmemory
Virtual Address
012
012
Physical memory
diskNeed to account for total virtual addressspace
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Types of Page Tables: Hierarchical
Page frame
Physical address (if present in memory)
Physical address (if present in memory)
Pointer to base of Page Directory
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“Walking” the Page Table
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Page Table Lookup
Each process requires its own page tables. Base address loaded on process switch.
Page Tables can be paged…and cached!Page Table directory can be cached but not paged. Why not?
Total memory needed to store paging structures for fully allocated system = 4.4MB4 bytes for each PTDE or PTE1 page table directory w/ 1024 entries = 4K1K page tables each with 1K entries (4 bytes/ea) = 4M
But… Page directory can be “sparse” – so don’t require all page tables to be allocated. For example, assuming a single process ran in a 4M virtual memory space = Total: 8KB of tables1 page directory = 4K 1 page table of 1K entries each pointing to a
4K page = 4K
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Translation Lookaside Buffer (TLB)
Walking the page table would require multiple memory accesses for each memory reference.
TLB is a cache of most recently used virtual physical address mappings.
Done in parallel with access via paging unit. Single TLB shared by all processes, so must flush the TLB on a context switch (each process has own linear physical address mapping!)
Lookup is in hardware, but maintenance (flush on context swap, replacement algorithm on miss, page table walking) can be handled in hardware (e.g. PowerPC, Intel x86) or software (Sparc, MIPS, ARM)
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TLB (cont’d)
Page Table (Process A)
Page Table (Process B)
Page frame addr.POSGWDUCVirtual page number
virtual page number offset
Virtual address
031
031 1112
TLB (cache) lookup [often fully associative]
If entry present in TLB, don’t need to walk the page tableIf not present
Walk the page tableEvict an entry from TLBInsert new mapping
Flush TLB (except for Global pages) whenever process switch!
Tag + V
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TLB (cont’d)
Page frame addr.POSGWDUCVirtual page number
virtual page number offset
Virtual address
031
031 1112
TLB (cache) lookup [often fully associative]
By including ASID in tag we can allow PTEs from different processesto remain in the TLB to improve performance. No longer need to flushTLB on context switch. [Used in MIPS, Alpha, Sparc]. Global bit (G)avoids ASID comparison (OS, shared libraries)
ASID
ASID
Address SpaceIdentifier
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Page Table vs. TLB
Page table(s)
Provide translation from virtual to physical address if resident in memory
Indicates where page can be found on swap device (backing store) if not resident in memory
Translation lookaside buffer (TLB)
A cache of translations from virtual address to physical address
Same protection bits, etc. as in the page table entry
Hardware/software cooperation
TLB in hardware
Page table look up in hardware or software
Page table management in software
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Paging and Caching
virtualphysical
physical
virtual
tag
index
Disadvantage:Virtual address must be translated to physical address firstMust wait for TLB translation (or page table walk if miss)
SolutionSize cache so that virtual page offsetis same size as cache line index
Cache and TLB lookup in parallel
Physically Tagged – Physically Indexed
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Paging and Caching (cont’d)
virtualphysical
physical
virtual
tag
index
AdvantageNo TLB required
Can use on cache missMust store ASID in cache
Different processes can use same virtualaddress for different physical locations
DisadvantageAliasing (Synonyms)Different virtual addresses can map to samephysical address at different cache locations!
Virtually Tagged – Virtually Indexed
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Pentium Address Translation
CPU
VPN VPO
20 12
TLBT TLBI
416
...
TLB (16 sets, 4 entries/set)VPN1 VPN2
1010
PDE PTE
PDBR
PPN PPO
20 12
Page tables
TLB
miss
TLB
hit
Physical
address
(PA)
Result
32
...
CT CO
20 5
CI
7
L2 and
Main memory
L1 (128 sets, 4 lines/set)
L1
hit
L1
miss
Virtual (Linear) Address
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Intel Nehalem and AMD Opteron
