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ECE 550D Fundamentals of Computer Systems and Engineering Fall 2017 Instruction Set Architectures (ISAs) and MIPS Prof. John Board Duke University Slides are derived from work by Profs. Tyler Bletsch and Andrew Hilton (Duke)
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ECE 550DFundamentals of Computer Systems and Engineering

Fall 2017

Instruction Set Architectures (ISAs) and MIPS

Prof. John BoardDuke University

Slides are derived from work byProfs. Tyler Bletsch and Andrew Hilton (Duke)

2

Last time…

• Who can remind us what we did last time?• Finite State Machines• Division

3

Now: Moving to software

• C is pretty low level• Most of you: in 551, can program in C

• Others: assume you know programming, pointers, etc.• But compiled into assembly…

• Lower level programming• What does assembly look like?• How does software communicate with hardware?• What variations can there be?• Advantages/disadvantages?

4

Assembly

• Assembly programming:• 1 machine instruction at a time• Still in “human readable form”

• Much “lower level” than any other programming• Limited number of registers vs unlimited variables• Ability to access memory with some work

“Register 1”How to say “\$1” out loud:

5

Registers

• Two places processors can store data• Registers (saw these---sort of):

• In processor• Few of them (e.g., 32 – typically more than the 1 in the

protocomputer!)• Fast (more on this much later in semester)

• Memory (later):• Outside of processor• Huge (e.g., 4-64GB)• Slow (generally about 100—200x slower than registers, more later)

• For now: think of registers like “variables”• But only 32 of them• E.g., \$1 = \$2 + \$3 much like x = y + z

6

Simple, Running Example

// silly C code

int sum, temp, x, y;while (true){

temp = x + y;sum = sum + temp;

}

// equivalent MIPS assembly code

loop: lw \$1, Memory[1004]lw \$2, Memory[1008]add \$3, \$1, \$2add \$4, \$4, \$3j loop

OK, so what does this assembly code mean?Let’s dig into each line …

(And note the C code is terrible – didn’t initialize sum or x or y! Infinite loop that will eventually overflow unless they are all 0 to start)

Memory references don’t quite work like this…we’ll

correct this later.

7

Simple, Running Example

loop: lw \$1, Memory[1004] lw \$2, Memory[1008]add \$3, \$1, \$2add \$4, \$4, \$3j loop

NOTES“loop:” = line label (in case we need to refer to this instruction’s PC)lw = “load word” = read a word (32 bits) from memory\$1 = “register 1” à put result read from memory into register 1Memory[1004] = address in memory to read from (where x lives)

Note: almost all MIPS instructions put destination (where result gets written) first (in this case, \$1)

But also note every assembly language is different – some give source first, destination last!

8

Simple, Running Example

loop: lw \$1, Memory[1004] lw \$2, Memory[1008]add \$3, \$1, \$2add \$4, \$4, \$3j loop

NOTESlw = “load word” = read a word (32 bits) from memory\$2 = “register 2” à put result read from memory into register 2Memory[1008] = address in memory to read from (where y lives)

9

Simple, Running Example

loop: lw \$1, Memory[1004] lw \$2, Memory[1008]add \$3, \$1, \$2add \$4, \$4, \$3j loop

NOTESadd \$3, \$1, \$2= add what’s in \$1 to what’s in \$2 and put result in \$3

10

Simple, Running Example

loop: lw \$1, Memory[1004] lw \$2, Memory[1008]add \$3, \$1, \$2add \$4, \$4, \$3j loop

NOTESadd \$4, \$4, \$3= add what’s in \$4 to what’s in \$3 and put result in \$4

Note: this instruction overwrites previous value in \$4

11

Simple, Running Example

loop: lw \$1, Memory[1004] lw \$2, Memory[1008]add \$3, \$1, \$2add \$4, \$4, \$3j loop

NOTESj = “jump”loop = PC of instruction at label “loop” (the first lw instruction above)sets next PC to the address labeled by “loop”

Note: all other instructions in this code set next PC = PC++ (actually PC=PC+4 to be precise since MIPS is byte-oriented machine with 32 bit words and 32 bit instructions)

12

Assembly too high level for machine

• Human readable is not (easily) machine executable• add \$1, \$2, \$3

• Instructions are numbers too!• Bit fields (like FP numbers)

• Instruction Format• Establishes a mapping from “instruction” to binary values• Which bit positions correspond to which parts of the instruction

(operation, operands, etc.)• In MIPS, each assembly instruction has a unique 32-bit

representation:• add \$3, \$2, \$7 ßà 00000000010001110001100000100000

• lw \$8, Mem[1004] ßà 10001100000010000000001111101100

• Assembler does this translation• Humans don’t typically need to write raw bits

13

Compilers vs Assemblers

• Compilers translate high level language code into assembly –HARD to write a compiler, VERY HARD to write a good compiler

• Assemblers translate assembly language code into machine code – EASY to write – 1-to-1 translation, lots of table lookup, don’t need to perform great insights to write an assembler!

14

What Must be Specified?

• Instruction “opcode”• What should this operation do? (add, subtract,…)

• Location of operands and result• Registers (which ones?)• Memory (what address?)• Immediates, i.e. constants included with the instruction

(protocomputer couldn’t do this!) (what value?)• Data type and Size – a single bit? A byte? A 32 bit word? A

64 bit double precision number?• Usually included in opcode• E.g., signed vs unsigned int (if it matters)

• What instruction comes next?• Sequentially next instruction by default, or jump (conditional or

not) elsewhere

15

The ISA

• Instruction Set Architecture (ISA)• Contract between hardware and software• Specifies everything hardware and software need to agree on

• Instruction encoding and effects• Memory endian-ness (discussed before?)• (lots of other things that won’t make sense yet)

• Many different ISAs• x86 and x86_64 (Intel and AMD)• POWER (IBM)• MIPS• ARM• SPARC (Oracle)

16

Endian-ness

• Big-Endian • Little-Endian

Problem: how do you store a 32 bit number, say 0x12345678, starting at location 0 in a byte-addressable memory?

Address Value (hex)0003 780002 560001 340000 12

Address Value (hex)0003 120002 340001 560000 78

Big Endian Byte Order: The most significant byte (the "big end") of the data is placed at the byte with the lowest address. The rest of the data is placed in order in the next three bytes in memory.Little Endian Byte Order: The least significant byte (the "little end") of the data is placed at the byte with the lowest address. The rest of the data is placed in order in the next three bytes in memory.

17

Our focus: MIPS

• We will work with MIPS – the name of a computer processor originating as a class project at Stanford University, turned into the MIPS computer company which commercialized it• Intel x86 assembly is ugly and complicated (x86_64 is less ugly, but

still nasty)• MIPS is relatively “clean” and easy, with a very elegant assembly

language• More on this in a minute

18

But I don’t have a MIPS computer?

• We’ll be using SPIM• Simulates the MIPS

• Command line version: spim• Graphical version: qtspim

• Edit in emacs, run in SPIM• Or the editor of your choice-• Professor Hilton wrote this!

19

ISAs: RISC vs CISC

• Two broad categories of ISAs:• Complex Instruction Set Computing

• Came first, days when people always directly wrote assemblyarchitects were trying to bridge the gap between assembly and high level languages to simplify complier writing

• Big complex instructions • Reduced Instruction Set Computing – popularized by Hennessy and

Patterson, your textbook authors, at Stanford and Berkeley respectively in the 1980s.

• Goal: make hardware simple and fast• Write in high level language, let compiler do the dirty work

• Rely on compiler to optimize for you• Note:

• Sometimes fuzzy: ISAs may have some features of each• Common mis-conception: not about how many different instructions!

20

ISAs: RISC vs CISC

Reduced Instruction Set Computing• Simple, fixed length instruction encoding• Few memory addressing modes• Instructions have one effect• “Many” registers (e.g., 32)• Three-operand arithmetic (dest = src1 op src2)• Load-store ISA – defined below

21

ISAs: RISC vs CISC

• Complex Instruction Set Computing• Variable length instruction encoding (sometimes quite complex)• Many addressing modes, some quite complex• Side-effecting and/or complex instructions • Few registers (e.g., 8)• Various operand models

• Stack • Two-operand (dest = src op dest)• Implicit operands

• Can operate directly on memory• Register = Memory op Register• Memory = Memory op Register• Memory = Memory op Memory

22

• Memory location: how to specify address

• Simple (RISCy)• Register + Immediate (e.g., address = \$4 + 16)• Register + Register (e.g., address= \$4 + \$7)

• Complex (CISCy)• Auto-increment (e.g., address = \$4; \$4 = \$4 + 4;)• Scaled Index (e.g., address = \$4 + (\$2 <<2) + 0x1234)• Memory indirect (e.g., address = memory[\$4])

23

• Contrast with• General memory operands (\$4 = mem[\$5] + \$3)• Memory/memory operations: mem[\$4] = mem[\$5] + \$3

24

Stored Program Computer

• Instructions: a fixed set of built-in operations

• Instructions and data are stored in memory• Allows general purpose computation!

• Fetch-Execute Cyclewhile (!done)

fetch (and decode) instruction

execute instruction

• Effectively what hardware does• This is what the SPIM Simulator does

Stack

Code

Static Data

Heap

25

How are Instructions Executed?

• Instruction Fetch: Read instruction bits from memory

• Decode:Figure out what those bits mean

• Operand Fetch:Read registers (+ mem to get sources)

• Execute:Do the actual operation (e.g., add the #s)

• Result Store:Write result to register or memory

• Next Instruction:Figure out mem addr of next insn, repeat

InstructionFetch

InstructionDecode

OperandFetch

Execute

ResultStore

NextInstruction

26

More Details on Execution?

• Previous slides high level overview• Called von Neumann model• John von Neumann: Eniac• Stored program computer: both the program and the data the program

operates on are stored in the same memory – breakthrough idea• More details: How hardware works

• Later in the course

• Now, diving into assembly programming/MIPS

27

Assembly Programming

• How do you write an assembly program?

• How do you write a program (in general)?

28

5 Step Plan (ECE 551)

• 5 Steps to write any program:1. Work an example yourself2. Write down what you did3. Generalize steps from 24. Test generalized steps on different example5. Translate generalized steps to code

29

How to Write a Program

• How Prof. Hilton teaches programming:1. Work an example yourself2. Write down what you did3. Generalize steps from 24. Test generalized steps on different example5. Translate generalized steps to code

Develop Algorithm In (Familiar) HigherLevel Language

Then translate to lower level language

30

Why do I bring this up? <end day 1>

• Very Hard:

• Easier:

ProblemCorrectly Working

Assembly

ProblemCorrectly Working

AssemblyAlgorithmHigh-level

Language or pseudo-code

Implementation

31

Our focus

• We will focus on the assembly step• Assume you know how to devise an algorithm for a problem

• I’ll use C.

ProblemCorrectly Working

AssemblyAlgorithmHigh-level Language

Implementation

32

Simplest Operations We Might Want?

• What is the simplest computation we might do?• Add two numbers:

x = a + b;add \$1, \$2, \$3

“Add \$2 + \$3, and store it in \$1”

Note: when writing assembly, basically pick reg for a, reg for b, reg for xWe have 32 registers (really 28 – four of them are special) - Not enough

regs for all variables? We’ll talk about that later…

33

MIPS Integer Registers

• Recall: registers• Fast• In CPU• Directly compute on them

• R0 is a special case – hardwired to 0• Because 0 is such an important constant

• Leaving 31 x 32-bit GPRs • Also floating point registers• A few special purpose regs too

• PC = Address of next insn, not part of the 32

34

\$0 0000 0000

\$1 1234 5678

\$2 C001 D00D

\$4 9999 9999

\$5 ABAB ABAB

\$6 0000 0001

\$7 0000 0002

\$8 0000 0000

\$9 0000 0000

\$10 0000 0000

\$11 0000 0000

\$12 0000 0000

… …

PC 0000 1000

Instruction

100C …

1010 …

PC tells us where to execute next

35

\$0 0000 0000

\$1 1234 5678

\$2 C001 D00D

\$4 9999 9999\$5 ABAB ABAB

\$6 0000 0001\$7 0000 0002

\$8 0000 0000

\$9 0000 0000

\$10 0000 0000

\$11 0000 0000

\$12 0000 0000

… …

PC 0000 1000

100C …

1010 …

9999 99990000 00019999 999A

36

\$0 0000 0000

\$1 1234 5678

\$2 C001 D00D

\$4 9999 9999

\$5 ABAB ABAB

\$6 0000 0001

\$7 0000 0002

\$8 9999 999A\$9 0000 0000

\$10 0000 0000

\$11 0000 0000

\$12 0000 0000

… …

PC 0000 1000

100C …

1010 …

Add writes its result to its destination register

37

\$0 0000 0000

\$1 1234 5678

\$2 C001 D00D

\$4 9999 9999

\$5 ABAB ABAB

\$6 0000 0001

\$7 0000 0002

\$8 9999 999A

\$9 0000 0000

\$10 0000 0000

\$11 0000 0000

\$12 0000 0000

… …

PC 0000 1004

100C …

1010 …

And goes to the sequentially next instruction(PC = PC + 4)

38

\$0 0000 0000

\$1 1234 5678

\$2 C001 D00D

\$4 9999 9999

\$5 ABAB ABAB

\$6 0000 0001

\$7 0000 0002

\$8 9999 999A

\$9 0000 0000

\$10 0000 0000

\$11 0000 0000

\$12 0000 0000

… …

PC 0000 1004

100C …

1010 …

You all do the next instruction!

39

\$0 0000 0000

\$1 1234 5678

\$2 C001 D00D

\$4 9999 9999

\$5 9999 999C\$6 0000 0001

\$7 0000 0002

\$8 9999 999A

\$9 0000 0000

\$10 0000 0000

\$11 0000 0000

\$12 0000 0000

… …

PC 0000 1008

100C …

1010 …

We set \$5 equal to \$8 (9999 999A) + \$7 (2) = 9999 999C

and PC = PC +4

40

\$0 0000 0000

\$1 1234 5678

\$2 C001 D00D

\$4 9999 9999

\$5 9999 999C

\$6 0000 0001

\$7 0000 0002

\$8 9999 999A

\$9 0000 0000

\$10 0000 0000

\$11 0000 0000

\$12 0000 0000

… …

PC 0000 1008

100C …

1010 …

Its perfectly fine to have \$6 as a src and a dstThis is just like x = x + x; in C, Java, etc:

1 + 1 = 2

41

\$0 0000 0000

\$1 1234 5678

\$2 C001 D00D

\$4 9999 9999

\$5 9999 999C

\$6 0000 0002\$7 0000 0002

\$8 9999 999A

\$9 0000 0000

\$10 0000 0000

\$11 0000 0000

\$12 0000 0000

… …

PC 0000 100C

100C …

1010 …

Its perfectly fine to have \$6 as a src and a dstThis is just like x = x + x; in C, Java, etc:

1 + 1 = 2

42

MIPS Instruction Formats

R-type: Register-Register

Op31 26 01516202125

Rs Rt shamtRd func561011

Op

31 26 01516202125

Rs Rt immediate

I-type: Register-Immediate

Op

31 26 025target

J-type: Jump / Call

TerminologyOp = opcodeRs, Rt, Rd = register specifierImmediate – 16 bit constant included with the instruction itselfTarget – 26 bits used to compute a jump addressShamt – Shift Amount, if relevantFunc – essentially a second opcode if relevant

43

op a 6-bit operation code.rs a 5-bit source register.rt a 5-bit target (source) register.rd a 5-bit destination register.shmt a 5-bit shift amount.func a 6-bit function field.

Example: add \$1, \$2, \$3 (yes we write it and store it in different orders!)

R Type: <OP> rd, rs, rt

op rs rt rd shmt func000000 00010 00011 00001 00000 100000

R-type: Register-Register

Op31 26 01516202125

Rs Rt shamtRd func561011

44

Register Value\$0 0000 0000\$1 1234 5678\$2 C001 D00D\$3 1BAD F00D\$4 9999 9999\$5 9999 999C\$6 0000 0002\$7 0000 0002\$8 9999 999A\$9 0000 0000\$10 0000 0000… …PC 0000 100C

Address Instruction Insn Val in Hex

1000 add \$8, \$4, \$6 0086 40201004 add \$5, \$8, \$7 0107 28201008 add \$6, \$6, \$6 00C6 3020100C … …

1010 … …

Remember: all instructions and our most common data types are all exactly 32 bits (or 4 bytes) long

45

qtspim: Shows you similar state

Registers

Data memory is in this tab Your program is in the “text” region of memory

Code

46

Other Similar Instructions

• sub \$rDest, \$rSrc1, \$rSrc2

• mul \$rDest, \$rSrc1, \$rSrc2 (pseudo instruction)• div \$rDest, \$rSrc1, \$rSrc2 (pseudo instruction)• and \$rDest, \$rSrc1, \$rSrc2• or \$rDest, \$rSrc1, \$rSrc2

• xor \$rDest, \$rSrc1, \$rSrc2• …

• End of Appendix B: listing of all instructions• Good reference, don’t need to read every insn• Will provide insn reference on tests

47

Pseudo Instructions

• Some “instructions” are pseudo instructions for the convenience of assembly language programmers

• Actually assemble into 2 instructions:

• mul \$1, \$2, \$3 is reallymul \$2, \$3mflo \$1

• mul takes two srcs, writes special regs lo and hi• Because when you multiply 2 32 bit numbers, how long is the answer?

• Lowest 32 bits to low, highest 32 bits to hi• Lo and hi are not part of the 32 register GPR set, they are separate

• mflo moves from lo into dst reg – is a real instruction• Since more than 32 bits in the answer might be mathematically correct

but also might be an overflow• If overflow matters, need to see if any bit in hi is ”1” before continuing

48

Pseudo Instructions

• Div – similar issues but for quotient and remainder• div \$t1, \$t2, \$t3 will set \$t1 to the integer division

of \$t2/\$t3 (which is the real instruction div \$t2 \$t3)

• So all ”real” instructions take 32 bits to store, but pseudo instructions sometimes get translated into 2 (or in principle more) actual instructions to make certain frequently performed groups of operations easier to write. (Some pseudo instructions just rename single instructions - below!)

• And poor design in my view to have same name be both real and pseudo instruction, difference is 2 or 3 operands

49

What if I want to add a constant?

• Suppose I need to do• x = x + 1

• Idea one: Put 1 in a register, use add• Problem: How to put 1 in a register?

• Idea two: Have instruction that adds an immediate• Note: also solves problem in idea one

50

• Immediate: 16 bit value

I-Type <op> rt, rs, immediate

op rs rt immediate001000 00010 00001 0000 0000 0110 0100

Op

31 26 01516202125

Rs Rt immediate

I-type: Register-Immediate

51

Using addi to put a constant in register

• Can use addi to put a constant into a register:• x = 42;• Can be done with • addi \$7, \$0, 42• Because \$0 is always 0.

• Common enough it has its own pseudo instruction:• li \$7, 42• Stands for load immediate, works for 16-bit immediate

• Note this pseudo-instruction only takes one real instruction to implement, but makes your code more readable

52

Many instructions have Immediate Forms

• Add is not the only one with an immediate form• andi, ori, xori, sll, sr, sra, …

• No subi• Why not?

• No muli or divi• Though some ISAs have them

53

Assembly programming something “useful”

•Consider the following C fragment:

int tempF = 87;

int a = tempF – 32;a = a * 5;

int tempC = a / 9;

•Lets write assembly for it• First, need registers for our variables:

• tempF = \$3• a = \$4• tempC = \$5

• Now, give it a try (use \$6, \$7,… as temps if you need)…• (This code did not check for overflows)

li \$3, 87

li \$6, 5mul \$4, \$4, \$6

li \$6, 9div \$5, \$4, \$6

54

Accessing Memory

• MIPS is a “load-store” ISA• Who can remind us what that means?• Only load and store instructions access memory• (and that is all those instructions do)

• Contrast to x86, which allows• add reg = (memory location) + reg

• Or even• add (memory location) = (memory location) + reg• add (memory location) = (memory location) + (memory location)

• And worse in architectures with direct support for pointers!

55

Back to the Simple, Running Example

• assume \$6=1004=address of variable x in C code example• and recall that 1008=address of variable y in C code example

loop: lw \$1, Memory[1004] à lw \$1, 0(\$6) # put val of x in \$1lw \$2, Memory[1008] à lw \$2, 4(\$6) # put val of y in \$2add \$3, \$1, \$2add \$4, \$4, \$3j loop

Register 6 is filling the role of a pointer in c: \$6 = &x, and we know (somehow) that y is stored consecutively in memory after x

56

• Load Word Example• lw \$1, 100(\$2) # \$1 = Mem[\$2+100]

I-Type <op> rt, rs, immediate

Register +

Memory

Register

op rs rt immediate100011 00010 00001 0000 0000 0110 0100

Op31 26 01516202125

Rs Rt immediate

I-type: Register-Immediate

57

• Store Word Example• sw \$1, 100(\$2) # Mem[\$2+100] = \$1

I-Type <op> rt, rs, immediate

Register +

Memory

Register

op rs rt immediate101011 00010 00001 0000 0000 0110 0100

Op31 26 01516202125

Rs Rt immediate

I-type: Register-Immediate

58

Data sizes / types

• Loads and Stores come in multiple sizes• Reflect different data types

• The w in lw/sw stands for “word” (= 32 bits)• Can also load bytes (8 bits), half words (16 bits)• Smaller sizes have signed/unsigned forms• See Appendix B for all variants

59

# in \$1# in \$2# in \$3…lw \$1, 0(\$2)lw \$4, 0(\$3)sw \$1, 0(\$4)lw \$2, 0(\$3)sw \$1, 16(\$2)

• int x• int * p• int ** q• …• x = *p;• **q = x;

• p = *q;• p[4] = x;

Nb p[4] is fifth element of array originating at p (since first element is p[0])

60

Executing Memory OpsRegister Value\$0 0000 0000\$1 1234 5678\$2 0000 8004\$3 0000 8010\$4 9999 9999\$5 9999 999C\$6 0000 0002\$7 0000 0002\$8 9999 999A\$9 0000 0000\$10 0000 0000\$11 0000 0000\$12 0000 0000… …PC 0000 1000

1000 lw \$1, 0(\$2)

1004 lw \$4, 4(\$3)

1008 sw \$1, 8(\$4)

100C lw \$2, 0(\$3)

1010 …

… …8000 F00D F00D8004 C001 D00D8008 1234 43218010 4242 42428014 0000 8000

61

Executing Memory OpsRegister Value\$0 0000 0000\$1 C001 D00D\$2 0000 8004\$3 0000 8010\$4 9999 9999\$5 9999 999C\$6 0000 0002\$7 0000 0002\$8 9999 999A\$9 0000 0000\$10 0000 0000\$11 0000 0000\$12 0000 0000… …PC 0000 1004

1000 lw \$1, 0(\$2)

1004 lw \$4, 4(\$3)

1008 sw \$1, 8(\$4)

100C lw \$2, 0(\$3)

1010 …

… …8000 F00D F00D8004 C001 D00D8008 1234 43218010 4242 42428014 0000 8000

62ECE 550 (Hilton): ISA/MIPS 62

Executing Memory OpsRegister Value\$0 0000 0000\$1 C001 D00D\$2 0000 8004\$3 0000 8010\$4 0000 8000\$5 9999 999C\$6 0000 0002\$7 0000 0002\$8 9999 999A\$9 0000 0000\$10 0000 0000\$11 0000 0000\$12 0000 0000… …PC 0000 1008

1000 lw \$1, 0(\$2)

1004 lw \$4, 4(\$3)

1008 sw \$1, 8(\$4)

100C lw \$2, 0(\$3)

1010 …

… …8000 F00D F00D8004 C001 D00D8008 1234 43218010 4242 42428014 0000 8000

63

Executing Memory OpsRegister Value\$0 0000 0000\$1 C001 D00D\$2 0000 8004\$3 0000 8010\$4 0000 8000\$5 9999 999C\$6 0000 0002\$7 0000 0002\$8 9999 999A\$9 0000 0000\$10 0000 0000\$11 0000 0000\$12 0000 0000… …PC 0000 100C

1000 lw \$1, 0(\$2)

1004 lw \$4, 4(\$3)

1008 sw \$1, 8(\$4)

100C lw \$2, 0(\$3)

1010 …

… …8000 F00D F00D8004 C001 D00D8008 C001 D00D8010 4242 42428014 0000 8000

64

Executing Memory OpsRegister Value\$0 0000 0000\$1 C001 D00D\$2 4242 4242\$3 0000 8010\$4 0000 8000\$5 9999 999C\$6 0000 0002\$7 0000 0002\$8 9999 999A\$9 0000 0000\$10 0000 0000\$11 0000 0000\$12 0000 0000… …PC 0000 1010

1000 lw \$1, 0(\$2)

1004 lw \$4, 4(\$3)

1008 sw \$1, 8(\$4)

100C lw \$2, 0(\$3)

1010 …

… …8000 F00D F00D8004 C001 D00D8008 C001 D00D8010 4242 42428014 0000 8000

65

Making control decision

• Control constructs—decide what to do next:

if (x == y) {

…}

else {…

}…

while (z < q) {

…}

InstructionFetch

InstructionDecode

OperandFetch

Execute

ResultStore

NextInstruction

66

The Program Counter (PC)

• Special register (PC) that points to instructions• Contains memory address (like a pointer)• Instruction fetch is

• inst = mem[pc]• So far, have fetched sequentially: PC= PC + 4

• Assumes 4 byte insns• True for MIPS• X86: variable size (nasty)

• May want to specify non-sequential fetch• Change PC in other ways• Problem: can’t fit complete 32 bit jump address into a single

instruction! (not a problem on machines with variable length instructions…)

67

• PC relative addressing (the +4 is critical! From fetch)• Branch Not Equal Example• bne \$1, \$2, 100 # If (\$1!= \$2) goto [PC+4+400] , i.e.

branch 100 instructions ahead of the next instruction

I-Type <op> rt, rs, immediate (resume here)

PC ++

4

Op31 26 01516202125

Rs Rt immediate

I-type: Register-Immediate

<<2Reg Reg

!=ß What’s this???

68

MIPS Compare and Branch

• Compare and Branch [really asking is (rs-rt) = or != 0]• beq rs, rt, offset • bne rs, rt, offset

• Compare to zero and Branch• blez rs, offset• bgtz rs, offset• bltz rs, offset• bgez rs, offset

• Also pseudo instruction for unconditional branch (b)

69

MIPS jump, branch, compare instructions

• Inequality to something other than 0: require 2 insns• Conditionally set reg, branch if not zero or if zero

• slt \$1,\$2,\$3 \$1 = (\$2<\$3) ? 1 : 0 “Set if Less Than”• Compare less than; signed 2’s comp.

• slti \$1,\$2,100 \$1 = (\$2 < 100) ? 1 : 0 • Compare < constant; signed 2’s comp.

• sltu \$1,\$2,\$3 \$1 = (\$2 < \$3) ? 1 : 0 • Compare less than; unsigned

• sltiu \$1,\$2,100 \$1 = (\$2 < \$3) ? 1 : 0 \$1=0• Compare < constant; unsigned

• beqz \$1,100 if (\$1 == \$2) go to PC+4+400• Branch if equal to 0

• bnez \$1,100 if (\$1!= \$2) go to PC+4+400• Branch if not equal to 0

70

• \$1= 0…00 0000 0000 0000 0001• \$2= 0…00 0000 0000 0000 0010• \$3= 1…11 1111 1111 1111 1111• After executing these instructions:

slt \$4,\$2,\$1

slt \$5,\$3,\$1sltu \$6,\$2,\$1

sltu \$7,\$3,\$1

• What are values of registers \$4 - \$7? Why?\$4 = ; \$5 = ; \$6 = ; \$7 = ;

Signed vs. Unsigned Comparison

71

• \$1= 0…00 0000 0000 0000 0001• \$2= 0…00 0000 0000 0000 0010• \$3= 1…11 1111 1111 1111 1111• After executing these instructions:

slt \$4,\$2,\$1

slt \$5,\$3,\$1sltu \$6,\$2,\$1

sltu \$7,\$3,\$1

• What are values of registers \$4 - \$7? Why?\$4 = 0 ; \$5 = 1 ; \$6 = 0 ; \$7 = 0 ;

Signed vs. Unsigned Comparison

72

//assume x in \$1//assume y in \$2//assume z in \$3…beq \$1,\$2, 2addi \$3, \$3, 2b 1

b is branch pseudo-op

C and Assembly with branches

int x;

int y;int z;

…if (x != y) {

z = z + 2;}

else {z = z -4;

}

73

//assume x in \$1//assume y in \$2//assume z in \$3…beq \$1, \$2, L_elseaddi \$3, \$3, 2b L_end

L_end:

Labels

• Counting insns?• Error prone• Tricky: pseudo-insns• Un-maintainable

• Better: let assembler count• Use a label• Symbolic name for target• Assembler computes offset

• And always gets the pesky “+4” correct!

• And knows when you’ve used a pseudo-op (what if addi here were 3 op mult)

74

• 16-bit immediate limits to +/- 32K instructions• Usually fine, but sometimes need more…• J-type instructions provide longer range, unconditional jump:

• Specifies lowest 28 bits of PC• Upper 4 bits unchanged• Range: 64 Million instruction (256 MB)• Definitely want assembler helping you to compute the address!

• Can jump anywhere in 32 bit space with jr \$reg (jump register) : pc ß \$reg (actual address, not instruction count, etc)

J-Type <op> immediate

Op

31 26 025target

J-type: Jump / Call

75

Remember our F2C program fragment?

• Consider the following C fragment:

int tempF = 87; li \$3, 87int a = tempF – 32; addi \$4, \$3, -32

a = a * 5; li \$6, 5mul \$4, \$4, \$6

int tempC = a / 9; li \$6, 9div \$5, \$4, \$6

• If we were really doing this… We would write a function to convert f2c and call it

76

More likely: a function, or subroutine

• Like this:int f2c (int tempF) {

int a = tempF – 32;

a = a * 5; int tempC = a / 9;

return tempC;}

……

int tempC = f2c(87);

77

First, how does a “normal” computer do functions / subroutines?

• Back to protocomputer for a few minutes on the board

78

On MIPS now: Need a way to call f2c and return

• Call: Jump… but also remember where to go back• May be many calls to f2c() in the program• Need some way to know where we were• Instruction for this jal• jal label

• Store PC +4 into register \$31 (hardwired for this function)• Jump to label

• Return: Jump… back to wherever we were• Instruction for this jr• jr \$31• Jump back to address stored by jal in \$31

• WARNING: MIPS does subroutines differently from every other computer I know! And I know a lot of computers!

• SO FAR, NO SUPPORT FOR NESTED OR RECURSIVE CALLS!

79

More likely: a function to convert

•Like this:int f2c (int tempF) {

int a = tempF – 32;

a = a * 5; int tempC = a / 9;

return tempC;} //jr \$31……

int tempC = f2c(87); //jal f2c

•But that’s not all…

80

More likely: a function to convert

•Like this:int f2c (int tempF) {

int a = tempF – 32;

a = a * 5; int tempC = a / 9;

return tempC;} //jr \$31……

int tempC = f2c(87); //jal f2c

•Need to pass 87 as argument to f2c

81

More likely: a function to convert

•Like this:int f2c (int tempF) {

int a = tempF – 32;

a = a * 5; int tempC = a / 9;

return tempC;} //jr \$31……

int tempC = f2c(87); //jal f2c

•Need to return tempC to caller

82

More likely: a function to convert

•Like this:int f2c (int tempF) {

int a = tempF – 32;

a = a * 5; int tempC = a / 9;

return tempC;} //jr \$31……

int tempC = f2c(87); //jal f2c

•Also, may want to use same registers in multiple functions• What if f2c called something? Would re-use \$31 (i.e. overwrite and

destory)

83

Calling Convention

• “Normal” computers often used the stack for all argument and result passing, but Hennessy et al. determined most functions need a small number of arguments and pass back a small number of results, arguing for making the common case fast

• All of these are reasons for a calling convention for functions• (Most of it) Not part of the hardware design per se, just an agreement

that programmers have made as to wise ways to use this ISA so my code will be interoperable with yours

• Agreement of how registers are used• Where arguments are passed, results returned• Who must save what if they want to use it• Etc..

84

16 s0 callee saves. . .

23 s7

24 t8 temporary (cont’d)

25 t9

26 k0 reserved for OS kernel27 k1

28 gp pointer to global area

29 sp stack pointer

30 fp frame pointer

0 zero constant1 at reserved for assembler

2 v0 expression evaluation &

3 v1 function results

4 a0 arguments

5 a16 a2

7 a3

8 t0 temporary: caller saves

. . .

15 t7

MIPS Register Usage/Naming Conventions

Only \$0 and \$31 are in fact special in hardware – rest is conventionImportant: The only general purpose registers are the \$s and \$t registers.

Everything else has a specific usage:\$a = arguments, \$v = return values, \$ra = return address, etc.

Also 32 floating-point registers: \$f0 .. \$f31

85

Caller Save (Temporary) Registers

• Caller save registers• If some code is about to call another function (it is the caller)...• And it needs the value currently in a caller saves register (\$t0,\$t1...) in

the future (after the function it is about to call returns)• Then it has to save it on the stack before the call• And restore it after the call

• One other important caller save register: \$ra!!!• As well as \$fp when we define that soon

• Where do we do this saving? The stack – more later – for now, a special place in memory with last in – first out behavior

86

Callee Save (Persistent) Registers

• Callee save registers• If a function that has just been called (the callee) wants to use a callee

saves register (at all), it has to save it to the stack before using it• And restore it back to its original value before it returns to its caller• But, it can assume any function it calls will not change the register

• Either won’t use it, or will save/restore it

87

More likely: a function to convert

int f2c (int tempF) {

int a = tempF – 32;a = a * 5;

int tempC = a / 9;return tempC;

}

tempF is in \$a0 by calling convention

88

More likely: a function to convert

int f2c (int tempF) {

int a = tempF – 32;a = a * 5;

int tempC = a / 9;return tempC;

}We can use \$t0 for a temp (like a) without saving it

89

More likely: a function to convert

int f2c (int tempF) {

int a = tempF – 32;a = a * 5;

int tempC = a / 9;return tempC;

}

f2c:addi \$t0, \$a0, -32li \$t1, 5mul \$t0, \$t0, \$t1li \$t1, 9div \$t2, \$t0, \$t1

90

More likely: a function to convert

int f2c (int tempF) {

int a = tempF – 32;a = a * 5;

int tempC = a / 9;return tempC;

}

f2c:addi \$t0, \$a0, -32li \$t1, 5mul \$t0, \$t0, \$t1li \$t1, 9div \$t2, \$t0, \$t1addi \$v0, \$t2, 0jr \$ra

91

f2c:addi \$t0, \$a0, -32li \$t1, 5mul \$t0, \$t0, \$t1li \$t1, 9div \$t2, \$t0, \$t1addi \$v0, \$t2, 0jr \$ra

More likely: a function to convert

int f2c (int tempF) {

int a = tempF – 32;a = a * 5;

int tempC = a / 9;return tempC;

}

A smarter compiler would just dodiv \$v0, \$t0, \$t1

92

f2c:addi \$t0, \$a0, -32li \$t1, 5mul \$t0, \$t0, \$t1li \$t1, 9div \$t2, \$t0, \$t1addi \$v0, \$t2, 0jr \$ra

More likely: a function to convert

int f2c (int tempF) {

int a = tempF – 32;a = a * 5;

int tempC = a / 9;return tempC;

}......int tempC = f2c(87)

93

More likely: a function to convert

int f2c (int tempF) {

int a = tempF – 32;a = a * 5;

int tempC = a / 9;return tempC;

}......int tempC = f2c(87)

f2c:addi \$t0, \$a0, -32li \$t1, 5mul \$t0, \$t0, \$t1li \$t1, 9div \$t2, \$t0, \$t1addi \$v0, \$t2, 0jr \$ra

94

More likely: a function to convert

int f2c (int tempF) {

int a = tempF – 32;a = a * 5;

int tempC = a / 9;return tempC;

}......int tempC = f2c(87)

f2c:addi \$t0, \$a0, -32li \$t1, 5mul \$t0, \$t0, \$t1li \$t1, 9div \$t2, \$t0, \$t1addi \$v0, \$t2, 0jr \$ra

95

More likely: a function to convert

int f2c (int tempF) {

int a = tempF – 32;a = a * 5;

int tempC = a / 9;return tempC;

}......int tempC = f2c(87)

f2c:addi \$t0, \$a0, -32li \$t1, 5mul \$t0, \$t0, \$t1li \$t1, 9div \$t2, \$t0, \$t1addi \$v0, \$t2, 0jr \$ra

Note: no callee-save registers needed in this case – pretty typical!

96

What it would take to make SPIM happy

.globl f2c # f2c can be called from any file

.text # goes in “text” region (i.e. code)f2c: # (remember memory picture?)addi \$t0, \$a0, -32li \$t1, 5mul \$t0, \$t0, \$t1li \$t1, 9div \$t2, \$t0, \$t1addi \$v0, \$t2, 0jr \$ra

.end f2c # end of this function

Could put it into a file f2c.s by itself or could be in a file with more functions –maybe MyLibrary.s

97

gcc –S (Intel architecture here)

main(){

int a,b,c; a = 6;

b = 12;

c = a*b;

printf("After much computation: %d * %d = %d\n",a,b,c);}

.file "assemtest.c” .section .rodata .align 8.LC0: .string "After much computation: %d * %d = %d\n” .text.globl main .type main, @functionmain:.LFB2: pushq %rbp.LCFI0: movq %rsp, %rbp.LCFI1: subq \$16, %rsp.LCFI2: movl \$6, -4(%rbp) movl \$12, -8(%rbp) movl -4(%rbp), %eax imull -8(%rbp), %eax movl %eax, -12(%rbp) movl -12(%rbp), %ecx movl -8(%rbp), %edx movl -4(%rbp), %esi movl \$.LC0, %edi movl \$0, %eax call printf leave ret

And some more bookkeeping code…

98

Assembly Language (MIPS again, cont.)

• Directives: tell the assembler what to do...• Format “.”<string> [arg1], [arg2] …

• Examples• .data # start a data segment – preload values. • .text # start a code segment.• .align n # align segment on 2n byte boundary.• .ascii <string> # store a string in memory.• .asciiz <string> # store a null terminated string in memory• .word w1, w2, . . . , wn # store n words in memory (giving values).• .space n # reserve n bytes of space (uninitialized)

99

The Stack

• Will need to use the stack for…• Saving return addresses when more than

one subroutine call deep• Local variables whose address is taken in

c for instance• (Can’t have “address of register”)• Or that won’t all fit in the available

general purpose registers • Saving registers

• Across calls • Spilling variables (not enough regs)

• Passing more than 4 arguments• Returning more than 2 results

Stack

Code

Static Data

Heap

00000000

FFFFFFFC

100

Stack Layout

• Two registers for stack:• Stack pointer (\$sp): Points at end (bottom) of stack (essential)• Frame pointer (\$fp): Points at top of current stack frame (a

convenience for human programmers – could live without but MIPS typically uses)

• Most machines have a dedicated, special SP in hardware, but not the MIPS, up to the assembly language programmer (or compiler) to manage it properly

101

Procedures Use the Stack

• In general, procedure calls obey stack discipline• Local procedure state contained in stack frame• Minimal stack frame just saves \$ra but lots more can go there• Where we can save registers• When a procedure is called, a new frame opens• When a procedure returns, the frame collapses

• Leaf procedures on MIPS *might* not have a stack frame• Procedure stack is in memory

• Starts at “top” (highest address, 0xFFFFFFFC) of memory and grows down

A AB

ABC

AB

AA calls BB calls C

C returnsB returns

102

\$fp

...

Callee SavedRegisters

Local Variables

\$sp

Arguments andlocal variables atfixed offset from FP

Grows and shrinksas needed

(old FP, RA)

Dynamic area

Argument 5

Argument 6

Caller’s Frame

Current Frame

103

MIPS/GCC Procedure Calling Conventions

Calling Procedure• Step-1: Setup the arguments:

• The first four arguments (arg0-arg3) are passed in registers \$a0-\$a3 • Remaining arguments are pushed onto the stack

(in reverse order, arg5 is at the top of the stack)

• Step-2: Save caller-saved registers• Save registers \$t0-\$t9 if they contain live values at the call site.

• Step-3: Execute a jal instruction.

• Step-4: Cleanup stack (if more than 4 args) – i.e. pop the arguments you just passed back off after you return

104

MIPS/GCC Procedure Calling Conventions (cont.)

Called Routine (if any frame is needed)• Step-1: Establish stack frame.

• Subtract the frame size from the stack pointer.subiu \$sp, \$sp, <frame-size>

• Sometimes, frame size is padded to power-of-2 boundary, in that case, minimum frame size is typically 32 bytes (8 words)

• How do we know how big it is? You (programmer or compiler) designed it!

• Step-2: Save callee saved registers in the frame.• Register \$fp is always saved. (caller’s \$fp)• Register \$ra is saved if routine makes a call.• Registers \$s0-\$s7 are saved if they are used.

• Step-3: Establish Frame pointer• Add the stack <frame size> - 4 to the address in \$sp

addiu \$fp, \$sp, <frame-size> - 4Frame pointer isn’t strictly necessary, but helps with debugging.

We’ll see examples with and without it.

105

MIPS/GCC Procedure Calling Conventions (cont.)

On return from a call• Step-1: Put returned values in registers \$v0, [\$v1].

(if values are returned)• Step-2: Restore callee-saved registers.

• Restore \$fp and other saved registers. [\$ra, \$s0 - \$s7]• Step-3: Pop the stack

jr \$ra

106

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at 0000 0000

\$v0 4242 4242

\$v1 0000 8010

\$a0 0000 1234

\$a1 5678 0001

\$a2 0000 0002

\$a3 0000 0007

\$t0 9999 999A

\$t1 0000 0000

\$s0 0042 0420

\$sp 0000 FFE0

\$fp 0000 FFF0

\$ra 0000 2348

PC 0000 1000

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8

FFD4

FFD0

FFCC

FFC8

FFC4

FFC0

FFBC

Just did jal 1000

107

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at 0000 0000

\$v0 4242 4242

\$v1 0000 8010

\$a0 0000 1234

\$a1 5678 0001

\$a2 0000 0002

\$a3 0000 0007

\$t0 9999 999A

\$t1 0000 0000

\$s0 0042 0420

\$sp 0000 FFE0

\$fp 0000 FFF0

\$ra 0000 2348

PC 0000 1000

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8

FFD4

FFD0

FFCC

FFC8

FFC4

FFC0

FFBC

\$sp, \$fp still describe callers frame

108

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at 0000 0000

\$v0 4242 4242

\$v1 0000 8010

\$a0 0000 1234

\$a1 5678 0001

\$a2 0000 0002

\$a3 0000 0007

\$t0 9999 999A

\$t1 0000 0000

\$s0 0042 0420

\$sp 0000 FFD0

\$fp 0000 FFF0

\$ra 0000 2348

PC 0000 1004

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8

FFD4

FFD0

FFCC

FFC8

FFC4

FFC0

FFBC

Allocate space on stack

109

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at 0000 0000

\$v0 4242 4242

\$v1 0000 8010

\$a0 0000 1234

\$a1 5678 0001

\$a2 0000 0002

\$a3 0000 0007

\$t0 9999 999A

\$t1 0000 0000

\$s0 0042 0420

\$sp 0000 FFD0

\$fp 0000 FFF0

\$ra 0000 2348

PC 0000 1008

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8

FFD4

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBC

Save \$fp

110

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at 0000 0000

\$v0 4242 4242

\$v1 0000 8010

\$a0 0000 1234

\$a1 5678 0001

\$a2 0000 0002

\$a3 0000 0007

\$t0 9999 999A

\$t1 0000 0000

\$s0 0042 0420

\$sp 0000 FFD0

\$fp 0000 FFF0

\$ra 0000 2348

PC 0000 100C

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

Save \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBC

111

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at 0000 0000

\$v0 4242 4242

\$v1 0000 8010

\$a0 0000 1234

\$a1 5678 0001

\$a2 0000 0002

\$a3 0000 0007

\$t0 9999 999A

\$t1 0000 0000

\$s0 0042 0420

\$sp 0000 FFD0

\$fp 0000 FFF0

\$ra 0000 2348

PC 0000 1010

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

Save \$s0 (caller saves)

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBC

112

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at 0000 0000

\$v0 4242 4242

\$v1 0000 8010

\$a0 0000 1234

\$a1 5678 0001

\$a2 0000 0002

\$a3 0000 0007

\$t0 9999 999A

\$t1 0000 0000

\$s0 0042 0420

\$sp 0000 FFD0

\$fp 0000 FFDC

\$ra 0000 2348

PC 0000 1014

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBC

Setup \$fp

113

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at 0000 0000

\$v0 4242 4242

\$v1 0000 8010

\$a0 0000 1234

\$a1 5678 0001

\$a2 0000 0002

\$a3 0000 0007

\$t0 9999 999A

\$t1 0000 0000

\$s0 0042 0420

\$sp 0000 FFD0

\$fp 0000 FFDC

\$ra 0000 2348

PC 0000 1014

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

\$sp, \$fp now describe new frame, ready to start

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBC

114

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at 0000 0000

\$v0 4242 4242

\$v1 0000 8010

\$a0 0000 1234

\$a1 5678 0001

\$a2 0000 0002

\$a3 0000 0007

\$t0 9999 999A

\$t1 0000 0000

\$s0 5678 1235

\$sp 0000 FFD0

\$fp 0000 FFDC

\$ra 0000 2348

PC 0000 1018

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBC

Do some computation..

115

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at 0000 0000

\$v0 4242 4242

\$v1 0000 8010

\$a0 0000 1234

\$a1 5678 0001

\$a2 0000 0002

\$a3 0000 0007

\$t0 9999 999A

\$t1 0000 0000

\$s0 5678 1235

\$sp 0000 FFD0

\$fp 0000 FFDC

\$ra 0000 101C

PC 0000 4200

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

Call another function (not pictured, takes no args)

jal sets \$ra, PC

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBC

116

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at ???? ????

\$v0 ???? ????

\$v1 ???? ????

\$a0 ???? ????

\$a1 ???? ????

\$a2 ???? ????

\$a3 ???? ????

\$t0 ???? ????

\$t1 ???? ????

\$s0 ???? ????

\$sp ???? ????

\$fp ???? ????

\$ra ???? ????

PC ???? ????

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

Other function can do whatIt wants to the regs as it computes And make a stack frame

Of its own

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBC

117

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at ???? ????

\$v0 8675 3090

\$v1 ???? ????

\$a0 ???? ????

\$a1 ???? ????

\$a2 ???? ????

\$a3 ???? ????

\$t0 ???? ????

\$t1 ???? ????

\$s0 5678 1235

\$sp 0000 FFD0

\$fp 0000 FFDC

\$ra 0000 101C

PC 0000 101C

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBCBut before it returns, it is responsible for restoring certain registers

Including \$sp and \$fp,and \$s0Value returned in \$v0

118

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at ???? ????

\$v0 8675 3090

\$v1 ???? ????

\$a0 ???? ????

\$a1 ???? ????

\$a2 ???? ????

\$a3 ???? ????

\$t0 DCED 42C5

\$t1 ???? ????

\$s0 5678 1235

\$sp 0000 FFD0

\$fp 0000 FFDC

\$ra 0000 101C

PC 0000 1020

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBCDo some more computation

119

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at ???? ????

\$v0 0001 0002

\$v1 ???? ????

\$a0 ???? ????

\$a1 ???? ????

\$a2 ???? ????

\$a3 ???? ????

\$t0 DCED 42C5

\$t1 ???? ????

\$s0 5678 1235

\$sp 0000 FFD0

\$fp 0000 FFDC

\$ra 0000 101C

PC 0000 1024

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

120

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at ???? ????

\$v0 0001 0002

\$v1 ???? ????

\$a0 ???? ????

\$a1 ???? ????

\$a2 ???? ????

\$a3 ???? ????

\$t0 DCED 42C5

\$t1 ???? ????

\$s0 0042 0420

\$sp 0000 FFD0

\$fp 0000 FFDC

\$ra 0000 101C

PC 0000 1028

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBCRestore registers to return

121

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at ???? ????

\$v0 0001 0002

\$v1 ???? ????

\$a0 ???? ????

\$a1 ???? ????

\$a2 ???? ????

\$a3 ???? ????

\$t0 DCED 42C5

\$t1 ???? ????

\$s0 0042 0420

\$sp 0000 FFD0

\$fp 0000 FFDC

\$ra 0000 2348

PC 0000 102C

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBCRestore registers to return

122

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at ???? ????

\$v0 0001 0002

\$v1 ???? ????

\$a0 ???? ????

\$a1 ???? ????

\$a2 ???? ????

\$a3 ???? ????

\$t0 DCED 42C5

\$t1 ???? ????

\$s0 0042 0420

\$sp 0000 FFD0

\$fp 0000 FFF0

\$ra 0000 2348

PC 0000 1030

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBCRestore registers to return

123

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at ???? ????

\$v0 0001 0002

\$v1 ???? ????

\$a0 ???? ????

\$a1 ???? ????

\$a2 ???? ????

\$a3 ???? ????

\$t0 DCED 42C5

\$t1 ???? ????

\$s0 0042 0420

\$sp 0000 FFE0

\$fp 0000 FFF0

\$ra 0000 2348

PC 0000 1034

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBCRestore registers to return

124

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at ???? ????

\$v0 0001 0002

\$v1 ???? ????

\$a0 ???? ????

\$a1 ???? ????

\$a2 ???? ????

\$a3 ???? ????

\$t0 DCED 42C5

\$t1 ???? ????

\$s0 0042 0420

\$sp 0000 FFE0

\$fp 0000 FFF0

\$ra 0000 2348

PC 0000 1034

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

FFBCRestore registers to returnNow \$sp, \$fp describe caller’s frame

125

Execution example: Calling with framesReg Value

\$0 0000 0000

\$at ???? ????

\$v0 0001 0002

\$v1 ???? ????

\$a0 ???? ????

\$a1 ???? ????

\$a2 ???? ????

\$a3 ???? ????

\$t0 DCED 42C5

\$t1 ???? ????

\$s0 0042 0420

\$sp 0000 FFE0

\$fp 0000 FFF0

\$ra 0000 2348

PC 0000 2348

1000 subiu \$sp, \$sp, 16

1004 sw \$fp, 0(\$sp)

1008 sw \$ra, 4(\$sp)

100C sw \$s0, 8(\$sp)

1018 jal 4200

1020 lw \$v0, 4(\$t0)

1024 lw \$s0, -4(\$fp)

1028 lw \$ra, -8(\$fp)

102C lw \$fp, -12(\$fp)

1034 jr \$ra

FFF0 0001 0070

FFEC 1234 5678

FFE8 9999 9999

FFE4 0000 2568

FFE0 0001 0040

FFDC

FFD8 0042 0420

FFD4 0000 2348

FFD0 0000 FFF0

FFCC

FFC8

FFC4

FFC0

126

• Write C (or pseudocode) first, translate C -> Assembly• One function at a time• Pick registers for each variable

• Must be in memory? Give it a stack slot (refer to by \$fp+num)• Live across a call? Use an \$s register• Otherwise, a \$t

• Write prolog – boilerplate• Save ra/fp (if needed)• Save any \$s registers you use

• Translate line by line• Write epilog - boilerplate

127

Why do we need FP?

• The frame pointer is not always required• Can often get away without it

• When/why do we need it?• Debugging tools (gdb) use it to find frames• If you have variable length arrays

• Stack pointer changes by amount not know at compile time• Variables still at constant offset from frame pointer

• How to reference stuff without it?• Everything is offset from the stack pointer: -4(\$sp), -8(\$sp), etc.

• Good practice for this class to use it• Don’t prematurely optimize

128

System Call Instruction

• System call is used to communicate with the operating system and request services (memory allocation, I/O)• syscall instruction in MIPS

• Sort of like a procedure call, but call to ask OS for help• SPIM supports “system calls lite”

1. Load system call code into register \$v0• Example: if \$v0==1, then syscall will print an integer

2. Load arguments (if any) into registers \$a0, \$a1, or \$f12 (for floating point)

3. syscall

4. Results returned in registers \$v0 or \$f0

129

SPIM System Call Support

code service ArgType Arg/Result1 print int \$a02 print float \$f123 print double \$f124 print string \$a0 (string address)5 read integer integer in \$v06 read float float in \$f07 read double double in \$f0 & \$f18 read string \$a0=buffer, \$a1=length9 sbrk \$a0=amount address in \$v010 exit

Plus a few more for general file IO which we shouldn’t need.

130

Echo number and string.textmain:

li \$v0, 5 # code to read an integersyscall # do the read (invokes the OS)move \$a0, \$v0 # copy result from \$v0 to \$a0

li \$v0, 1 # code to print an integersyscall # print the integer

li \$v0, 4 # code to print stringla \$a0, nln # address of string (newline)syscall

li \$v0, 8 # code to read a stringla \$a0, name # address of buffer (name)li \$a1, 8 # size of buffer (8 bytes)syscall

la \$a0, name # address of string to printli \$v0, 4 # code to print a stringsyscall

jr \$31 # return

.data

.align 2name: .word 0,0nln: .asciiz "\n"

131

MIPS Assembly General Rules

• One instruction per line.• Numbers are base-10 integers or Hex w/ leading 0x.• Identifiers: alphanumeric, _, . string starting in a letter or _• Labels: identifiers starting at the beginning of a line followed

by “:”• Comments: everything following # till end-of-line.• Instruction format: Space and “,” separated fields.

• [Label:] <op> reg1, [reg2], [reg3] [# comment]• [Label:] <op> reg1, offset(reg2) [# comment]• .Directive [arg1], [arg2], . . .

132

All of MIPS in two pages

• Print this quick reference linked from the course page

133

Mapping C variables to memory

134

Memory Layout

Stack

Data

TextReserved0

2n-1

Heap

• Memory is array of bytes, but there are conventions as to what goes where in this array

• Text: instructions (the program to execute)

• Data: global variables• Stack: local variables and other

per-function state; starts at top & grows down

• Heap: dynamically allocated variables; grows up

• What if stack and heap overlap????

135

Memory Layout: Example

int anumber = 3;

int factorial (int x) {if (x == 0) {return 1;

}else {return x * factorial (x – 1);

}}

int main (void) {int z = factorial (anumber);printf(“%d\n”, z);return 0;

}

Stack

Data

TextReserved0

2n-1

Heap

136

Memory Layout: Example

int anumber = 3;

int factorial (int x) {if (x == 0) {

return 1;

}

else {

return x * factorial (x – 1);

}

}

int main (void) {

int z = factorial (anumber);

printf(“%d\n”, z);

return 0;

}

Stack

Data

Text

Reserved0

2n-1

Heap

.dataanumber: .word 3

.text

.globl factorialfactorial:; find x in \$a0.; if more args than 4, ; find them in stack...

.globl mainmain:; make local z exist by ; subtracting 4 from \$spaddiu \$sp, \$sp, -4...

Global

Param

Local

137

What is an array?

• Array is nothing but a contiguous chunk of memory.• The name of the array is a pointer to the beginning of the

chunk of memory array has.• So int array[100] is a contiguous chunk of memory which is of

size 100*4 = 400 bytes.• so array is almost of type int*

(not exactly int* to be very exact but good enough for our purposes)

From “Arrays and Pointers” by Anand George, SourceLens.org. Link.

138

So..

• C pointer notation vs. array notation:• array[0] is equal to *(array + 0 ) or *(array)• array[1] is equal to *(array + 1)• array[2] is equal to *(array + 2)• ...

• In C pointer math, the units are elements• In MIPS memory accesses, the units are bytes

• If array points to 0x1000, then:• array[0] is *(array+0), and it lives at (0x1000+0)*4 = 0x1000• array[1] is *(array+1), and it lives at (0x1000+1)*4 = 0x1004• array[2] is *(array+2), and it lives at (0x1000+2)*4 = 0x1008• ...

139

Pointers vs. arrays

• How they’re similar:• Both are represented by a memory address which has one or more bytes of content at it

• How they differ:• Pointers store a memory address in memory. Only allocated one word (4 bytes on MIPS)

• Global:char* name=NULL; → .data

name: .word 0

• Local:char* name=NULL; → addiu \$sp, \$sp, -16 ; assuming 3 other words needed

sw \$0, 12(\$sp)

• Arrays are allocated enough space for the array itself. Array declaration by itself doesn’t store a memory address into memory, compiler just knows where the array lives and makes references to it use that memory region.

• Global:char name[40]=“”; → .data

name: .space 40 ; allocates 40 bytes

• Local:char name[40]=“”; → addiu \$sp, \$sp, -52 ; assuming 3 other words needed

sb \$0, 12(\$sp) ; only need to set first byte to null

140

• Pointers to a string literal: put string in read-only data region, store address to it.

• Global:char* name=“hello”; → .data

name: .word str_hello #for the pointer.datastr_hello: .asciiz “hello” #real string

• Local:char* name=“hello”; → addiu \$sp, \$sp, -16 ; assuming 3 other words needed

la \$t0, str_hellosw \$t0, 12(\$sp)

• Arrays set to string literal: Allocate space for the string and initialize it.

• Global:char name[40]=“hello”; → .data

name: .asciiz “hello”.space 34 #5 chars and NULL above

• Local:char name[40]=“hello”; → addiu \$sp, \$sp, -52 ; assuming 3 other words needed

add \$a0, \$sp, 12 ; destination for copy

la \$a1, str_hello ; source for copy

jal memset ; std function to copy memory

141

Pointers vs. arrays

• When you pass an array to a function or store a reference to an array, then you’re using pointers.

int func(int* ar) {...}

int my_array[50];

func(my_array);

• ar gets the address of the start of my_array• Still true for this syntax:

int func(int ar[]) {...}

int func(int ar[40]) {...}

142

Multidimensional Arrays

• Again contiguous chunk of data.• Behaves like

• array of arrays in the case of 2 dimensions.• array of array of array in 3 dimension and so on.

• All are different interpretations and syntaxes on single chunk of contiguous memory

From “Arrays and Pointers” by Anand George, SourceLens.org. Link.

143

Multidimensional Arrays syntax

int mytable[10][20];

• We have 10 arrays of array of 20 integers.• So total 10*20*4 = 800 bytes of contiguous memory.• As before, the array name acts as a memory address to the

beginning of the array.• Type of the pointer is sort of like int**, but the row size

needs to be known, so it’s actually int (*mytable)[20]

• How to access? Pointer arithmetic.myarray[x][y]

is equal to*(myarray+x*20+y)

144

2D arrays in MIPS

• Global:int a[10][20];int b[10][20] = {{1,2,3,...,20},{101,102,...,120},...}

→ .dataa: .space 800b: .word 1,2,3,4,5,6,7,8,9,10,101,...

• Local:int a[10][20];int b[10][20] = {{1,2,3,...,20},{101,102,...,120},...}

→ addiu \$sp, \$sp, -1612 ; assuming 3 other words needed; no initialization for a, so it has whatever trash was on the stack already

li \$t0,1sw \$t0, 12(\$sp)li \$t0,2sw \$t0, 16(\$sp)li \$t0,3sw \$t0, 20(\$sp)... ; lots of initialization code

145

• sizeof tells you how big something is, in bytes

• For variables declared as arrays, this is the size of the array:int array[10]; // sizeof(array) is 10*4 = 40 bytes

int array2d[10][20] // sizeof(array2d) is 10*20*4=800

• For pointers, this is the size of one pointer:int* p; // sizeof(p) is 4 bytes

// (assuming we’re on a 32-bit system)

• This is true even if the pointer is used to refer to an array:p = array; // p gets the address of the array.

// sizeof(p) is still 4 bytes

146

Summary

• MIPS ISA and Assembly Programming• We’ll use qtspim (with spim for automated testing)• Have seen most basic instruction types• See Appendix B for full insn reference

• Check the course page “resources” section for example MIPS programs!

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