ECE U530 Digital Hardware Synthesis -...

ECEU530 F’05

ECE U530Digital Hardware Synthesis

• Lecture 1:• Overview• Organization• What is an ASIC ?• Why FPGAs?• Hardware Description Languages and VHDL

ECE U530 F06lect01.ppt

Prof. Miriam [email protected]

Sept 6, 2006

ECE U530 F’062lect01.ppt

What is the course about?

ECEU530 follows closely the material learned in ECEU322 (ECE1382): Digital Logic Design

• Digital Logic Design using VHDL• Synthesize VHDL to FPGAs• VHDL:

• Combinational Logic Design• Sequential Logic Design• System Design• Writing Testbenches

• Synthesis tools• Targetting FPGAs

ECEU530 F’05


Getting Help• Web: Blackboard

• Copies of lectures, assignments, handouts, solutions• Clarifications to assignments• Questions answered

• Personal help• Professor: Office Hours 10:30 to 11:30 am Tues and Wed

or by appointment• Email: [email protected]


Reading• Required Textbook:

Ashenden, The Designer's Guide to VHDL2nd Edition, Morgan Kaufmann, 2001

• Recommended Text:

Mano and Kime, Logic and Computer Design Fundamentals, 3rd Edition Prentice Hall, 2004

ECEU530 F’05


Programming Assignments• All assignments are expected to represent individual

work !• Programming Assignments will be submitted

electronically. Tools:• Xilinx ISE version 6.2i • Modelsim 5.7e

• Programming assignments will be done on WinCOEsystems. Computers are available on the second floor of Snell Engineering.

• You must have a COE account for this class:• Go to http://www.coe.neu.edu/computer/

then click on HELP!then click on Account Information For New Users


Programming Assignments• I have the tools (at work) on a PC. Can I work there, • then upload the tools ?• Yes, but ...

It is your responsibility to make sure:1. You are using the same version of the tools:• Version 6.2i of the Xilinx ISE tools• Version 5.7e of Modelsim

2. Your programs run under the WinCOE toolsi.e. no problems with formatting, etc.

You can download evaluation versions from Xilinx and Modelsim. These are newer versions of the tools. YOU MUST MAKE SURE YOUR ANSWERS WORK on the WinCOE system !!

ECEU530 F’05


Policies: Grading• Midterm Exam (30%)

• Midterm Exam in class Tuesday, November 1

• Homework and Programming Assignments (30%)• Frequent homeworks (1 or 2 per week)• most will be programming assigments using

Xilinx and Modelsim

• Final Project (30%)December 13 at 1:00pm


Our Design Flow

ECEU530 F’05


How to learn VHDL

• The course textbook:Ashenden, The Designer's Guide to VHDL2nd Edition, Morgan Kaufmann, 2001

• Many VHDL web pages• VHDL on line tutorial:

http://www.vhdl-online.de/tutorial/• The Green Mountain VHDL tutorial:

http://www.gmvhdl.com/VHDL.html• VHDL tutorial: learn by example

http://esd.cs.ucr.edu/labs/tutorial/• The VHDL mini reference:

http://www.eng.auburn.edu/department/ee/mgc/vhdl.html


Why VHDL ?• VHDL more dominant in FPGA design than Verilog• VHDL tools more advanced than tools for other

languages:• SystemC has no synthesis tool for FPGAs • HandelC does not have a good simulation environment

...

• We may look at SystemC later in the semester

ECEU530 F’05


An Integrated Circuit

•Measurement of chip size, gate count: the number of logic gates•A logic gate = a two-input NAND gate

Pin-grid array (PGA) packageWafer (holding hundreds of dice)

Silicon die or chip


CMOS is based on a MOSFET

p-well

n+ n+

L

Oxide (SiO2)

Polysilicon

W

Metal

The smallest feature size, λ=L/2 (unit: micron or µm)e.g., λ=0.25 µm in a 0.5 micron process

ECEU530 F’05


ASIC (Application-Specific IC)• Not all ICs are ASICs IC = Integrated Circuit

• CPU, microprocessor• TTL ICs (74-series)• ROMs, DRAMs, and SRAMs

• Some ICs are ASICs• Toy chips (e.g. ICs for e-pets, talking dolls, and so on)• DSP processors ?• MPEG II decoder, xDSL ICs• ICs for interfacing between memory and microprocessor

• Types of ASICs• Full-custom ASICs• Semicustom ASICs: cell-based, gate-array-based• Programmable ASICs: PLD, FPGA


Taxonomy of Digital Hardware

ECEU530 F’05


Full-Custom ASICs• Some (or all) logic cells are customized• All mask layers are customized• Design for:

• High speed• Low power• Small size

• Applications:• Analog IC• Mixed analog/digital ASIC• Memory cells• FPGA cells


Full-Custom ASICs (2) • Advantages

• Optimal performance

–area–speed–power

• Disadvantages• Time/effort to design• Time to market• Cost• Cannot change once fabricated

ECEU530 F’05


Fixed blocks

Flexible block

Cell-based ASICs (CBICs)• Use predesigned logic cells (standard cells) in

combination with larger cells (megacells)• Standard cells

• AND/OR gates, NAND/NOR gates, ..• Multiplexers, adders, ...• Flip-flops, latches, registers, ...

• Mega cells (full-custom blocks, system-level macros, fixed blocks, cores, functional standard blocks, or IP)• Microcontrollers, mP, MPEG decoder• RAM, ROM

• All mask layers are customized• Custom blocks can be embedded


Cell-Based ASICs (2) • Advantages

• Faster to design the Custom Logic• Can optimize some logic cells:

–choose dfferent library components for different drive requirements

• Disadvantages• Time/effort to design

– Less than full-custom, worse than other design styles• Time to market• Cost

–still need a full mask set• Cannot change once fabricated

ECEU530 F’05


Gate-Array Based ASICs• Gate array (or prediffused array)

• Transistors are predifined on the silicon wafer• Base array: the predifined pattern of transistors• Base cell: the smalles element that is replicated to make the

base array

• Masked gate array (MGA)• Only the top few layers of metal are defined by the designer

using custom masks• The designer chooses from a gate-array library of

predesigned logic cells (macros)

• Types of MGA ASICs• Channeled gate arrays• Channelless gate arrays• Structured gate arrays


Gate-Array Based ASICs (2) • Advantages

• Faster to design the Semi-custom Logic• Lower cost

–only need top few layers of mask• Lower fabrication time

• Disadvantages• Cannot optimize for performance• Time to market

– faster than CBICs, slower than FPGAs• Cannot change once fabricated

ECEU530 F’05


Programmable Logic• Not all programmable logic is FIELD programmable• PLAs and PALs implement AND-OR logic• Useful for implementing combinational logic• PLA : Programmable Logic Array

• programmable AND, programmable OR Planes

• PAL: Programmable Array Logic• programmable AND, fixed OR plane

• PLAs and PALs• similar architectures• “Programmable” by adding connections• May be mask programmable or field programmable depending

on design, chip


PAL (Programmable Array Logic)

��

��

��

��

��

��

� ��

� �� !�� "#�� $

321321 xxxxxx +=

32121 xxxxx +=

ECEU530 F’05


Field Programmable Logic (FPL)• FPL:

• Logic for computing functions• Interconnect• I/O

• CPLD• Complex, Programmable Logic Device• Computations based on PAL

• FPGA• Field Programmable Gate Array• Computations based on LUT: Look up table


Field Programmable Logic (2) • Advantages

• Low cost • Very low fabrication time• Fast time to market • Volatile:

–Can change once fabricated

• Disadvantages• Cannot optimize for performance• Wasted area to allow reprogrammability• Volatile:

–lose design on power down

ECEU530 F’05


FPGA•FPGAs do not contain AND or OR planes•Three elements:

• Logic blocks• I/O blocks• Interconnection wires and

switches

��

��

�

��

� ��

��


Lookup Table (LUT)

%&�

%&�

%&�

%&�

��

��

�

111

001

010

100

fx2x1

�

%

%

�

��

��

�

ECEU530 F’05


SRAM-controlled Switches

�#�'

�#�' �#�'

�� ( ��

�� ( ��

�� ( ��

�� ( ��


ASIC Cell Libraries• FPGA: a library of logic cells that make up bigger

components• MGAs and CBICs:

• ASIC vendor: using an ASIC-vendor library–Enter and simulate the design thru a set of design tools

approved by the vendor• Library vendor: purchasing a cell library

–Use a phantom library whose cells are empty boxes but contain enough information for layout

–The vendor will fills in the empty boxes after receiving the netlist• In-house design: developing a cell library in-house

• Qualified cell library: the cell library that meets the foundry specifications• An ASIC foundry only provides manufacturing without design

help

ECEU530 F’05


Cell Information•A physical layout

• The designer may not actually see the layout

•A behavioral model• A high-level model to shorten the

simulation time• A Verilog/VHDL model

•A detailed timing model• Determined by performing a simulation

of each cell including the parasitic elements

• The simulation models are derived from measurements on special chips (process control monitors, PCMs, or drop-ins)

•A test strategy•A circuit schematic

• A netlist description for the layout versus schematic (LVS) check

•A cell icon• An icon for schematic entry

•A wire-load model• A model for estimating the parasitic

capacitance of wires before routing

•A routing model• A model tells where it can and cannot

place wires over the cell, as well as the location and types of the connections


Losses due to delayed market entry

•Simplified revenue model• Product life = 2W, peak at W• Time of market entry defines a

triangle, representing market penetration

• Triangle area equals revenue

•Loss • The difference between the

on-time and delayed triangle areas

On-time Delayedentry entry

Peak revenue

Peak revenue from delayed entry

Market rise Market fall

W 2W

Time

D

On-time

Delayed

Rev

enue

s ($

)

ECEU530 F’05


0

200

400

600

800

1000

1200

1400

Exploding: Cost of IC Mask Set

Process (µµµµ) 2.0 … 0.8 0.6 0.35 0.25 0.180.15

0.13

Single Mask cost ($K)

1.5 1.5 2.5 4.5 7.5 1222

40

# of Masks 12 12 12 16 20 2628

30

Mask Set cost ($K)

18 18 30 72 150 312616

1,200


Cost of an ASIC• Quote from

“Spending on masks can pay off, Sematech finds”By David LammersEE Times, July 30, 2003

• A mask set for 130-nm logic devices costs $750,000, on average. Saying that "we think we have a decent handle on mask cost projections," Trybula said that Sematech expects the price tag to rise to $1.6 million for 90-nm technology and $3 million for a 65-nm mask set. "The price goes up very significantly" after that, Trybula said.

ECEU530 F’05


Why FPGAs ?• FPGAs allow you to take advantage of latest

technology • FPGAs are high volume, custom designs • FPGA manufacturers pay the high cost of a mask set

• sell same chip to thousands of customers

• Disadvantages• Designs mapped on FPGAs are slower, larger, dissipate more

power than designs implemented on ASICs• Disadvantages amount to sticking with one or two previous

generations of ASIC chip

• Advantages• No NRE (Non-recurring Engineering cost) for an FPGA• Fast time to market• FPGA CAD tools are cheaper than ASIC CAD tools


ASIC Market – FPGAs vs. ASICs

per m

onth

ECEU530 F’05


When to use FPGAs?

• Replace components on a board• easier to integrate a single chip

• Replace an ASIC• ASICs getting expensive to fabricate• FPGAs getting denser

• Accelerate algorithms that run in software• for embedded systems• but PCs are getting faster all the time ...

–factor of 2 speed increase in PC parallels afactor of 4 speedup in an FPGA: 2xclock + 2x area

• Goals: • High performance design• Fast design turn around


Classification of Digital Hardware• Chips can be:

• Gate Array or Custom

• Programmable Logic can be:• Mask Programmable (Program once, in the foundary)• Field Programmable (Program anywhere)

• Field Programmable Logic can be:• Program once• Reprogrammable

• Reprogrammable Logic can be:• Reprogrammable out of the circuit (EEPROM based)• Reprogrammable in the circuit

–Reconfigurable Logic is Reprogrammable in the circuit

ECEU530 F’05


SRAM-based FPGAs• Programmed by loading configuration memory cells

from an external source• Memory cells are distributed among the logic they

control• Configuration memory is written once for each

application• high speed read/write is NOT important• stability and density of RAM IS important•


Gates

FPGA Density

1985

10M

1M

10K

100K

1K

1989 1993 1997 2001

XC2000

XC3000

XC4000

Virtex

Virtex-IIApprox. 65% growthper year

ECEU530 F’05


Xilinx FPGA Architecture

CLB Configurable Logic Block

IOB Input/Output BlockPSM

Programmable Switch MatrixPIP Programmable Interconnect

Point


There are no Logic Gates on an FPGA

• Logic Gates are implemented via a LUT:• Look up table

ECEU530 F’05


FPGA CAD FLOW• Synthesis• Technology Mapping• Placement • Routing• Timing Analysis• Bitstream generation and download

• Simulation, simulation, simulation ...


Trends in Digital Hardware• Improvements in device technology

• Smaller circuits• Higher performance• More devices per chip

• Higher degree of integration • More complex systems• Lower cost of computation• Higher reliability

ECEU530 F’05


Hardware Design Challenges• Use most recent technology

• To be competitive in performance

• Reduce design cost• To be competitive in price

• Speed up design time• Time to market is critical


Modern FPGAs• Take advantage of the latest technology

• .13 micron, .09 micron ...

• High cost is amortized over many customers• Millions of transistors per FPGA• Millions of gate equivalents per FPGA

• One gate equivalent = 1 2-input NAND gate (4 transistors)• Difficult to measure in FPGA due to LUT technology

• Clock speeds greater than 100 MHz• Integrate larger logic blocks:

• Memories• Multipliers• Processor cores

ECEU530 F’05


FPGAs require ASIC design styles• Density and performance of best FPGAs rival ASICs

of 1 or 2 years ago• Same design issues:

• controlling complexity• ability to simulate


10,000

1,000

100

10

1

0.1

0.01

0.001

Logic transistors per chip

(in millions)

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2003

2005

2007

2009

Note: logarithmic scale

Moore’s law• The most important trend in microelectronics

• Predicted in 1965 by Intel co-founder Gordon Moore• IC transistor capacity has doubled roughly every 18 months

for the past several decades

ECEU530 F’05


Moore’s Law: CPUs and Memory


1981 1984 1987 1990 1993 1996 1999 2002

Leading edgechip in 1981

10,000transistors

Leading edgechip in 2002

150,000,000transistors

Graphical illustration of Moore’s law

• Something that doubles frequently grows more quickly than most people realize!• A 2002 chip can hold about 15,000 1981 chips inside itself

ECEU530 F’05


Facts about the Transistor• In 2002, 1018 transistors are produced.• This is about 100 times more transistors than there

are ants in the world!• More transistors are produced per year in DRAMsonly than grains of rice.• One grain of rice can buy 100’s of transistors!


��

��

The Importance of CAD Tools

[©Keutzer]

Source:SEMATECH

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

�!"�

�!"#

�!"!

�!!$

�!!%

&��

&��#

&��!

#"'��(��)�� )�*�+��,��

&�'��(��)�� ,��

ECEU530 F’05


Evolution of the EDA Industry

[©Keutzer]

-��*��

.��./0��*�� 1 ��

�� 2 �*)�� )��

��)�� 2 /�� 3�*��

� ��2 ��

4��5�� +�6


IC Design Steps (cont.)

�� 7��1*��*/��

7��1*��*/��

8� �� */��

8� �� */��

9��*37/��

��*37/�

Figs. [©Sherwani]

ECEU530 F’05


��

��

��

��

IC Design Steps (cont.)

�� 7��1*��*/��

7��1*��*/��

8� �� */��

8� �� */��

�*��:�-��/��

�*��:�-��/��

;<�09= /�>�0>/�>�0�9> ��

(�<��0�9> �>0 >/>0�9 >/��

?��1*��*/��

?��1*��*/��

��/��

��/��


Libraries/IP: Incorporates pre-designed implementation from lower abstraction level into higher level.

Systemspecification

Behavioralspecification

RTspecification

Logicspecification

To final implementation

Compilation/Synthesis:Automates exploration and insertion of implementation details for lower level.

Test/Verification: Ensures correct functionality at each level, thus reducing costly iterations between levels.

Compilation/Synthesis

Libraries/IP

Test/Verification

Systemsynthesis

Behaviorsynthesis

RTsynthesis

Logicsynthesis

Hw/Sw/OS

Cores

RTcomponents

Gates/Cells

Model simulat./checkers

Hw-Swcosimulators

HDL simulators

Gatesimulators

Design Synthesis• The manner in which we convert our concept of

desired system functionality into an implementation

ECEU530 F’05


Design Methodology• Specification• Design domains - abstraction level• Top-down vs. Bottom-up design• Schematic based vs. HDL based• Getting it right – Simulation and verification• Design libraries


Specification• A specification of what to construct is the first major

step.• Compromise between what is wanted and what can

be made• Requires experience

• Requirements must be considered at many levels• System, sub-system, Board

• Specifications can be verified by system simulations

ECEU530 F’05


Design domains

Structural Behavioral

Geometric

Processor, memory

ALU, registersCell

Device, gate

Transistor

Program

State machineModule

Boolean equationTransfer function

IC

Macro

Functional unit

Gate

Masks

Gajski chart


Design Domains (2)• Behavioral:

• Abstract function

• Structural:• Interconnection of parts

• Geometric:• physical objects with sizes and position

ECEU530 F’05


Abstraction levels and synthesis

Architectural level Logic level Circuit level

Beh

avio

ral l

evel

Stru

ctur

al le

vel

For I=0 to I=15Sum = Sum + array[I]

0

0 0

0

State

Memory

+

Control

Clk

Architecturesynthesis

Logicsynthesis

Circuitsynthesis

Layout level

Layoutsynthesis

Ideal synthesis system

(Library)(register level)


• Choice of algorithm• Definition of functional modules• Definition of design hierarchy• Split up in small boxes - split up in small boxes - split

up in small boxes • Define required units ( adders, state machine, etc.)• Floor-planning• Map into chosen technology

(synthesis, schematic, bitstream)• Behavioral simulation tools

Top - down design

ECEU530 F’05


Comment by one of the main designers of a Pentium processor

The design was made in a typical top - down , bottom - up , inside - out design methodology

Bottom - up• Build basic units in technology• Build generic modules of use• Put modules together

• Hope that you arrived at some reasonable architecture

• Gate level simulation tools• Old fashioned design methodology a la discrete logic


Symbol

Schematic

Basic gate Logic module

Long and tedious

Schematic based• Symbol of module defines interface• Schematic of module defines function• Top - down: Make first symbol and then schematic• Bottom - up: Make first Schematic and then symbol

ECEU530 F’05


always @(posedge clk)beginif (set) coarse <= #(test.ff_delay) offset;else if (coarse == count_roll_over)

coarse <= #(test.ff_delay) 0;else coarse <= #(test.ff_delay) coarse + 1;end

Synthesis based• Define modules and their behavior in a hardware

description language (also used for simulation)• Use synthesis tools to generate netlist


Getting it right - Simulation• Simulate the design at all levels:

• behavioral level• netlist level• netlist with timing information

• Behavioral simulation at system/module level (Verilog, VHDL)

• All functions must be simulated and verified• Worst case data must be used if exhaustive

simulation impossible• Use programming approach to verify large set of

functions(not looking at waveform displays)

ECEU530 F’05


Hardware Synthesis• Architectural Synthesis

• Determine the interconnection of large building blocks

• Logic Synthesis• Determine the interconnection of logic gates

• Geometric level Synthesis (Place and Route)• Determine positions and connections


Circuit Optimization• Performance (speed)

• Delay and cycle time• Latency• Throughput -- for pipelined applications

• Area• Power

ECEU530 F’05


Our Design Flow


How to Describe FPGA Designs• Use CAD Tools

• CAD Tools translate your design into an FPGA architecture

• Two types of design entry:• Schematic capture

–This is what you used in ECE U322 (ECE 1382)• Hardware Description Language

–This is what this class is about

• CAD tools translate both types of descriptions to FPGA hardware

ECEU530 F’05


The Need for HDLs• Technology trends

• 1 billion transistor chip running at 20 GHz in 2007

• Need for Hardware Description Languages• Systems become more complex• Design at the gate and flip-flop level becomes

very tedious and time consuming

• HDLs allow• Design and debugging at a higher level before

conversion to the gate and flip-flop level• Tools for synthesis do the conversion

• VHDL, Verilog are the most popular• VHDL – VHSIC Hardware Description Language


HDLs vs. Programming Languages• Procedural programming languages provide

algorithms, or the how of implenting a design• for computation• for data manipulation• typically independent of the hardware it is running on

• Hardware description languages describe a system• Interfaces are important• May want to describe in different ways

–behavior–structure

• May want to specify specific physical properties

ECEU530 F’05


HDLs vs. Programming Languages (2)• Procedural programming languages:

• sequential execution• structural information less important• exact timing information is NOT important

• Hardware description languages:• Parallel execution• I/O ports, building blocks• Exact timing information IS important


Why Describe a System?• Design Specification

• Unambiguous definition of components and interfaces• Documentation

• Design Simulation• verify performance prior to/after design implementation

–functional correctness–timing

• Design Synthesis• Automatic generation of a hardware design

• Component and Design Reuse• Technology Independence

ECEU530 F’05



Date post:	08-Oct-2019
Category:	Documents
Upload:	others
View:	5 times
Download:	0 times

ECE U530 Digital Hardware Synthesis -...

Documents