ECE232: Hardware Organization and Designeuler.ecs.umass.edu/ece232/pdf/02-Adder-11.pdf ·...

Adapted from Computer Organization and Design, Patterson & Hennessy, UCB

ECE232: Hardware Organization and Design

Part 2: Datapath Design – Binary Numbers and Adders

http://www.ecs.umass.edu/ece/ece232/

ECE232: Adders 2 Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass Koren

Computer Organization

� 5 classic components of any computer

� Today we will look at datapaths (adder, multiplier, …)

Processor (CPU)

Computer

Control

Datapath

Memory Devices

Input

Output


Unsigned Binary Integers

� Given an n-bit number

0

0

1

1

2n

2n

1n

1n 2x2x2x2xx ++++= −

−

−

− L

� Range: 0 to +2n – 1

� Example

• 0000 0000 0000 0000 0000 0000 0000 10112

= 0 + … + 1×23 + 0×22 +1×21 +1×20

= 0 + … + 8 + 0 + 2 + 1 = 1110

� Using 32 bits

• 0 to +4,294,967,295

x0xn-1


2’s-Complement Signed Integers

� Given an n-bit number

0

0

1

1

2n

2n

1n

1n 2x2x2x2xx ++++−= −

−

−

− L

� Bit n-1 is sign bit

• 1/0 for negative/non-negative numbers

� Range: –2n – 1 to +2n – 1 – 1

� Example

� 1111 1111 1111 1111 1111 1111 1111 11002

= –1×231 + 1×230 + … + 1×22 +0×21 +0×20

= –2,147,483,648 + 2,147,483,644 = –410

� Using 32 bits

• –2,147,483,648 to +2,147,483,647

• Most-negative: 1000 0000 … 0000

• Most-positive: 0111 1111 … 1111

x0xn-1

-81000

-71001

70111

60110

50101

40100

30011

20010

10001

00000

-11111

-21110

-31101

-41100

-51011

-61010

decimal2’s comp.

binary


Signed Negation

� To get –X complement X and add 1

• Complement means 1 → 0, 0 → 1

x1x

11111...111xx 2

−=+

−==+

� Example: negate +2

• +2 = 0000 0000 … 00102

• –2 = 1111 1111 … 11012 + 1= 1111 1111 … 11102

� Subtraction: y – x = y + (x +1)

� Representing a number using more bits

• Preserve the numeric value

� Replicate the sign bit to the left

� Examples: 8-bit to 16-bit

• +5: 0000 0101 => 0000 0000 0000 0101

• –5: 1111 1011 => 1111 1111 1111 1011

Sign Extension


Disadvantage of Signed-Magnitude Method

� Operation may depend on the signs of the operands

� Example - adding a positive number X and a negative number -Y : X+(-Y)

� If Y>X, final result is -(Y-X)

� Calculation -

• switch order of operands

• perform subtraction rather than addition

• attach the minus sign

� A sequence of decisions must be made, costing excess control logic and execution time

� This is avoided in the 2’s complement method


Overflow in 2’s Comp Add/Subtract (1)

� Example -

01001 9 11001 -7

1 00010 2

Carry-out discarded - does not indicate overflow

� In general, if X and Y have opposite signs - no overflow can occur regardless of whether there is a carry-out or not

� Examples -


� If X and Y have the same sign and result has different sign -overflow occurs

� Examples -

10111 -9

10111 -9

1 01110 14 = -18 mod 32

• Carry-out and overflow

01001 9

00111 7

0 10000 -16 = 16 mod 32

• No carry-out but overflow

Overflow in 2’s Comp Add/Subtract (2)


Ripple Carry Adder

� Addition• most frequent operation

• used also for multiplication and division

• fast two-operand adder essential

� Simple parallel adder

• for adding xn-1,xn-2,...,x0 and yn-1,yn-2,…,y0

• using n full adders

� Full adder

• combinational digital circuit with input bits xi,yi and

incoming carry bit ci, producing output sum bit si and

outgoing carry bit ci+1

• incoming carry for next FA with input bits xi+1,yi+1

• si = xi ⊕ yi ⊕ ci

• ci+1 = xi ⋅ yi + ci ⋅ (xi + yi)


Full-Adder (FA)

� Examine the Full Adder table

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

x y Cin Cout S

Cout = x • y + Cin • (x + y)

S = x’y’c + x’yc’ + xy’c’ + xyc

= x ⊕ y ⊕ c

In general, for bit i:

ci+1 = xi yi + ci (xi+yi)

where ci+1 = Cout, ci= Cin

Half adder has 2 inputs. In principle HA is same as FA, with Cin set to 0.

x

y

Cin

Cout

Sum

�


Parallel Adder: Ripple Carry

� In a parallel arithmetic unit

• All 2n input bits available at the same time

• Carry propagates from the FA to the right to FA to the left

• Carries ripple through all n FAs before we can claim that the sum outputs are correct and may be used in further calculations

� Each FA has a finite delay


Example

• x3,x2,x1,x0=1111

• y3,y2,y1,y0=0001

• ∆FA - operation time - delay

• Assuming equal delays for sum and carry-out

• Longest carry propagation chain when adding two 4-bit numbers

� In synchronous arithmetic units -time allowed for adder's operation is worst-case delay - n∆FA


Subtraction using Ripple Carry Adder

� Suppose you are performing X-Y operation

• Complement Y bits

• Force C0 to 1

• add

� Example: X = 0101, Y = 0010; Compute X – Y

� First step: Complement Y

• 1101

� Second step: add 0101 + 1101 + 1 = 0011


Carry Look Ahead Adder

� Problem with Ripple Carry Adder

• Slow

• How much is the delay for a 64 bit adder?

� Solution

• Shorten carry propagation delay

• Wouldn’t it be great to generate all carry signals in parallel?

• How do you do that?

� Observation

1. If Xi = Yi = 1, a carry will be generated, Cin does not matter

2. If Xi = Yi = 0, no carry will be generated by the FA, Cin does not matter

3. When does Cin matter in Cout generation?

• Xi Yi = 01

• Xi Yi = 10

� Carry Look Ahead Adder uses the above observation to generate carry signals in parallel


Carry Look Ahead Adder

Gi =Xi. Yi : generated carry ; Pi=Xi + Yi : propagated carry

C0

X3 Y3

CLL (carry look-ahead logic)

C3

C4

p3 g3

X2 Y2

C2

p2 g2

X1 Y1

C1

p1 g1

X0 Y0

p0 g0

S3S2 S1 S0


Plumbing analogy

p0

c0g0

c1

p0

c0g0

p1g1

c2

p0

c0g0

p1g1

p2g2

p3g3

c4

c1 = g0 + c0 p0

c2 = g1 + g0 p1 + c0 p0 p1

c4 = g3 + g2 p3 + g1 p2p3 + g0 p1 p2p3 + c0 p0 p1 p2 p3


Delay of Carry Look Ahead Adders

� Let τ be the delay of a gate

� If inputs are available at time t=0, when are p and g signals available?

X3 Y3

p3 g3

X2 Y2

p2 g2

X1 Y1

p1 g1

X0 Y0

p0 g0

C0

CLL (carry look-ahead logic)C4

p3 g3 p2 g2 p1 g1 p0 g0

C1C2C3


Delay of Carry Look Ahead Adders

� Which signal will be generated last?

• How long will it take?

C0

CLL (carry look-ahead logic)C4

p3 g3 p2 g2 p1 g1 p0 g0

C1C2C3


Gates are limited to two inputs

� C4=g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0

τ

τ

2τ

3τ

What if there were 6 inputs?





Total Delay

� τ+3τ+ τ +2τ = 7τ� What is the delay of

a 5 bit CLA?

� 6 bit CLA? 7 bit CLA?

� 8 bit CLA?

C0

X3 Y3

(carry look-ahead logic)

C3

C4

p3 g3

X2 Y2

C2

p2 g2

X1 Y1

C1

p1 g1

X0 Y0

p0 g0

S3S2 S1 S0

G* P*

CLL


2-level Carry Look Ahead (16-bit)

� n=16 - 4 groups, 4-bit each

CLL


Plumbing Analogy

p0g0

p1g1

p2g2

p3g3

G*0

p1

p2

p3

P*0


Carry Select Adder

� Principle: speculative

n-bit adder n-bit adderCarry propagate delay

CP(2n) = 2*CP(n)

n-bit adder n-bit addern-bit adder 1 0

Cout

CP(2n) = CP(n) + CP(mux)

Carry-select adder

Compute both, select one

MUX


Summary

� Throw hardware for performance

� Ripple Carry: least hardware, slowest

� CLA: faster, more hardware

� Carry Select: even faster, even more hardware

� Other techniques available, e.g., Carry skip adder

• See http://www.ecs.umass.edu/ece/koren/arith/simulator/

� Combination of these techniques – hybrid adders

� Reading: Chapter 2 - Section 2.4


Different circuit implementation of a CLL

MCC - Manchester Carry module


64-bit Hybrid Adder

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