ECE448_rrtrtrtlecture7_FPGAs

8/10/2019 ECE448_rrtrtrtlecture7_FPGAs

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George Mason UniversityECE 448 FPGA and ASIC Design with VHDL

FPGA Devices

ECE 448

Lecture 7


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2ECE 448 FPGA and ASIC Design with VHDL

Reading

S. Brown and Z. Vranesic,Fundamentals of Digital

Logic with VHDL Design

Chap ter 3.6.5 Field-Programmable Gate Arrays

P. Chu, FPGA Prototyping by VHDL Examples

Chapter 2.2, FPGA

Required

Recommended


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Recommended Reading

Xilinx, Inc.

Spartan-3E FPGA Fam ily

Modu le 1:

Int roduc t ion

Featu resA rchi tectural Overview

Package Marking

Modu le 2:

Conf igurable Logic B lock (CLB)

and Sl ice Resources

Dedicated Mult ipl iers
http://www.xilinx.com/support/documentation/data_sheets/ds312.pdfhttp://www.xilinx.com/support/documentation/data_sheets/ds312.pdfhttp://www.xilinx.com/support/documentation/data_sheets/ds312.pdfhttp://www.xilinx.com/support/documentation/data_sheets/ds312.pdfhttp://www.xilinx.com/support/documentation/data_sheets/ds312.pdf


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Required Reading

Xilinx, Inc.Spartan-3 Generation FPGA User Guide

Extended Spartan-3A , Spartan-3E, and Spartan-3

FPGA Fam il ies

Chapter 5 Using Con f igurable Log ic Blocks (CLBs)

Chapter 6 Using Look -Up Tables as Distr ibuted

RAM

Chapter 7 Using Look -Up Tables as Shif t Registers

(SRL16) [up to L ibrary Prim it ives]


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designs must be sentfor expensive and time

consuming fabrication

in semiconductor foundry

bought off the shelf

and reconfigured by

designers themselves

Two competing implementation approaches

ASICApplicationSpecific

IntegratedCircuit

FPGAFieldProgrammable

GateArray

designed all the wayfrom behavioral description

to physical layout

no physical layout design;design ends with

a bitstreamused

to configure a device


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BlockRAMs

BlockRAMs

Configurable

Logic

Blocks

I/OBlocks

What is an FPGA?

Block

RAMs


7/767ECE 448 FPGA and ASIC Design with VHDL

Which Way to Go?

Off-the-shelf

Low development cost

Short time to market

Reconfigurability

High performance

ASICs FPGAs

Low power

Low cost in

high volumes



Other FPGA Advantages

Manufacturing cycle for ASIC is very costly,lengthy and engages lots of manpower

Mistakes not detected at design time have

large impact on development time and cost FPGAs are perfect for rapid prototyping of

digital circuits

Easy upgrades like in case of software Unique applications

reconfigurable computing



Major FPGA Vendors

SRAM-based FPGAs Xilinx, Inc.

Altera Corp.

Lattice Semiconductor Atmel

Flash & antifuse FPGAs Actel Corp. (Microsemi SoC Products Group)

Quick Logic Corp.

~ 51% of the market

~ 34% of the market~ 85%



Xilinx

Primary products: FPGAs and the associated CAD

software

Main headquarters in San Jose, CA

Fabless* Semiconductor and Software Company UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996}

Seiko Epson (Japan)

TSMC (Taiwan)

Samsung (Korea)

ProgrammableLogic Devices ISE Alliance and Foundation

Series Design Software


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13/76George Mason UniversityECE 448 FPGA and ASIC Design with VHDL

CLB Structure



Programmable

interconnect

Programmable

logic blocks

The Design Warriors Guide to FPGAs

Devices, Tools, and Flows. ISBN 0750676043

Copyright 2004 Mentor Graphics Corp. (www.mentor.com)

General structure of an FPGA



CLB CLB

CLB CLB

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Configurable logic block (CLB)




Xilinx Spartan 3E CLB



COUT

D Q

CK

S

REC

D Q

CK

REC

O

G4G3G2G1

Look-Up

TableCarry

&

Control

Logic

O

YB

Y

F4F3F2F1

XB

X

Look-Up

Table

F5IN

BY

SR

S

Carry

&

Control

Logic

CINCLKCE

SLICE

CLB Slice = 2 Logic Cells


17/7617

16-bit SR

16 x 1 RAM

4-input LUT




Xilinx Multipurpose LUT (MLUT)

16 x 1 ROM(logic)



CLB Structure



CLB Slice Structure

Each slice contains two sets of the

following: Four-input LUT

Any 4-input logic function,

or 16-bit x 1 sync RAM (SLICEM only)

or 16-bit shift register (SLICEM only)

Carry & Control Fast arithmetic logic

Multiplier logic

Multiplexer logic

Storage element Latch or flip-flop

Set and reset

True or inverted inputs

Sync. or async. control


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COUT

D Q

CK

S

REC

D Q

CK

REC

O

G4G3G2G1

Look-Up

TableCarry

&

Control

Logic

O

YB

Y

F4F3F2F1

XB

X

Look-Up

Table

F5IN

BY

SR

S

Carry

&

Control

Logic

CINCLKCE

SLICE

Multipurpose Look-Up Table (MLUT)



16-bit SR

16 x 1 RAM

4-input LUT




MLUT as 16x1 ROM

16 x 1 ROM(logic)

LUT (L k U T bl ) i th B i ROM


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LUT (Look-Up Table) in the Basic ROM

Mode

Look-Up tablesare primary

elements for

logic

implementation

Each LUT can

implement any

function of

4 inputsx1 x2 x3 x4

y

x1 x2

y

LUT

x1x2x3x4

y

0

x10

x2x3x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

0100010

101001100

0

x10

x2x3x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

1111111

111110000

x1 x2 x3 x4

y

x1 x2 x3 x4

y

x1 x2

y

x1 x2

y

LUT

x1x2x3x4

y

0

x10

x2x3x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

0100010

101001100

0

x10

x2x3x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

0100010

101001100

0

x10

x2x3x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

1111111

111110000

0

x10

x2x3x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

1111111

111110000

5 Input Functions implemented using


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5-Input Functions implemented using

two LUTs

One CLB Slice can implement any function of 5 inputs Logic function is partitioned between two LUTs

F5 multiplexer selects LUT

A4

A3

A2

A1WS DI

D

LUT

ROMRAM

1

0

F4

F3

F2

F1

A4

A3

A2

A1

WS DI

D

LUT

ROM

RAM

F5

GXOR

G

nBX

BX

1

0

BX

X

F5

A4

A3

A2

A1WS DI

D

LUT

ROMRAM

A4

A3

A2

A1WS DI

D

LUT

ROMRAM

1

0

1

0

F4

F3

F2

F1

A4

A3

A2

A1

WS DI

D

LUT

ROM

RAM

A4

A3

A2

A1

WS DI

D

LUT

ROM

RAM

F5

GXOR

G

F5

GXOR

G

nBX

BX

1

0

nBX

BX

1

0

BX

X

F5


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16-bit SR

16 x 1 RAM

4-input LUT




MLUT as 16x1 RAM

16 x 1 ROM(logic)


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RAM16X1S

O

D

WE

WCLKA0

A1

A2

A3

RAM32X1S

O

DWE

WCLKA0A1A2A3A4

RAM16X2S

O1

D0

WE

WCLKA0

A1

A2

A3

D1

O0

=

=

LUT

LUT or

LUT

RAM16X1D

SPO

D

WE

WCLK

A0

A1

A2

A3

DPRA0 DPO

DPRA1

DPRA2

DPRA3

or

Distributed RAM

CLB LUT configurable asDistributed RAM A single LUT equals 16x1

RAM

Two LUTs Implement Single

and Dual-Port RAMs Cascade LUTs to increase

RAM size

Synchronous write

Synchronous/Asynchronous

read Accompanying flip-flops used

for synchronous read


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16-bit SR

16 x 1 RAM

4-input LUT




MLUT as 16-bit Shift Register (SRL16)

16 x 1 ROM(logic)


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D Q

CE

D Q

CE

D Q

CE

D Q

CE

LUT

INCE

CLK

DEPTH[3:0]

OUTLUT =

Shift Register

Each LUT can beconfigured as shift register Serial in, serial out

Dynamically addressabledelay up to 16 cycles

For programmablepipeline

Cascade for greater cycledelays

Use CLB flip-flops to add

depth

Using Multipurpose Look Up Tables


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29

Using Multipurpose Look-Up Tables

in the Shift Register Mode (SRL16)

ECE 448 FPGA and ASIC Design with VHDL

Inferred from behavioral description in VHDL

for shift-registers with-one serial input, one serial output

-no reset, no set

Cascading LUT Shift Registers into Shift


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30

Cascading LUT Shift Registers into Shift

Registers Longer than 16 bits



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Shift Register

Register-rich FPGA Allows for addition of pipeline stages to increase

throughput

Data paths must be balanced to keep desiredfunctionality

64

Operation A

4 Cycles 8 Cycles

Operation B

3 Cycles

Operation C

64

12 Cycles

3 Cycles

9-Cycle imbalance


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32

Logic Cell = of a CLB Slice



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33

CLB Slice = 2 Logic Cells



34/76

George Mason University

Examples:

Determine the amount ofSpartan 3 resources needed

to implement a given circuit

m


35/76

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

w

a

b

c

d

yF

clk

0 1 runCircuit 1:

Top level


36/76

1

01

0

0

1

23

4

5

6

7

cin

x y

cout

s


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1

0

1

0

0

1

2

3

4

5

6

7

x y

cout

s

>>2

x3

x2

x1

x0

y3

y2

y1

y0

y1

y0

z

w3

w2

w1

w0

a

b

c

d

a

e

f

g

h

3

Priority Encoder

Half

Adder

g

h

i

e i

y

a

b

c

d

Circuit 2:

Ffunction


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COUT

D Q

CK

S

REC

D Q

CK

REC

O

G4G3G2G1

Look-Up

TableCarry

&

Control

Logic

O

YB

Y

F4F3F2F1

XB

X

Look-Up

Table

F5IN

BY

SR

S

Carry

&

Control

Logic

CINCLKCE

SLICE

Carry & Control Logic


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Full-adder

x

ycouts

FA

x +y +cin= ( cout s )22 1

x y cout s

0

0

0

01

1

1

1

0

0

1

10

0

1

1

0

0

0

10

1

1

1

0

1

1

01

0

0

1

cin

0

1

0

10

1

0

1

cin

F ll dd


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Full-adderAlternative implementations

x y cout s

0

0

1

1

0

1

0

1

0

1

cin

cin

cin

cin

cin

cin

F ll dd


42/76

x

yA2

A1

XOR D

0 1

Cin

Cout

S

p

g

Full-adderAlternative implementations

Implementation used to generate fast carry logicin Xilinx FPGAs

x y cout

00

1

1

01

0

1

y

y

cin

cin

p = x y

g = y

s= p cin= x y cin


43/76


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Critical Path for an

Adder Implemented UsingXilinx Spartan 3/Spartan 3E

FPGAs

Number and Length of Carry Chains


45/76

Number and Length of Carry Chains

for Spartan 3E FPGAs


46/76

Bottom Operand Input to Carry Out Delay

TOPCYF

0.9 ns for Spartan 3


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Carry Propagation Delay

tBYP


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Carry Input to Top Sum Combinational Output Delay

TCINY



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Each CLB contains separatelogic and routing for the fastgeneration of sum & carrysignals

Increases efficiency andperformance of adders,subtractors, accumulators,comparators, and counters

Carry logic is independent ofnormal logic and routingresources

Fast Carry Logic

LSB

MSB

CarryLog

ic

Routing


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Accessing Carry Logic

All major synthesis tools can infer carrylogic for arithmetic functions

Addition (SUM


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Embedded Multipliers


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Combinational and Registered Multiplier


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53

Combinational and Registered Multiplier

ECE 448FPGA and ASIC Design with VHDL

Dedicated Multiplier Block


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54ECE 448FPGA and ASIC Design with VHDL

Dedicated Multiplier Block

Interface of a Dedicated Multiplier


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55ECE 448FPGA and ASIC Design with VHDL

Interface of a Dedicated Multiplier

3 W t U D di t d H d


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56

3 Ways to Use Dedicated Hardware

Three (3) ways to use dedicated(embedded) hardware

Inference

Instantiation CORE Generator


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Unsigned vs Signed Multiplication


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Unsigned vs. Signed Multiplication

11111111x

11100001

1515x

225

11111111x

00000001

-1-1x

1

Unsigned Signed


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CORE Generator


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CORE Generator


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62

FPGA Block RAM

Block RAM


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63

Block RAM

Spartan-3

Dual-Port

Block RAM

P

ortA

P

ortB

Block RAM

Most efficient memory implementation

Dedicated blocks of memory

Ideal for most memory requirements

4 to 36 memory blocks in Spartan 3E

18 kbits = 18,432 bits per block (16 k without parity bits)

Use multiple blocks for larger memories

Builds both single and true dual-port RAMs

Synchronous write and read (different from distributed RAM)

RAM Blocks and Multipliers in Xilinx FPGAs


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64

RAM blocks

Multipliers

Logic blocks

RAM Blocks and Multipliers in Xilinx FPGAs




Spartan-3E Block RAM Amounts


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65

Spartan-3E Block RAM Amounts


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Single-Port Block RAM


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68

Single Port Block RAM

DI[w-p-1:0]

DO[w-p-1:0]

Dual-Port Block RAM


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69

Dual Port Block RAM

DIA[wA-pA-1:0]

DOA[wA-pA-1:0]

DOA[wB-pB-1:0]

DIB[wB-pB-1:0]


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Input/Output Blocks(IOBs)

Basic I/O Block Structure


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D

EC

Q

SR

D

EC

Q

SR

D

EC

Q

SR

Three-StateControl

Output Path

Input Path

Three-State

Output

Clock

Set/Reset

Direct Input

RegisteredInput

FF Enable

FF Enable

FF Enable

IOB Functionality


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IOB Functionality

IOB provides interface between thepackage pins and CLBs

Each IOB can work as uni- or bi-directional

I/O Outputs can be forced into High Impedance

Inputs and outputs can be registered

advised for high-performance I/O

Inputs can be delayed


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Spartan-3E Family Attributes


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FPGA Nomenclature


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FPGA Nomenclature

FPGA device present on theDi il t B 2 b d


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Digilent Basys2 board

XC3S100E-4CP132

Spartan 3E

family

100 k

equivalent

logic gates

speed

grade

-4= standard

performance

132 pins

package type

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