Division and square root are common functions used in digital systems such as microprocessors. Microprocessors that have hardware to perform division and square root are able to do those functions with fewer clock cycles, and more power effictiently. This implementation utilizes a 36 bit multiplication unit to implement the Goldschmidt algorithm with enough precision to give a large amount of accuracy, and it also utilizes a two stage pipeline in order to increase the efficiency of the implementation.
1 ECEN 4233 – Implentation of Goldschmidt’s algorithm for 16 bit division and square root Cale Spratt and Jeremy Storm, Oklahoma State University Abstract— Division and square root are common functions used in digital systems such as microprocessors. Microprocessors that have hardware to perform division and square root are able to do those functions with fewer clock cycles, and more power effictiently. This implementation utilizes a 36 bit multiplication unit to implement the Goldschmidt algorithm with enough precision to give a large amount of accuracy, and it also utilizes a two stage pipeline in order to increase the efficiency of the implantation. Index Terms—Goldschmidt’s Algorithms, Carry Propagate Adder, Full Adder, Half Adder, Carry Save Array Multiplier —————————— —————————— 1 INTRODUCTION In this implemtation, the designed hardware can per- form these operations: a) Division b) Square Root c) Multiplication Division and square root are common mathematical functions. Due to the importance of the two functions, it is beneficial to create an implementation that runs efficiently and that produces accurate, reliable results after each use. To decrease the amount of clock cycles that are required to perform division or square root, the design has been pipelined, allowing for two different divisions or or square roots to be performed at the same time. Implementing Goldschmidt’s algorithms requires the use of a multiplier, and because of this, the designed hardware can also implement multiplication, with the addition of a few control lines, allowing for this module to be even more functional. Most applications that uti- lize any division method are dependent upon the preci- sion expectations that the hardware outputs. For our implementation we assumed lower precision with a sign bit, integer bit, and 14-bits of precision for values falling between [1,2) and (-2,-1]. If our design had requested a larger division subset then we would have expanded the precision and implemented a modified approximation protocol to account for more effective number of interations. If a division is to occur then the approxima- tion muxes with select the corresponding sign value of 0.75 or -0.75, otherwise a square root is assumed and the value will be 0.833. It is very important to select the correct approximation to create the proper division. The value must always fall to the left of the quotient when on an exponentially decreasing graph. Our module uses the control muxes, “A” and “B”, to select the registers or input values we are going to propagate through the multiplier. Specific output values have been mapped to certain registers to create a specific pipelining process. 2 DIVISION 2.1 Goldschmidt Method The Goldschmidt method is a method for approximating the zeroes of a real function. This method calculates Q = N/D. It is an iterative method that successively gives a better approximation after each iteration. The amount of bits of error grows quadratically after each successive iteration. The equation for determining the quotient is K1 is obtained from utilizing the intial approximation that is provided from the mux unit dependent upon mathematical operation. The number of iterations needed is equal to (n/log_2(radix)), where n is the number of bits of precision.
Transcript
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ECEN 4233 – Implentation of Goldschmidt’s algorithm for 16 bit division and square root
Cale Spratt and Jeremy Storm, Oklahoma State University
Abstract— Division and square root are common functions used in digital systems such as microprocessors. Microprocessors that
have hardware to perform division and square root are able to do those functions with fewer clock cycles, and more power
effictiently. This implementation utilizes a 36 bit multiplication unit to implement the Goldschmidt algorithm with enough precision to
give a large amount of accuracy, and it also utilizes a two stage pipeline in order to increase the efficiency of the implantation.
Index Terms—Goldschmidt’s Algorithms, Carry Propagate Adder, Full Adder, Half Adder, Carry Save Array Multiplier
—————————— ——————————
1 INTRODUCTION
In this implemtation, the designed hardware can per-
form these operations:
a) Division
b) Square Root
c) Multiplication
Division and square root are common mathematical
functions. Due to the importance of the two functions,
it is beneficial to create an implementation that runs
efficiently and that produces accurate, reliable results
after each use. To decrease the amount of clock cycles
that are required to perform division or square root, the
design has been pipelined, allowing for two different
divisions or or square roots to be performed at the
same time.
Implementing Goldschmidt’s algorithms requires the
use of a multiplier, and because of this, the designed
hardware can also implement multiplication, with the
addition of a few control lines, allowing for this module
to be even more functional. Most applications that uti-
lize any division method are dependent upon the preci-
sion expectations that the hardware outputs. For our
implementation we assumed lower precision with a sign
bit, integer bit, and 14-bits of precision for values falling
between [1,2) and (-2,-1]. If our design had requested a
larger division subset then we would have expanded the
precision and implemented a modified approximation
protocol to account for more effective number of
interations. If a division is to occur then the approxima-
tion muxes with select the corresponding sign value of
0.75 or -0.75, otherwise a square root is assumed and
the value will be 0.833. It is very important to select the
correct approximation to create the proper division. The
value must always fall to the left of the quotient when
on an exponentially decreasing graph. Our module uses
the control muxes, “A” and “B”, to select the registers
or input values we are going to propagate through the
multiplier. Specific output values have been mapped to
certain registers to create a specific pipelining process.
2 DIVISION
2.1 Goldschmidt Method
The Goldschmidt method is a method for approximating
the zeroes of a real function. This method calculates Q =
N/D. It is an iterative method that successively gives a
better approximation after each iteration. The amount
of bits of error grows quadratically after each successive
iteration. The equation for determining the quotient is
K1 is obtained from utilizing the intial approximation
that is provided from the mux unit dependent upon
mathematical operation.
The number of iterations needed is equal to (n/log_2(radix)), where n is the number of bits of precision.
2 HIGH SPEED PROJECT SPRAT, STORM
3 Hardware Modules
A. Initial Approximation
The initial approximation (IA) module consists of 3
16-bit mux units that cascade a combination of signed
approximations based on the mathematical function
requested. The inputs values are between [1,2) or (-2,-
1]. There are only three constant approximations of
0.75, -0.75, and 0.833 where the first two correspond to
specified signed divisions. The value 0.833 is the ap-
proximation used for a square root operation. A 2-bit
selection input is provided to the cascaded muxes to
select the operational approximation for calculation.
Area is 96 gates. Delay is 6∆.
B. Multiplexers
We have a total of three multiplexor sets that assist
in implementing the expected mathematical operation
for each interation of the pipeline stages. Multiplexor
“A” is used to delinieate between the 16-bit values from
the intitial approximation unit, inputs N and D, and the
two register units C and D. A 3-bit mux selection input
determines the 16-bit mux output value that is propa-
gated to our multiplier. All values passed to the multi-
plier through the muxes will be spliced with two addi-
tional bits for higher precision during multiplication. The
table below provides all selection bit operations for
multiplexor “A”. Area is 288 gates. Delay is 9∆.
Mux Select (3 bits) Output (16 bits)
000 ---
001 Regc
010 ----
011 D
100 Regd
101 IA
110 ---
111 N
Multiplexor “B” is implemented to select a 16-bit
output value from inputs of initial approximation, regis-
ter A and register B. This mux has the intented opera-
tion of provide the second multiplication value for our
CSAM multiplier. The logic table for multiplexor “B” is
listed below. Area is 96 gates. Delay is 6∆.
Mux Select (2 bits) Output (16 bits)
00 Rega
01 Regb
10 Rega
11 IA
Multiplexor “Two’s” was devoted to propagating ei-
ther a 16-bit two or three to the 2’s complement mod-
ule in order to perform either a division or square root.
The table for the logic is provided below. Area is 96
gates. Delay is 6∆.
Mux Select (1 bit) Output (16 bits)
0 16’h4000
1 16’h6000
SPRAT, STORM HIGH SPEED PAPER 3
The multiplexor for the 2’s complement logic unit
has an area of 48 gates and 3∆ based on the layout of the
unit.
C. Signed Carry Save Array Multiplier (CSAM)
The Carry Save Array Multiplier (CSAM) is a pipe-
lined module to give the external register units the abil-
ity to store the appropriate multiplication value. Our
multiplier was instantiated to be 36-bits with two 18-bit
inputs from pre-module muxes. This multiplier gives
one integer and sign bits, with 16-bits of precision.
Three 18-bit register modules that incorporate latch
control were placed between the multiplication array
and the Carry Propagate Adders (CPA). This in required
to allow the expected pipelining capability. These regis-
ters store the carries and sum values for propagation
into the CPAs. The implementation was developed to
utilize 16-bit external registers so all the inputs and
outputs have to be extended or spliced to meet the
processing requirements. The most-significant two bits
are always removed following the CPA sum being calcu-
lated. In other words we have performed the same
function as a rounding unit would. Area is 2433 gates.
Delay is 37∆ .
D. 2’s Complement Module
The complement subtractor has to be integrated
to perform both division and square root functions. An
input mux determined the complement value designat-
ed for the intended mathematical operation. For the
division operation, the 2’s complement logic uses a 16-
bit value of 2 that implements as
an output from the 2’s selection mux. A 16-bit value of
3 will be implemented for a square root operation. Our
2’s complement module has 16-bit inputs and outputs
but they have to be modified to include one additional
integer bit for the multiplier value being utilized. We
concatenate one bit after the left-most bit for the mul-
tiplier and one bit to the right-most bit of the subtractor
value. After the subtraction is complete then the addi-
tional integer bit is removed before propagating the
output. Area is 144 gates for 16-bits. Delay is 55∆
E. Total Area and Delay
The total area for the entire block is the sume of the ini-
tial approximation unit, two input muxes,
squareroot/division mux, multiplier and the 2’s comple-
ment logic unit. This area comes out to be 3105 gates.
The delay also follows the same process and comes out
