ECET 581

11/16/200611/16/2006 WSN Mote- MCU & Sensor HardwareWSN Mote- MCU & Sensor Hardware 11

ECET 581ECET 581

Wireless Sensor NetworksWireless Sensor Networks

Mote – MCU & Sensor HardwareMote – MCU & Sensor Hardware1 of 31 of 3

Fall 2006Fall 2006

http://www.etcs.ipfw.edu/~linhttp://www.etcs.ipfw.edu/~lin


WSN Mote & Sensor HardwareWSN Mote & Sensor Hardware

Computing Platform ArchitectureComputing Platform Architecture Processor ArchitectureProcessor Architecture Software ArchitectureSoftware Architecture Distributed ComputingDistributed Computing Hardware/Software CodependenciesHardware/Software Codependencies ADC and Sensors InterfacesADC and Sensors Interfaces


Computing Platform ArchitectureComputing Platform Architecture

The Instruction Set Architecture (ISA)The Instruction Set Architecture (ISA)• Lowest-level of abstractionLowest-level of abstraction• Providing access to processor instructionsProviding access to processor instructions• Data transfer: CPU Data transfer: CPU ↔ ↔ RegistersRegisters

Machine ArchitectureMachine Architecture• System communication busesSystem communication buses• Memory elementsMemory elements• Peripheral componentsPeripheral components

Machine ImplementationMachine Implementation• Logic gatesLogic gates• TransistorsTransistors


Computing Platform ArchitectureComputing Platform Architecture Design PrinciplesDesign Principles

• Hierarchy of LayersHierarchy of Layers• Separating implementation from interfaceSeparating implementation from interface

Influenced by designs ofInfluenced by designs of• Various computer systems: Mainframe Various computer systems: Mainframe

computers, Mini computers, Microcomputers, computers, Mini computers, Microcomputers, MicrocontrollersMicrocontrollers

• Advancement in physical implementation Advancement in physical implementation capabilitiescapabilities

Vacuum tube, semiconductors, processesVacuum tube, semiconductors, processes Moore’s Law – empirical observation in 1965 by Moore’s Law – empirical observation in 1965 by

Gordon E. Moore that the number of transistors on an Gordon E. Moore that the number of transistors on an IC for the minimum component cost, double every 24 IC for the minimum component cost, double every 24 monthsmonths


Major Abstraction Layers – A Major Abstraction Layers – A Computer SystemComputer System

Users - InterfacesUsers - Interfaces Applications – System call interfacesApplications – System call interfaces Programming LanguagesProgramming Languages CompilersCompilers AssemblersAssemblers Process Instructions SetsProcess Instructions Sets Processor Data PathsProcessor Data Paths Logic BlocksLogic Blocks Logic GatesLogic Gates TransistorsTransistors Semiconductor SystemsSemiconductor Systems


Abstraction Layers – Operation Abstraction Layers – Operation ViewView

User Interface

System Call Interface

Instruction Set Arch.

Bus Interface

User

Application

Operating System

Processor

Memory, Peripherals


Processor ArchitectureProcessor Architecture

Control UnitControl Unit Combinational UnitCombinational Unit

• ALUALU• ComparatorsComparators• ShiftersShifters

Storage ElementsStorage Elements• CPU registersCPU registers

OperationsOperations• Instruction fetchInstruction fetch• Instruction decodeInstruction decode• Operand fetchOperand fetch• Instruction executionsInstruction executions• StorageStorage


TI MSP430161x Mixed Signal MCUTI MSP430161x Mixed Signal MCU


TI MSP430161x Mixed Signal RISC TI MSP430161x Mixed Signal RISC MCU MCU Functional BlocksFunctional Blocks


TI MSP430161x RegistersTI MSP430161x Registers

RISC ArchitectureRISC Architecture• 27 core instructions27 core instructions• 24 emulated instructions24 emulated instructions• 7 addressing modes7 addressing modes• Constant generatorConstant generator

Buses:Buses:• 16-bit Memory Data Bus 16-bit Memory Data Bus • 16-bit Mem. Addr Bus16-bit Mem. Addr Bus

16-bit Gen. Purpose Reg: R0-16-bit Gen. Purpose Reg: R0-R15R15

Single-cycle register Single-cycle register operationsoperations

Memory-to-memory atomic Memory-to-memory atomic addressingaddressing

Bit, byte, and word procesisngBit, byte, and word procesisng


MSP 430 Memory MapMSP 430 Memory Map Flash MemoryFlash Memory

• (x) 512 byte memory (x) 512 byte memory segmentssegments

• 4KB – 8 mem. seg4KB – 8 mem. seg Flash In-System Flash In-System

Programming MethodsProgramming Methods• Self programming – Self programming –

normal softwarenormal software• JTAG – out/in-systemJTAG – out/in-system• Bootstrap Loader Bootstrap Loader

(BSL)(BSL)• Data storageData storage

Flash Control RegistersFlash Control Registers


Operating ModesOperating Modes Active Mode (AM)Active Mode (AM)

• All clocks are activeAll clocks are active Low-Power Mode 0 (LPM0)Low-Power Mode 0 (LPM0)

• CPU – disabledCPU – disabled• Subsystem clock (SMCLK) and Auxiliary Clock (ACLK) - active; Main Subsystem clock (SMCLK) and Auxiliary Clock (ACLK) - active; Main

system clock (MCLK) - disabledsystem clock (MCLK) - disabled Low-Power Mode 1 (LPM1)Low-Power Mode 1 (LPM1)

• CPU disabledCPU disabled• ACLK, SMLK active; SMCLK disabledACLK, SMLK active; SMCLK disabled

Low-Power Mode 2 (LPM2)Low-Power Mode 2 (LPM2)• CPU disabledCPU disabled• MCLK and SMCLK – disabled, ACLK - activeMCLK and SMCLK – disabled, ACLK - active

Low-Power Mode 3 (LPM3)Low-Power Mode 3 (LPM3)• CPU disabledCPU disabled• MCLK and SMCLK disabled, ACLK - activeMCLK and SMCLK disabled, ACLK - active

Low-Power Mode 4 (LPM4)Low-Power Mode 4 (LPM4)• CPU disabledCPU disabled• ACLK, MCLK, SMCLK - disabledACLK, MCLK, SMCLK - disabled


MSPF2xx Enhanced Clock SystemMSPF2xx Enhanced Clock System

• Very Low-PowerVery Low-Power Oscillator (VLO)Oscillator (VLO)

• Digitally Controlled Digitally Controlled Oscillator (DCO)Oscillator (DCO)


TI MSP430161x ADCTI MSP430161x ADC


TI MSP430F20x2 Flexible ADC10TI MSP430F20x2 Flexible ADC10

10-bit ADC10-bit ADC 200ksps+200ksps+ Autoscan: A3-A2-A1-A0Autoscan: A3-A2-A1-A0 Single sequence, Single sequence,

Repeat-single, Repeat-Repeat-single, Repeat-sequencesequence

Int/ext refInt/ext ref TA SOC (Start of TA SOC (Start of

Conversion) triggers – Conversion) triggers – Timer-A (Timer/Counter Timer-A (Timer/Counter with 3 capture/compare with 3 capture/compare registers)registers)

Direct Transfer Direct Transfer Controller (DTC)Controller (DTC)


USI Fast Synchronous Data USI Fast Synchronous Data TransferTransfer

SPI ModeSPI Mode• 8/16-bit shift register8/16-bit shift register• MSB/LSB firstMSB/LSB first

I2 Mode SupportI2 Mode Support• START/STOP START/STOP

detectiondetection• Arbitration lost Arbitration lost

detectiondetection Interrupt DrivenInterrupt Driven Reduces CPU LoadReduces CPU Load


USI Fast Synchronous Data USI Fast Synchronous Data TransferTransfer

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