Economical realisation of asynchronous sequentialcircuits using random-access memories

Babu Thomas, B.E., M.Sc.(Eng.), and Prof. P.C. Chandrasekharan, B.E., M.Sc.(Eng.), M.S., Ph.D.

Indexing terms: Computers and computation, Asynchronous sequential circuits, Race and hazards, Stateassignment

Abstract: This paper shows that by taking advantage of a fairly uniform delay distribution in semiconductorrandom-access memories (ROMs and read-write memories in integrated circuit form) it is possible to realiseasynchronous sequential circuits (ASCs) economically. It is shown that the ASC so designed will functionwithout fault, in spite of the presence of races and essential hazards in the ASC.

1 Introduction

ASCs, because of their faster response, are sometimes preferredover synchronous circuits. At times the design of an ASC mayprove to be difficult because of constraints on state assign-ments and the presence of essential hazards. A very recentpaper [1] by Ditzinger and Lipp describes a method by whichprogrammable logic arrays and random-access memories canbe used as ASCs with direct feedback and arbitrary state-assignment, provided certain design conditions based on actualmeasurements on the device to be used are satisfield. Sholl andYang [2] have suggested a method of using read-only memories(ROMs) to design ASCs, where arbitrary state-assignment isnot possible.

This paper shows that ASCs with direct feedback can berealised using random-access memories, {random-access read-only memory (ROM) and random-access read-write memory(RAM)} with the following advantages:

(a) No measurements on the memory device need be madebefore using it as an ASC.

(b) State assignment is arbitrary.(c) The ASC will function without fault, in spite of the

presence of races and essential hazards in the circuit.In the subsequent Sections, it will be shown that the inherentuniform delay distribution in the memories favours the designof the ASCs as described above.

2 Realisation of ASCs using random-access memories

In the usual procedure adopted in designing an ASC, the stateassignments are made in such a way that race conditions donot exist in the circuit. In this paper, this restriction is relaxed,thus making the state assignment arbitrary. The transitiontable for the ASC will have 2n x 2m cells, where n is the num-ber of inputs and m is the number of state variables and therandom-access memory used to realise the ASC will have.(n + m) address inputs and k outputs (k > m). Such an ASC isshown in Fig. 1.

2.1. Operation of the ASC in the presence of race conditions:

Race conditions are said to exist in an ASC if more than onenext-state variable is required to change at the same time.Under race conditions, if the circuit can land in more than onestable state, the race is said to be critical [3]. It will now beshown that when an ASC is realised using random-accessmemories (with direct feedback), the existence of race con-ditions will not cause faulty operation of the ASC, providedcertain delay constraints are satisfied.

Fig. 1 gives a simplified representation of a random-access

Paper 1290E, first received 12th May and in revised form 5thNovember 1980The authors are with the Department of Electrical Electronics &Communication Engineering, College of Engineering, Madras 600025,India

memory. Assume that the propagation delay tB of the bufferis zero. When a certain address is present at the address inputs,one of the 2n+m outputs Pt(i = 1,. . . , 2 n + m ) of the addressdecoder is selected. The outputs Yx, . . . , Ym will assumestates, depending upon how they have been programmed withrespect to the selected output Ph of the address decoder.There is a finite delay (ty) associated with the change of anyYj(f = 1,. . ., m). This delay is caused by the active devices(turn on or turn off time) present at the matrix points of theconnection matrix. Assume that this delay is zero. Now,whenever the input address changes a new Pt is selected. Whena new Pt is selected the corresponding outputs Yt,. . . , Ym

change state simultaneously (ty = 0). Hence the state variableschange state simultaneously. Therefore there is no possibilityfor races to occur in the circuit.

Now the restrictions ty = 0 and tB = 0 are removed. Thismay introduce delays between the instants of change of state-variables Yi,..., Ym, when the address of the decoderchanges. Let the maximum delay (worst case) that can occurbetween the instants of change of any two Yjs be tYY, then

V ~"~ Bmax )' V (1)

The suffixes max and min indicate the maximum and mini-mum values of the variables. Eqn. 1 is obtained as follows. IfYp experiences, say, maximum delay, then that delay is(hmax + tBmax)- If ^k experiences minimum delay, then thatdelay is (tymin + tBmin). Hence the difference between thesetwo delays tYY is the maximum possible delay between anytwo Yjs (1 <p and k<m,p¥:k).

Eqn. 1 gives the maximum delay that may exist betweenany two state variables which appear as address inputs (feed-back inputs) to the random-access memory shown in Fig. 1.If the wrong states (race condition) appearing at the addressinputs due to the delay tYY are to be ineffective, then thedevice should not respond to these wrong states. To determineunder what conditions the device will not respond to thewrong states,, some experiments were carried out. The resultsof the experiments are summarised as below. (Details of theexperiments are given in Appendix 6.1)

(a) The response of random-access memory devices to thedelay tYY is technology dependent.

Ki Vm

2 n * m xmconnection matrix

Fig. 1ASC

random-access memorySimple representation of a random-access memory used as an

IEE PROC, Vol. 128, Pt. E, No. 3, MA Y1981 0143-7062/81/030129 + 04 $01.50/0 129

(b) For CMOS technology, the delay tYY does not resultin faulty operation of the ASC if

tYY < 0.3 tc (2)

where tamin is the minimum access time of the device. Similarly,for bipolar technology the corresponding relationship is

fyy < tamin 0)

From relations 1, 2 and 3 it is seen that the minimumvalues of delay times or propagation times should be known.Normally, the data sheets of the devices do not give thisinformation. It has been found that the minimum value ofpropagation delay tpd for any device can be got as (SeeAppendix 6.2)

'pdmin ~~ 'pdtyp Vpdmax *pdtyp) v v

Eqn. 4 implies that the maximum and minimum delay valuesare symmetrical about the typical value.

2.2. Operation of the ASC in the presence of essentialhazards

If a next-state variable is a function of other present-statevariables and if all next-state variables do not 'see' a change ofstate of an input variable at the same time, essential hazardsresult. Whenever an input changes, the maximum differencebetween the instants when Y}s change state is tYY. In

other words, the maximum difference between the instants atwhich the YjS 'see' an input change is tYy- Essential hazardscannot occur if relations 2 and 3 are satisfied for the twotechnologies considered.

Table 1 gives some examples of ROMs and RAMs whichcould be used as ASCs as discussed in this paper.

Table 1: Examples of bipolar memories which could be used as ASCs

ROM tBbmax tyy ta Reference

3602A \2622A j

3602 \3622 ]

3608 \3628 j

3636-1

DM 74S288\*DM74S188 j

22

22

22

22

5

5

5

5

5

2

22

22

22

22

5

5

5

5

5

2

34

34

34

34

6

40

50

50

35

14

[•4

4

8

f 7

(e

DM74S189 *DM 74S289(RAM)

15

Assumption: ty — tB. Minimum values are got using eqn. 4All units are in nanoseconds(a), (£>): These are assumed to be one gate delay*Schottky devices

2.3 Race and essential hazard considerations in ASCs usinglarge capacity memories

Very large capacity memories do not have the same structure

of one (Fig. 2). All feedback lines are to be connected to thesame decoder (X decoder) since the tracking of delay values isvery close for such a connection [1]. The gating circuit andthe.Y decoder are the extra circuitry in Fig. 2, comparedwith the memory of Fig. 1. Let the gating circuit and bufferdelay be tGB. Any ASC constructed using memories such asshown in Fig. 2 will not malfunction because of raceconditions provided

YY <

for bipolar memories, where

Yy = (t tGBmax) ~ (t tGBmin)

(5)

(6)

The variable tamin is the minimum value of propagation delay(access time) between X decoder inputs and any Yj and tYY isas defined in Section 2.1.

Any two F;s 'see' an input change (X decoder inputs) witha delay of tYY = (tymax + tGBmax) - (tymin + tGBmin) whichis same as eqn. 6. If tYY < tamin, the circuit cannot land in awrong state, i.e. essential hazards cannot cause faulty operationof the ASC. Similarly, any two Yjs 'see' an input change(Y decoder inputs) with a delay of

tYY = (tDmax + tGBmax) — (tDmin + tGBmin)

~ '•amax *amin \')

where

~ VD "•"

is the maximum access time and

itDmin *" ^GBmin)

and tD corresponds to the Y decoder delay. Essential hazardswill not cause a malfunction if tYY < tamin. Using eqn. 7, thiscondition is given by

-tn .) < (8)

From eqn. 4, romjn is given by

^arnin ~ tatyp Vamax t,

random-access memoryatypj

inputs x , , . . . ,xn

outputs

R g 2 Gmeml represmtation of a iarge.capacity random-accessas shown in Fig. 1. There are two (X and Y) decoders instead memory used as an ASC

Table 2: Examples of large-capacity bipolar memories, which could be used as ASCs

ROM*

DM 87S229/228DM 74S387/287

tymax

0.50.5

HiBmax

2 X 5

2 X 5

tymin tGBmin

2 2 X 2

2 2 X 2

tamax

7050

*atyp

5735

tamin

4410

t Y Y

99

Reference

77

(a) one gate delay is assumed, (6) two gate delays are assumedMinimum values are obtained using eqn. 4All units are in nanoseconds,*Schottky

130 IEEPROC, Vol. 128, Pt. E, No. 3, MA Y 1981

Using the above equation, eqn. 8 becomes,

i.e.

1.33 tatyp

(9)

Any bipolar random-access memory (with XY decoders)satisfying conditions 5 and 9 can be used as an ASC withdirect feed-back. Table 2 gives some examples.

It is worth noting that in the expressions for tYY (eqns. 1and 6), it is unlikely that while one output of a circuitexperiences maximum delay, simultaneously another outputof the same circuit will experience minimum delay in responseto an input change. In other words, the factor of safetyassociated with eqns. 1 and 6 (and hence with the methodproposed here) will be actually more in a practical situation,than what has been assumed in this paper.

2.3 Some practical considerationsWhen an ASC has more than one output (multiple outputs)delays such as tYY (given by relations 1 and 6) may give wrongoutputs for the circuits (say circuit C) into which the outputsof the ASC operate. The above statement is true irrespective ofthe type of hardware used to realise the ASC. When theoutputs of the ASC are used independently, then the aboveproblem does not arise. The following method may be adoptedto avoid faulty operation of circuits like C (for bipolarcircuits). Choose the propagation delay tc of circuit C suchthat tYY <tcmin. This may reduce the speed of operation ofthe system in which the ASC is operating, but an improvement

• of speed compared with the corresponding synchronoussystem is possible, if circuits like C are clocked at a rate whichis greater than the clock of the synchronous system.

2.4 Cost reductionIn realising an ASC as per the method proposed in this paper,no measurement need be made on the device to be used as anASC, whereas such a measurement is necessary in a similarmethod proposed in Reference 1. Thus the cost of implementingthe ASC decreases.

There is another aspect of the proposed method whichreduces the cost of implementing the ASC, especially when thecircuit has a large number of states. Since the state assignmentis a arbitrary, no extra techniques need be employed not onlyrace conditions. Thus arbitrary state assignment not onlyeliminates the need for detecting race conditions in the designof the ASC, but also does not force the designer to createextra states in the circuit so as to avoid race conditions (see forexample Reference 5). It can clearly be seen that the abovementioned advantages will effect a considerable amount ofsaving in the design and hardware cost of the ASC, especiallywhen the circuit is a large-state ASC.

3 Conclusion

It has been shown that ASCs which are not affected in theiroperation by race and essential hazard conditions can beconstructed using bipolar random-access memories. Themethod given in this paper has the advantage that no measure-ments need be made on the device to be used as an ASC,whereas the method described in Reference 1, needs such ameasurement. This advantage directly reduces the cost ofimplementing an ASC. The economy of implementing large-state ASCs using the proposed method was indicated.

4 Acknowledgment

The authors wish to thank the referees for their constructivecomments.

IEE PROC, Vol. 128, Pt. E, No. 3, MA Y1981

5 References

1 DITIZINGER, A., and LIPP, H.M.: 'Use of memories andprogrammable logic arrays for asynchronous sequentialcircuits', IEE J. Comput. and Digital Tech., 1979, 2, (5),pp. 213-220

2 SHOLL, H.A., and YANG, S.C.: 'Design of asynchronous sequentialnetworks using read-only memories, IEEE Trans., 1975, C-24, pp.195-206

3 LEE, C.S.: 'Modern switching theory and digital design (PrenticeHall, 1978) pp. 368

4 Intel semiconductor memory book (Wiley Interscience, 1978) pp.351,360,67

5 EDWARDS, F.H.: 'Principles of switching circuits', 1973, pp. 187-190

6 TTL data book, National Semiconductor, 1976, pp. 1. 126,1.377 Memory data book, National Semiconductor, 1977, pp. 5.3, 2.8,

2.23,5.28,5.58 Intel component data catalog, 1979, p. 4.459 Signetics data book, 1972, pp. 115, 50, 54

6 Appendix

6.1 Details of experiments conducted to determine theminimum pulse width that a logical device can pass

In Section 2.1 the maximum delay than can occur between theinstants of change of any two YjS was defined as tYY. Thisthen would be the maximum delay between any two of thefeedback address inputs of the ASC. Experiments wereconducted on CMOS and bipolar devices to determine therelationship between tYYmin and the propagation delaytpd of a device, where tYYmin corresponds to the value of tYY

for which the output of the device falls below its thresholdlevel. The procedure adopted was to apply to one input ofa device a pulse of duration tYY (from the output of adevice whose fabrication technology is the same as that of thedevice under test, so as to simulate the feedback input of theASC). The above procedure gave the same results as wereobtained when two inputs with a delay of tYY wereapplied to a device under test. Table 3 gives the result ofthe tests done on bipolar devices. The threshold for the abovedevices is 1.5 V and tpd and tYYmin are defined with respectto the threshold where tYYmin is the value at which theoutput of the device falls just short of 1.5 V. It is found that astraight line fits (method of least squares) the data in Table 3,giving the expression,

tYYr = 1.6*Pd

The above result can be stated thus: a logical device (bipolar)cannot pass a pulse whose width is less than 1.6 times thepropagation delay of that device. In other words, tYY asdefined in the body of the paper should be such that

tYY < 1.6 tPd (10)

if the ASC is not to be affected by race and essential hazardconditions. To obtain a higher reliability, minimum value isassumed for tpd Hence relation 10 is given by,

tYY = 1.6 tpdmin

Representing tpd by ta, the access time of the memory device,tYY is written as tYY < 1.6 tamin.

Normally tamin is not specified in the data sheets. It canbe computed knowing the maximum and typical values ofta. In Appendix 6.2 this computation is shown where a factorTable 3: Measurements on bipolar devices

Measuredvaluesin ns

xpdtYYmin

Device

7432

1020

(without the standard load circuit)

7486

1222

7485

2030

74121 7448

35 6060 100

74123

2540

131

of safety of 40% is associated with tamin. Thus tYY will begiven as

tYY (11)

The values for tYY and tamin as obtained from the data sheetscorrespond to full fan-out of the outputs concerned. But in anASC as proposed in this paper all outputs may not have fullfan out. This will tend to decrease tYY and tamin slightly,but the net effect can be neglected for all practical purposes.Experiments done with CMOS devices yielded a relationshipfor tYY as

tYY <03tamin

It was found that there is no device which can satisfy thisrelationship. For CMOS devices tYY = 160ns which gives:a value of 533ns for tamin. Even if a device with such avalue for tamin is available, it will be slower compared with asimilar bipolar device.

6.2 Determination of minimum propagation delayThe data sheets of integrated circuit devices normally specifyonly the maximum and typical values of propagation delaytimes. But there are certain devices for which the minimumvalue also is given, in addition to maximum and typical values.Examples for TTL devices are as follows [9]: 7442, 43, 44,70, 72, 73, 74, 76, 98, 107, 121, 164, 166, 194, 195. Someof the memory devices for which the minimum propagationdelay is specified are 2115 and DM 54S3 87/287 (See Table 4).

It is found from the data sheet of the above devices thatfor a majority of them the minimum and maximum values are.

symmetrically distributed around the typical value. Some suchdevices are listed below in Table 4 (SI. No. 1 and 2).Table 4: Propagation delays of bipolar devices

SI. No.

12345

Device

74121DM 54S387/287 (PROM)744274742115 (RAM) Series

Propagation delay

min

151010105

f y p

3535221415

max

5560302530

Reference

97994

In the view of the above discussion, it can be said that theminimum and maximum values of propagation delay have asymmetrical distribution around the typical value, i.e.

Vmox hyp) \hyp

hence

= t typ \Jmax '•typ) (12)

There are certain devices like 7474 and 2115 shown in Table4 for which the minimum values are closer to the typicalvalues than the value obtained from eqn. 12. This onlyensures a greater factor of safety for the value of tmin, in thecontext of fault-free operation of the ASC. Some devices like7442 have a minimum value which is less than the correspond-ing minimum value for a symmetrical distribution. Thisdeviation in minimum value for 7442 is found to be 4/10 =40% (maximum deviation observed in the examples quoted).To take care of such deviations, a factor of safety of 40% isto be incorporated in eqn. 12. (See eqn. 11.)

132 IEEPROC, Vol. 128, Pt. E, No. 3.MAY1981