Edgar Sánchez-Sinencio
TI J. Kilby Chair Professor
ECEN 607 (ESS)
Texas A&M University
1
2
Next we review the conventional Op Amp Design frequency response compensation techniques
and also we introduced a simple LV Current-
Mode based Op Amp using resistors as
transconductors. Difference Differential
Amplifiers are also introduced.
M3 M4
M1 M2
M5
M6
M7
M8
M9
inV
bsV
inV
1pC
High
Impedance
1ov
2pCov
LC
1
2
3
DDV
SSV 1~3VA
Node is a low impedance
M1=M2; M3=M4
Ignoring zeros we can model this topology as:
Input
Stage
+
-
Second
StageOutput
Stage
inV
inV
1oi 2oi
1oR 1pC 2oR2pC 3oR
LCov
1 2 3
L
mp
ppp
VVVV
p
oop
p
op
oo
mV
oo
mV
C
g
sss
AAAsA
C
gg
C
gg
gg
gA
gg
gA
T8
3
321
76042
76
6
31
1
321
22
1121
;111
;;;
000
00
3
3
UNCOMPENSATED CMOS OPERATIONAL AMPLIFIER
3
UNCOMPENSATED CMOS OPERATIONAL AMPLIFIER STABILITY
ISSUES
• The low frequency voltage gain is high enough for a number of
applications.
• The open loop poles are far from the origin, this can cause stability
problems for closed loop applications.
• Closed loop poles might end very close to the jw axis and some in
the RHP.
• How to tackle this stability problem will be discussed next.
4
Two-Stage Uncompensated Amplifier
Uncompensated Operational Amplifier
problemsstability causing axis j the toclose are Poles
gg
g
gg
gAAA
0706
6m
0402
2m2V1VV
5
inv
VDD
M3 M4
M6
M1 M2
2
I o2
I o
I6
Ig
Vout
I7
M7M5
VSS
Io
inv
Large voltage gain
5
Employing a simple capacitor will split correctly the poles but will generate a
Zero in the RHP.
Using an RC compensation can eliminate the zero and split poles. The resistor
can be implemented with transistor in the ohmic region.
Improved internally compensated CMOS operational
amplifier. Better bias for the output stage (M8 and M9)
6
M1
M4
M2
CC
Vout
M6
VDD
M8
B
A
M9
VSS
M7M5
inv
biasv
M1
0
M11
M3
Analog and Mixed Signal Center, TAMU (ESS)
6
A variation at the output stage with class – AB is shown below.
CMOS op-amp with class-AB output stage and RC pole splitting.
7
VDD
M3 M4
M9
M1M2
2
I o2
I o
M5
VSS
Io
M10
in
v
4DSv
+
6GSvI6
-
+
M6
IL
CLCC
M8
I10
M7+
-biasV
inv
7GSv
9GSv
7
“Pole Splitting” can be carried out with a compensation capacitor
feedback and a voltage buffer as shown below
Two-Stage amplifier with source follower compensation scheme
• Without M12 and M11 a zero in the PRH
• With buffer (voltage follower), zero is eliminated and pole splitting
(due to CC ) is kept. 8
Ibias
M5
M3
M1
M4
M2
M6 M9
CC
M10 M12
M11
M8
Out
M7
inv
inv
8
An Improved Frequency Compensation
Technique for CMOS Operational Amplifiers
using Current Buffers
ECEN 607 (ESS)Courtesy of Hatem Osman
• The first stage is a differential-input/single-ended output stage, and
the second stage is a class A or class AB inverting output stage.
• Transfer Function
• Pole/zero locations
Background.-
Two-Stage Op-amp with Miller compensation
gm1gm2
Cc
CLro2ro1 Cp
VOUT
VIN,p
VIN,n
• DC Gain
RHP zero
Dominant Pole
Non-dominant Pole
• Pole Splitting
• Pole-zero position diagram
Increasing Cc achieves sufficient pole-splitting thus improving the PM. However, the
larger Cc shifts the RHP zero to lower frequencies thus ruining the PM.
Two-Stage Op-amp with Miller compensation
gm1gm2
Cc
CLro2ro1 Cp
VOUT
VIN,p
VIN,n
• Pole/zero locations
• Introducing a small series resistance in series with Cc may cancel the
RHP zero or shift it to the LHP.
• Disadvantages:
• To achieve a sufficient phase margin, second pole cross-over of the unity gain
frequency should be avoided.
Thus, the Op-amp stability is severely degraded for capacitive loads of the same
order as compensation capacitor.
Miller Op-amp with Nulling Resistance
gm1gm2
Cc
CLro2ro1 Cp
VOUT
VIN,p
VIN,n
Rc
• Pole/zero locations
No zero
LHP zero – Can be used to cancel the
first non-dominant pole.
• The RHP zero is a result of the feed-forward path through Cc.
• The RHP zero can be eliminated if we cut the feed-forward path
and make the compensation capacitor unidirectional.
Improved compensation technique
gm1gm2
Cc
CLro2ro1 Cp
VOUT
VIN,p
VIN,n
V1
gm1gm2
Cc
CLro2ro1 Cp
VOUT
VIN,p
VIN,n
V1
Virtual Ground
Improved compensation technique
• DC Gain
Dominant Pole
Non-dominant Pole
gm1gm2
Cc
CLro2ro1 Cp
VOUT
VIN,p
VIN,n
V1
Virtual Ground
Improved compensation technique
Miller compensation with nulling
resistance
Improved compensation technique
Dominant pole
Non-dominant pole
Gain-bandwidth product
Phase margin
Dominant pole
Non-dominant pole
Gain-bandwidth product
Phase margin
• Miller compensation with nulling resistance.
• Improved compensation technique.
Circuit Implementation
CcRc
CL
VOUT
VIN,pVIN,n
VDD
VSS
VB,pVB,p Mp,0
Mp,1 Mp,1
Mn,1 Mn,1 Mn,2
Mp,2
Cc
CL
VOUT
VIN,pVIN,n
VDD
VSS
VB,pVB,p Mp,0
Mp,1 Mp,1
Mn,1 Mn,1 Mn,2
Mp,2VB,p
Mn,3
Mp,3
VB,n
Mp,4
• Miller compensation with nulling resistance.
• Improved compensation technique.
Other performance parameters- PSR
CcRc
CL
VOUT
VIN,pVIN,n
VDD
VSS
VB,pVB,p Mp,0
Mp,1 Mp,1
Mn,1 Mn,1 Mn,2
Mp,2
Cc
CL
VOUT
VIN,pVIN,n
VDD
VSS
VB,pVB,p Mp,0
Mp,1 Mp,1
Mn,1 Mn,1 Mn,2
Mp,2VB,p
Mn,3
Mp,3
VB,n
Mp,4
VSS
PSR
-20log(Av,0)
freq
fp1
VSS
PSR
-20log(Av,0)
freq
fp1 1/ro1Cp GBW
• Better PSR at high
frequencies.
• Design an OTA with GBW > 5MHz, CL=10pF, PM>70, and SR> 2
V/µs.
Design Example – Miller Compensation
CcRc
CL
VOUT
VIN,pVIN,n
VDD
VSS
VB,pVB,p Mp,0
Mp,1 Mp,1
Mn,1 Mn,1 Mn,2
Mp,2
• Choose Cc=CL/2= 5 pF.
• GBW > 5MHz
• SR > 2 V/µS
• PM > 70°
Let
Then
• Choose Rc > 1/gm2
• Simulation results
Design Example – Miller Compensation
OL Transfer function Negative supply rejection
Positive supply rejection Transient step response
• Capacitive load driving capability
• PM > 70° for CL < 15 pF.
Design Example – Miller Compensation
• Design an OTA with GBW > 5MHz, CL=10pF, PM>70, and SR> 2
V/µs.
Design Example – Improved Compensation
• Choose Cc=CL/2= 5 pF.
• GBW > 5MHz
• SR > 2 V/µS
In order to make the current transformer
biased during slewing interval
• PM > 70°
Let
Then
Let’s use gm2=6gm1 like the miller Op-
amp to make a comparison between
the capacitive driving capability.
For the same capacitive load driving
capability, the second stage will
consume less current making it suitable
for low power applications
Cc
CL
VOUT
VIN,pVIN,n
VDD
VSS
VB,pVB,p Mp,0
Mp,1 Mp,1
Mn,1 Mn,1 Mn,2
Mp,2VB,p
Mn,3
Mp,3
VB,n
Mp,4
• Simulation results
Design Example – Improved Compensation
OL Transfer function Negative supply rejection
Positive supply rejection Transient step response
• Capacitive load driving capability
• PM > 70° for CL < 100 pF.
Design Example – Improved Compensation
• Summary of Simulation results
Design Example – Improved Compensation
Parameter Spec Miller
Compensation
Improved
Compensation
GBW > 5MHz 5.5 MHz 6 MHz
PM > 70° 75° 87.6°
SR+ > 2 V/µs 2.75 V/µs 3 V/µs
SR- > 2 V/µs 3 V/µs 3.15 V/µs
PSR- - -65.6 dB
At (0-3.1 kHz)
-51.9 dB
At (0-245.4 kHz)
PSR+ - -97.2 dB
At (0-44 kHz)
-37.2 dB
At (0-538.9 kHz)
DC gain - 64.5 dB 51.3 dB
Current
consumption
- 80 µA 110 µA
Capacitive load
driving capability
- PM > 70° forCL < 15 pF
PM > 70° for
CL < 100 pF
Using another current buffer Op Amp topology.
• Improve SR at the expense of power consumption.
Two-Stage amplifier with Current Buffer compensation scheme.
25
Ibias
M5
M3
M1
M4
M2
M6 M9
CC
M10
M12
M11
M8M7
Vout
inv
in
v
25
Differential Output Two Stage Amp with a capacitor compensationwith a current Buffer ( Common Gate)
26
27
Note that the current-mirror introduces an extra inversion which must be taken into consideration for the single ended version.P.J. Hurst, Lewis, S.H. ; Keane, J.P. ; Aram, F. ; Dyer, K.C. “ Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers” IEEE Transactions on Circuits and Systems I, Volume: 51 , Issue: 2, Feb. 2004
Note that this and previous structure are fully differential but this approachcould be used for single output topologies.
Compensation using a current buffer ( current gain)
28
29
Elements of Current-Mirror Cc compensated
Besides the above zero the
amp has three poles
Note that the common-gate and current mirror topologies under ideal case are
almost identical, however in practice the one using current-mirrors is more power hungry
and has a larger parasitic capacitance CB
Summary for Two Stage Op Amp Architecture Designs
inV
biasV5Q
ssI
inV
biasI
7Q
6Q
LC
• Roots close to the j axis for uncompensated
• Potentially unstable for some values of CL
Ibias = CLSR*2.5
• Improved output stage optimal bias of Q6 and Q7
• No significant change of pole locations.
Av (0) -> +
Av () -> -
Pole splitting => one dominant pole
z1 Phase deteriorates phase marginThe good and the bad news
1ps2ps
oVinV
biasV5Q
ssI
inV
biasI
10Q
9Q
7Q
6Q
oV
inV
biasV5Q
ssI
inV
biasI
10Q
9Q
7Q
6Q
CC
1ps2ps
1z
Analog and Mixed Signal Center, TAMU (ESS)
30
Two possible solutions to cancel z1 and keeping sp2 > t =GBW and sp1 small
Internally Compensated
with RC CC
Internally Compensated
with unity gain buffer
(Q10, Q11)
biasV
ssI
oV
CC 10Q
11Q
Operational Amplifier (conventional) Architectures.
biasV
ssI
oV
CCLC
inV
inV
Analog and Mixed Signal Center, TAMU (ESS)
Reader.- See the internally Op Amp compensated with current gain buffer in previous pages
31
32
Compared to two-stage Op Amp, folded cascode Op Amp has:
• Improved input common-mode range (ICMR)
• Improved power supply rejection (PSR)
• Push-pull output stage
• Self compensation
Folded-cascode Op Amp broken into stages
[Allen]
The extended ICMR is achieved
The bias currents I4 and I5 should be designed such that I6 and I7 never
goes to zero (i.e. 𝐼4,5 = 1.2𝐼3 → 1.5𝐼3)
Poor noise performance: In addition to the input transistors, transistors M4,5
and M10,11 generate significant current noise
Folded Cascode OpAmp
33
RA and RB are the resistances looking into the sources of M6 and M7
𝑅𝐴 =𝑟𝑑𝑠6+ 1 𝑔𝑚10
1+𝑔𝑚6𝑟𝑑𝑠6≈
1
𝑔𝑚6and 𝑅𝐵 =
𝑟𝑑𝑠7+𝑅𝐼𝐼
1+𝑔𝑚7𝑟𝑑𝑠7≈
𝑅𝐼𝐼
𝑔𝑚7𝑟𝑑𝑠7where 𝑅𝐼𝐼 = 𝑔𝑚9𝑟𝑑𝑠9𝑟𝑑𝑠11
The currents 𝑖7 and 𝑖10 is expressed as
𝑖7 =𝑔𝑚2(𝑟𝑑𝑠2 𝑟𝑑𝑠5)
𝑅𝐵+(𝑟𝑑𝑠2 𝑟𝑑𝑠5)
𝑣𝑖𝑛
2=
𝑔𝑚2
𝑘+1
𝑣𝑖𝑛
2where 𝑘 =
𝑅𝐵
𝑟𝑑𝑠2 𝑟𝑑𝑠5
𝑖10 = −𝑔𝑚1(𝑟𝑑𝑠1 𝑟𝑑𝑠4)
𝑅𝐴+(𝑟𝑑𝑠1 𝑟𝑑𝑠4)
𝑣𝑖𝑛
2≈ −𝑔𝑚1
𝑣𝑖𝑛
2
Thus, the transfer function can be found as follows
𝑣𝑜𝑢𝑡𝑣𝑖𝑛
=𝑔𝑚1
2+
𝑔𝑚2
2 𝑘 + 1𝑅𝑜𝑢𝑡 =
2 + 𝑘
2 + 2𝑘𝑔𝑚1𝑅𝑜𝑢𝑡
Where
𝑅𝑜𝑢𝑡 = 𝑔𝑚9𝑟𝑑𝑠9𝑟𝑑𝑠11 𝑔𝑚7𝑟𝑑𝑠7 𝑟𝑑𝑠2 𝑟𝑑𝑠5
Where 𝑘 is the low-frequency unbalance factor
Small Signal Analysis
34
The frequency response is dominated primarily by the output pole due to the high
output impedance
𝑃𝑜𝑢𝑡 =−1
𝑅𝑜𝑢𝑡𝐶𝑜𝑢𝑡 In order to have sufficient phase margin, all other pole should be located will above
the GBW
Pole at source of M6 (Folding node) 𝑃𝐴 = −1
𝑅𝐴 𝐶𝑔𝑠+2𝐶𝑏𝑑≈ −
𝑔𝑚6
𝐶𝑔𝑠+2𝐶𝑏𝑑
Pole at source of M7 (Folding node) 𝑃𝐵 = −1
𝑅𝐵 𝐶𝑔𝑠+2𝐶𝑏𝑑≈ −
𝑔𝑚7
𝐶𝑔𝑠+2𝐶𝑏𝑑
Pole at drain of M6 𝑃6 = −𝑔𝑚10
2𝐶𝑔𝑠+2𝐶𝑏𝑑
Pole at source of M8 𝑃8 = −𝑔𝑚8𝑟𝑑𝑠8𝑔𝑚10
𝐶𝑔𝑠+𝐶𝑏𝑑
Pole at source of M9 𝑃9 = −𝑔𝑚9
𝐶𝑔𝑠+𝐶𝑏𝑑
Remarks:
We assumed 𝑅𝐵 ≈ 1 𝑔𝑚7 because at high frequency, where this pole has influence,
𝐶𝑜𝑢𝑡 shunts the drain of 𝑀7 to ground.
Frequency Response
35
[Allen]
Output stage of folded cascode OpAmp
The following model is used to calculate the
negative PSR
• The gate, source and drain of M11 varies with VSS
• The gate, source of M9 varies with Vss
The transfer function 𝑉𝑜𝑢𝑡 𝑉𝑠𝑠 can be found as𝑉𝑜𝑢𝑡
𝑉𝑠𝑠=
𝑠𝐶𝑔𝑑9𝑅𝑜𝑢𝑡
𝑠𝐶𝑜𝑢𝑡𝑅𝑜𝑢𝑡+1
𝑃𝑆𝑅𝑅− can be calculated
𝑃𝑆𝑅𝑅− =𝐴𝑣 𝑉𝑜𝑢𝑡 𝑉𝑠𝑠
Power Supply Rejection
36
At low frequency, we assume that other source of 𝑉𝑠𝑠 injection becomes
significant
Low frequency PSRR- is at least as large as the magnitude of the
differential voltage gain 𝐴𝑣
PSRR+ can be derived similarly: the primary source of injection is through
the gate-drain capacitor of M
Power Supply Rejection
37
[Allen]
Slew Rate
38
𝑆𝑅+ = 𝑆𝑅− =𝐼3𝐶𝐿
The bias currents 𝐼4,5 should be designed such that 𝐼6,7 never goes to zero
𝐼4,5 = 1.2𝐼3 → 1.5𝐼5
Maximum Available Output Swing
39
𝑉𝑜𝑢𝑡 𝑚𝑎𝑥 = 𝑉𝐷𝐷 − 𝑉𝑆𝐷5 − 𝑉𝑆𝐷7𝑉𝑜𝑢𝑡 𝑚𝑖𝑛 = 𝑉𝑠𝑠 + 𝑉𝐷𝑆9 + 𝑉𝐷𝑆11
The output common mode level 𝑉𝑜𝑐𝑚 is often dictated by the circuit that
interface with the amplifier (e.g. 𝑉𝑜𝑐𝑚 = 𝑉𝐷𝐷 2)
Noise Analysis
40
The noise current of M1, M4 and M10 goes directly to the output
At low and medium frequencies, noise contribution of the cascode
transistors (M6 and M8) can be neglected
Total output noise current becomes
𝑖𝑜𝑢𝑡2 = 8𝐾𝑇𝛾 𝑔𝑚1 + 𝑔𝑚4 + 𝑔𝑚10
Input referred noise density
𝑣𝑛,𝑖𝑛2 =
8𝐾𝑇𝛾
𝑔𝑚11 +
𝑔𝑚4
𝑔𝑚1+
𝑔𝑚10
𝑔𝑚1
Half circuit model
Folded Cascode Op Amp Design Procedure
41
Design approach for the folded cascode Op Amp using long-channel model
[Allen]
Design Example
42
Design a folded cascode Op Amp to comply with the following
specifications using 0.18μm CMOS technology
Parameter Spec
Slew rate > 10 V μs
Load Capacitor 10pF
Power Supply ±1 V
Max/Min Output Voltage ±0.5 V
GBW > 10 MHz
Min Input CM Voltage −0.3 V
Max Input CM Voltage 1 V
Differential Voltage Gain > 60 dB
Power Dissipation < 2mW
Design Example (Cont.)
43
Solution:
From the value of the slew rate we can get I3I3 = SR × CL > 10 × 106 10 × 10−12 I3 ≥ 100μA
Select I3 = 120μA
𝐼4,5 will be designed such that 𝐼6,7 never goes to zero
I4 = I5 = 1.2I3 to 1.5I3Select I4 = I5 = 1.25I3 = 150μA
Knowing 𝐼4 and 𝐼3, we can get the quiescent, min, and max values of 𝐼6,7
𝐼6,𝑄 = 𝐼7,𝑄 = 𝐼4 − 0.5𝐼3 = 90𝜇𝐴
𝐼6 𝑚𝑖𝑛 = 𝐼7 𝑚𝑖𝑛 = 𝐼4 − 𝐼3 = 20𝜇𝐴
𝐼6 𝑚𝑎𝑥 = 𝐼7 𝑚𝑎𝑥 = 𝐼4 = 150𝜇𝐴
From the min and maximum output voltages we can get overdrive voltage of
transistors 𝑀4−11
𝑉𝑆𝐷𝑠𝑎𝑡 4−7 𝑚𝑎𝑥= 0.5 𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡 𝑚𝑎𝑥 = 0.25 𝑉
𝑉𝐷𝑆𝑠𝑎𝑡 8−11 𝑚𝑎𝑥= 0.5 𝑉𝑜𝑢𝑡 𝑚𝑖𝑛 − 𝑉𝑆𝑆 = 0.25 𝑉
Design Example (Cont.)
44
The value of 𝐺𝐵 gives 𝑔𝑚1,2
𝑔𝑚1,2 = 𝐺𝐵 × 𝐶𝐿 ≥ 628.3 𝜇𝐴 𝑉
Thus, choose 𝑔𝑚1,2 = 700 𝜇𝐴 𝑉
From 𝑔𝑚1,2 and 𝐼1,2, we can obtain 𝑉𝐷𝑆𝑠𝑎𝑡(1,2)
𝑉𝐷𝑆𝑠𝑎𝑡 1,2 =2𝐼1
𝑔𝑚1=
𝐼3
𝑔𝑚1= 0.17 𝑉
The minimum input common mode voltage defines 𝑉𝐷𝑆𝑠𝑎𝑡3𝑉𝑖𝑐𝑚 𝑚𝑖𝑛 = 𝑉𝑆𝑆 + 𝑉𝐷𝑆𝑠𝑎𝑡(3) + 𝑉𝑇𝑛 + 𝑉𝐷𝑆𝑠𝑎𝑡 1
Thus, 𝑉𝐷𝑆𝑠𝑎𝑡 3 = 0.13𝜇𝐴 for 𝑉𝑇𝑛 = 0.4 𝑉
We need to check that the maximum input common mode voltage is satisfied
𝑉𝑖𝑐𝑚 𝑚𝑎𝑥 = 𝑉𝐷𝐷 − 𝑉𝑆𝐷𝑠𝑎𝑡 4 + 𝑉𝑇𝑛 = 1.15 𝑉Meets the spec
Design Example (Cont.)
45
Now, we have the bias currents 𝐼𝐷 and overdrive voltage 𝑉𝐷𝑆𝑠𝑎𝑡 of all the transistors.
Thus, we can obtain 𝑊 𝐿 of all the transistors from the ACM model or square-law
model if long-channel transistors are used.
The channel length of the transistors should be chosen to satisfy the specified
voltage gain.
The current flowing in transistors 𝑀6−11 can have any value from 20 𝜇𝐴 to
150 𝜇𝐴 depending on the amplitude and polarity of the differential input voltage.
Therefore, they should be sized such that the worst case 𝑉𝐷𝑆𝑠𝑎𝑡 of each transistor
meets the specified limits on the output voltages.
Bias voltages of the cascode transistors 𝑉𝑃𝐵2 and 𝑉𝑁𝐵2 are chosen such that
𝑉𝑃𝐵2
Simulation Results
46
DC operating point
Transistor 𝑾 𝑳 𝑰𝑫 𝝁𝑨 𝑽𝑫𝑺𝒔𝒂𝒕
𝑀1,2 18 1 120 0.13
𝑀3 24 1 60 0.16
𝑀4,5 72 1 150 0.23
𝑀6,7 72 1 90 0.23
𝑀8,9 12 1 90 0.24
𝑀10,11 12 1 90 0.24
Simulation Results
47
Input common-mode range
Minimum input common mode voltage is 0.28 V
ICMR testbench
Simulation Results
48
Output Swing
The gain is perfectly linear for −0.5 ≤ 𝑉𝑜𝑢𝑡 ≤ 0.5
Output Swing Testbench
Simulation Results
49
Open loop response
𝐴𝑣 > 60 𝑑𝐵𝐺𝐵 > 10 𝑀𝐻𝑧
Open loop response testbench
Simulation Results
50
Slew Rate
𝑆𝑅+, 𝑆𝑅− > 10 𝑉 𝜇𝑠
Slew-rate testbench
Simulation Results
51
PSRR
PSRR+ testbench PSRR- testbench
Summary of Results
52
The following simulation results for 𝐶𝐿 = 10𝑝𝐹, 𝑉𝐷𝐷 = 1 𝑉 and 𝑉𝑆𝑆 = −1𝑉
Parameter Spec Simulation
SR+ > 10 V μs 11.3 V μs
SR- > 10 V μs 11.18 V μs
Max/Min Output Voltage ±0.5 V −0.65 → 0.61 𝑉
GBW > 10 MHz 10.7 𝑀𝐻𝑧
Min Input CM Voltage −0.3 V −0.28 𝑉
Max Input CM Voltage 1 V 1 𝑉
Differential Voltage Gain > 60 dB 62 𝑑𝐵
PSRR+ - 65.64 𝑑𝐵
PSRR- - 75.86 𝑑𝐵
Power Dissipation < 2 mW 840 𝜇𝑊
Techniques for Wideband Amplifiers
Focus the improvement in the load of the differential pair
Conventional
Current Mirror
at the output load
Wideband Alternative
R
CF
Frequency Dependent
Current Mirror (FDCM)
CF >> Cgs
0.1K < R < 1K
Low Frequency
Behavior
CF
Ib
High Frequency
Behavior
T. Itakura and T. Iida, “A Feedforward Technique with Frequency-Dependent Current Mirrors for a Low-Voltage
Wideband Amplifier,” IEEE J. Solid-State Circuits, Vol. 31, No.6, pp. 847-849, June 1996. 53
An example of its use:
Wideband Amplifier with Feedforward Technique
• What is the optimal value of R1 as a function og GmP3 ?
• CF1 by passes two current mirrors.
• CF2 is fed forward to the input of another FDCM and signal
is amplified.
3PM
3PM
3R
inv
1R
bI
1FC
1nM
1PM
2PM
2nM
2FC
2R
inv
4PM
DDV
ov
LC
4nM
SSV
54
Next, we discuss different families of wideband reported in the
literature.
F. Centurelli et al, “A Bootstrap Technique for Wideband Amplifiers,” IEEE Trans. on Circuits
And Systesm – I, Vol. 49, No. 10, pp. 1474-1480, October 2002
• An alternative is to
connect CF instead
to nodes B to nodes A
LR LR
4nM3nM
1nM
ov
ov
B B
SSRFC FC
A A
inv
inv2nM
55
FOLDED-CASCODE WIDEBAND AMPLIFIER ( See page 11 for cascode)
OUTV
Conventional Folded-Cascode (FC)
4PM
2PM
3nM
3PM
1PM
5nM
4nM
LC
4bV
2bV
inv
tailI
inv
1bV
1bV
FC with Capacitive Feedforward
4bV
1FR
1bV
1FC2FC
inv
inv
tailI
1bV
2bV LC
outV
Differential Wideband Amplifier
F. Opt Eynde, W. Sansen, “A CMOS Wideband Amplifier with 800MHz Bandwidth,” IEEE Custom Integrated Circuits Conf., pp. 9.1.1-9.1.4, 1991
3nM4nM
biasI1b
V
oV
LC
1FR
1bV
2bV
oV
1FC
inV
1bV
2bVLC
DDV
SSV
oV
2FC
2FR
56
57
M4 M10
M12M5 M6 M14
IB IB IBIB
ibM1 M3 M8
VDD
Vbias
B
A
R
iR
Xvin
ix
M13 M2 M9
VSS
M11
io- io+
ON OP
v+ Figure 1
io+
io-
Figure 1V- X
OP
ON
X
OP
ON
Fig. 1 Transconductance Amp
Basic Structure based on current-mode
Fig 2
Pseudo Differential Op Amp
iR = Vin/R
iX = - iR
IB > iR
-
E.K.F. Lee, “ Low-Voltage Opamp Design and Differential Difference Amplifier Design Using Linear Transconductor with Resistor Input
, “ IEEE Trans. Circuits and Systems II,vol. 47, pp 776-778, Aug. 2000
58
v+
Figure 2
io+
io-
v-
VSS
R1
VDD
CC
R1
vo
Vbias
Transimpedanceamplifier
v1+
Figure 2
io1+
io1-
v1-
v2+
Figure 2
io2+
io2-
v2-
Transimpedanceamplifier
vo
Fig 3 VCVS Amplifier: Op Amp
DDA
59
References
Analog & Mixed-Signal Center (AMSC)
SS Rajput, SS Jamuar, Low voltage analog circuit design techniques, IEEE Circuits and
Systems Magazine, pp. 24-42, 2002
S. Yan and E. Sánchez-Sinencio, Low Voltage Analog Circuit Design Techniques: A Tutorial,
IEICE Trans. Fundamentals, Vol. E83-A, No. 2, pp 179-196, February 2000
E. Sánchez-Sinencio and Andreas G. Andreou, Eds. “ Low-Voltage/Low-Power Integrated
Circuits and Systems “, IEEE Press, Piscataway, NJ 1999
X. Xie, M.C. Schneider, E. Sanchez-Sinencio and S.H.K. Embabi, “ Sound Design of Low
Power Nested Transconductance-Capacitance Compensation Amplifiers”, IEE
Electronics Letters, Vol. 35, pp.956-958, June 1999.
A. Rodriguez-Vazquez and E. Sánchez-Sinencio, Eds., Special Issue on Low-Voltage and
Low-Power Analog and Mixed-Signal Circuits and Systems, IEEE Trans. on Circuits
and Systems I, vol. 42, No. 11, November 1995
J. Crols, J.; Steyaert, M.; Switched-opamp: an approach to realize full CMOS switched capacitor circuits at very low power supply voltages” IEEE Journal of Solid-State Circuits,, Volume: 29 , Issue: 8 , Aug. 1994 Pages:936 - 942
60
References
Analog & Mixed-Signal Center (AMSC)
Very low-voltage analog signal processing based quasi-floating gate transistors,J
Ramirez-Angulo, AJ Lopez-Martin, RG Carvajal, et all, IEEE J. Solid-State Circuits, pp
434- 442, March 2004
Low threshold CMOS circuits with low standby current
Stan, M.R. Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium
on , 10-12 Aug. 1998 Pages:97 - 99
A dynamic threshold voltage MOSFET (DTMOS) for ultra low voltage operation Assaderaghi, F.;
Sinitsky, D.; Parke, S.; Bokor, J.; Ko, P.K.; Chenming Hu;
Electron Devices Meeting, 1994. Technical Digest., International , 11-14 Dec. 1994 Pages:809 -
812
Resizing rules for MOS analog-design reuse
Galup-Montoro, C.; Schneider, M.C.; Coitinho, R.M.;
Design & Test of Computers, IEEE ,Volume: 19 , Issue: 2 , March-April 2002 Pages:50 - 58
An MOS transistor model for analog circuit design .Cunha, A.I.A.; Schneider, M.C.; Galup-
Montoro, C.; Solid-State Circuits, IEEE Journal of ,Volume: 33 , Issue: 10 , Oct. 1998
Pages:1510 – 151
Series-parallel association of FET's for high gain and high frequency applications
Galup-Montoro, C.; Schneider, M.C.; Loss, I.J.B.; Solid-State Circuits, IEEE Journal
of ,Volume: 29 , Issue: 9 , Sept. 1994 Pages:1094 - 1101
61
References
Analog & Mixed-Signal Center (AMSC)
S. M. Mallya abd J. H. Nevin, “ Design Procedures for a Fully Differential Folded Cascode CMOS
Operational Amplifier”, IEEE J. of Solid-State Circuits, Vol 24, No. 6, pp1737-1740,
December 1989.
D. B. Ribner, M. A. Copeland. and M. Milkovic, “8OMHz low offsetfully-differential and single-
ended opamps,” in Proc. IEEE Custom Integruted Circuits Con/., 1983, pp. 74-75.
This reference discusses three different Op Amp topologies:
S. Rabii and B. A. Wooley, “ A 1.8V-V Digital Audio Sigma-Delta Modulator in 0.8-um CMOS”,
IEEE J. of Solid-State Circuits, Vol. 32, N0. 6, pp. 783-796, June 1997
CMOS Analog Circuit Design, P.E. Allen, D.R. Holberg, Oxford University Press, 3rd
Edition, 2012