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EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuits
Lecture 11Lecture 11Wire modelingWire modelingCMOS logicCMOS logic
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AnnouncementsAnnouncementsNo lab this week
Lab 4 reports due next weekHardware lab next week
Homework #5 due todayNo new homework this week
Midterm 1 on Thursday, 6:30-8pm, 105 North G.Material until last lecture, homework 5, lab 4Review session tonight 6-7:30pm, 60 EvansCheck the web page for extra office hours
There is a lecture on ThNo lecture on October 24
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Class MaterialClass Material
Last lectureScalingWires
Today’s lectureWire modelsCMOS logic gates
Reading (Chapters 4, 6)
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INTERCONNECTINTERCONNECT
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Wire Resistance Wire Resistance
W
LH
R = ρH W
L
Sheet ResistanceRo
R1 R2
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Interconnect Resistance Interconnect Resistance
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Dealing with ResistanceDealing with Resistance
Selective Technology ScalingUse Better Interconnect Materials
reduce average wire-lengthe.g. copper, silicides
More Interconnect Layersreduce average wire-length
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PolycidePolycide Gate MOSFETGate MOSFET
n+n+
SiO2
PolySilicon
Silicide
p
Silicides: WSi 2, TiSi2, PtSi2 and TaSi
Conductivity: 8-10 times better than Poly
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Sheet ResistanceSheet Resistance
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Modern InterconnectModern Interconnect
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Example: Intel 0.25 micron ProcessExample: Intel 0.25 micron Process
5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric
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Modern InterconnectModern Interconnect
90nm process
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INTERCONNECTINTERCONNECT
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InterconnectInterconnectModelingModeling
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The Lumped ModelThe Lumped ModelVout
Drivercwire
VinClumped
Rdriver Vout
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The Lumped RCThe Lumped RC--ModelModelThe Elmore DelayThe Elmore Delay
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The Elmore DelayThe Elmore DelayRC ChainRC Chain
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Wire ModelWire Model
Assume: Wire modeled by N equal-length segments
For large values of N:
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The Distributed RCThe Distributed RC--lineline
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StepStep--response of RC wire as a response of RC wire as a function of time and spacefunction of time and space
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
time (nsec)
volta
ge (
V)
x= L/10
x = L/4
x = L/2
x= L
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Driving an RCDriving an RC--lineline
Vin
Rs Vout(rw,cw,L)
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RCRC--ModelsModels
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CMOS LogicCMOS Logic
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Combinational vs. Sequential LogicCombinational vs. Sequential Logic
Combinational Sequential
Output = f(In) Output = f(In, Previous In)
CombinationalLogicCircuit
OutInCombinational
LogicCircuit
OutIn
State
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Static CMOS CircuitStatic CMOS Circuit
At every point in time (except during the switching transients) each gate output is connected to eitherVDD or Vssvia a low-resistive path.
The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).
This is in contrast to the dynamic circuit style, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
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Static Complementary CMOSStatic Complementary CMOSVDD
F(In1,In2,…InN)
In1In2
InN
In1In2
InN
PUN
PDN
PMOS only
NMOS only
PUN and PDN are dual logic networksPUN and PDN functions are complementary
……
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NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection
Transistor can be thought of as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
X Y
A B
Y = X if A AND B
X Y
A
B Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
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PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection
X Y
A B
Y = X if A AND B = A + B
X Y
A
B Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
PMOS switch closes when switch control input is low
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Threshold DropsThreshold DropsVDD
VDD → 0PDN
0 → VDD
CL
CL
PUN
VDD
0 → VDD - VTn
CL
VDD
VDD
VDD → |VTp|
CL
S
D S
D
VGS
S
SD
D
VGS
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Next LectureNext Lecture
CMOS logic - properties