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EE141EE141--Spring 2004Spring 2004Digital Integrated Digital Integrated CircuitsCircuits
Lecture 17Lecture 17
PTLPTLDynamic LogicDynamic Logic
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Administrative StuffAdministrative StuffNo Lab this weekHw 6 posted – Due April 1Project due Fr by 5:30pm
Electronic reports only!Send report (using template from web-site) to [email protected] NOT forget to include your SPICE file
Will be out of town on Th. Lecture by Prof. Vladimirescu on adders
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ScheduleSchedule
Last lecture: project intro, PTLToday:
Dynamic Logic
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PassPass--TransistorTransistorLogicLogic
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PassPass--Transistor LogicTransistor Logic
Inpu
ts
Switch
Network
OutOut
A
B
B
B
• N transistors
• No static consumption
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NMOS Only Logic: NMOS Only Logic: Level Restoring TransistorLevel Restoring Transistor
M2
M1
Mn
Mr
OutA
B
VDDVDDLevel Restorer
X
• Advantage: Full Swing
• Restorer adds capacitance, takes away pull down current at X
• Ratio problem
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Restorer SizingRestorer Sizing
0 100 200 300 400 5000.0
1.0
2.0
W/Lr =1.0/0.25 W/Lr =1.25/0.25
W/Lr =1.50/0.25
W/Lr =1.75/0.25
Vol
tage
[V]
Time [ps]
3.0•Upper limit on restorer size•Pass-transistor pull-downcan have several transistors in stack
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Solution 2: Single Transistor Pass Gate with Solution 2: Single Transistor Pass Gate with VVTT=0=0
Out
VDD
VDD
2.5V
VDD
0V 2.5V
0V
WATCH OUT FOR LEAKAGE CURRENTS
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Complementary Pass Transistor LogicComplementary Pass Transistor Logic
A
B
A
B
B B B B
A
B
A
B
F=AB
F=AB
F=A+B
F=A+B
B B
A
A
A
A
F=A⊕ΒÝ
F=A⊕ΒÝ
OR/NOR EXOR/NEXORAND/NAND
F
F
Pass-Transistor
Network
Pass-TransistorNetwork
AABB
AABB
Inverse
(a)
(b)
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Solution 3: Transmission GateSolution 3: Transmission Gate
A B
C
C
A B
C
C
B
CL
C = 0 V
A = 2.5 V
C = 2.5 V
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Resistance of Transmission GateResistance of Transmission Gate
Vout
0 V
2.5 V
2.5 VR
n
Rp
0.0 1.0 2.00
10
20
30
Vout, V
Res
ista
nce
, oh
ms
Rn
Rp
Rn || Rp
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Delay in Transmission Gate NetworksDelay in Transmission Gate Networks
V1 Vi-1
C
2.5 2.5
0 0
Vi Vi+1
CC
2.5
0
Vn-1 Vn
CC
2.5
0
In
V1 Vi Vi+1
C
Vn-1 Vn
CC
In
ReqReq Req Req
CC
(a)
(b)
C
Req Req
C C
Req
C C
Req Req
C C
Req
C
In
m
(c)
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Delay OptimizationDelay Optimization
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Transmission Gate Full AdderTransmission Gate Full Adder
A
B
P
Ci
VDDA
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup
Similar delays for sum and carry
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Dynamic LogicDynamic Logic
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Dynamic CMOSDynamic CMOS
In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type) devices
Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type) transistors
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Dynamic GateDynamic Gate
In1
In2 PDN
In3
Me
Mp
Clk
Clk
Out
CL
Out
Clk
Clk
A
BC
Mp
Me
Two phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)
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Dynamic GateDynamic Gate
In1
In2 PDN
In3
Me
Mp
Clk
Clk
Out
CL
Out
Clk
Clk
A
BC
Mp
Me
Two phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)
on
off
1
off
on
((AB)+C)
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Conditions on OutputConditions on Output
Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.Inputs to the gate can make at most one transition during evaluation.
Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
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Properties of Dynamic GatesProperties of Dynamic GatesLogic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary CMOS)
Full swing outputs (VOL = GND and VOH = VDD)Non-ratioed - sizing of the devices does not affect the logic levelsFaster switching speeds
reduced load capacitance due to lower input capacitance (Cin)
reduced load capacitance due to smaller output loading (Cout)
no Isc, so all the current provided by PDN goes into discharging CL
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Properties of Dynamic GatesProperties of Dynamic Gates
Overall power dissipation usually higher than static CMOS
no static current path ever exists between VDD and GND (including Psc)no glitchinghigher transition probabilitiesextra load on Clk
PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn
low noise margin (NML)
Needs a precharge/evaluate clock
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Issues in Dynamic Design 1: Issues in Dynamic Design 1: Charge LeakageCharge Leakage
CL
Clk
Clk
Out
A
Mp
Me
Leakage sources
CLK
VOut
Precharge
Evaluate
Dominant component is subthreshold current
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Solution to Charge LeakageSolution to Charge Leakage
CL
Clk
Clk
Me
Mp
A
B
Out
Mkp
Same approach as level restorer for pass-transistor logic
Keeper
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Issues in Dynamic Design 2: Issues in Dynamic Design 2: Charge SharingCharge Sharing
CL
Clk
Clk
CA
CB
B=0
A
OutMp
Me
Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness
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Charge Sharing ExampleCharge Sharing Example
CL=50fF
Clk
Clk
A A
B B B !B
CC
Out
Ca=15fF
Cc=15fF
Cb=15fF
Cd=10fF
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Charge SharingCharge Sharing
CLVDD CLVout t( ) Ca VDD VTn VX( )–( )+=
or
∆Vout Vout t( ) VDD–CaCL-------- VDD VTn VX( )–( )–= =
∆Vout VDD
CaCa CL+----------------------⎝ ⎠⎜ ⎟⎛ ⎞
–=
case 1) if ∆Vout < VTn
case 2) if ∆Vout > VTnB = 0
Clk
X
CL
Ca
Cb
A
Out
Mp
Ma
VDD
Mb
Clk Me
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Solution to Charge RedistributionSolution to Charge Redistribution
Clk
Clk
Me
Mp
A
B
OutMkp
Clk
Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)
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Issues in Dynamic Design 3: Issues in Dynamic Design 3: BackgateBackgate CouplingCoupling
CL1
Clk
Clk
B=0
A=0
Out1Mp
Me
Out2
CL2In
Dynamic NAND Static NAND
=1=0
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BackgateBackgate Coupling EffectCoupling Effect
-1
0
1
2
3
0 2 4 6
Vol
tage
Time, ns
Clk
In
Out1
Out2
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Issues in Dynamic Design 4: Clock Issues in Dynamic Design 4: Clock FeedthroughFeedthrough
CL
Clk
Clk
B
A
OutMp
Me
Coupling between Out and Clk input of the prechargedevice due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.
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Clock Clock FeedthroughFeedthrough
-0.5
0.5
1.5
2.5
0 0.5 1
Clk
Clk
In1
In2
In3
In4
Out
In &Clk
Out
Time, ns
Vol
tage
Clock feedthrough
Clock feedthrough
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Other EffectsOther Effects
Capacitive couplingSubstrate couplingMinority charge injectionSupply noise (ground bounce)
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Next LectureNext Lecture
Arithmetic circuits and adders