Self-aligned channel stop with Local Oxidation (LOCOS)
Si3N4 CVDpad oxide
Si
LOCOS Process Flow
3Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
B+ channelstop
implant
Si
thermal oxidation(high temperature)
FOX
Self-alignedchannel stop
pp
B
dose~1013/cm2
4Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
If poly or metal lines lie on top of the Field Oxide (FOX), they will form a parasitic MOS structure.If these lines carrying a high voltage, they may create an inversion layer of free carriers at the Si substrate and shorts out neighboring devices. The relatively highly doped Si underneath (the “channel stop”) raises the threshold voltage of this parasitic MOS. If this threshold voltage value is higher than the highest circuit voltage, inversion will not occur.
SiO2
p-Si
metal
Comment: Field Oxide Channel Inversion
InversionLayer
Device 1Device 2
5Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
Comments : Non self-aligned alternative:
P.R.1
SiO2
P+ P+
SiP+ P+
SiO2
2B+
3
Disadvantages1 Two lithography steps2 Channel stop doping not FOX aligned
6Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
Self-aligned Source and Drain
n+n+
poly-Si gateAs+
n+n+
As+
Off Alignment
Perfect Alignment
* The n+ S/D always follows gate
7Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
Comment: Non self-aligned Alternative
.n+n+ 2
.n+n+
Solution: Use gate overlap to avoid offset error.
.n+n+ 1
Channel not linked to S/D
Straycapacitance
Disadvantages: Two lithography steps, excess gate overlap capacitance
8Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
Lightly Doped Drain (LDD)
LDD(1E17-to 1E18/cm3)
9Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
Lightly Doped Source/Drain MOSFET (LDD)
The n-pockets (LDD) doped to medium conc (~1E18) are used to smear out the strong E-field between the channel and heavily doped n+ S/D, in order to reduce hot-carrier generation.
n+ n+n nSiO2
CVD oxidespacer
p-sub
10Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
n implantfor LDD
SiO2
CVD SiO2
Directional RIE of CVD Oxide
CVD conformaldeposition SiO2
LDD Process Flow using Ion Implantation
11Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
Spacer left when CVD SiO2is just cleared on flat region.
nn
0.05µm
0.25µm
n+ n+
n+ implant
n n
12Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
Self-Aligned Silicide Process (SALICIDE) using Ion
Implantation and Metal-Si reaction
n+n+
TiSi2 (metal)poly-gate
Metal silicides are metallic.They lower the sheet resistance of S/D and the poly-gate
13Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
n+n+SiO2
oxide spacer
SALICIDE Process Flow
14Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
n+n+SiO2
Ti
Ti deposition
Si
TiTiSi2
TiTi
Selective etch to remove unreacted Ti only
.
2)700(
2
2
SiOwithreactnotwillTi
TiSiSiTiCtreatmentheat o
→+>
15Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
Salicide Gate TEM
16Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
Self-aligned Oxide Gap
n+
poly-I
poly-II
small oxide spacing < 30nm
inversioncharge layerpoly-I
substrate
Gateoxide
poly-IIMOSFET
MOSCapacitor
DRAM structure ( MOSFET with a capacitor)
V (plate)
For a small spacing between poly-I and poly-II, inversion charges between MOSFET and Capacitor are electrically linked. No need for a separate n+ island.
Thermal Oxide grown conformal on poly-I
17Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
Process Flow of MEMS Rotating Mechanisms
Micro-turbineEngine
In-Plane Movement
18Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
Process Flow for a Hinge Structure
Out-of-plane Movement
19Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
Layout of Thermal Bimorph Actuator
(See 143 Lab Manual for details)
20Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
After Patterning Poly-Si ( Mask #2)
TopView
CrossSection
Poly SiAluminum Oxide Si substrate Al-Poly contact
21Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
After Patterning Intermediate Oxide ( Mask #3, Contact-Hole Cut)
TopView
CrossSection
Poly SiAluminum Oxide Si substrate Al-Poly contact
22Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
After Aluminum patterning (Mask #4)
To contact pad
TopView
CrossSection
Poly SiAluminum Oxide Si substrate Al-Poly contact
23Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
After XeF2 selective etching of Si Substrate (Final Structure)
To contact pad
Poly SiAluminum Oxide Si substrate Al-Poly contact
TopView
CrossSection
24Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
SubstrateBoron doped (100)SiResistivity= 20 Ω-cm
Thermal Oxidation~100Å pad oxide
CVD Si3N4~ 0.1 um
LithographyPattern Field OxideRegions
RIE removal of Nitride and pad oxide
Channel StopImplant: 3x1012 B/cm2
60keV
Thermal Oxidation to grow 0.45um oxide
Wet EtchNitrdie and pad oxide
Ion Implant forThresholdVoltage control8x1011 B/cm2 35keV
Thermal OxidationTo grow 250Ågate oxide
LPCVDPoly-Si~ 0.35um
Dope Poly-Si to n+with PhosphorusDiffusion source
A Generic NMOS Process Flow
25Professor N Cheung, U.C. Berkeley
Lecture 20EE143 S06
LithographyPoly-Si Gate pattern
RIE Poly-Si gate
Source /Drain Implantation~ 1016 As/cm2 80keV
Thermal OxidationGrow ~0.1um oxide on poly-SiAnd source/drian
LPCVDSiO2~0.35um
LithographyContact Window pattern
RIE removal of CVD oxide and thermal oxide
Sputter DepositAl metal~0.7um
LithographyAl interconnect pattern
RIE etch of Al metallization
Sintering at ~400oC in H2 ambientto improve contact resistanceand to reduce oxide interface charge
